coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14471 -gerrit commit 4f867369f6292dfb82885ff943985066a158ce8a Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Apr 19 18:04:21 2016 -0700 soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds Add chromeos required gnvs feature, the gnvs table stays in both CBMEM and acpi dsdt tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 29 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 29 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 7 +++++++ 4 files changed, 67 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7d28313..a300417 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -16,12 +16,15 @@ */ #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <soc/nvs.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -125,3 +128,29 @@ unsigned long southbridge_write_acpi_tables(device_t device, { return acpi_write_hpet(device, current, rsdp); } + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} + +void southbridge_inject_dsdt(device_t device) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 2d20805..3605cc3 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -25,4 +25,6 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt); unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); +void southbridge_inject_dsdt(device_t device); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h new file mode 100644 index 0000000..616faae --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -0,0 +1,29 @@ +/* + * NOTE: The layout of the global_nvs_t structure below must match the layout + * in soc/intel/apollolake/acpi/globalnvs.asl !!! + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_NVS_H_ +#define _SOC_APOLLOLAKE_NVS_H_ + +#include <vendorcode/google/chromeos/gnvs.h> + +struct global_nvs_t { + /* Miscellaneous */ + uint8_t unused[256]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __attribute__((packed)); + +#endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index aadf18b..44497c0 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -15,10 +15,12 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/pci_ids.h> #include <reg_script.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -53,11 +55,16 @@ static void soc_lpc_add_io_resources(device_t dev) static void soc_lpc_read_resources(device_t dev) { + struct global_nvs_t *gnvs; + /* Get the PCI resources of this device. */ pci_dev_read_resources(dev); /* Add IO resources to LPC. */ soc_lpc_add_io_resources(dev); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } static struct device_operations device_ops = {

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Patch set updated for coreboot: mainboard/amenia: Enable LPC IO decodes
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14470 -gerrit commit 2d47cbba6718fff2755b688d026cc81727bb737d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Apr 21 20:07:09 2016 -0700 mainboard/amenia: Enable LPC IO decodes Change-Id: I3b278fc458b551b9bed2f53aa8089a55c84edf5a Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/mainboard.c | 24 +++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/pci_devs.h | 2 ++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 0d3896d..7662bab 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -15,9 +15,13 @@ * GNU General Public License for more details. */ +#include <device/pci.h> #include <device/device.h> #include <soc/gpio.h> +#include <soc/lpc.h> #include "ec.h" +#include <soc/intel/apollolake/chip.h> +#include <soc/pci_devs.h> /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config amenia_gpios[] = { @@ -134,12 +138,30 @@ static const struct pad_config amenia_gpios[] = { }; +static void lpc_decode_enable(void *chip_info) +{ + uint16_t lpc_en; + const struct soc_intel_apollolake_config *config = chip_info; + + /* IO Decode Enable */ + lpc_en = GAMEL_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(LPC_DEV, LPC_EN, lpc_en); + + /* + * Set in PCI generic decode range registers. + * EC host command range is in 0x800-0x9ff. + */ + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); +} + static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); + lpc_decode_enable(chip_info); mainboard_ec_init(); } struct chip_operations mainboard_ops = { - .init = mainboard_init, + .init = mainboard_init }; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 7b8caaf..0936428 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -26,6 +26,7 @@ #include <device/pci_def.h> #define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot)) #define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) +#define PCI_DEV(bus, slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) #else #include <arch/io.h> #define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0) @@ -51,5 +52,6 @@ #define P2SB_DEV PCI_DEV(0, 0xd, 0) #define PMC_DEV PCI_DEV(0, 0xd, 1) #define SPI_DEV PCI_DEV(0, 0xd, 2) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #endif

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New patch to review for coreboot: soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14471 -gerrit commit e9729d726c845d52783a3cc410a89890ffd25eeb Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Apr 19 18:04:21 2016 -0700 soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds Add chromeos required gnvs feature, the gnvs table stays in both CBMEM and acpi dsdt tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 29 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 29 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 7 +++++++ 4 files changed, 67 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7d28313..a300417 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -16,12 +16,15 @@ */ #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <soc/nvs.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -125,3 +128,29 @@ unsigned long southbridge_write_acpi_tables(device_t device, { return acpi_write_hpet(device, current, rsdp); } + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} + +void southbridge_inject_dsdt(device_t device) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 2d20805..3605cc3 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -25,4 +25,6 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt); unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); +void southbridge_inject_dsdt(device_t device); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h new file mode 100644 index 0000000..616faae --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -0,0 +1,29 @@ +/* + * NOTE: The layout of the global_nvs_t structure below must match the layout + * in soc/intel/apollolake/acpi/globalnvs.asl !!! + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_NVS_H_ +#define _SOC_APOLLOLAKE_NVS_H_ + +#include <vendorcode/google/chromeos/gnvs.h> + +struct global_nvs_t { + /* Miscellaneous */ + uint8_t unused[256]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __attribute__((packed)); + +#endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index aadf18b..44497c0 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -15,10 +15,12 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/pci_ids.h> #include <reg_script.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -53,11 +55,16 @@ static void soc_lpc_add_io_resources(device_t dev) static void soc_lpc_read_resources(device_t dev) { + struct global_nvs_t *gnvs; + /* Get the PCI resources of this device. */ pci_dev_read_resources(dev); /* Add IO resources to LPC. */ soc_lpc_add_io_resources(dev); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } static struct device_operations device_ops = {

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New patch to review for coreboot: mainboard/amenia: Enable LPC IO decodes
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14470 -gerrit commit 0042fe86be7df7f3cd988513195b1da2997de191 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Apr 21 20:07:09 2016 -0700 mainboard/amenia: Enable LPC IO decodes Change-Id: I3b278fc458b551b9bed2f53aa8089a55c84edf5a Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/mainboard.c | 24 +++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/pci_devs.h | 2 ++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 0d3896d..7662bab 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -15,9 +15,13 @@ * GNU General Public License for more details. */ +#include <device/pci.h> #include <device/device.h> #include <soc/gpio.h> +#include <soc/lpc.h> #include "ec.h" +#include <soc/intel/apollolake/chip.h> +#include <soc/pci_devs.h> /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config amenia_gpios[] = { @@ -134,12 +138,30 @@ static const struct pad_config amenia_gpios[] = { }; +static void lpc_decode_enable(void *chip_info) +{ + uint16_t lpc_en; + const struct soc_intel_apollolake_config *config = chip_info; + + /* IO Decode Enable */ + lpc_en = GAMEL_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(LPC_DEV, LPC_EN, lpc_en); + + /* + * Set in PCI generic decode range registers. + * EC host command range is in 0x800-0x9ff. + */ + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); +} + static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); + lpc_decode_enable(chip_info); mainboard_ec_init(); } struct chip_operations mainboard_ops = { - .init = mainboard_init, + .init = mainboard_init }; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 7b8caaf..0936428 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -26,6 +26,7 @@ #include <device/pci_def.h> #define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot)) #define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) +#define PCI_DEV(bus, slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) #else #include <arch/io.h> #define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0) @@ -51,5 +52,6 @@ #define P2SB_DEV PCI_DEV(0, 0xd, 0) #define PMC_DEV PCI_DEV(0, 0xd, 1) #define SPI_DEV PCI_DEV(0, 0xd, 2) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #endif

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New patch to review for coreboot: soc/intel/apollolake: Enable LPC bus interface
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14469 -gerrit commit a21eba4d6e4641c8b9e8a395f5f3a968daf80569 Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Fri Feb 5 11:27:44 2016 -0800 soc/intel/apollolake: Enable LPC bus interface Enables LPC serial IRQ as well as adds some LPC constants. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> --- src/soc/intel/apollolake/chip.h | 4 ++++ src/soc/intel/apollolake/include/soc/lpc.h | 34 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 23 +++++++++++++++++++- 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46..a5c7ac2 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -32,6 +32,10 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h new file mode 100644 index 0000000..f349ec3 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/lpc.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_APOLLOLAKE_LPC_H +#define _SOC_APOLLOLAKE_LPC_H + +/* PCI Configuration Space (D31:F0): LPC */ +#define SERIRQ_CNTL 0x64 /* Serial IRQ Control Register */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ + +#endif //_SOC_APOLLOLAKE_LPC_H diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 902ada2..aadf18b 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,6 +20,25 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/pci_ids.h> +#include <reg_script.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/lpc.h> +#include "chip.h" + +static const struct reg_script lpc_serirq_enable[] = { + /* Setup SERIRQ, enable continuous mode */ + REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) + REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), +#endif + REG_SCRIPT_END +}; + +static void lpc_init(struct device *dev) +{ + reg_script_run_on_dev(dev, lpc_serirq_enable); +} + static void soc_lpc_add_io_resources(device_t dev) { @@ -45,7 +64,9 @@ static struct device_operations device_ops = { .read_resources = &soc_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, + .init = &lpc_init }; static const struct pci_driver soc_lpc __pci_driver = {

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New patch to review for coreboot: mainboard/amenia: Enable Chrome EC Interface/Keyboard
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14468 -gerrit commit d9caec0a2869e18c894b9c68057d610d32ed2996 Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Mon Feb 8 09:45:37 2016 -0800 mainboard/amenia: Enable Chrome EC Interface/Keyboard Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 3 ++ src/mainboard/intel/amenia/Makefile.inc | 1 + src/mainboard/intel/amenia/acpi/superio.asl | 28 +++++++++++++ src/mainboard/intel/amenia/devicetree.cb | 4 ++ src/mainboard/intel/amenia/dsdt.asl | 3 ++ src/mainboard/intel/amenia/ec.c | 52 +++++++++++++++++++++++ src/mainboard/intel/amenia/ec.h | 65 +++++++++++++++++++++++++++++ src/mainboard/intel/amenia/mainboard.c | 2 + 8 files changed, 158 insertions(+) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index f1946b5..be98b86 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -5,6 +5,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_PD select HAVE_ACPI_TABLES select MAINBOARD_HAS_LPC_TPM select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index 472a5aa..363c21e 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -3,5 +3,6 @@ bootblock-$(CONFIG_LPC_TPM) += bootblock.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c diff --git a/src/mainboard/intel/amenia/acpi/superio.asl b/src/mainboard/intel/amenia/acpi/superio.asl new file mode 100644 index 0000000..8804829 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/superio.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* mainboard configuration */ +#include "../ec.h" + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838..65fa8b7 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,10 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # EC host command range is in 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index ba4e722..19e7360 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -36,4 +36,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/apollolake/acpi/sleepstates.asl> + + #include "acpi/superio.asl" + } diff --git a/src/mainboard/intel/amenia/ec.c b/src/mainboard/intel/amenia/ec.c new file mode 100644 index 0000000..5b18b71 --- /dev/null +++ b/src/mainboard/intel/amenia/ec.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_ERR, "mainboard: EC init\n"); + post_code(0xf0); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); + post_code(0xf1); +} diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h new file mode 100644 index 0000000..6408815 --- /dev/null +++ b/src/mainboard/intel/amenia/ec.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 9949061..0d3896d 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -17,6 +17,7 @@ #include <device/device.h> #include <soc/gpio.h> +#include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config amenia_gpios[] = { @@ -136,6 +137,7 @@ static const struct pad_config amenia_gpios[] = { static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); + mainboard_ec_init(); } struct chip_operations mainboard_ops = {

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New patch to review for coreboot: mainboard/amenia: Add GPIO setup for TPM in bootblock
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14467 -gerrit commit 372d6e48b7b48c6325b881cdf512978a7150b04b Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Apr 18 13:36:19 2016 -0700 mainboard/amenia: Add GPIO setup for TPM in bootblock Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/Makefile.inc | 2 ++ src/mainboard/intel/amenia/bootblock.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index 00d738e..472a5aa 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -1,3 +1,5 @@ +bootblock-$(CONFIG_LPC_TPM) += bootblock.c + romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/amenia/bootblock.c b/src/mainboard/intel/amenia/bootblock.c new file mode 100644 index 0000000..d075336 --- /dev/null +++ b/src/mainboard/intel/amenia/bootblock.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> + +static const struct pad_config tpm_spi_configs[] = { + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ +}; + +static void tpm_enable(void) +{ + /* Configure gpios */ + gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs)); +} + +void bootblock_mainboard_init(void) { + if (IS_ENABLED(CONFIG_LPC_TPM)) + tpm_enable(); +}

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New patch to review for coreboot: soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usable
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14466 -gerrit commit eeb58c7ad77610a52c63755268d5a0a4782b96f4 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Apr 21 14:59:12 2016 -0700 soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usable coreboot writes RDSP at 0xf0000. Since depthcharge wipes usable memory before starting kernel it can't find RDSP. Change-Id: I584bd5d24248cf38f46342615cf3b0252a821b2a Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/northbridge.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index 00e3501..775c89e 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -109,8 +109,8 @@ static int mc_add_dram_resources(device_t dev, int index) /* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ ram_resource(dev, index++, 0, 640); - /* 0xc0000 -> top_of_ram, skipping the legacy VGA region */ - base_k = 768; + /* 0x100000 -> top_of_ram, skipping the legacy VGA region */ + base_k = 1024; size_k = (tseg / KiB) - base_k; ram_resource(dev, index++, base_k, size_k);

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New patch to review for coreboot: soc/intel/apollolake: Actually include PCI IRQ definitions
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14465 -gerrit commit ac4386bfb9184f4ad4322e82189f998e32407738 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Apr 21 14:53:33 2016 -0700 soc/intel/apollolake: Actually include PCI IRQ definitions Change-Id: I3854781049851b5aa5b2dbf3257ece2fee76c3e2 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/acpi/soc_int.asl | 1 + src/soc/intel/apollolake/acpi/southbridge.asl | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index 83a831f..7db23ee 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -51,6 +51,7 @@ #define SPI2_INT 37 #define UFS_INT 38 #define EMMC_INT 39 +#define PMC_INT 40 #define SDIO_INT 42 #endif /* _SOC_INT_DEFINE_ASL_ */ diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index cc52676..46d7013 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,3 +17,6 @@ /* LPSS device */ #include "lpss.asl" + +/* PCI IRQ assignment */ +#include "pci_irqs.asl"

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Patch set updated for coreboot: buildgcc: Drop --target from python and expat
by Stefan Reinauer 21 Apr '16

21 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14464 -gerrit commit ffa7654f9ca14d7c6b11b7a589d37c9c3cd1aa01 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 21 19:29:51 2016 -0700 buildgcc: Drop --target from python and expat Both packages are not using the target architecture. Drop it, and remove them from package_uses_targetarch Change-Id: I58efde4cb7cc39e7e3c31527eb7682e318928100 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e9ce774..c138473 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -289,8 +289,7 @@ is_package_enabled() package_uses_targetarch() { - if [ "$1" = "GCC" ] || [ "$1" = "GDB" ] || [ "$1" = "BINUTILS" ] || \ - [ "$1" = "PYTHON" ] || [ "$1" = "EXPAT" ]; then + if [ "$1" = "GCC" ] || [ "$1" = "GDB" ] || [ "$1" = "BINUTILS" ]; then true else false @@ -511,7 +510,7 @@ build_GCC() { build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ - --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed + --prefix=$TARGETDIR || touch .failed $MAKE || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -520,7 +519,7 @@ build_EXPAT() { build_PYTHON() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${PYTHON_DIR}/configure --prefix=$TARGETDIR \ - --target=${TARGETARCH} || touch .failed + || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed

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coreboot-gerrit April 2016