coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Enable LPC bus interface
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14469 -gerrit commit 912a31e08db6338dbc3a6862babdd4b87da1f3bd Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Fri Feb 5 11:27:44 2016 -0800 soc/intel/apollolake: Enable LPC bus interface Enables LPC serial IRQ as well as adds some LPC constants. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> --- src/soc/intel/apollolake/chip.h | 4 ++++ src/soc/intel/apollolake/include/soc/lpc.h | 30 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 23 ++++++++++++++++++++++- 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46..a5c7ac2 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -32,6 +32,10 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h new file mode 100644 index 0000000..87e92c3 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/lpc.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_LPC_H +#define _SOC_APOLLOLAKE_LPC_H + +/* PCI Configuration Space (D31:F0): LPC */ +#define SERIRQ_CNTL 0x64 /* Serial IRQ Control Register */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ + +#endif //_SOC_APOLLOLAKE_LPC_H diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 902ada2..aadf18b 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,6 +20,25 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/pci_ids.h> +#include <reg_script.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/lpc.h> +#include "chip.h" + +static const struct reg_script lpc_serirq_enable[] = { + /* Setup SERIRQ, enable continuous mode */ + REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) + REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), +#endif + REG_SCRIPT_END +}; + +static void lpc_init(struct device *dev) +{ + reg_script_run_on_dev(dev, lpc_serirq_enable); +} + static void soc_lpc_add_io_resources(device_t dev) { @@ -45,7 +64,9 @@ static struct device_operations device_ops = { .read_resources = &soc_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, + .init = &lpc_init }; static const struct pci_driver soc_lpc __pci_driver = {

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Patch set updated for coreboot: mainboard/amenia: Enable Chrome EC Interface/Keyboard
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14468 -gerrit commit 2159debd0b8c17a6b41e7e3ec8df9fd28c51c2c2 Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Mon Feb 8 09:45:37 2016 -0800 mainboard/amenia: Enable Chrome EC Interface/Keyboard Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 3 ++ src/mainboard/intel/amenia/Makefile.inc | 1 + src/mainboard/intel/amenia/acpi/superio.asl | 25 ++++++++++++ src/mainboard/intel/amenia/devicetree.cb | 4 ++ src/mainboard/intel/amenia/dsdt.asl | 3 ++ src/mainboard/intel/amenia/ec.c | 52 ++++++++++++++++++++++++ src/mainboard/intel/amenia/ec.h | 62 +++++++++++++++++++++++++++++ src/mainboard/intel/amenia/mainboard.c | 4 +- 8 files changed, 151 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index f1946b5..be98b86 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -5,6 +5,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_PD select HAVE_ACPI_TABLES select MAINBOARD_HAS_LPC_TPM select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index 472a5aa..363c21e 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -3,5 +3,6 @@ bootblock-$(CONFIG_LPC_TPM) += bootblock.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c diff --git a/src/mainboard/intel/amenia/acpi/superio.asl b/src/mainboard/intel/amenia/acpi/superio.asl new file mode 100644 index 0000000..db14d17 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/superio.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838..65fa8b7 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,10 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # EC host command range is in 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index ba4e722..19e7360 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -36,4 +36,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/apollolake/acpi/sleepstates.asl> + + #include "acpi/superio.asl" + } diff --git a/src/mainboard/intel/amenia/ec.c b/src/mainboard/intel/amenia/ec.c new file mode 100644 index 0000000..7055936 --- /dev/null +++ b/src/mainboard/intel/amenia/ec.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Google Inc. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_ERR, "mainboard: EC init\n"); + post_code(0xf0); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); + post_code(0xf1); +} diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h new file mode 100644 index 0000000..ab8bcba --- /dev/null +++ b/src/mainboard/intel/amenia/ec.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 42ea07d..4250de0 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -18,13 +18,11 @@ #include <device/pci.h> #include <device/device.h> #include <soc/gpio.h> -<<<<<<< HEAD -======= #include <soc/lpc.h> #include "ec.h" #include <soc/intel/apollolake/chip.h> #include <soc/pci_devs.h> ->>>>>>> 2d47cbb... mainboard/amenia: Enable LPC IO decodes +#include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config amenia_gpios[] = {

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Patch set updated for coreboot: soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14471 -gerrit commit 9512e4fddaf854f34400ac104c2115ce23049101 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Apr 19 18:04:21 2016 -0700 soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds Add chromeos required gnvs feature, the gnvs table stays in both CBMEM and acpi dsdt tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 37 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 7 ++++++ 4 files changed, 75 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7d28313..a300417 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -16,12 +16,15 @@ */ #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <soc/nvs.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -125,3 +128,29 @@ unsigned long southbridge_write_acpi_tables(device_t device, { return acpi_write_hpet(device, current, rsdp); } + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} + +void southbridge_inject_dsdt(device_t device) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 2d20805..3605cc3 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -25,4 +25,6 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt); unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); +void southbridge_inject_dsdt(device_t device); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h new file mode 100644 index 0000000..8b3a3af --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the global_nvs_t structure below must match the layout + * in soc/intel/apollolake/acpi/globalnvs.asl !!! + * + */ + +#ifndef _SOC_APOLLOLAKE_NVS_H_ +#define _SOC_APOLLOLAKE_NVS_H_ + +#include <vendorcode/google/chromeos/gnvs.h> + +struct global_nvs_t { + /* Miscellaneous */ + uint8_t unused[256]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __attribute__((packed)); + +#endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index aadf18b..44497c0 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -15,10 +15,12 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/pci_ids.h> #include <reg_script.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -53,11 +55,16 @@ static void soc_lpc_add_io_resources(device_t dev) static void soc_lpc_read_resources(device_t dev) { + struct global_nvs_t *gnvs; + /* Get the PCI resources of this device. */ pci_dev_read_resources(dev); /* Add IO resources to LPC. */ soc_lpc_add_io_resources(dev); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } static struct device_operations device_ops = {

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Patch set updated for coreboot: mainboard/amenia: Enable LPC IO decodes
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14470 -gerrit commit 84b1ba9bbfe048d23a69627ae1d99df193ccc1f3 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Apr 21 20:07:09 2016 -0700 mainboard/amenia: Enable LPC IO decodes Change-Id: I3b278fc458b551b9bed2f53aa8089a55c84edf5a Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/mainboard.c | 29 ++++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/pci_devs.h | 2 ++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 9949061..42ea07d 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -15,8 +15,16 @@ * GNU General Public License for more details. */ +#include <device/pci.h> #include <device/device.h> #include <soc/gpio.h> +<<<<<<< HEAD +======= +#include <soc/lpc.h> +#include "ec.h" +#include <soc/intel/apollolake/chip.h> +#include <soc/pci_devs.h> +>>>>>>> 2d47cbb... mainboard/amenia: Enable LPC IO decodes /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config amenia_gpios[] = { @@ -133,11 +141,30 @@ static const struct pad_config amenia_gpios[] = { }; +static void lpc_decode_enable(void *chip_info) +{ + uint16_t lpc_en; + const struct soc_intel_apollolake_config *config = chip_info; + + /* IO Decode Enable */ + lpc_en = GAMEL_LPC_EN | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(LPC_DEV, LPC_EN, lpc_en); + + /* + * Set in PCI generic decode range registers. + * EC host command range is in 0x800-0x9ff. + */ + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); +} + static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); + lpc_decode_enable(chip_info); + mainboard_ec_init(); } struct chip_operations mainboard_ops = { - .init = mainboard_init, + .init = mainboard_init }; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 7b8caaf..0936428 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -26,6 +26,7 @@ #include <device/pci_def.h> #define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot)) #define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func)) +#define PCI_DEV(bus, slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) #else #include <arch/io.h> #define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0) @@ -51,5 +52,6 @@ #define P2SB_DEV PCI_DEV(0, 0xd, 0) #define PMC_DEV PCI_DEV(0, 0xd, 1) #define SPI_DEV PCI_DEV(0, 0xd, 2) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #endif

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New patch to review for coreboot: google: nyan_big: Match CBFS_SIZE with the cbfs size in fmap for ChromeOS
by Paul Kocialkowski 22 Apr '16

22 Apr '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14474 -gerrit commit a3741868c08a043cd1d95e6f5daf82a31b333a3e Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Fri Apr 22 15:13:18 2016 +0200 google: nyan_big: Match CBFS_SIZE with the cbfs size in fmap for ChromeOS When building for ChromeOS, it is expected that Coreboot will only occupy the first MiB of the SPI flash, according to the nyan fmap description. Otherwise, it makes sense to use the full ROM size. Change-Id: I88f444c99abec340c778fd0a56972e16d2d63c4f Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/mainboard/google/nyan_big/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index fdd40f6..c0cbc62 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -95,6 +95,11 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 +config CBFS_SIZE + hex + default 0x100000 if CHROMEOS + default ROM_SIZE + config EC_GOOGLE_CHROMEEC_BOARDNAME string default "big"

1 0

New patch to review for coreboot: libpayload: Add nyan config
by Paul Kocialkowski 22 Apr '16

22 Apr '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14473 -gerrit commit c5fec719c257eb6761b1596414c545a5720f0c85 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Fri Apr 22 15:11:37 2016 +0200 libpayload: Add nyan config This adds a libpayload config for nyan, that should fit all nyan devices. Change-Id: I6b86a03054a7625534fd38ee6a21d3b91fb43589 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- payloads/libpayload/configs/config.nyan | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/payloads/libpayload/configs/config.nyan b/payloads/libpayload/configs/config.nyan new file mode 100644 index 0000000..8bc0be9 --- /dev/null +++ b/payloads/libpayload/configs/config.nyan @@ -0,0 +1,10 @@ +CONFIG_LP_GPL=y +CONFIG_LP_ARCH_ARM=y +# CONFIG_LP_CURSES is not set +CONFIG_LP_SKIP_CONSOLE_INIT=y +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +# CONFIG_LP_STORAGE is not set +CONFIG_LP_TIMER_TEGRA_1US=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y

1 0

New patch to review for coreboot: chromeos: Ensure that the last file in FW_MAIN_ is not also the first one
by Paul Kocialkowski 22 Apr '16

22 Apr '16

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14472 -gerrit commit 9efe63607bf1b2549c1f9218a03e5176a8fd69a7 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Fri Apr 22 11:10:03 2016 +0200 chromeos: Ensure that the last file in FW_MAIN_ is not also the first one In the case where one of the FW_MAIN_ regions is empty, the last file (empty) will also appear to be first and have a zero offset, making head complain. This is a very borderline use case, since the FW_MAIN_ regions should have been filled previously, but an extra check doesn't hurt. Change-Id: I15491c5b4a5e7d1f9fb369cc5fa4e3875e2dad3b Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/vendorcode/google/chromeos/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 0ae6fb0..2b579d1 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -138,7 +138,7 @@ $(obj)/FW_MAIN_%.bin: $(obj)/coreboot.rom tail -1 | \ sed "s,^(empty)[[:space:]]$0x[0-9a-f]*$\tnull\t.*$$,\1," \ > $@.tmp.size - if [ -n "$$(cat $@.tmp.size)" ]; then \ + if [ -n "$$(cat $@.tmp.size)" ] && [ $$( printf "%d" $$(cat $@.tmp.size)) -gt 0 ]; then \ head -c $$( printf "%d" $$(cat $@.tmp.size)) $@.tmp > $@.tmp2 && \ mv $@.tmp2 $@; \ else \

1 0

Patch set updated for coreboot: buildgcc: Add option to bootstrap a host gcc
by Nico Huber 22 Apr '16

22 Apr '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13473 -gerrit commit 8b1533fb89e707c9ce3bab642d45f16ef62441de Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:10:17 2016 +0100 buildgcc: Add option to bootstrap a host gcc Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. v3: Some library controversy: gcc likes the libraries it ships with most but we don't want to install shared libraries. So we build them static --disable-shared) and install only the minimum (libgcc, libada, libstdc++). However, as the code of these libraries might be used to build a shared library we have to compile them with `-fPIC`. v4: o Updated getopt strings. o The workaround for clang (-fbracket-depth=1024) isn't needed for bootstrapping and also breaks the build, as clang is only used for the first stage in that case and gcc doesn't know that option. So far build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Ubuntu 14.04 "Trusty Tahr" (i386) o Debian 8 "Jessie" (x86_64) (building python (-S) works too) o current Arch Linux (x86_64) o FreeBSD 10.3 (x86_64) (with gcc-aux package) and with clang host compiler, thus C only: `make BUILDGCC_OPTIONS="-b"` on o Debian 8 "Jessie" (x86_64) o FreeBSD 10.3 (x86_64) Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 54 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 6 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fae8bd3..df5aa45 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="April 3rd, 2016" -CROSSGCC_VERSION="1.38" +CROSSGCC_DATE="April 20th, 2016" +CROSSGCC_VERSION="1.39" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -30,6 +30,7 @@ LANGUAGES=c DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 +BOOTSTRAP=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -342,6 +343,9 @@ build_for_target() build() { if package_uses_targetarch $1; then + if [ $BOOTSTRAP -eq 1 -a ! -f "${TARGETDIR}/.GCC.success" ]; then + build_for_host GCC + fi build_for_target $1 else build_for_host $1 @@ -386,6 +390,8 @@ myhelp() printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n" printf " (defaults to $PACKAGE)\n" printf "GCC specific options:\n" + printf " [-b|--bootstrap] bootstrap the host compiler before building\n" + printf " the cross compiler\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-l|--languages <languages>] comma separated list of target languages\n" @@ -498,8 +504,35 @@ build_BINUTILS() { $MAKE install DESTDIR=$DESTDIR || touch .failed } - -build_GCC() { +bootstrap_GCC() { + CC="$CC" \ + CFLAGS="$HOSTCFLAGS" \ + CFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + CXXFLAGS="$HOSTCFLAGS" \ + CXXFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CXXFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + ../gcc-${GCC_VERSION}/configure \ + --prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \ + --enable-bootstrap \ + --disable-werror --disable-nls \ + --disable-shared --disable-multilib \ + --disable-libssp --disable-libquadmath --disable-libcc1 \ + ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ + --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ + --with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \ + --with-pkgversion="coreboot bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + && \ + $MAKE $JOBS BOOT_CFLAGS="$HOSTCFLAGS" BUILD_CONFIG="" bootstrap && \ + $MAKE install-gcc \ + install-target-libgcc \ + maybe-install-target-libada \ + maybe-install-target-libstdc++-v3 \ + DESTDIR=$DESTDIR && \ + ln -s gcc $DESTDIR$TARGETDIR/bin/cc || touch .failed +} + +build_cross_GCC() { # Work around crazy code generator in GCC that confuses CLANG. $CC --version | grep clang >/dev/null 2>&1 && \ HOSTCFLAGS="$HOSTCFLAGS -fbracket-depth=1024" @@ -537,6 +570,14 @@ build_GCC() { fi } +build_GCC() { + if [ "$1" = host ]; then + bootstrap_GCC + else + build_cross_GCC + fi +} + build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed @@ -642,11 +683,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:p:l:P:j:D:tSys: -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:bp:l:P:j:D:tSys: -- "$@") eval set "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:p:l:P:j:D:tSys: $*) + args=$(getopt Vhcd:bp:l:P:j:D:tSys: $*) set -- $args fi @@ -662,6 +703,7 @@ while true ; do -c|--clean) shift; clean=1;; -t|--savetemps) shift; SAVETEMPS=1;; -d|--directory) shift; TARGETDIR="$1"; shift;; + -b|--bootstrap) shift; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;;

1 0

Patch set updated for coreboot: soc/intel/apollolake: Enable LPC bus interface
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14469 -gerrit commit 36b0993200f59f0c4ab47e2c43d45c33012629d3 Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Fri Feb 5 11:27:44 2016 -0800 soc/intel/apollolake: Enable LPC bus interface Enables LPC serial IRQ as well as adds some LPC constants. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> --- src/soc/intel/apollolake/chip.h | 4 ++++ src/soc/intel/apollolake/include/soc/lpc.h | 34 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 23 +++++++++++++++++++- 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46..a5c7ac2 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -32,6 +32,10 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h new file mode 100644 index 0000000..f349ec3 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/lpc.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_APOLLOLAKE_LPC_H +#define _SOC_APOLLOLAKE_LPC_H + +/* PCI Configuration Space (D31:F0): LPC */ +#define SERIRQ_CNTL 0x64 /* Serial IRQ Control Register */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ + +#endif //_SOC_APOLLOLAKE_LPC_H diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 902ada2..aadf18b 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,6 +20,25 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/pci_ids.h> +#include <reg_script.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/lpc.h> +#include "chip.h" + +static const struct reg_script lpc_serirq_enable[] = { + /* Setup SERIRQ, enable continuous mode */ + REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) + REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), +#endif + REG_SCRIPT_END +}; + +static void lpc_init(struct device *dev) +{ + reg_script_run_on_dev(dev, lpc_serirq_enable); +} + static void soc_lpc_add_io_resources(device_t dev) { @@ -45,7 +64,9 @@ static struct device_operations device_ops = { .read_resources = &soc_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, + .init = &lpc_init }; static const struct pci_driver soc_lpc __pci_driver = {

1 0

Patch set updated for coreboot: mainboard/amenia: Enable Chrome EC Interface/Keyboard
by Andrey Petrov 22 Apr '16

22 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14468 -gerrit commit 82ffa58301d1efaf8693b4fe2f400135820ffb12 Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Mon Feb 8 09:45:37 2016 -0800 mainboard/amenia: Enable Chrome EC Interface/Keyboard Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 3 ++ src/mainboard/intel/amenia/Makefile.inc | 1 + src/mainboard/intel/amenia/acpi/superio.asl | 25 ++++++++++++ src/mainboard/intel/amenia/devicetree.cb | 4 ++ src/mainboard/intel/amenia/dsdt.asl | 3 ++ src/mainboard/intel/amenia/ec.c | 52 ++++++++++++++++++++++++ src/mainboard/intel/amenia/ec.h | 62 +++++++++++++++++++++++++++++ src/mainboard/intel/amenia/mainboard.c | 2 + 8 files changed, 152 insertions(+) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index f1946b5..be98b86 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -5,6 +5,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_PD select HAVE_ACPI_TABLES select MAINBOARD_HAS_LPC_TPM select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc index 472a5aa..363c21e 100644 --- a/src/mainboard/intel/amenia/Makefile.inc +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -3,5 +3,6 @@ bootblock-$(CONFIG_LPC_TPM) += bootblock.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c diff --git a/src/mainboard/intel/amenia/acpi/superio.asl b/src/mainboard/intel/amenia/acpi/superio.asl new file mode 100644 index 0000000..db14d17 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/superio.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index c54e838..65fa8b7 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,10 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # EC host command range is in 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index ba4e722..19e7360 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -36,4 +36,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/apollolake/acpi/sleepstates.asl> + + #include "acpi/superio.asl" + } diff --git a/src/mainboard/intel/amenia/ec.c b/src/mainboard/intel/amenia/ec.c new file mode 100644 index 0000000..7055936 --- /dev/null +++ b/src/mainboard/intel/amenia/ec.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Google Inc. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_ERR, "mainboard: EC init\n"); + post_code(0xf0); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); + post_code(0xf1); +} diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h new file mode 100644 index 0000000..ab8bcba --- /dev/null +++ b/src/mainboard/intel/amenia/ec.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 9949061..0d3896d 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -17,6 +17,7 @@ #include <device/device.h> #include <soc/gpio.h> +#include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config amenia_gpios[] = { @@ -136,6 +137,7 @@ static const struct pad_config amenia_gpios[] = { static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); + mainboard_ec_init(); } struct chip_operations mainboard_ops = {

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coreboot-gerrit April 2016