Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13356
-gerrit
commit 68a78f55b263f2e303b739dac58f3a00ec0d3e54
Author: Lance Zhao <lijian.zhao(a)intel.com>
Date: Thu Nov 12 18:19:41 2015 -0800
soc/apollolake: Add lpc device driver
A dedicated pci device driver required for LPC devices as the legacy IO range
need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to
also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver
system will have assertion on load RTC DXE driver in UEFI payloads.
Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35
Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/lpc.c | 48 +++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 70ab515..98db608 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -34,6 +34,7 @@ ramstage-y += chip.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
ramstage-y += uart.c
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
new file mode 100644
index 0000000..80e693c
--- /dev/null
+++ b/src/soc/intel/apollolake/lpc.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_ids.h>
+
+static void soc_lpc_add_io_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Add the default claimed legacy IO range for the LPC device. */
+ res = new_resource(dev, 0);
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void soc_lpc_read_resources(device_t dev)
+{
+ /* Get the PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add IO resources to LPC. */
+ soc_lpc_add_io_resources(dev);
+}
+
+static struct device_operations device_ops = {
+ .read_resources = &soc_lpc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+};
+
+static const struct pci_driver soc_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = PCI_DEVICE_ID_APOLLOLAKE_LPC,
+};
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13356
-gerrit
commit df6c21aa4b5a1a8cd2d38b42db08fa19550ccd21
Author: Lance Zhao <lijian.zhao(a)intel.com>
Date: Thu Nov 12 18:19:41 2015 -0800
soc/apollolake: Add lpc device driver
A dedicated pci device driver required for LPC devices as the legacy IO range
need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to
also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver
system will have assertion on load RTC DXE driver in UEFI payloads.
Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35
Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/lpc.c | 47 +++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 70ab515..98db608 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -34,6 +34,7 @@ ramstage-y += chip.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
ramstage-y += uart.c
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
new file mode 100644
index 0000000..2154e77
--- /dev/null
+++ b/src/soc/intel/apollolake/lpc.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/pci_ids.h>
+
+static void soc_lpc_add_io_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Add the default claimed legacy IO range for the LPC device. */
+ res = new_resource(dev, 0);
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void soc_lpc_read_resources(device_t dev)
+{
+ /* Get the PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add IO resources to LPC. */
+ soc_lpc_add_io_resources(dev);
+}
+
+static struct device_operations device_ops = {
+ .read_resources = &soc_lpc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+};
+
+static const struct pci_driver soc_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = PCI_DEV_ID_APOLLOLAKE_LPC,
+};
Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14244
-gerrit
commit 8a34c558b13b67b9572f1e3861ae1de79ffb8aaf
Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Date: Mon Apr 4 19:52:35 2016 +0200
libpayload/libc: Fix memset/sizeof usage
Since r is a pointer, memset(r, 0, sizeof(r)) would only zero the first
4 (or 8) bytes of the newly allocated struct align_region_t.
An alternative to this patch would be to use calloc, or introduce a new
zalloc (zeroed allocation; a single-element calloc) and use that.
This fixes Coverity ID 1291160.
Change-Id: Ic3e3487ce749eeebf6c4836e62b8a305ad766e7e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
---
payloads/libpayload/libc/malloc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c
index 7099e47..b7ac1a7 100644
--- a/payloads/libpayload/libc/malloc.c
+++ b/payloads/libpayload/libc/malloc.c
@@ -366,7 +366,7 @@ static struct align_region_t *allocate_region(int alignment, int num_elements,
if (r == NULL)
return NULL;
- memset(r, 0, sizeof(r));
+ memset(r, 0, sizeof(*r));
if (num_elements != 0) {
r->alignment = alignment;
Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13356
-gerrit
commit bf251e8333de8ecd61294a40fc00ed890c5f00eb
Author: Lance Zhao <lijian.zhao(a)intel.com>
Date: Thu Nov 12 18:19:41 2015 -0800
soc/apollolake: Add lpc device driver
A dedicated pci device driver required for LPC devices as the legacy IO range
need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to
also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver
system will have assertion on load RTC DXE driver in UEFI payloads.
Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35
Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/lpc.c | 47 +++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 70ab515..98db608 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -34,6 +34,7 @@ ramstage-y += chip.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
ramstage-y += uart.c
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
new file mode 100644
index 0000000..06f1a85
--- /dev/null
+++ b/src/soc/intel/apollolake/lpc.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void soc_lpc_add_io_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Add the default claimed legacy IO range for the LPC device. */
+ res = new_resource(dev, 0);
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void soc_lpc_read_resources(device_t dev)
+{
+ /* Get the PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add IO resources to LPC. */
+ soc_lpc_add_io_resources(dev);
+}
+
+static struct device_operations device_ops = {
+ .read_resources = &soc_lpc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+};
+
+static const struct pci_driver soc_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = PCI_DEV_ID_APOLLOLAKE_LPC,
+};
the following patch was just integrated into master:
commit c445b4fc773296be525123eb472ea27ac807339f
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Mar 31 17:27:05 2016 -0700
chromeos: Simplify fill_lb_gpios even further
A long time ago many Chrome OS boards had pages full of duplicated
boilerplate code for the fill_lb_gpios() function, and we spent a lot of
time bikeshedding a proper solution that passes a table of lb_gpio
structs which can be concisely written with a static struct initializer
in http://crosreview.com/234648. Unfortunately we never really finished
that patch and in the mean time a different solution using the
fill_lb_gpio() helper got standardized onto most boards.
Still, that solution is not quite as clean and concise as the one we had
already designed, and it also wasn't applied consistently to all recent
boards (causing more boards with bad code to get added afterwards). This
patch switches all boards newer than Link to the better solution and
also adds some nicer debug output for the GPIOs while I'm there.
If more boards need to be converted from fill_lb_gpio() to this model
later (e.g. from a branch), it's quite easy to do with:
s/fill_lb_gpio(gpio++,\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\));/\t{\1, \2, \4, \3},/
Based on a patch by Furquan Shaikh <furquan(a)google.com>.
BUG=None
BRANCH=None
TEST=Booted on Oak. Ran abuild -x.
Change-Id: I449974d1c75c8ed187f5e10935495b2f03725811
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/14226
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
See https://review.coreboot.org/14226 for details.
-gerrit