the following patch was just integrated into master:
commit d68e0476e9d8249c6cee28ca526d2e8818d703a4
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Mar 1 17:01:35 2016 -0800
intel/skylake: Do not log wake source on reset
Skip logging a wake source when just resetting without coming from
S3 or S5 state. This will prevent the occasional spurious event
like PCI PME from showing up in the event log.
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=run warm reboot teset on chell and ensure no wake source is logged
Change-Id: If739034dc9022b37c90b9cc849a00c604383e70f
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: e7b5cc91adc3ed10df7cebd758cf8144216b9890
Original-Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329846
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331173
Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13991
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13991 for details.
-gerrit
the following patch was just integrated into master:
commit d47d77692aedb154c6104f50527d0819523bce20
Author: mgarima <medha.garima(a)intel.com>
Date: Mon Feb 29 15:11:18 2016 +0530
intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PM
Enable SDHCI runtime PM since the display flicker due to
SCC Power Gatingis addressed by 0x82 microcode
BRANCH=glados
BUG=chrome-os-partner:44663
TEST=Check if display flicker is gone when SCC is power-gated
Change-Id: I7d1ac6e77a0d2e0a25414df6130862efcdae2c82
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: b552120cfeff09d16cb79652b7de7296121858ba
Original-Change-Id: Id82df475b262e8a91f0a93f8ddf80002b05c52f3
Original-Signed-off-by: Medha Garima <medha.garima(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329651
Original-Commit-Ready: Jenny Tc <jenny.tc(a)intel.com>
Original-Tested-by: Jenny Tc <jenny.tc(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331172
Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13990
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13990 for details.
-gerrit
the following patch was just integrated into master:
commit fe4d62708af53afd3e2df2074545f26f5e01c671
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Feb 25 17:17:35 2016 -0600
soc/intel/skylake: add option to statically clock gate 8254 timer
In order to save more power by shutting down clocks add the
ability to optionally clock gate the 8254 programmable interrupt
timer. When doing this the platforms lose their "PC"-ness which
certain payloads and OSes rely on such as SeaBIOS.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Enabled option on chell. Noted the bit is set upon booting.
Change-Id: I01f9d177bbde417d1efec2e16656a07dcebccbde
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 662575aa6a63656dedfa0ce1f202f5fac0205477
Original-Change-Id: Ib4a613cf1c28fc96c36fa2987c4b58a05beab178
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329411
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331171
Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13985 for details.
-gerrit
the following patch was just integrated into master:
commit 898e965abb64044dd432563af4d9de2c50d9f718
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Wed Feb 24 14:56:32 2016 +0530
glados/chell: send an extra VR mailbox command
MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode
has been updated since v76, and it requires an an extra VR mailbox
command should be sent from coreboot to pcode.
BUG=chrome-os-partner:48511
BRANCH=None
TEST=Verified on glados, clean S0ix entry and exit.
IMVP8 power is also pretty low
CQ-DEPEND=CL:329393
Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2
Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1
Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329480
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13983
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13983 for details.
-gerrit
the following patch was just integrated into master:
commit af31a998c95f377e65798b8fdae1e303f67de45d
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Wed Feb 24 14:31:40 2016 +0530
soc/intel/skylake: add option to enable VR specific mailbox cmd
Adding an option to enable VR specific mailbox command.
When set, an extra VR mailbox command specifically for
the MPS IMPV8 VR will be sent.
BUG=chrome-os-partner:48511
BRANCH=None
TEST=Verified on glados, clean S0ix entry and exit.
IMVP8 power is also pretty low
Change-Id: Ia5a23cbb1eca8b463eb7c7c279b74635f1d6b9f7
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: c90a799b51fe35bf184dca6ffce59c89a60f9917
Original-Change-Id: Iffd3fbcb9a15611eefc942529e6cdafba859fb2e
Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329393
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13982
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13982 for details.
-gerrit
the following patch was just integrated into master:
commit d2077af1af39f5e27d36a7a8d697dc0d64c1d33f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Mar 7 14:44:01 2016 -0600
vendorcode/intel/fsp/fsp1_1/skylake: update FspUpdVpd.h 1.9.0
The previous copy of FspUpdVpd.h was not up to date w.r.t. the
FSP release being used for skylake boards. Fix that.
BUG=chrome-os-partner:50863
BRANCH=None
TEST=Built and booted on chell.
Change-Id: I39896c04d35189b0fb2c903eefda4e5b7c57084a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: fd647f354b8d9946b2217751cf1af845f29191b7
Original-Change-Id: I4ad131af6c563c9c33eb2b9207b13617ff24385d
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331290
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13984
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13984 for details.
-gerrit
the following patch was just integrated into master:
commit 0bdfec85789f56167757a17a8dd18ca7418a51b3
Author: Yidi Lin <yidi.lin(a)mediatek.com>
Date: Tue Feb 16 20:42:10 2016 +0800
mediatek/mt8173: memlayout: Create DRAM DMA region for NOR flash DMA read.
NOR flash has a hardware limitation that it can't access SRAM region
after 4GB mode is enabled. We add a DRAM DMA region after 0x40000000
for NOR flash driver. So that the NOR flash driver can use this region
after 4GB mode is enabled.
BRANCH=none
BUG=chormoe-os-partner:49229
TEST=Boot to kernel on rev4 w/ 2GB ram and rev3 w/ 4GB ram.
And check /proc/meminfo.
Change-Id: I4a86f0028b26509589ec8d09e2d077920446ece1
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: dc61ec55187959101a9e891fe5e93928e9b8176e
Original-Change-Id: Ifedc9e2dfba5d294297b3a28134997ac1dd38f94
Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327962
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331177
Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13989
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13989 for details.
-gerrit
the following patch was just integrated into master:
commit c6d7dcc832521ad6e5d90ad82af384ec3d24aa09
Author: Yidi Lin <yidi.lin(a)mediatek.com>
Date: Thu Feb 4 17:26:48 2016 +0800
mediatek/mt8173: detect sdram size at runtime
Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect
the DRAM size at runtime.
BUG=chrome-os-partner:49427
BRANCH=none
TEST=Boot to kernel
Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223
Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed
Original-Signed-off-by: PH Hsu <ph.hsu(a)mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327961
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331176
Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13988 for details.
-gerrit
the following patch was just integrated into master:
commit 9a64ec4dd239f2b757dff9effe3b10510034e62c
Author: Yidi Lin <yidi.lin(a)mediatek.com>
Date: Mon Jan 18 11:06:19 2016 +0800
mediatek/mt8173: mmu: update mmu range before DRAM is initialized.
The DRAM size can not be determined before DRAM is initialized. Since
mt8173 only support 2GB and 4GB DRAM models. We map 0x0 to the end of
2GB DRAM address before DRAM is initialized.
BRANCH=none
BUG=none
TEST=boot to kernel
Change-Id: I27a00106b0aa91c3dacfcd2bcd9208f08b108dc5
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9720e67c86f0d37a08f7c32e900996c75d60288a
Original-Change-Id: I87d9c6ac11486decde102b7821f550c2f1a51f1c
Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327960
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331175
Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13987
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13987 for details.
-gerrit
the following patch was just integrated into master:
commit fd99eca8001c9178b3b2b15ca7d76437305c31aa
Author: Jitao Shi <jitao.shi(a)mediatek.com>
Date: Fri Jan 8 15:59:46 2016 +0800
Add a driver for the parade ps8640
BRANCH=none
BUG=none
TEST=none
Change-Id: Icf397ce2ffdaed5048367daf2086c067984fea0a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: b5a88793ccfc46af196300791a300be67b70f5b1
Original-Change-Id: I75adf2688c9c8b9a2338f7dee5d0ac10e7181529
Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321056
Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13981
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13981 for details.
-gerrit