coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

1 participants
1119 discussions

New patch to review for coreboot: coreinfo: Allow numbers in addition to F keys
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14065 -gerrit commit 13b27c00025e8f9c2fe7c304d4fad199375067c2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 23:17:28 2016 -0800 coreinfo: Allow numbers in addition to F keys When using coreinfo on a serial console (at least with gtkterm, picocom and minicom on Ubuntu 15.10) you can't send F keys to the payload. Allow 1..9 for F1..F9 Change-Id: Ie3a11fa1de57c7345737a1ccaff177f407cd5e48 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/coreinfo.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 41b5f12..d15a678 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -227,6 +227,8 @@ static void loop(void) halfdelay(10); while (1) { + int ch = -1; + #if IS_ENABLED(CONFIG_SHOW_DATE_TIME) print_time_and_date(); wrefresh(menuwin); @@ -237,20 +239,21 @@ static void loop(void) if (key == ERR) continue; - if (key >= KEY_F(1) && key <= KEY_F(9)) { - unsigned char ch = key - KEY_F(1); - - if (ch <= ARRAY_SIZE(categories)) { - if (ch == ARRAY_SIZE(categories)) - continue; - if (categories[ch].count == 0) - continue; + if (key >= KEY_F(1) && key <= KEY_F(9)) + ch = key - KEY_F(1); + if (key >= '1' && key <= '9') + ch = key - '1'; - curwin = ch; - print_submenu(&categories[curwin]); - redraw_module(&categories[curwin]); + if (ch >= 0 && ch <= ARRAY_SIZE(categories)) { + if (ch == ARRAY_SIZE(categories)) + continue; + if (categories[ch].count == 0) continue; - } + + curwin = ch; + print_submenu(&categories[curwin]); + redraw_module(&categories[curwin]); + continue; } if (key == KEY_ESC)

1 0

Patch merged into coreboot/master: nb/amd/mct_ddr3: Consolidate duplicated code
by gerrit＠coreboot.org 12 Mar '16

12 Mar '16

the following patch was just integrated into master: commit 2d987fe0fbd2c5271e7b9c4a183558cb6f4dc35a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 8 18:25:15 2016 -0600 nb/amd/mct_ddr3: Consolidate duplicated code read_dqs_read_data_timing_registers() and read_read_dqs_timing_control_registers() served essentially the same function but had slightly different semantics, causing confusion and needlessly complex Family15h code. Consolidate both into read_dqs_read_data_timing_registers() and adjust surrounding code to match new semantics. Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13994 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13994 for details. -gerrit

1 0

Patch merged into coreboot/master: payloads/seabios: Add "git revision" to the SeaBIOS version menu
by gerrit＠coreboot.org 12 Mar '16

12 Mar '16

the following patch was just integrated into master: commit 3aa91dc7be67ced7d0d5cad5bfe0fb497d40e3db Author: Antonello Dettori <dev(a)dettori.io> Date: Mon Mar 7 23:56:57 2016 +0000 payloads/seabios: Add "git revision" to the SeaBIOS version menu Add an option to specify a git revision from which to build SeaBIOS. Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640 Signed-off-by: Antonello Dettori <dev(a)dettori.io> Reviewed-on: https://review.coreboot.org/13937 Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13937 for details. -gerrit

1 0

Patch set updated for coreboot: payloads/seabios: Add "git revision" to the SeaBIOS version menu
by Antonello Dettori 12 Mar '16

12 Mar '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13937 -gerrit commit 564bbdcc17a7f4c09dd97188850f2f79139b42f2 Author: Antonello Dettori <dev(a)dettori.io> Date: Mon Mar 7 23:56:57 2016 +0000 payloads/seabios: Add "git revision" to the SeaBIOS version menu Add an option to specify a git revision from which to build SeaBIOS. Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/external/Makefile.inc | 2 ++ payloads/external/SeaBIOS/Kconfig | 16 ++++++++++++++++ payloads/external/SeaBIOS/Makefile.inc | 9 +++++++++ 3 files changed, 27 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index bbad643..3c20e13 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -46,6 +46,8 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(top)/$(DOTCONFIG) AS="$(AS_x86_32)" IASL="$(IASL)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_REVISION=$(CONFIG_SEABIOS_REVISION) \ + CONFIG_SEABIOS_REVISION_ID=$(CONFIG_SEABIOS_REVISION_ID) \ CONFIG_PAYLOAD_CONFIGFILE=$(CONFIG_PAYLOAD_CONFIGFILE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 5a9d52f..94aac8f 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -12,9 +12,25 @@ config SEABIOS_MASTER bool "master" help Newest SeaBIOS version +config SEABIOS_REVISION + bool "git revision" + help + Select this option if you have a specific commit or branch + that you want to use as the revision from which to + build SeaBIOS. + + You will be able to specify the name of a branch or a commit id + later. endchoice +config SEABIOS_REVISION_ID + string "Insert a commit's SHA-1 or a branch name" + depends on SEABIOS_REVISION + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. + config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" default 0 diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 4b134c8..0ac04d7 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,6 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master TAG-$(CONFIG_SEABIOS_STABLE)=b3ef39f532db52bf17457ba931da758eeb38d6b4 +TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -15,6 +16,14 @@ seabios: git clone http://review.coreboot.org/p/seabios.git seabios fetch: seabios +ifeq ($(TAG-y),) + echo "Error: The specified tag is invalid" +ifeq ($(CONFIG_SEABIOS_REVISION),y) + echo "Error: There is no revision specified for SeaBIOS" + false +endif + false +endif cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ] || \ [ "$(TAG-y)" = "origin/master" ]; then \ echo " Fetching new commits from the SeaBIOS git repo"; \

1 0

Patch set updated for coreboot: payloads/seabios: Add "git revision" to the SeaBIOS version menu
by Antonello Dettori 12 Mar '16

12 Mar '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13937 -gerrit commit 1c6f7f83f98e613018f461d9514b23fb9cefcf76 Author: Antonello Dettori <dev(a)dettori.io> Date: Mon Mar 7 23:56:57 2016 +0000 payloads/seabios: Add "git revision" to the SeaBIOS version menu Add an option to specify a git revision from which to build SeaBIOS. Change-Id: Ifbf3b82e784f79395ab7cd07c5804f72928d7640 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/external/Makefile.inc | 2 ++ payloads/external/SeaBIOS/Kconfig | 16 ++++++++++++++++ payloads/external/SeaBIOS/Makefile.inc | 15 ++++++++++++--- 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index bbad643..3c20e13 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -46,6 +46,8 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(top)/$(DOTCONFIG) AS="$(AS_x86_32)" IASL="$(IASL)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_REVISION=$(CONFIG_SEABIOS_REVISION) \ + CONFIG_SEABIOS_REVISION_ID=$(CONFIG_SEABIOS_REVISION_ID) \ CONFIG_PAYLOAD_CONFIGFILE=$(CONFIG_PAYLOAD_CONFIGFILE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 5a9d52f..94aac8f 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -12,9 +12,25 @@ config SEABIOS_MASTER bool "master" help Newest SeaBIOS version +config SEABIOS_REVISION + bool "git revision" + help + Select this option if you have a specific commit or branch + that you want to use as the revision from which to + build SeaBIOS. + + You will be able to specify the name of a branch or a commit id + later. endchoice +config SEABIOS_REVISION_ID + string "Insert a commit's SHA-1 or a branch name" + depends on SEABIOS_REVISION + default "origin/master" + help + The commit's SHA-1 or branch name of the revision to use. + config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" default 0 diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 4b134c8..bc1c68b 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,6 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master TAG-$(CONFIG_SEABIOS_STABLE)=b3ef39f532db52bf17457ba931da758eeb38d6b4 +TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -15,10 +16,18 @@ seabios: git clone http://review.coreboot.org/p/seabios.git seabios fetch: seabios +ifeq ($(TAG-y),) + echo "Error: The specified tag is invalid" +ifeq ($(CONFIG_SEABIOS_REVISION),y) + echo "Error: There is no revision specified for SeaBIOS" + false +endif + false +endif cd seabios; git show $(TAG-y) >/dev/null 2>&1 ; if [ $$? -ne 0 ] || \ - [ "$(TAG-y)" = "origin/master" ]; then \ - echo " Fetching new commits from the SeaBIOS git repo"; \ - git fetch; fi + [ "$(TAG-y)" = "origin/master" ]; then \ + echo " Fetching new commits from the SeaBIOS git repo"; \ + git fetch; fi checkout: fetch echo " Checking out SeaBIOS revision $(TAG-y)"

1 0

Patch set updated for coreboot: util/ifdtool: add option to change chip density
by Jan Tatje 12 Mar '16

12 Mar '16

Jan Tatje just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14032 -gerrit commit 55eecea569ca602a43aca2223d567d6ff6ede273 Author: Jan Tatje <jan(a)jnt.io> Date: Fri Mar 11 00:52:07 2016 +0100 util/ifdtool: add option to change chip density Adds -D / --density option to change the chip density. This is only implemented for IFD version 1 as I do not have an IFD version 2 to test this. Density of both chips is changed by default, but a chip can be selected using -C / --chip. Change-Id: Iba7affbf6cbefa3147b7b0e019298d905e694716 Signed-off-by: Jan Tatje <jan(a)jnt.io> --- util/ifdtool/ifdtool.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 112 insertions(+), 3 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 8a12725..85c6d4d 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -28,6 +28,7 @@ #endif static int ifd_version; +static int selected_chip = 0; static const struct region_name region_names[MAX_REGIONS] = { { "Flash Descriptor", "fd" }, @@ -748,6 +749,59 @@ static void set_em100_mode(char *filename, char *image, int size) set_spi_frequency(filename, image, size, freq); } +static void set_chipdensity(char *filename, char *image, int size, + unsigned int density) +{ + fdbar_t *fdb = find_fd(image, size); + fcba_t *fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4)); + + printf("Setting chip density to "); + decode_component_density(density); + printf("\n"); + + switch (ifd_version) { + case IFD_VERSION_1: + /* fail if selected density is not supported by this version */ + if ( (density == COMPONENT_DENSITY_32MB) || + (density == COMPONENT_DENSITY_64MB) || + (density == COMPONENT_DENSITY_UNUSED) ) { + printf("error: Selected density not supported in IFD version 1.\n"); + exit(EXIT_FAILURE); + } + break; + case IFD_VERSION_2: + /* I do not have a version 2 IFD nor do i have the docs. */ + printf("error: Changing the chip density for IFD version 2 has not been" + " implemented yet.\n"); + exit(EXIT_FAILURE); + default: + printf("error: Unknown IFD version\n"); + exit(EXIT_FAILURE); + break; + } + + /* clear chip density for corresponding chip */ + switch (selected_chip) { + case 1: + fcba->flcomp &= ~(0x7); + break; + case 2: + fcba->flcomp &= ~(0x7 << 3); + break; + default: /*both chips*/ + fcba->flcomp &= ~(0x3F); + break; + } + + /* set the new density */ + if (selected_chip == 1 || selected_chip == 0) + fcba->flcomp |= (density); /* first chip */ + if (selected_chip == 2 || selected_chip == 0) + fcba->flcomp |= (density << 3); /* second chip */ + + write_image(filename, image, size); +} + static void lock_descriptor(char *filename, char *image, int size) { int wr_shift, rd_shift; @@ -1075,6 +1129,10 @@ static void print_usage(const char *name) " -i | --inject <region>:<module> inject file <module> into region <region>\n" " -n | --newlayout <filename> update regions using a flashrom layout file\n" " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" + " -D | --density <512|1|2|4|8|16> set chip density (512 in KByte, others in MByte)\n" + " -C | --chip <0|1|2> select spi chip on which to operate\n" + " can only be used once per run:\n" + " 0 - both chips (default), 1 - first chip, 2 - second chip\n" " -e | --em100 set SPI frequency to 20MHz and disable\n" " Dual Output Fast Read Support\n" " -l | --lock Lock firmware descriptor and ME region\n" @@ -1090,9 +1148,10 @@ int main(int argc, char *argv[]) int opt, option_index = 0; int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0; int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0; - int mode_layout = 0, mode_newlayout = 0; + int mode_layout = 0, mode_newlayout = 0, mode_density = 0; char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL; int region_type = -1, inputfreq = 0; + unsigned int new_density = 0; enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; static struct option long_options[] = { @@ -1102,6 +1161,8 @@ int main(int argc, char *argv[]) {"inject", 1, NULL, 'i'}, {"newlayout", 1, NULL, 'n'}, {"spifreq", 1, NULL, 's'}, + {"density", 1, NULL, 'D'}, + {"chip", 1, NULL, 'C'}, {"em100", 0, NULL, 'e'}, {"lock", 0, NULL, 'l'}, {"unlock", 0, NULL, 'u'}, @@ -1110,7 +1171,7 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "df:xi:n:s:eluvh?", + while ((opt = getopt_long(argc, argv, "df:D:C:xi:n:s:eluvh?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1169,6 +1230,51 @@ int main(int argc, char *argv[]) exit(EXIT_FAILURE); } break; + case 'D': + mode_density = 1; + new_density = strtoul(optarg, NULL, 0); + switch (new_density) { + case 512: + new_density = COMPONENT_DENSITY_512KB; + break; + case 1: + new_density = COMPONENT_DENSITY_1MB; + break; + case 2: + new_density = COMPONENT_DENSITY_2MB; + break; + case 4: + new_density = COMPONENT_DENSITY_4MB; + break; + case 8: + new_density = COMPONENT_DENSITY_8MB; + break; + case 16: + new_density = COMPONENT_DENSITY_16MB; + break; + case 32: + new_density = COMPONENT_DENSITY_32MB; + break; + case 64: + new_density = COMPONENT_DENSITY_64MB; + break; + case 0: + new_density = COMPONENT_DENSITY_UNUSED; + break; + default: + printf("error: Unknown density\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + break; + case 'C': + selected_chip = strtol(optarg, NULL, 0); + if (selected_chip > 2) { + fprintf(stderr, "error: Invalid chip selection\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + break; case 's': // Parse the requested SPI frequency inputfreq = strtol(optarg, NULL, 0); @@ -1239,7 +1345,7 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + - mode_unlocked) == 0) { + mode_unlocked + mode_density) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); @@ -1300,6 +1406,9 @@ int main(int argc, char *argv[]) if (mode_spifreq) set_spi_frequency(filename, image, size, spifreq); + if (mode_density) + set_chipdensity(filename, image, size, new_density); + if (mode_em100) set_em100_mode(filename, image, size);

1 0

Patch set updated for coreboot: skylake mainboards: Configure gpio PADRSTCFG to PLTRST
by Patrick Georgi 12 Mar '16

12 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13992 -gerrit commit 134ab458783c4a5243c50847d68be81d65719dc8 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Mon Feb 29 13:20:44 2016 +0530 skylake mainboards: Configure gpio PADRSTCFG to PLTRST With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki <naresh.solanki(a)intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/chell/gpio.h | 8 +++--- src/mainboard/google/lars/gpio.h | 48 ++++++++++++++++++------------------ src/mainboard/intel/kunimitsu/gpio.h | 10 ++++---- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 0503e3e..05897eb 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), /* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ @@ -155,14 +155,14 @@ static const struct pad_config gpio_table[] = { /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index 5aee237..e187795 100644 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -72,19 +72,19 @@ static const struct pad_config gpio_table[] = { /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ /* GPP_A16 */ -/* SD_PWR_EN */ /* GPP_A17 */ -/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), -/* ISH_GP1 */ /* GPP_A19 */ -/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), -/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), -/* ISH_GP5 */ /* GPP_A23 */ -/* CORE_VID0 */ /* GPP_B0 */ -/* CORE_VID1 */ /* GPP_B1 */ -/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), -/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), +/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), +/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), +/* GYRO_INT */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), @@ -152,15 +152,15 @@ static const struct pad_config gpio_table[] = { /* ITCH_SPI_D2 */ /* GPP_D21 */ /* ITCH_SPI_D3 */ /* GPP_D22 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), -/* SATAXPCIE1 */ /* GPP_E1 */ -/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), -/* CPU_GP0 */ /* GPP_E3 */ -/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), -/* SATA_DEVSLP1 */ /* GPP_E5 */ -/* SATA_DEVSLP2 */ /* GPP_E6 */ -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), -/* SATALED# */ /* GPP_E8 */ +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* TCH_PNL_INTR* */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), @@ -186,8 +186,8 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), -/* I2C5_SCL */ /* GPP_F11 */ +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index de51fb5..d310396 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), @@ -160,14 +160,14 @@ static const struct pad_config gpio_table[] = { /* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), /* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SSD_PEDET */ PAD_CFG_NC(GPP_E2), /* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -181,7 +181,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),

1 0

Patch set updated for coreboot: intel/fsp1.1: Mark graphics init done after SiliconInit phase
by Patrick Georgi 12 Mar '16

12 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13986 -gerrit commit f93b6eb45a653b9b6ca590286d6f59273ef5b1cf Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Mar 7 13:21:56 2016 -0800 intel/fsp1.1: Mark graphics init done after SiliconInit phase If the VBT was provided to the FSP GOP driver then graphics init will be done as part of SiliconInit step and we can mark that when it is completed. This will result in the "oprom" flag being set properly in the coreboot gpio table and the netboot firmware will have video. [pg: avoided conflict with Quark that comes without silicon_init_params.GraphicsConfigPtr] BUG=chrome-os-partner:50864 BRANCH=glados TEST=boot image.net.bin on chell and get working graphics without being setuck in a reboot loop thinking graphics needs to be started when it already has been. Change-Id: I0e481b4be57096ed5c60d78e3fa00f3bb2a4eae1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 089d93c712431d1b5923e844137c558994555e95 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331301 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-(cherry picked from commit eeb9d470d8118422feb39ca71106972f2882e240) Original-Change-Id: Ic59bad27eb9f184ca3eba24643851bfadfe23ab5 Original-Reviewed-on: https://chromium-review.googlesource.com/331355 --- src/drivers/intel/fsp1_1/ramstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 277b609..834f148 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootmode.h> #include <arch/acpi.h> #include <cbmem.h> #include <cbfs.h> @@ -140,6 +141,14 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) timestamp_add_now(TS_FSP_SILICON_INIT_END); printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + /* Mark graphics init done after SiliconInit if VBT was provided */ +#if IS_ENABLED(CONFIG_GOP_SUPPORT) + /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs + * to be #if'd out instead of using if(). */ + if (silicon_init_params.GraphicsConfigPtr) + gfx_set_init_done(1); +#endif + display_hob_info(fsp_info_header); soc_after_silicon_init(); }

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Consolidate duplicated code
by Timothy Pearson 12 Mar '16

12 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13994 -gerrit commit 6c4e0571223722866d000b224fd3ca25431556db Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 8 18:25:15 2016 -0600 nb/amd/mct_ddr3: Consolidate duplicated code read_dqs_read_data_timing_registers() and read_read_dqs_timing_control_registers() served essentially the same function but had slightly different semantics, causing confusion and needlessly complex Family15h code. Consolidate both into read_dqs_read_data_timing_registers() and adjust surrounding code to match new semantics. Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 97 ++++-------------------- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 100 ++++++++++++++++++------- 2 files changed, 87 insertions(+), 110 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index fc08154..182fab0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -17,8 +17,11 @@ static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); -static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); +static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, + uint8_t dct, uint8_t dimm, uint32_t index_reg); + +static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, + uint8_t dct, uint8_t dimm, uint32_t index_reg); static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -383,76 +386,6 @@ static void write_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x3 | (dimm << 8), dword); } -static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) - mask = 0x3e; - else - mask = 0x3f; - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); - delay[3] = (dword >> 24) & mask; - delay[2] = (dword >> 16) & mask; - delay[1] = (dword >> 8) & mask; - delay[0] = dword & mask; - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); - delay[7] = (dword >> 24) & mask; - delay[6] = (dword >> 16) & mask; - delay[5] = (dword >> 8) & mask; - delay[4] = dword & mask; - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); - delay[8] = dword & mask; -} - -static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) - mask = 0x3e; - else - mask = 0x3f; - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= (delay[3] & mask) << 24; - dword |= (delay[2] & mask) << 16; - dword |= (delay[1] & mask) << 8; - dword |= delay[0] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8), dword); - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= (delay[7] & mask) << 24; - dword |= (delay[6] & mask) << 16; - dword |= (delay[5] & mask) << 8; - dword |= delay[4] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8), dword); - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); - dword &= ~mask; - dword |= delay[8] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8), dword); -} - /* DQS Position Training * Algorithm detailed in the Fam10h BKDG Rev. 3.62 section 2.8.9.9.3 */ @@ -982,7 +915,7 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, continue; read_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - read_read_dqs_timing_control_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); + read_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); for (lane = 0; lane < MAX_BYTE_LANES; lane++) if ((current_phy_phase_delay[lane] + current_read_dqs_delay[lane]) > max_delay) max_delay = (current_phy_phase_delay[lane] + current_read_dqs_delay[lane]); @@ -1409,10 +1342,10 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.4 (2 C) * For each Read DQS Delay value from 0 to 1 UI */ - for (current_read_dqs_delay[lane] = 0; current_read_dqs_delay[lane] < 0x40; current_read_dqs_delay[lane] += 2) { + for (current_read_dqs_delay[lane] = 0; current_read_dqs_delay[lane] < 0x20; current_read_dqs_delay[lane]++) { print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 161 current_read_dqs_delay[lane] ", current_read_dqs_delay[lane], 6); - if ((current_read_dqs_delay[lane] >> 1) >= (32 - 16)) { + if (current_read_dqs_delay[lane] >= (32 - 16)) { check_antiphase = 1; } else { check_antiphase = 0; @@ -1433,7 +1366,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x264); if ((dword & 0x1ffffff) != 0) { print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 162 early abort: F2x264 ", dword, 6); - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 0; /* Fail */ continue; } } @@ -1444,16 +1377,16 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x268) & 0x3ffff; print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 163 read results: F2x268 ", dword, 6); if (dword & (0x3 << (lane * 2))) - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 0; /* Fail */ else - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 1; /* Pass */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 1; /* Pass */ if (check_antiphase == 1) { /* Check antiphase results */ dword = Get_NB32_DCT(dev, dct, 0x26c) & 0x3ffff; if (dword & (0x3 << (lane * 2))) - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - (current_read_dqs_delay[lane] >> 1))] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - current_read_dqs_delay[lane])] = 0; /* Fail */ else - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - (current_read_dqs_delay[lane] >> 1))] = 1; /* Pass */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - current_read_dqs_delay[lane])] = 1; /* Pass */ } } } @@ -1511,8 +1444,8 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay)); /* Program the Read DQS Timing Control register with the center of the passing window */ - current_read_dqs_delay[lane] = region_center << 1; - passing_read_dqs_delay_found = 1; + current_read_dqs_delay[lane] = region_center; + passing_dqs_delay_found[lane] = 1; /* Commit the current Read DQS Timing Control settings to the hardware registers */ write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index f0e670b..da71816 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -475,40 +475,84 @@ static void write_dram_phase_recovery_control_registers(uint16_t* current_total_ } } -static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) { - uint8_t lane; + uint8_t shift; uint32_t dword; + uint32_t mask; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t rdt_reg; + if (is_fam15h()) { + mask = 0x3e; + shift = 1; + } + else { + mask = 0x3f; + shift = 0; + } - /* Calculate DRAM Read DQS Timing register location */ - if ((lane == 0) || (lane == 1) || (lane == 2) || (lane == 3)) - rdt_reg = 0x5; - if ((lane == 4) || (lane == 5) || (lane == 6) || (lane == 7)) - rdt_reg = 0x6; - if (lane == 8) - rdt_reg = 0x7; - rdt_reg |= (dimm << 8); + /* Lanes 0 - 3 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); + delay[3] = ((dword >> 24) & mask) >> shift; + delay[2] = ((dword >> 16) & mask) >> shift; + delay[1] = ((dword >> 8) & mask) >> shift; + delay[0] = (dword & mask) >> shift; + + /* Lanes 4 - 7 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); + delay[7] = ((dword >> 24) & mask) >> shift; + delay[6] = ((dword >> 16) & mask) >> shift; + delay[5] = ((dword >> 8) & mask) >> shift; + delay[4] = (dword & mask) >> shift; + + /* Lane 8 (ECC) */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); + delay[8] = (dword & mask) >> shift; +} - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, rdt_reg); - if ((lane == 7) || (lane == 3)) { - current_total_delay[lane] = (dword >> 24) & 0x3f; - } - if ((lane == 6) || (lane == 2)) { - current_total_delay[lane] = (dword >> 16) & 0x3f; - } - if ((lane == 5) || (lane == 1)) { - current_total_delay[lane] = (dword >> 8) & 0x3f; - } - if ((lane == 8) || (lane == 4) || (lane == 0)) { - current_total_delay[lane] = dword & 0x3f; - } +static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +{ + uint8_t shift; + uint32_t dword; + uint32_t mask; - if (is_fam15h()) - current_total_delay[lane] >>= 1; + if (is_fam15h()) { + mask = 0x3e; + shift = 1; + } + else { + mask = 0x3f; + shift = 0; } + + /* Lanes 0 - 3 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); + dword &= ~(mask << 24); + dword &= ~(mask << 16); + dword &= ~(mask << 8); + dword &= ~mask; + dword |= ((delay[3] << shift) & mask) << 24; + dword |= ((delay[2] << shift) & mask) << 16; + dword |= ((delay[1] << shift) & mask) << 8; + dword |= (delay[0] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8), dword); + + /* Lanes 4 - 7 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); + dword &= ~(mask << 24); + dword &= ~(mask << 16); + dword &= ~(mask << 8); + dword &= ~mask; + dword |= ((delay[7] << shift) & mask) << 24; + dword |= ((delay[6] << shift) & mask) << 16; + dword |= ((delay[5] << shift) & mask) << 8; + dword |= (delay[4] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8), dword); + + /* Lane 8 (ECC) */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); + dword &= ~mask; + dword |= (delay[8] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8), dword); } static uint32_t convert_testaddr_and_channel_to_address(struct DCTStatStruc *pDCTstat, uint32_t testaddr, uint8_t channel) @@ -1596,7 +1640,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Retrieve the total delay values from pass 1 of DQS receiver enable training */ read_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - read_read_dqs_timing_control_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); + read_dqs_read_data_timing_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); for (lane = 0; lane < 8; lane++) { current_total_delay[lane] += current_rdqs_total_delay[lane];

1 0

New patch to review for coreboot: parade/ps8640: Clean up
by Patrick Georgi 12 Mar '16

12 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14064 -gerrit commit 1f32b218d9cb60fa427977f23df0864ca7f52bf6 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Mar 12 09:28:59 2016 +0100 parade/ps8640: Clean up Sort out some style issues that were identified by Paul. Change-Id: I9ed946ae613c87234f8c9824eb14b8d28909dfcf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/drivers/parade/ps8640/ps8640.c | 2 +- src/drivers/parade/ps8640/ps8640.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c index 08de2ee..dea7be3 100644 --- a/src/drivers/parade/ps8640/ps8640.c +++ b/src/drivers/parade/ps8640/ps8640.c @@ -25,7 +25,7 @@ int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out) { int ret; u8 edid[EDID_LENGTH * 2]; - u32 edid_size; + int edid_size; i2c_writeb(bus, chip + 2, PAGE2_I2C_BYPASS, EDID_I2C_ADDR | I2C_BYPASS_EN); diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h index 9e483b6..f7b4006 100644 --- a/src/drivers/parade/ps8640/ps8640.h +++ b/src/drivers/parade/ps8640/ps8640.h @@ -42,4 +42,3 @@ enum { int ps8640_init(uint8_t bus, uint8_t chip); int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out); #endif -

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2016