coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch set updated for coreboot: nb/amd/mct_ddr3: Use correct initial UI setting dor DRAM training
by Timothy Pearson 13 Mar '16

13 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14073 -gerrit commit 6cbe4bc128a5a595f566e1b540d8188ec22f25f5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Mar 12 17:17:23 2016 -0600 nb/amd/mct_ddr3: Use correct initial UI setting dor DRAM training Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a did not take into account the default UI setting introduced in change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM instability and occassional failure to boot. Use the correct 1UI value for the modified function semantics. Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 182fab0..15b5ea4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1703,7 +1703,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) - current_read_dqs_delay[internal_lane] = 0x20 << 1; + current_read_dqs_delay[internal_lane] = 0x20; write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); /* Calculate and program MaxRdLatency */

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New patch to review for coreboot: nb/amd/mct_ddr3: Use correct initial UI setting dor DRAM training
by Timothy Pearson 13 Mar '16

13 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14073 -gerrit commit 2e96023e38934e125ed3c542fd78c46d8d6c3a2d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Mar 12 17:17:23 2016 -0600 nb/amd/mct_ddr3: Use correct initial UI setting dor DRAM training Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a did not take into account the default UI setting introduced in change Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM instability and failure to boot. Use the correct 1UI value for the modified function semantics. Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 182fab0..15b5ea4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1703,7 +1703,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) - current_read_dqs_delay[internal_lane] = 0x20 << 1; + current_read_dqs_delay[internal_lane] = 0x20; write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); /* Calculate and program MaxRdLatency */

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Patch merged into coreboot/master: northbridge/intel/i82830: Unify UDELAY selection
by gerrit＠coreboot.org 12 Mar '16

12 Mar '16

the following patch was just integrated into master: commit 63db6142b6198fc3d6660e58228eeedd2eac59bd Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 24 13:25:42 2016 -0800 northbridge/intel/i82830: Unify UDELAY selection Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13783 for details. -gerrit

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New patch to review for coreboot: coreinfo: Pretty print RAM addresses
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14072 -gerrit commit 9fe5e9e2e28ab81b36997a6bab5b16900ddbddce Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 12:17:48 2016 -0800 coreinfo: Pretty print RAM addresses Instead of 500, print 0x00000500 in the ram dump module. Change-Id: Id250bd99f36dad4088ab88953fb371c400b4231b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/ramdump_module.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/coreinfo/ramdump_module.c b/payloads/coreinfo/ramdump_module.c index a0ccc4f..8401a61 100644 --- a/payloads/coreinfo/ramdump_module.c +++ b/payloads/coreinfo/ramdump_module.c @@ -30,7 +30,7 @@ static void dump_ram(WINDOW *win, uint32_t addr, int row, int col) int i, x = 0, y = 0, count = 0; volatile uint8_t *ptr = (void *)(addr); - mvwprintw(win, 0, col + 54, "RAM address: %10x", addr); + mvwprintw(win, 0, col + 54, "RAM address: 0x%08x", addr); /* Dump 256 bytes of RAM. */ for (i = 1; i < 257; i++) {

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New patch to review for coreboot: libpayload: Move MEMMAP_RAM_ONLY to generic options
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14071 -gerrit commit 79f2a78cd88b2b691c73b276328965ccae2f9595 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 12:14:46 2016 -0800 libpayload: Move MEMMAP_RAM_ONLY to generic options MEMMAP_RAM_ONLY is not an architecture specific option, hence move it out of the architecture specific menu. Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/libpayload/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index ef452ac..3c579e6 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -80,6 +80,10 @@ config REMOTEGDB help Enable Remote GDB debugging support. +config MEMMAP_RAM_ONLY + bool "Only consider RAM entries in memory map for further processing" + default n + endmenu menu "Architecture Options" @@ -110,10 +114,6 @@ config ARCH_MIPS endchoice -config MEMMAP_RAM_ONLY - bool "Only consider RAM entries in memory map for further processing" - default n - config MULTIBOOT bool "Multiboot header support" depends on ARCH_X86

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New patch to review for coreboot: libpayload: Drop CONFIG_LP_CHROMEOS
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14070 -gerrit commit 52182cc463c994d5e1ae9a6b117122c17ea572ec Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 12:12:14 2016 -0800 libpayload: Drop CONFIG_LP_CHROMEOS This is adding complexity to the code more than it saves space, plus some of the tables could potentially be interesting outside of the ChromeOS context. Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/libpayload/Kconfig | 6 ------ payloads/libpayload/configs/config.arm64-generic | 1 - payloads/libpayload/configs/config.purin | 1 - payloads/libpayload/configs/config.veyron | 1 - payloads/libpayload/configs/defconfig | 1 - payloads/libpayload/configs/defconfig-arm | 1 - payloads/libpayload/configs/defconfig-mips | 1 - payloads/libpayload/configs/defconfig-tinycurses | 1 - payloads/libpayload/include/sysinfo.h | 6 ------ payloads/libpayload/libc/coreboot.c | 5 ----- 10 files changed, 24 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index e95f31b..ef452ac 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -80,12 +80,6 @@ config REMOTEGDB help Enable Remote GDB debugging support. -config CHROMEOS - bool "ChromeOS specific features" - default n - help - Enable ChromeOS specific features. - endmenu menu "Architecture Options" diff --git a/payloads/libpayload/configs/config.arm64-generic b/payloads/libpayload/configs/config.arm64-generic index cca00b3..a2d596c 100644 --- a/payloads/libpayload/configs/config.arm64-generic +++ b/payloads/libpayload/configs/config.arm64-generic @@ -11,7 +11,6 @@ # CONFIG_LP_DEVELOPER is not set CONFIG_LP_COMPILER_GCC=y # CONFIG_LP_COMPILER_LLVM_CLANG is not set -CONFIG_LP_CHROMEOS=y # # Architecture Options diff --git a/payloads/libpayload/configs/config.purin b/payloads/libpayload/configs/config.purin index adb93b1..c4f225b 100644 --- a/payloads/libpayload/configs/config.purin +++ b/payloads/libpayload/configs/config.purin @@ -12,7 +12,6 @@ CONFIG_LP_GPL=y CONFIG_LP_COMPILER_GCC=y # CONFIG_LP_COMPILER_LLVM_CLANG is not set # CONFIG_LP_REMOTEGDB is not set -CONFIG_LP_CHROMEOS=y # # Architecture Options diff --git a/payloads/libpayload/configs/config.veyron b/payloads/libpayload/configs/config.veyron index aca5817..47d54ea 100644 --- a/payloads/libpayload/configs/config.veyron +++ b/payloads/libpayload/configs/config.veyron @@ -12,7 +12,6 @@ CONFIG_LP_GPL=y CONFIG_LP_COMPILER_GCC=y # CONFIG_LP_COMPILER_LLVM_CLANG is not set # CONFIG_LP_REMOTEGDB is not set -CONFIG_LP_CHROMEOS=y # # Architecture Options diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 1d516f7..53320e7 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -11,7 +11,6 @@ # CONFIG_LP_DEVELOPER is not set CONFIG_LP_COMPILER_GCC=y # CONFIG_LP_COMPILER_LLVM_CLANG is not set -# CONFIG_LP_CHROMEOS is not set # # Architecture Options diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm index fa7e4f6..5b0ebe6 100644 --- a/payloads/libpayload/configs/defconfig-arm +++ b/payloads/libpayload/configs/defconfig-arm @@ -11,7 +11,6 @@ # CONFIG_LP_DEVELOPER is not set CONFIG_LP_COMPILER_GCC=y # CONFIG_LP_COMPILER_LLVM_CLANG is not set -# CONFIG_LP_CHROMEOS is not set # # Architecture Options diff --git a/payloads/libpayload/configs/defconfig-mips b/payloads/libpayload/configs/defconfig-mips index 0b05f87..5b78777 100644 --- a/payloads/libpayload/configs/defconfig-mips +++ b/payloads/libpayload/configs/defconfig-mips @@ -11,7 +11,6 @@ # CONFIG_LP_DEVELOPER is not set CONFIG_LP_COMPILER_GCC=y # CONFIG_LP_COMPILER_LLVM_CLANG is not set -# CONFIG_LP_CHROMEOS is not set # # Architecture Options diff --git a/payloads/libpayload/configs/defconfig-tinycurses b/payloads/libpayload/configs/defconfig-tinycurses index 7e74fb2..ad0a8cf 100644 --- a/payloads/libpayload/configs/defconfig-tinycurses +++ b/payloads/libpayload/configs/defconfig-tinycurses @@ -11,7 +11,6 @@ # CONFIG_LP_DEVELOPER is not set CONFIG_LP_COMPILER_GCC=y # CONFIG_LP_COMPILER_LLVM_CLANG is not set -# CONFIG_LP_CHROMEOS is not set # # Architecture Options diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index b97ae14..2110d88 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -66,10 +66,8 @@ struct sysinfo_t { u32 cmos_range_start; u32 cmos_range_end; u32 cmos_checksum_location; -#if IS_ENABLED(CONFIG_LP_CHROMEOS) u32 vbnv_start; u32 vbnv_size; -#endif char *version; char *extra_version; @@ -86,25 +84,21 @@ struct sysinfo_t { struct cb_framebuffer *framebuffer; -#if IS_ENABLED(CONFIG_LP_CHROMEOS) int num_gpios; struct cb_gpio gpios[SYSINFO_MAX_GPIOS]; int num_macs; struct mac_address macs[SYSINFO_MAX_MACS]; char *serialno; -#endif unsigned long *mbtable; /** Pointer to the multiboot table */ struct cb_header *header; struct cb_mainboard *mainboard; -#if IS_ENABLED(CONFIG_LP_CHROMEOS) void *vboot_handoff; u32 vboot_handoff_size; void *vdat_addr; u32 vdat_size; -#endif #if IS_ENABLED(CONFIG_LP_ARCH_X86) int x86_rom_var_mtrr_index; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 3abd610..7ad8e06 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -78,7 +78,6 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info) info->serial = ((struct cb_serial *)ptr); } -#if IS_ENABLED(CONFIG_LP_CHROMEOS) static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info) { struct lb_range *vbho = (struct lb_range *)ptr; @@ -128,8 +127,6 @@ static void cb_parse_mac_addresses(unsigned char *ptr, info->macs[i] = macs->mac_addrs[i]; } -#endif - static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) { struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; @@ -349,7 +346,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_MAINBOARD: info->mainboard = (struct cb_mainboard *)ptr; break; -#if IS_ENABLED(CONFIG_LP_CHROMEOS) case CB_TAG_GPIO: cb_parse_gpios(ptr, info); break; @@ -368,7 +364,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_SERIALNO: cb_parse_string(ptr, &info->serialno); break; -#endif case CB_TAG_TIMESTAMPS: cb_parse_tstamp(ptr, info); break;

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New patch to review for coreboot: libpayload: Unify defconfigs
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14069 -gerrit commit 4f60d666f0d92000bd70ab7213d7c9a5f9a20732 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 11:51:18 2016 -0800 libpayload: Unify defconfigs Bring defconfig and defconfig-tinycurses in sync, so that defconfig and defconfig-tinycurses only differ in the selection of the curses implementation. Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/libpayload/configs/defconfig | 1 + payloads/libpayload/configs/defconfig-tinycurses | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 37bf50d..1d516f7 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_LP_CURSES=y CONFIG_LP_PDCURSES=y CONFIG_LP_CBFS=y CONFIG_LP_LZMA=y +CONFIG_LP_LZ4=y # # Console Options diff --git a/payloads/libpayload/configs/defconfig-tinycurses b/payloads/libpayload/configs/defconfig-tinycurses index f876903..7e74fb2 100644 --- a/payloads/libpayload/configs/defconfig-tinycurses +++ b/payloads/libpayload/configs/defconfig-tinycurses @@ -21,7 +21,7 @@ CONFIG_LP_ARCH_X86=y # CONFIG_LP_ARCH_ARM64 is not set # CONFIG_LP_ARCH_MIPS is not set # CONFIG_LP_MEMMAP_RAM_ONLY is not set -CONFIG_LP_MULTIBOOT=y +# CONFIG_LP_MULTIBOOT is not set # # Standard Libraries @@ -52,7 +52,7 @@ CONFIG_LP_SERIAL_IOBASE=0x3f8 CONFIG_LP_VIDEO_CONSOLE=y CONFIG_LP_VGA_VIDEO_CONSOLE=y # CONFIG_LP_GEODELX_VIDEO_CONSOLE is not set -# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y CONFIG_LP_PC_KEYBOARD=y CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y # CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set @@ -71,8 +71,18 @@ CONFIG_LP_STORAGE_ATAPI=y CONFIG_LP_STORAGE_AHCI=y CONFIG_LP_STORAGE_AHCI_ONLY_TESTED=y CONFIG_LP_TIMER_RDTSC=y -# CONFIG_LP_USB is not set -# CONFIG_LP_USB_GEN_HUB is not set +CONFIG_LP_USB=y +CONFIG_LP_USB_UHCI=y +CONFIG_LP_USB_OHCI=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y +# CONFIG_LP_USB_XHCI_MTK_QUIRK is not set +CONFIG_LP_USB_HID=y +CONFIG_LP_USB_HUB=y +# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set +CONFIG_LP_USB_MSC=y +CONFIG_LP_USB_GEN_HUB=y +CONFIG_LP_USB_PCI=y # CONFIG_LP_UDC is not set # CONFIG_LP_BIG_ENDIAN is not set CONFIG_LP_LITTLE_ENDIAN=y

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New patch to review for coreboot: libpayload: Make comment into help text
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14068 -gerrit commit 44c89e9f9938b6a82a83967b4bec5960833eab44 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 11:48:44 2016 -0800 libpayload: Make comment into help text Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/libpayload/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 95bd045..e95f31b 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -629,10 +629,12 @@ config LITTLE_ENDIAN default n bool -# Whether the target system has an IO address space. config IO_ADDRESS_SPACE default n bool + help + This option is turned on if the target system has a separate + IO address space. This is typically only the case on x86. source "arch/arm/Kconfig" source "arch/arm64/Kconfig"

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New patch to review for coreboot: coreinfo: Use tinycurses
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14067 -gerrit commit 7b6d8a55c82fd3158a412d532ddc333785eff1e7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 11:47:00 2016 -0800 coreinfo: Use tinycurses When using PDcurses over a serial line, the background of coreinfo is not properly cleared. Hence use tinycurses, which was the only option when coreinfo was developed. Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index b08424b..c166fc4 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -117,7 +117,7 @@ else libpayload: printf "Building libpayload @ $(LIBCONFIG_PATH).\n" $(MAKE) -C $(LIBCONFIG_PATH) distclean - $(MAKE) -C $(LIBCONFIG_PATH) $(LIB_CONFIG) + $(MAKE) -C $(LIBCONFIG_PATH) $(LIB_CONFIG) KBUILD_DEFCONFIG=configs/defconfig-tinycurses $(MAKE) -C $(LIBCONFIG_PATH) DESTDIR=$(shell pwd)/$(LIBPAYLOAD_DIR) install endif

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New patch to review for coreboot: coreinfo: Drop LAR module
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14066 -gerrit commit 672b65f6580e976619d73b6e1edb54eecacbee9e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 23:24:01 2016 -0800 coreinfo: Drop LAR module The Lame ARchiver has been deprecated for about a decade. Let's remove the code. Change-Id: Ia05690ab63c68dd0a76ae1f180cbfa29df1f02ad Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/Kconfig | 8 +-- payloads/coreinfo/Makefile | 6 +- payloads/coreinfo/coreinfo.c | 4 -- payloads/coreinfo/lar_module.c | 140 ----------------------------------------- 4 files changed, 4 insertions(+), 154 deletions(-) diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index f1d1bf9..54d7cb4 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -52,7 +52,7 @@ config PAYLOAD_INFO_DESC config PAYLOAD_INFO_VERSION string "Payload version" - default "0.1" + default "0.2" help The version number of this payload. @@ -98,12 +98,6 @@ config MODULE_RAMDUMP bool "Enable the RAM dump module" default y -config MODULE_LAR - bool "Enable the coreboot v3 LAR module" - help - LAR support must also be enabled in libpayload. - default n - config MODULE_CBFS bool "Enable the coreboot CBFS module" default y diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index c9f5c10..b08424b 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -20,7 +20,7 @@ srck := $(src)/../../util/kconfig obj := $(src)/build objk := $(src)/build/util/kconfig -export KERNELVERSION := 0.1.0 +export KERNELVERSION := 0.2.0 export KCONFIG_AUTOHEADER := $(obj)/config.h export KCONFIG_AUTOCONFIG := $(obj)/auto.conf export KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd @@ -55,8 +55,8 @@ OBJCOPY ?= objcopy INCLUDES = -I$(obj) -include $(LIBPAYLOAD_DIR)/libpayload/include/kconfig.h OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ - nvram_module.o bootlog_module.o ramdump_module.o lar_module.o \ - multiboot_module.o cbfs_module.o coreinfo.o + nvram_module.o bootlog_module.o ramdump_module.o multiboot_module.o \ + cbfs_module.o coreinfo.o OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) TARGET = $(obj)/coreinfo.elf diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index d15a678..5fc1bcc 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -24,7 +24,6 @@ extern struct coreinfo_module multiboot_module; extern struct coreinfo_module nvram_module; extern struct coreinfo_module bootlog_module; extern struct coreinfo_module ramdump_module; -extern struct coreinfo_module lar_module; extern struct coreinfo_module cbfs_module; struct coreinfo_module *system_modules[] = { @@ -52,9 +51,6 @@ struct coreinfo_module *firmware_modules[] = { #if IS_ENABLED(CONFIG_MODULE_BOOTLOG) &bootlog_module, #endif -#if IS_ENABLED(CONFIG_MODULE_LAR) - &lar_module, -#endif #if IS_ENABLED(CONFIG_MODULE_CBFS) &cbfs_module, #endif diff --git a/payloads/coreinfo/lar_module.c b/payloads/coreinfo/lar_module.c deleted file mode 100644 index 2cfd762..0000000 --- a/payloads/coreinfo/lar_module.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * This file is part of the coreinfo project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "coreinfo.h" - -#if IS_ENABLED(CONFIG_MODULE_LAR) - -static struct LAR *lar; -static int lcount, selected; -static char **lnames; -static const char *compression_table[4] = {"none", "LZMA", "NRV2B", "zeroes"}; - -static int lar_module_init(void) -{ - int index = 0; - struct larent *larent; - - lar = openlar(NULL); - - if (lar == NULL) - return 0; - - while ((larent = readlar(lar))) - lcount++; - - lnames = malloc(lcount * sizeof(char *)); - - if (lnames == NULL) - return 0; - - rewindlar(lar); - - while ((larent = readlar(lar))) - lnames[index++] = strdup((const char *) larent->name); - - return 0; -} - -static int lar_module_redraw(WINDOW *win) -{ - int i, row = 2; - struct larstat stat; - - print_module_title(win, "LAR Listing"); - - if (lar == 0) { - mvwprintw(win, 11, 61 / 2, "Bad or missing LAR"); - return 0; - } - - /* Draw a line down the middle. */ - for (i = 2; i < 21; i++) - mvwaddch(win, i, 30, ACS_VLINE); - - /* Draw the names down the left side. */ - for (i = 0; i < lcount; i++) { - if (i == selected) - wattrset(win, COLOR_PAIR(3) | A_BOLD); - else - wattrset(win, COLOR_PAIR(2)); - - mvwprintw(win, 2 + i, 1, "%.25s", lnames[i]); - } - - /* Get the information for the LAR. */ - if (larstat(lar, lnames[selected], &stat)) { - printf("larstat failed\n"); - return 0; - } - - wattrset(win, COLOR_PAIR(2)); - - mvwprintw(win, row++, 32, "Offset: 0x%x", stat.offset); - - if (stat.compression) { - mvwprintw(win, row++, 32, "Compression: %s", - compression_table[stat.compression]); - mvwprintw(win, row++, 32, "Compressed length: %d", stat.len); - mvwprintw(win, row++, 32, "Compressed checksum: 0x%x", - stat.compchecksum); - } - - mvwprintw(win, row++, 32, "Length: %d", stat.reallen); - mvwprintw(win, row++, 32, "Checksum: 0x%x", stat.checksum); - mvwprintw(win, row++, 32, "Load address: 0x%llx", stat.loadaddress); - mvwprintw(win, row++, 32, "Entry point: 0x%llx", stat.entry); - - return 0; -} - -static int lar_module_handle(int key) -{ - int ret = 0; - - if (lar == NULL) - return 0; - - switch (key) { - case KEY_DOWN: - if (selected + 1 < lcount) { - selected++; - ret = 1; - } - break; - case KEY_UP: - if (selected > 0) { - selected--; - ret = 1; - } - break; - } - - return ret; -} - -struct coreinfo_module lar_module = { - .name = "LAR", - .init = lar_module_init, - .redraw = lar_module_redraw, - .handle = lar_module_handle -}; - -#else - -struct coreinfo_module lar_module = { -}; - -#endif

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coreboot-gerrit March 2016