coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch merged into coreboot/master: nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
by gerrit＠coreboot.org 13 Mar '16

13 Mar '16

the following patch was just integrated into master: commit bc5ad1087b571f22181f7d3edc91354c03269fbf Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Mar 12 17:17:23 2016 -0600 nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a did not take into account the default UI setting introduced in change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM instability and occassional failure to boot. Use the correct 1UI value for the modified function semantics. Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14073 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14073 for details. -gerrit

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New patch to review for coreboot: pcengines/apu1: Enable USB overcurrent detection.
by Tobias Diedrich 13 Mar '16

13 Mar '16

Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14084 -gerrit commit 560607e62b242aa30d1a53ef587e416f6cd17377 Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Sun Mar 13 21:19:45 2016 +0100 pcengines/apu1: Enable USB overcurrent detection. The two external USB ports and the internal USB header have overcurrent protection chips with the low-active overcurrent signal connected to the chipset. The power-on default for this register disables the software detection of overcurrent conditions. After setting the register Linux correctly shows the overcurrent condition in the kernel log (tested by shorting the 5v and gnd lines on J14 / the internal USB header): [ 2015.229921] usb usb1-port3: over-current condition [ 2015.449925] usb usb1-port4: over-current condition Simlar for the external ports: [ 256.237916] usb usb1-port1: over-current condition [ 256.458084] usb usb1-port5: over-current condition Note that each signal is shared between two ports: usboc0#: External ports (port1/5) usboc1#: Internal ports (port3/4) Change-Id: I02d498053b8ec61dc206e74a96c4a1dcfd4fae92 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- src/mainboard/pcengines/apu1/mainboard.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index f91e879..f11d94b 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -230,6 +230,36 @@ const char *smbios_mainboard_serial_number(void) return serial; } +/* + * Set up "Over Current Control 1" (reg 0x58) on the first OHCI device. + * The remaining ports on the second device are for mcpie2/sdcard and + * can stay at the power-on default value. + * + * The schematic shows this transposed mapping for the first device: + * chipset port 0 -> port 1 (j12 external 2, usboc0#) + * chipset port 1 -> port 4 (j17 mpcie1) + * chipset port 2 -> port 2 (j14 header row1, usboc1#) + * chipset port 3 -> port 3 (j14 header row2, usboc1#) + * chipset port 4 -> port 0 (j12 external 1. usboc0#) + * + * Register mapping: + * bit0-3: Mapping for HS Port 0 + * bit4-7: Mapping for HS Port 1 + * bit8-11: Mapping for HS Port 2 + * bit12-15: Mapping for HS Port 3 + * bit16-19: Mapping for HS Port 4 + * bit20-31: Reserved (0) + * + * power-on default: 0xfffff + * A value >7 will disable the overcurrent detection. + */ +static void usb_oc_setup(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x12, 0)); + + pci_write_config32(dev, 0x58, 0x011f0); +} + static void mainboard_final(void *chip_info) { u32 mmio_base; @@ -245,6 +275,7 @@ static void mainboard_final(void *chip_info) configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); + usb_oc_setup(); } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: genbuild_h: Fix numeric comparison to remove error
by Martin Roth 13 Mar '16

13 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14080 -gerrit commit 0020fb08052d311b2febcc62c6e31febb4093bc3 Author: Martin Roth <martinroth(a)google.com> Date: Sat Mar 12 20:15:18 2016 -0700 genbuild_h: Fix numeric comparison to remove error Change the comparison of build_timeless from -eq to = This was generating an error if BUILD_TIMELESS wasn't set: util/genbuild_h/genbuild_h.sh: line 27: [: : integer expression expected This wasn't causing the script to fail, and won't even if 'set -e' is added to the script because the error happens inside an 'if' clause, which is specifically excluded from failue on 'set -e'. Change-Id: I6a4e147ece23e83ee682d72db35be9e5d4088c78 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/genbuild_h/genbuild_h.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index d68b867..044d901 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -24,7 +24,7 @@ export TZ=UTC top=`dirname $0`/../.. -if [ "${BUILD_TIMELESS}" -eq 1 ]; then +if [ "${BUILD_TIMELESS}" = "1" ]; then GITREV=Timeless TIMESOURCE="fixed" DATE=0

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New patch to review for coreboot: device/dram/ddr3: fix debug output
by Patrick Rudolph 13 Mar '16

13 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14083 -gerrit commit f1545204e3b99f0b7c662a5a6f122a0cb1080efa Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 13:02:16 2016 +0100 device/dram/ddr3: fix debug output Add missing punctuation and align output. No functionality is changed. Change-Id: Iee4d7a7c0e1070706fb60d7316fad49813963b51 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr3.c | 50 +++++++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index b5658ef..cb5b685 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -137,9 +137,9 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_CRC_ERROR; }; - printram(" Revision: %x\n", spd[1]); - printram(" Type : %x\n", spd[2]); - printram(" Key : %x\n", spd[3]); + printram(" Revision : %x\n", spd[1]); + printram(" Type : %x\n", spd[2]); + printram(" Key : %x\n", spd[3]); reg8 = spd[4]; /* Number of memory banks */ @@ -149,7 +149,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } param = 1 << (val + 3); - printram(" Banks : %u\n", param); + printram(" Banks : %u\n", param); /* SDRAM capacity */ capacity_shift = reg8 & 0x0f; if (capacity_shift > 0x06) { @@ -157,9 +157,9 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } if (capacity_shift < 0x02) { - printram(" Capacity: %u Mb\n", 256 << capacity_shift); + printram(" Capacity : %u Mb\n", 256 << capacity_shift); } else { - printram(" Capacity: %u Gb\n", 1 << (capacity_shift - 2)); + printram(" Capacity : %u Gb\n", 1 << (capacity_shift - 2)); } reg8 = spd[5]; @@ -180,7 +180,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* Module nominal voltage */ reg8 = spd[6]; - printram(" Supported voltages:"); + printram(" Supported voltages :"); if (reg8 & (1 << 2)) { dimm->flags.operable_1_25V = 1; dimm->voltage = 1250; @@ -214,7 +214,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } dimm->width = (4 << val); - printram(" SDRAM width : %u\n", dimm->width); + printram(" SDRAM width : %u\n", dimm->width); /* Memory bus width */ reg8 = spd[8]; @@ -225,7 +225,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } dimm->flags.is_ecc = val ? 1 : 0; - printram(" Bus extension : %u bits\n", val ? 8 : 0); + printram(" Bus extension : %u bits\n", val ? 8 : 0); /* Bus width */ val = reg8 & 0x07; if (val > 3) { @@ -233,7 +233,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } bus_width = 8 << val; - printram(" Bus width : %u\n", bus_width); + printram(" Bus width : %u\n", bus_width); /* We have all the info we need to compute the dimm size */ /* Capacity is 256Mbit multiplied by the power of 2 specified in @@ -282,7 +282,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* SDRAM Optional Features */ reg8 = spd[30]; - printram(" Optional features :"); + printram(" Optional features :"); if (reg8 & 0x80) { dimm->flags.dll_off_mode = 1; printram(" DLL-Off_mode"); @@ -299,7 +299,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* SDRAM Thermal and Refresh Options */ reg8 = spd[31]; - printram(" Thermal features :"); + printram(" Thermal features :"); if (reg8 & 0x80) { dimm->flags.pasr = 1; printram(" PASR"); @@ -326,27 +326,28 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) reg8 = spd[32]; if (reg8 & 0x80) dimm->flags.therm_sensor = 1; - printram(" Thermal sensor : %s\n", + printram(" Thermal sensor : %s\n", dimm->flags.therm_sensor ? "yes" : "no"); /* SDRAM Device Type */ reg8 = spd[33]; - printram(" Standard SDRAM : %s\n", (reg8 & 0x80) ? "no" : "yes"); + printram(" Standard SDRAM : %s\n", (reg8 & 0x80) ? "no" : "yes"); if (spd[63] & 0x01) { dimm->flags.pins_mirrored = 1; - printram(" DIMM Rank1 Address bits mirrored!!!\n"); } + printram(" Rank1 Address bits : %s\n", + (spd[63] & 0x01) ? "mirrored" : "normal"); dimm->reference_card = spd[62] & 0x1f; - printram(" DIMM Reference card %c\n", 'A' + dimm->reference_card); + printram(" DIMM Reference card: %c\n", 'A' + dimm->reference_card); dimm->manufacturer_id = (spd[118] << 8) | spd[117]; - printram(" DIMM Manufacturer ID %x\n", dimm->manufacturer_id); + printram(" Manufacturer ID : %x\n", dimm->manufacturer_id); dimm->part_number[16] = 0; memcpy(dimm->part_number, &spd[128], 16); - printram(" DIMM Part number %s\n", dimm->part_number); + printram(" Part number : %s\n", dimm->part_number); return ret; } @@ -397,7 +398,8 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } - printram(" XMP Profile 1\n"); + + printram(" XMP Profile : 1\n"); xmp = &spd[185]; /* Medium Timebase = @@ -412,7 +414,7 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } - printram(" XMP Profile 2\n"); + printram(" XMP Profile : 2\n"); xmp = &spd[220]; /* Medium Timebase = @@ -422,16 +424,18 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, dimm->dimms_per_channel = ((spd[178] >> 4) & 0x3) + 1; } - printram(" Max DIMMs per channel: %u\n", + + printram(" Max DIMMs/channel : %u\n", dimm->dimms_per_channel); - printram(" XMP Revision: %u.%u\n", spd[179] >> 4, spd[179] & 0xf); + printram(" XMP Revision : %u.%u\n", spd[179] >> 4, spd[179] & 0xf); /* calculate voltage in mV */ dimm->voltage = (xmp[0] & 1) * 50; dimm->voltage += ((xmp[0] >> 1) & 0xf) * 100; dimm->voltage += ((xmp[0] >> 5) & 0x3) * 1000; - printram(" Requested voltage: %u mV\n", dimm->voltage); + + printram(" Requested voltage : %u mV\n", dimm->voltage); /* SDRAM Minimum Cycle Time (tCKmin) */ dimm->tCK = xmp[1] * mtb;

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 13 Mar '16

13 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14082 -gerrit commit a4ea761bfc3219c09bc5edcf953c3db7e7aca0b5 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC16 array to make sure the DIMMs haven't been replaced. In case one of the CRC's doesn't match, start normal RAM training. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I974c5bce70692a706410180c2a512eb071364be0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 76 +++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 21 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0b27fe5..707cf60 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -368,6 +369,9 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } + /* fill in crc for MRC cache */ + ctrl->spd_crc[channel][slot] = spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid dimm->dimm[channel][slot].ranks = 0; @@ -3943,6 +3947,10 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, { int me_uma_size; int cbmem_was_inited; + int fast_boot; + ramctr_timing ctrl; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; dimm_info info; MCHBAR32(0x5f00) |= 1; @@ -3971,32 +3979,57 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - ramctr_timing ctrl; - memset(&ctrl, 0, sizeof (ctrl)); early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); + ctrl_cached = NULL; + } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + } + + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + fast_boot = 1; + + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot &= ctrl_cached->spd_crc[0][0] == + spd_ddr3_calc_crc(spds[0], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[0][1] == + spd_ddr3_calc_crc(spds[1], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[1][0] == + spd_ddr3_calc_crc(spds[2], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[1][1] == + spd_ddr3_calc_crc(spds[3], sizeof(spd_raw_data)); + + if (!fast_boot) + printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); + } else { + fast_boot = 0; } - if (!s3resume) { + + if (fast_boot) { + memcpy(&ctrl, ctrl_cached, sizeof (ctrl)); + printk(BIOS_DEBUG, "Using stored timings. Skipping RAM training.\n"); + } else { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + + printk(BIOS_DEBUG, "No valid stored timings found. Starting RAM training.\n"); + /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &info, &ctrl); @@ -4009,7 +4042,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Set MCU frequency */ dram_freq(&ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(&ctrl); } @@ -4052,7 +4085,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(&ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4090,7 +4123,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, write_controller_mr(&ctrl); - if (!s3resume) { + if (!fast_boot) { channel_test(&ctrl); } @@ -4106,7 +4139,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4116,7 +4149,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ @@ -4124,7 +4157,8 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - fill_smbios17(&info, (1000 << 8) / ctrl.tCK); + if (!fast_boot) + fill_smbios17(&info, (1000 << 8) / ctrl.tCK); } #define HOST_BRIDGE PCI_DEVFN(0, 0)

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 13 Mar '16

13 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14082 -gerrit commit c2e0c74e3d86566ae8ba6ca7c0a2d08d087c007f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC array to make sure the DIMMs haven't been replaced. In case one of the CRCs doesn't match, start RAM training. Should speed up boot time. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Test result: Doesn't work ! Needs to find out why MRC cache is always empty. Change-Id: I974c5bce70692a706410180c2a512eb071364be0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 71 ++++++++++++++++++++--------- 1 file changed, 50 insertions(+), 21 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0b27fe5..39f6f88 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -377,6 +378,7 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, dram_print_spd_ddr3(&dimm->dimm[channel][slot]); dimms++; + ctrl->spd_crc[channel][slot] = spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); ctrl->rank_mirror[channel][slot * 2] = 0; ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->dimm[channel][slot].flags.pins_mirrored; ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; @@ -3943,6 +3945,10 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, { int me_uma_size; int cbmem_was_inited; + int fast_boot; + ramctr_timing ctrl; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; dimm_info info; MCHBAR32(0x5f00) |= 1; @@ -3971,32 +3977,54 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - ramctr_timing ctrl; - memset(&ctrl, 0, sizeof (ctrl)); early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); + ctrl_cached = NULL; + } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + } + + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + fast_boot = 1; + + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot &= ctrl_cached->spd_crc[0][0] == + spd_ddr3_calc_crc(spds[0], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[0][1] == + spd_ddr3_calc_crc(spds[1], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[1][0] == + spd_ddr3_calc_crc(spds[2], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[1][1] == + spd_ddr3_calc_crc(spds[3], sizeof(spd_raw_data)); + } else { + fast_boot = 0; } - if (!s3resume) { + + if (fast_boot) { + memcpy(&ctrl, ctrl_cached, sizeof (ctrl)); + printk(BIOS_DEBUG, "Using stored timings. Skipping RAM training.\n"); + } else { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + + printk(BIOS_DEBUG, "No valid stored timings found. Starting RAM training.\n"); + /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &info, &ctrl); @@ -4009,7 +4037,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Set MCU frequency */ dram_freq(&ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(&ctrl); } @@ -4052,7 +4080,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(&ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4090,7 +4118,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, write_controller_mr(&ctrl); - if (!s3resume) { + if (!fast_boot) { channel_test(&ctrl); } @@ -4106,7 +4134,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4116,7 +4144,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ @@ -4124,7 +4152,8 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - fill_smbios17(&info, (1000 << 8) / ctrl.tCK); + if (!fast_boot) + fill_smbios17(&info, (1000 << 8) / ctrl.tCK); } #define HOST_BRIDGE PCI_DEVFN(0, 0)

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New patch to review for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 13 Mar '16

13 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14082 -gerrit commit 57dccde3e45d6d8b5bcb9f4d3bae42aa2579312f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC array to make sure the DIMMs haven't been replaced. In case one of the CRCs doesn't match, start RAM training. Should speed up boot time. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Test result: Doesn't work ! Needs to find out why MRC cache is always empty. Change-Id: I974c5bce70692a706410180c2a512eb071364be0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 78 ++++++++++++++++++++--------- 1 file changed, 53 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0b27fe5..975b91e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -184,6 +185,7 @@ typedef struct ramctr_timing_st { int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; + dimm_info info; } ramctr_timing; #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) @@ -377,6 +379,7 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, dram_print_spd_ddr3(&dimm->dimm[channel][slot]); dimms++; + ctrl->spd_crc[channel][slot] = spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); ctrl->rank_mirror[channel][slot * 2] = 0; ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->dimm[channel][slot].flags.pins_mirrored; ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; @@ -3943,7 +3946,10 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, { int me_uma_size; int cbmem_was_inited; - dimm_info info; + int fast_boot; + ramctr_timing ctrl; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; MCHBAR32(0x5f00) |= 1; @@ -3971,45 +3977,67 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - ramctr_timing ctrl; - memset(&ctrl, 0, sizeof (ctrl)); early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); + ctrl_cached = NULL; + } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + } + + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + fast_boot = 1; + + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot &= ctrl_cached->spd_crc[0][0] == + spd_ddr3_calc_crc(spds[0], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[0][1] == + spd_ddr3_calc_crc(spds[1], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[1][0] == + spd_ddr3_calc_crc(spds[2], sizeof(spd_raw_data)); + + fast_boot &= ctrl_cached->spd_crc[1][1] == + spd_ddr3_calc_crc(spds[3], sizeof(spd_raw_data)); + } else { + fast_boot = 0; } - if (!s3resume) { + + if (fast_boot) { + memcpy(&ctrl, ctrl_cached, sizeof (ctrl)); + printk(BIOS_DEBUG, "Using stored timings. Skipping RAM training.\n"); + } else { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + + printk(BIOS_DEBUG, "No valid stored timings found. Starting RAM training.\n"); + /* Get DDR3 SPD data */ - dram_find_spds_ddr3(spds, &info, &ctrl); + dram_find_spds_ddr3(spds, &ctrl.info, &ctrl); /* Find fastest common supported parameters */ - dram_find_common_params(&info, &ctrl); + dram_find_common_params(&ctrl.info, &ctrl); - dram_dimm_mapping(&info, &ctrl); + dram_dimm_mapping(&ctrl.info, &ctrl); } /* Set MCU frequency */ dram_freq(&ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(&ctrl); } @@ -4052,7 +4080,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(&ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4090,7 +4118,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, write_controller_mr(&ctrl); - if (!s3resume) { + if (!fast_boot) { channel_test(&ctrl); } @@ -4106,7 +4134,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4116,7 +4144,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ @@ -4124,7 +4152,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - fill_smbios17(&info, (1000 << 8) / ctrl.tCK); + fill_smbios17(&ctrl.info, (1000 << 8) / ctrl.tCK); } #define HOST_BRIDGE PCI_DEVFN(0, 0)

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New patch to review for coreboot: coreinfo: Only update time when it actually changes
by Stefan Reinauer 13 Mar '16

13 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14081 -gerrit commit 1e068d94c5b2241c81086986873d1629eb01538d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 13 00:46:09 2016 -0800 coreinfo: Only update time when it actually changes This makes cursor movements on the serial port a lot more bearable. Change-Id: I898beaaeb44feccf86cb79f5d9217543e67ac4d2 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/coreinfo.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 8a6b3f5..f2a93dc 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -113,6 +113,7 @@ static void print_submenu(struct coreinfo_cat *cat) #if IS_ENABLED(CONFIG_SHOW_DATE_TIME) static void print_time_and_date(void) { + static struct tm old_tm; struct tm tm; while (nvram_updating()) @@ -120,9 +121,13 @@ static void print_time_and_date(void) rtc_read_clock(&tm); - mvwprintw(menuwin, 0, 57, "%02d/%02d/%04d - %02d:%02d:%02d", - tm.tm_mon + 1, tm.tm_mday, 1900 + tm.tm_year, tm.tm_hour, - tm.tm_min, tm.tm_sec); + if (memcmp(&old_tm, &tm, sizeof(old_tm))) + mvwprintw(menuwin, 0, 57, "%02d/%02d/%04d - %02d:%02d:%02d", + tm.tm_mon + 1, tm.tm_mday, 1900 + tm.tm_year, + tm.tm_hour, tm.tm_min, tm.tm_sec); + + old_tm = tm; + wrefresh(menuwin); } #endif @@ -249,7 +254,6 @@ static void loop(void) while (1) { #if IS_ENABLED(CONFIG_SHOW_DATE_TIME) print_time_and_date(); - wrefresh(menuwin); #endif key = getch();

1 0

Patch set updated for coreboot: drivers/pc80: drop Kconfig
by Stefan Reinauer 13 Mar '16

13 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14079 -gerrit commit fe80eb5ce4518918528f6a5ca7ed3688b50b2776 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 17:35:14 2016 -0800 drivers/pc80: drop Kconfig This should be merged into the previous commit. Change-Id: I3bb50c9bcf3bcedcded8c0f51f68e0737117fc2a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/pc80/Kconfig | 1 - src/mainboard/dmp/vortex86ex/romstage.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig deleted file mode 100644 index 4a703b0..0000000 --- a/src/drivers/pc80/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/pc80/tpm/Kconfig diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index d84af32..a6aa59b 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <halt.h> -#include "drivers/pc80/i8254.c" +#include "drivers/pc80/pc/i8254.c" #include <northbridge/dmp/vortex86ex/northbridge.h> #include <southbridge/dmp/vortex86ex/southbridge.h> #include "northbridge/dmp/vortex86ex/raminit.c"

1 0

Patch merged into coreboot/master: coreinfo: Remove the LAR module
by gerrit＠coreboot.org 13 Mar '16

13 Mar '16

the following patch was just integrated into master: commit d43186418a54a1edd8d9887486b73c80007244fa Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Mar 11 17:30:14 2016 +0100 coreinfo: Remove the LAR module Since libpayload's LAR support was dropped in If6e36569cd, this module doesn't compile anymore. Change-Id: I98f25613a1728e94704d9e9ccb65fd6ba33968b9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/14037 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14037 for details. -gerrit

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coreboot-gerrit March 2016