Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13653
-gerrit
commit 1831972eea76a15aa2f2f038d439d41a325437fe
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue Feb 9 17:53:59 2016 -0800
bimgtool: Drop unused targets and variables from Makefile
dep has not been defined (and will hence break the build)
LDFLAGS is not used.
Change-Id: I4f91e1e7a176367aa4e1a1c63a2afc0b3186767e
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
util/bimgtool/Makefile | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/util/bimgtool/Makefile b/util/bimgtool/Makefile
index 3bd0f07..ca4a9d9 100644
--- a/util/bimgtool/Makefile
+++ b/util/bimgtool/Makefile
@@ -6,9 +6,8 @@ CFLAGS += -D_7ZIP_ST
CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
CFLAGS += -Wstrict-aliasing -Wshadow -Werror
-LDFLAGS += -g
-all: dep $(obj)/bimgtool
+all: $(obj)/bimgtool
clean:
rm -f $(obj)/bimgtool
the following patch was just integrated into master:
commit 3968653f25d9c2147f0b74aa4467a555204a4c9b
Author: Ben Gardner <gardner.ben(a)gmail.com>
Date: Thu Jan 14 17:15:37 2016 -0600
soc/fsp_baytrail: Add support for FSP MR 005
Baytrail FSP MR 005 adds two new fields:
AutoSelfRefreshEnable
APTaskTimeoutCnt
Add the device tree definitions.
Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de
Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com>
Reviewed-on: https://review.coreboot.org/12973
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang(a)intel.com>
See https://review.coreboot.org/12973 for details.
-gerrit
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13631
-gerrit
commit ea1e4e204ff9e2e4a1521ff5bf494e2c2c8ce4ef
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Feb 8 07:12:30 2016 -0800
soc/intel/quark: Call FSP SiliconInit
Optionally relocate FSP into DRAM and then call FSP SiliconInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_FSP_ENTRY_POINTS"
* Add "select DISPLAY_HOBS"
* Optionally add "select RELOCATE_FSP_INTO_DRAM"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* FSP entry points are displayed and
* The message "FspSiliconInit returned 0x00000000" is displayed and
* The HOBs are displayed correctly and
* The message "ERROR - Missing one or more required FSP HOBs!" is
not displayed
Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 7 +++++++
src/soc/intel/quark/Makefile.inc | 2 ++
src/soc/intel/quark/chip.c | 33 +++++++++++++++++++++++++++++++++
src/soc/intel/quark/chip.h | 31 +++++++++++++++++++++++++++++++
4 files changed, 73 insertions(+)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 08272f0..aab509a 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -174,6 +174,13 @@ config FSP_ESRAM_LOC
help
The location in ESRAM where a copy of the FSP binary is placed.
+config RELOCATE_FSP_INTO_DRAM
+ bool "Relocate FSP into DRAM"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+ help
+ Relocate the FSP binary into DRAM before the call to SiliconInit.
+
#####
# FSP PDAT binary
# The following options control the FSP platform data binary
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 915360a..e5594be 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -22,10 +22,12 @@ romstage-y += memmap.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
+ramstage-y += chip.c
ramstage-y += memmap.c
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
+CPPFLAGS_common += -I$(src)/soc/intel/quark
CPPFLAGS_common += -I$(src)/soc/intel/quark/include
# Chipset microcode path
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
new file mode 100644
index 0000000..f14dde0
--- /dev/null
+++ b/src/soc/intel/quark/chip.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "chip.h"
+#include <console/console.h>
+#include <fsp/ramstage.h>
+
+static void soc_init(void *chip_info)
+{
+ /* Perform silicon specific init. */
+ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
+ intel_silicon_init();
+ else
+ fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
+}
+
+struct chip_operations soc_intel_quark_ops = {
+ CHIP_NAME("Intel Quark")
+ .init = &soc_init,
+};
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h
new file mode 100644
index 0000000..59c8793
--- /dev/null
+++ b/src/soc/intel/quark/chip.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CHIP_H_
+#define _SOC_CHIP_H_
+
+#include <stdint.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+
+struct soc_intel_quark_config {
+ uint32_t junk;
+};
+
+extern struct chip_operations soc_ops;
+
+#endif
the following patch was just integrated into master:
commit 318ef96af346df886348f622f1cd711ade29011e
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Sun Feb 7 14:48:53 2016 -0800
soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach
FSP MemoryInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_HOBS"
* Add "select DISPLAY_UPD_DATA"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* MemoryInit returns 0 (success) and
* The the message "ERROR - Coreboot's requirements not met by FSP
binary!" is not displayed
Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/13447
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13447 for details.
-gerrit