coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: lumpy: Support native raminit
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13663 -gerrit commit 4d8b64c211797932294c9b7abf000415c98c2ddb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 03:01:37 2016 +0100 lumpy: Support native raminit Change-Id: Id695fb6e759b90cd91bb9760bb4fe2a459480b21 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/samsung/lumpy/Kconfig | 4 - src/mainboard/samsung/lumpy/devicetree.cb | 2 + src/mainboard/samsung/lumpy/romstage.c | 128 +++++++++++++++++++----------- 3 files changed, 83 insertions(+), 51 deletions(-) diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index d0f3844..e144545 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -21,10 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select HAVE_MRC -config USE_NATIVE_RAMINIT - bool - default n - config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 6bf571a..f73e603 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -14,6 +14,8 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms + register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 791afe9..3e3bd9a 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -31,6 +31,7 @@ #include <tpm.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -112,53 +113,9 @@ void rcba_config(void) RCBA32(FD) = reg32; } -void mainboard_fill_pei_data(struct pei_data *pei_data) +uint8_t *locate_spd(void) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, - .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1333, - .usb_port_config = { - { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ - { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ - { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ - { 0, 0, 0x0000 }, /* P4: Empty */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */ - { 0, 4, 0x0000 }, /* P9: Empty */ - { 0, 4, 0x0000 }, /* P10: Empty */ - { 1, 4, 0x0040 }, /* P11: Camera (no OC) */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, - }; - *pei_data = pei_data_template; - typedef const uint8_t spd_blob[256]; + typedef const uint8_t spd_blob[256]; spd_blob *spd_data; size_t spd_file_len; @@ -207,9 +164,86 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) if (spd_file_len < (spd_index + 1) * 256) die("Missing SPD data."); // leave onboard dimm address at f0, and copy spd data there. - memcpy(pei_data->spd_data[0], spd_data[spd_index], 256); + return spd_data[spd_index]; } +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pei_data_template = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, + .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, + .ec_present = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1333, + .usb_port_config = { + { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ + { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ + { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ + { 0, 0, 0x0000 }, /* P4: Empty */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */ + { 0, 4, 0x0000 }, /* P9: Empty */ + { 0, 4, 0x0000 }, /* P10: Empty */ + { 1, 4, 0x0040 }, /* P11: Camera (no OC) */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ + }, + }; + *pei_data = pei_data_template; + // leave onboard dimm address at f0, and copy spd data there. + memcpy(pei_data->spd_data[0], locate_spd(), 256); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 1, 1, 0 }, /* P0: Port 0 (OC0) */ + { 1, 1, 1 }, /* P1: Port 1 (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 0, 0, -1 }, /* P4: Empty */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */ + { 0, 0, -1 }, /* P9: Empty */ + { 0, 0, -1 }, /* P10: Empty */ + { 1, 0, -1 }, /* P11: Camera (no OC) */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd) +{ + memcpy(&spd[0], locate_spd(), 128); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ +}; + void mainboard_early_init(int s3resume) { init_bootmode_straps();

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Patch set updated for coreboot: stumpy: Add native raminit support
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13662 -gerrit commit 526f782c72f1397ac872f537fc16beb238171306 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 02:52:42 2016 +0100 stumpy: Add native raminit support Change-Id: Ibbb056ae209a16533757af925c8c833c94803834 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/samsung/stumpy/Kconfig | 4 ---- src/mainboard/samsung/stumpy/devicetree.cb | 2 ++ src/mainboard/samsung/stumpy/romstage.c | 25 +++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 50b1625..874dd6c 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -18,10 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MRC select INTEL_INT15 -config USE_NATIVE_RAMINIT - bool - default n - config CHROMEOS select PHYSICAL_REC_SWITCH select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index df91a72..901711b 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 87528af..ab1cb76 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -31,6 +31,7 @@ #include <superio/ite/it8772f/it8772f.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -203,6 +204,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; } +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 1, 1, 0 }, /* P0: Front port (OC0) */ + { 1, 0, 1 }, /* P1: Back port (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 1, 1, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, 4 }, /* P8: Back port (OC4) */ + { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, 0, 6 }, /* P12: Back port (OC6) */ + { 1, 0, 5 }, /* P13: Back port (OC5) */ +}; + void mainboard_early_init(int s3resume) { init_bootmode_straps();

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Patch set updated for coreboot: Fix butterfly usb map.
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13661 -gerrit commit cd4f9284d49ece043480c13f231400c78dcf462a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 02:51:48 2016 +0100 Fix butterfly usb map. This was copied from mrc structure despite them having fields in different order. Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/romstage.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 9a3157d..a5aa793 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -108,21 +108,21 @@ void rcba_config(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled usb oc pin length */ - { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ - { 0, 0, 0x0000 }, /* P3: Empty */ - { 0, 0, 0x0000 }, /* P4: Empty */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 0, 4, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ - { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ + /* enabled power usb oc pin */ + { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, 0, -1 }, /* P2: Camera (no OC) */ + { 0, 0, -1 }, /* P3: Empty */ + { 0, 0, -1 }, /* P4: Empty */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 0, 0, -1 }, /* P8: Empty */ + { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ + { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ }; void mainboard_get_spd(spd_raw_data *spd) {

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Patch set updated for coreboot: stout: Support native raminit
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13660 -gerrit commit 4848d744d8fd8aed1f5a4c0355bc5c866ec0abf1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 02:42:16 2016 +0100 stout: Support native raminit Change-Id: If64607d40a64ada8cfe4c3ad054be9d6571fc221 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/stout/Kconfig | 4 ---- src/mainboard/google/stout/devicetree.cb | 2 ++ src/mainboard/google/stout/romstage.c | 25 +++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 9dc2649..fdf462b 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 -config USE_NATIVE_RAMINIT - bool - default n - config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 1992664..7563bff 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -14,6 +14,8 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms + register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index d7046a3..aef06df 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -28,6 +28,7 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -137,6 +138,12 @@ static void early_ec_init(void) ec_write_cmd(EC_CMD_WARM_RESET); } } + +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} void mainboard_fill_pei_data(struct pei_data *pei_data) { @@ -209,3 +216,21 @@ int mainboard_should_reset_usb(int s3resume) void mainboard_config_superio(void) { } + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled usb oc pin length */ + {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, /* P2: Empty */ + {1, 0, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, /* P6: Empty */ + {0, 0, 0}, /* P7: Empty */ + {0, 0, 0}, /* P8: Empty */ + {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, /* P10: Empty */ + {0, 0, 0}, /* P11: Empty */ + {0, 0, 0}, /* P12: Empty */ + {1, 0, -1}, /* P13: Bluetooth (no OC) */ +};

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Patch set updated for coreboot: emeraldlake2: Support native raminit
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13666 -gerrit commit ead63080b5ab212f0e50babe75f8bc0266f4a40e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 03:09:46 2016 +0100 emeraldlake2: Support native raminit Change-Id: I808a739c91cb52782db46fd4897b6b913224d93f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/intel/emeraldlake2/Kconfig | 4 ---- src/mainboard/intel/emeraldlake2/romstage.c | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index ae233ab..90b40ac 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -13,10 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 #select MAINBOARD_HAS_CHROMEOS -config USE_NATIVE_RAMINIT - bool - default n - config CHROMEOS #select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 8528bff..1d6e699 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -154,6 +154,29 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; } +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 1, 0, 0 }, /* P0: Front port (OC0) */ + { 1, 0, 1 }, /* P1: Back port (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 1, 0, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, 4 }, /* P8: Back port (OC4) */ + { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, 0, 6 }, /* P12: Back port (OC6) */ + { 1, 0, 5 }, /* P13: Back port (OC5) */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + void mainboard_early_init(int s3resume) { }

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Patch set updated for coreboot: ktqm77: Support native raminit
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13664 -gerrit commit b8688e61e4fa7d5d75636f21581e958033363590 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 03:03:41 2016 +0100 ktqm77: Support native raminit Change-Id: Ic90d3aa714e5681c5021e2b05275d57dce428de0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/kontron/ktqm77/Kconfig | 4 ---- src/mainboard/kontron/ktqm77/romstage.c | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index ba5e3da..485978c 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -14,10 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_VMX select HAVE_MRC -config USE_NATIVE_RAMINIT - bool - default n - config MAINBOARD_DIR string default kontron/ktqm77 diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 8f3f900..82ac601 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -153,6 +153,29 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; } +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ + { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ + { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ + { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */ + { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */ + { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */ + { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */ + { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */ + { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + void mainboard_early_init(int s3resume) { /* Enable PEG10 (1x16) */

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Patch set updated for coreboot: link: Support native raminit
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13665 -gerrit commit 9362d79c79460c39f56ea554093cfac9ef3a3110 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 03:07:42 2016 +0100 link: Support native raminit Change-Id: I95173c06d334a340fa2157511a1d69f38877b264 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/link/Kconfig | 4 ---- src/mainboard/google/link/devicetree.cb | 2 ++ src/mainboard/google/link/romstage.c | 34 +++++++++++++++++++++++++++------ 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index c9bfa2e..ac06a62 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT -config USE_NATIVE_RAMINIT - bool - default n - config CHROMEOS select CHROMEOS_VBNV_CMOS select LID_SWITCH diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 5ac8d6b..437b3cb 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x00000200" register "gpu_pch_backlight" = "0x04000000" + register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 11afd4f..a975674 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -114,7 +114,7 @@ void rcba_config(void) RCBA32(FD) = reg32; } -static void copy_spd(struct pei_data *peid) +static uint8 *locate_spd(void) { const int gpio_vector[] = {41, 42, 43, 10, -1}; char *spd_file; @@ -135,10 +135,8 @@ static void copy_spd(struct pei_data *peid) if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); - memcpy(peid->spd_data[0], - spd_file + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); + return spd_file + + spd_index * sizeof(peid->spd_data[0]); } void mainboard_fill_pei_data(struct pei_data *pei_data) @@ -189,7 +187,31 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; - copy_spd(pei_data); + memcpy(peid->spd_data[0], + locate_spd(), + sizeof(peid->spd_data[0])); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 0, 0, -1 }, /* P0: Empty */ + { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ + { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ + { 1, 0, -1 }, /* P3: SDCARD (no OC) */ + { 0, 0, -1 }, /* P4: Empty */ + { 1, 0, -1 }, /* P5: WWAN (no OC) */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, -1 }, /* P8: Camera (no OC) */ + { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ + { 0, 0, -1 }, /* P10: Empty */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + memcpy(&spd[0], locate_spd(), 128); } void mainboard_early_init(int s3resume)

1 0

Patch set updated for coreboot: Make butterfly configurable MRC vs non-MRC.
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13659 -gerrit commit eb6c522f39a5f09f18fb48ffd11651b1fc0a9220 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 02:39:51 2016 +0100 Make butterfly configurable MRC vs non-MRC. Change-Id: I7b1e046d5895750d350dfa851a6f51c3a3a1613f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/Kconfig | 1 - src/mainboard/google/butterfly/romstage.c | 52 +++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 1fc9c0a..320981a 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_ENE_KB3940Q select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 65a294c..3992d0b 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -135,3 +135,55 @@ void mainboard_early_init(int s3resume) { void mainboard_config_superio(void) { } + + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pei_data_template = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .ddr3lv_support = 0, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* enabled usb oc pin length */ + { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ + { 0, 0, 0x0000 }, /* P3: Empty */ + { 0, 0, 0x0000 }, /* P4: Empty */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 0, 4, 0x0000 }, /* P8: Empty */ + { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ + { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ + }, + .ddr_refresh_rate_config = 2, /* Force double refresh rate */ + }; + *pei_data = pei_data_template; +}

1 0

Patch set updated for coreboot: Make MRC vs native a config rather than making a separate chipset for it.
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13658 -gerrit commit 0eeb6896b1ad86aff8018fee68cbfdd60ebf4cf0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 02:36:04 2016 +0100 Make MRC vs native a config rather than making a separate chipset for it. Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 7 +++--- src/cpu/intel/Makefile.inc | 2 -- src/mainboard/apple/macbookair4_2/Kconfig | 1 + src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 1 + src/mainboard/gigabyte/ga-b75m-d3v/Kconfig | 1 + src/mainboard/google/butterfly/Kconfig | 1 + src/mainboard/google/link/Kconfig | 6 +++++- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/parrot/devicetree.cb | 2 ++ src/mainboard/google/parrot/romstage.c | 25 +++++++++++++++++++++ src/mainboard/google/stout/Kconfig | 6 +++++- src/mainboard/intel/emeraldlake2/Kconfig | 6 +++++- src/mainboard/kontron/ktqm77/Kconfig | 6 +++++- src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t530/Kconfig | 1 + src/mainboard/lenovo/x220/Kconfig | 1 + src/mainboard/lenovo/x230/Kconfig | 1 + src/mainboard/samsung/lumpy/Kconfig | 6 +++++- src/mainboard/samsung/stumpy/Kconfig | 6 +++++- src/northbridge/intel/sandybridge/Kconfig | 30 ++++++++++---------------- src/northbridge/intel/sandybridge/Makefile.inc | 14 ++++++------ src/northbridge/intel/sandybridge/romstage.c | 3 +-- src/southbridge/intel/bd82x6x/Makefile.inc | 9 ++++---- src/southbridge/intel/bd82x6x/usb_ehci.c | 4 ++-- util/autoport/sandybridge.go | 1 + util/board_status/to-wiki/towiki.sh | 4 ++-- 28 files changed, 100 insertions(+), 49 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 35acad4..fdc4dff 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -253,8 +253,8 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config FLASHMAP_OFFSET hex "Flash Map Offset" - default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC - default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE + default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE default CBFS_SIZE if !ARCH_X86 default 0 help @@ -380,8 +380,7 @@ config CBFS_SIZE hex "Size of CBFS filesystem in ROM" default 0x100000 if HAVE_INTEL_FIRMWARE || \ NORTHBRIDGE_INTEL_X4X || \ - NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \ - NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \ + NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IVYBRIDGE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \ SOC_INTEL_BROADWELL diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 1234588..bd39039 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -20,9 +20,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 6e47a7b..c919481 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_EDID select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SANDYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 8a53bef..7ca0b5d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_X86 select CPU_INTEL_SOCKET_LGA1155 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig index ede8021..3caf155 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_X86 select CPU_INTEL_SOCKET_LGA1155 select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 320981a..1fc9c0a 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_ENE_KB3940Q select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 2d9a9de..c9bfa2e 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC @@ -16,6 +16,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT +config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS select CHROMEOS_VBNV_CMOS select LID_SWITCH diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index e9b55a4..56ebf86 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 0a54566..eacfe57 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x000001d4" register "gpu_pch_backlight" = "0x03aa0000" + register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 030f7c4..5897d13 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -28,6 +28,7 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -158,6 +159,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; } +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 0, 0, -1 }, /* P0: Empty */ + { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ + { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ + { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ + { 0, 0, -1 }, /* P4: Empty */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ + { 0, 0, -1 }, /* P9: Empty */ + { 1, 0, -1 }, /* P10: Camera (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + void mainboard_config_superio(void) { } diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 94229c4..9dc2649 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 select BOARD_ROMSIZE_KB_8192 @@ -16,6 +16,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 +config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 1d63e76..ae233ab 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -3,7 +3,7 @@ if BOARD_INTEL_EMERALDLAKE2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_SIO1007 select BOARD_ROMSIZE_KB_8192 @@ -13,6 +13,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 #select MAINBOARD_HAS_CHROMEOS +config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS #select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 9dc75cc..ba5e3da 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -3,7 +3,7 @@ if BOARD_KONTRON_KTQM77 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_WINBOND_W83627DHG select EC_KONTRON_IT8516E @@ -14,6 +14,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_VMX select HAVE_MRC +config USE_NATIVE_RAMINIT + bool + default n + config MAINBOARD_DIR string default kontron/ktqm77 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 65d37a7..27b3afc 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 6e257dd..000b156 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index df7c2db..edf2868 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 7b4ca7a..427794b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 02b9873..b7c49aa 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 1d336eb..2078cf0 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index ac19be5..d0f3844 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 # LPC47N207 selected for external LPC card @@ -21,6 +21,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select HAVE_MRC +config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index d4b8cc2..50b1625 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F # LPC47N207 selected for external LPC card @@ -18,6 +18,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MRC select INTEL_INT15 +config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS select PHYSICAL_REC_SWITCH select CHROMEOS_VBNV_CMOS diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 3e517b1..fd5e0a1 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -13,12 +13,6 @@ ## GNU General Public License for more details. ## -config NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC - bool - select MMCONF_SUPPORT - select MMCONF_SUPPORT_DEFAULT - select CPU_INTEL_MODEL_206AX - select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_SANDYBRIDGE bool @@ -28,13 +22,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI -config NORTHBRIDGE_INTEL_IVYBRIDGE_MRC - bool - select MMCONF_SUPPORT - select MMCONF_SUPPORT_DEFAULT - select CPU_INTEL_MODEL_306AX - select INTEL_GMA_ACPI - config NORTHBRIDGE_INTEL_IVYBRIDGE bool select MMCONF_SUPPORT @@ -43,7 +30,14 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI -if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE +if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE + +config USE_NATIVE_RAMINIT + bool "Use native raminit" + default y + help + Select if you want to use coreboot implementation of raminit rather than + System Agent/MRC.bin. You should answer Y. config VGA_BIOS_ID string @@ -68,10 +62,8 @@ config MRC_CACHE_SIZE config DCACHE_RAM_BASE hex - default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC - default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC - default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE - default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE + default 0xff7e0000 if !USE_NATIVE_RAMINIT + default 0xfefe0000 if USE_NATIVE_RAMINIT config DCACHE_RAM_SIZE hex @@ -87,7 +79,7 @@ config DCACHE_RAM_MRC_VAR_SIZE config HAVE_MRC bool "Add a System Agent binary" - depends on !NORTHBRIDGE_INTEL_IVYBRIDGE && !NORTHBRIDGE_INTEL_SANDYBRIDGE + depends on !USE_NATIVE_RAMINIT help Select this option to add a System Agent binary to the resulting coreboot image. diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 90abe4d..7a3c498 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) ramstage-y += ram_calc.c ramstage-y += northbridge.c @@ -25,12 +25,12 @@ ramstage-y += acpi.c ramstage-y += mrccache.c romstage-y += ram_calc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += raminit_mrc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += raminit_mrc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ../../../device/dram/ddr3.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ../../../device/dram/ddr3.c +ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +romstage-y += raminit.c +romstage-y += ../../../device/dram/ddr3.c +else +romstage-y += raminit_mrc.c +endif romstage-y += romstage.c romstage-y += mrccache.c romstage-y += iommu.c diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 04db608..7b367c5 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -70,8 +70,7 @@ void main(unsigned long bist) mainboard_config_superio(); /* USB is inited in MRC if MRC is used. */ - if (!(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC - || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC)) { + if (CONFIG_USE_NATIVE_RAMINIT) { early_usb_init(mainboard_usb_ports); } diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index a8dd7be..c85151c 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -46,10 +46,11 @@ romstage-y += reset.c romstage-y += early_spi.c early_pch_common.c romstage-y += early_rcba.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += early_me_mrc.c early_usb_mrc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += early_me_mrc.c early_usb_mrc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_thermal.c early_pch.c early_me.c early_usb.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_thermal.c early_pch.c early_me.c early_usb.c +ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c +else +romstage-y += early_me_mrc.c early_usb_mrc.c +endif ramstage-y += madt.c diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index b7cd5f0..c0cb1a9 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -35,7 +35,7 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) +#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) pci_write_config32(dev, 0x84, 0x930c8811); pci_write_config32(dev, 0x88, 0x24000d30); pci_write_config32(dev, 0xf4, 0x80408588); @@ -50,7 +50,7 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) +#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) struct resource *res; u8 access_cntl; diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 191c69f..080cc23 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -119,6 +119,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { KconfigBool["INTEL_EDID"] = true KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true + KconfigBool["USE_NATIVE_RAMINIT"] = true KconfigBool["INTEL_INT15"] = true KconfigBool["HAVE_ACPI_TABLES"] = true KconfigBool["HAVE_ACPI_RESUME"] = true diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 922e470..85334ef 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -326,9 +326,9 @@ EOF case $northbridge in INTEL_HASWELL) cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7";; - INTEL_IVYBRIDGE|INTEL_IVYBRIDGE_MRC|INTEL_FSP_IVYBRIDGE) + INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE) cpu_nice="Intel® 3rd Gen (Ivybridge) Core i3/i5/i7";; - INTEL_SANDYBRIDGE|INTEL_SANDYBRIDGE_MRC) + INTEL_SANDYBRIDGE) cpu_nice="Intel® 2nd Gen (Sandybridge) Core i3/i5/i7";; *) cpu_nice="$northbridge";;

1 0

Patch set updated for coreboot: Move gpio.h to gpio.c on sandy and ivy.
by Vladimir Serbinenko 09 Feb '16

09 Feb '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13657 -gerrit commit eb2915ce72e7fc538a60d0d874158f0997c970e4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 10 01:43:08 2016 +0100 Move gpio.h to gpio.c on sandy and ivy. Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/link/Makefile.inc | 1 + src/mainboard/google/link/gpio.c | 119 +++++++++ src/mainboard/google/link/gpio.h | 119 --------- src/mainboard/google/link/romstage.c | 2 - src/mainboard/google/parrot/Makefile.inc | 1 + src/mainboard/google/parrot/gpio.c | 275 +++++++++++++++++++++ src/mainboard/google/parrot/gpio.h | 275 --------------------- src/mainboard/google/parrot/romstage.c | 2 - src/mainboard/google/stout/Makefile.inc | 1 + src/mainboard/google/stout/gpio.c | 288 ++++++++++++++++++++++ src/mainboard/google/stout/gpio.h | 288 ---------------------- src/mainboard/google/stout/romstage.c | 2 - src/mainboard/intel/emeraldlake2/Makefile.inc | 1 + src/mainboard/intel/emeraldlake2/gpio.c | 102 ++++++++ src/mainboard/intel/emeraldlake2/gpio.h | 102 -------- src/mainboard/intel/emeraldlake2/romstage.c | 2 - src/mainboard/kontron/ktqm77/gpio.c | 299 +++++++++++++++++++++++ src/mainboard/kontron/ktqm77/gpio.h | 299 ----------------------- src/mainboard/kontron/ktqm77/romstage.c | 2 - src/mainboard/samsung/lumpy/Makefile.inc | 1 + src/mainboard/samsung/lumpy/gpio.c | 332 ++++++++++++++++++++++++++ src/mainboard/samsung/lumpy/gpio.h | 332 -------------------------- src/mainboard/samsung/lumpy/romstage.c | 2 - src/mainboard/samsung/stumpy/Makefile.inc | 1 + src/mainboard/samsung/stumpy/gpio.c | 306 ++++++++++++++++++++++++ src/mainboard/samsung/stumpy/gpio.h | 306 ------------------------ src/mainboard/samsung/stumpy/romstage.c | 2 - 27 files changed, 1727 insertions(+), 1735 deletions(-) diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index c366b08..b79e4d3 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -42,3 +42,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := spd +romstage-y += gpio.c diff --git a/src/mainboard/google/link/gpio.c b/src/mainboard/google/link/gpio.c new file mode 100644 index 0000000..ea6110e --- /dev/null +++ b/src/mainboard/google/link/gpio.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LINK_GPIO_H +#define LINK_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ + .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ + .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ + .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ + .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ + .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ + .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ + .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ + .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ + .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ + .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio36 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h deleted file mode 100644 index ea6110e..0000000 --- a/src/mainboard/google/link/gpio.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LINK_GPIO_H -#define LINK_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ - .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ - .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ - .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ - .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ - .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ - .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ - .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ - .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ - .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ - .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ - .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ - .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ - .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio28 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio1 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio12 = GPIO_INVERT, - .gpio14 = GPIO_INVERT, - .gpio15 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ - .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ - .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ - .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio36 = GPIO_DIR_OUTPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio36 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f40ba5..11afd4f 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -30,12 +30,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #include <tpm.h> #include <cbfs.h> diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 0d6ef2e..78e5b98 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -17,3 +17,4 @@ ramstage-y += ec.c romstage-y += chromeos.c ramstage-y += chromeos.c +romstage-y += gpio.c diff --git a/src/mainboard/google/parrot/gpio.c b/src/mainboard/google/parrot/gpio.c new file mode 100644 index 0000000..c3e3e2f --- /dev/null +++ b/src/mainboard/google/parrot/gpio.c @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PARROT_GPIO_H +#define PARROT_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NONE, /* NOT USED */ + .gpio1 = GPIO_MODE_NONE, /* NOT USED */ + .gpio2 = GPIO_MODE_NATIVE, /* NOT USED / PIRQE# */ + .gpio3 = GPIO_MODE_NONE, /* NOT USED / PIRQ#F */ + .gpio4 = GPIO_MODE_NONE, /* NOT USED / PIRQG# */ + .gpio5 = GPIO_MODE_NONE, /* NOT USED / PIRQH# */ + .gpio6 = GPIO_MODE_NONE, /* NOT USED / FAN TACH2 */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC SMI# */ + .gpio9 = GPIO_MODE_NATIVE, /* NOT USED / OC5# USB */ + .gpio10 = GPIO_MODE_NATIVE, /* NOT USED / OC6# USB */ + .gpio11 = GPIO_MODE_NONE, /* NOT USED / SMB_ALERT*/ + .gpio12 = GPIO_MODE_GPIO, /* Track Pad IRQ / LAN_PHY_PWR_CTRL / SMB_ALERT */ + .gpio13 = GPIO_MODE_NONE, /* NOT USED / HDA_DOCK_RST */ + .gpio14 = GPIO_MODE_NATIVE, /* NOT USED / OC7# USB */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT (INPUT to PantherPoint) */ + .gpio16 = GPIO_MODE_NONE, /* NOT USED / SATA4GP */ + .gpio17 = GPIO_MODE_GPIO, /* DEV MODE */ + .gpio18 = GPIO_MODE_NATIVE, /* PCIECLKRQ1# */ + .gpio19 = GPIO_MODE_NONE, /* BIOS BOOT STRAP (NOT USED)/ SATA1GP */ + .gpio20 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ2# */ + .gpio21 = GPIO_MODE_NONE, /* NOT USED / SATA0GP */ + .gpio22 = GPIO_MODE_NONE, /* NOT USED */ + .gpio23 = GPIO_MODE_NONE, /* NOT USED */ + .gpio24 = GPIO_MODE_NONE, /* NOT USED / MEM_LED */ + .gpio25 = GPIO_MODE_NATIVE, /* PCIECLKRQ3# */ + .gpio26 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ4# */ + .gpio27 = GPIO_MODE_NONE, /* S4,S5 WAKE? */ + .gpio28 = GPIO_MODE_NONE, /* On-Die PLL Voltage Regulator */ + .gpio29 = GPIO_MODE_NONE, /* NOT USED / SLP_LAN# */ + .gpio30 = GPIO_MODE_NATIVE, /* SUS_WARN# */ + .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_LOW, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_LOW, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX0 */ + .gpio65 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX1 */ + .gpio66 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX2 */ + .gpio67 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX3 */ + .gpio68 = GPIO_MODE_NONE, /* NOT USED / FAN TACK4 */ + .gpio69 = GPIO_MODE_GPIO, /* REC_MODE_L / FAN TACK5 */ + .gpio70 = GPIO_MODE_GPIO, /* SPI_WP1#_RPCH / FAN TACK7 */ + .gpio71 = GPIO_MODE_GPIO, /* LVDS/eDP / FAN TACK8 */ + .gpio72 = GPIO_MODE_NONE, /* NOT USED / BATLOW# */ + .gpio73 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ0#*/ + .gpio74 = GPIO_MODE_NONE, /* NOT USED / SML1ALERT# /PCHHOT# */ + .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_LOW, + .gpio75 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h deleted file mode 100644 index c3e3e2f..0000000 --- a/src/mainboard/google/parrot/gpio.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef PARROT_GPIO_H -#define PARROT_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_NONE, /* NOT USED */ - .gpio1 = GPIO_MODE_NONE, /* NOT USED */ - .gpio2 = GPIO_MODE_NATIVE, /* NOT USED / PIRQE# */ - .gpio3 = GPIO_MODE_NONE, /* NOT USED / PIRQ#F */ - .gpio4 = GPIO_MODE_NONE, /* NOT USED / PIRQG# */ - .gpio5 = GPIO_MODE_NONE, /* NOT USED / PIRQH# */ - .gpio6 = GPIO_MODE_NONE, /* NOT USED / FAN TACH2 */ - .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ - .gpio8 = GPIO_MODE_GPIO, /* EC SMI# */ - .gpio9 = GPIO_MODE_NATIVE, /* NOT USED / OC5# USB */ - .gpio10 = GPIO_MODE_NATIVE, /* NOT USED / OC6# USB */ - .gpio11 = GPIO_MODE_NONE, /* NOT USED / SMB_ALERT*/ - .gpio12 = GPIO_MODE_GPIO, /* Track Pad IRQ / LAN_PHY_PWR_CTRL / SMB_ALERT */ - .gpio13 = GPIO_MODE_NONE, /* NOT USED / HDA_DOCK_RST */ - .gpio14 = GPIO_MODE_NATIVE, /* NOT USED / OC7# USB */ - .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT (INPUT to PantherPoint) */ - .gpio16 = GPIO_MODE_NONE, /* NOT USED / SATA4GP */ - .gpio17 = GPIO_MODE_GPIO, /* DEV MODE */ - .gpio18 = GPIO_MODE_NATIVE, /* PCIECLKRQ1# */ - .gpio19 = GPIO_MODE_NONE, /* BIOS BOOT STRAP (NOT USED)/ SATA1GP */ - .gpio20 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ2# */ - .gpio21 = GPIO_MODE_NONE, /* NOT USED / SATA0GP */ - .gpio22 = GPIO_MODE_NONE, /* NOT USED */ - .gpio23 = GPIO_MODE_NONE, /* NOT USED */ - .gpio24 = GPIO_MODE_NONE, /* NOT USED / MEM_LED */ - .gpio25 = GPIO_MODE_NATIVE, /* PCIECLKRQ3# */ - .gpio26 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ4# */ - .gpio27 = GPIO_MODE_NONE, /* S4,S5 WAKE? */ - .gpio28 = GPIO_MODE_NONE, /* On-Die PLL Voltage Regulator */ - .gpio29 = GPIO_MODE_NONE, /* NOT USED / SLP_LAN# */ - .gpio30 = GPIO_MODE_NATIVE, /* SUS_WARN# */ - .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_OUTPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_LOW, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_LOW, - .gpio9 = GPIO_LEVEL_LOW, - .gpio10 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_LOW, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - .gpio14 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_LOW, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_LOW, - .gpio23 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_LOW, - .gpio30 = GPIO_LEVEL_LOW, - .gpio31 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio12 = GPIO_INVERT, - .gpio15 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ - .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ - .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ - .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_INPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio47 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_INPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_INPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_INPUT, - .gpio56 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_INPUT, - .gpio61 = GPIO_DIR_INPUT, - .gpio62 = GPIO_DIR_INPUT, - .gpio63 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_LOW, - .gpio41 = GPIO_LEVEL_LOW, - .gpio42 = GPIO_LEVEL_LOW, - .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_LOW, - .gpio45 = GPIO_LEVEL_LOW, - .gpio46 = GPIO_LEVEL_LOW, - .gpio47 = GPIO_LEVEL_LOW, - .gpio48 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_LOW, - .gpio50 = GPIO_LEVEL_LOW, - .gpio51 = GPIO_LEVEL_LOW, - .gpio52 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_LOW, - .gpio54 = GPIO_LEVEL_LOW, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_LOW, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_LOW, - .gpio59 = GPIO_LEVEL_LOW, - .gpio60 = GPIO_LEVEL_LOW, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX0 */ - .gpio65 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX1 */ - .gpio66 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX2 */ - .gpio67 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX3 */ - .gpio68 = GPIO_MODE_NONE, /* NOT USED / FAN TACK4 */ - .gpio69 = GPIO_MODE_GPIO, /* REC_MODE_L / FAN TACK5 */ - .gpio70 = GPIO_MODE_GPIO, /* SPI_WP1#_RPCH / FAN TACK7 */ - .gpio71 = GPIO_MODE_GPIO, /* LVDS/eDP / FAN TACK8 */ - .gpio72 = GPIO_MODE_NONE, /* NOT USED / BATLOW# */ - .gpio73 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ0#*/ - .gpio74 = GPIO_MODE_NONE, /* NOT USED / SML1ALERT# /PCHHOT# */ - .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_INPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_LOW, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_LOW, - .gpio71 = GPIO_LEVEL_LOW, - .gpio72 = GPIO_LEVEL_LOW, - .gpio73 = GPIO_LEVEL_LOW, - .gpio74 = GPIO_LEVEL_LOW, - .gpio75 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 60c3f01..030f7c4 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -29,11 +29,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #include <cbfs.h> #include <tpm.h> #include "ec/compal/ene932/ec.h" diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index 256948d..f151e4f 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -22,3 +22,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c SRC_ROOT = $(src)/mainboard/google/stout +romstage-y += gpio.c diff --git a/src/mainboard/google/stout/gpio.c b/src/mainboard/google/stout/gpio.c new file mode 100644 index 0000000..7fffe8b --- /dev/null +++ b/src/mainboard/google/stout/gpio.c @@ -0,0 +1,288 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STOUT_GPIO_H +#define STOUT_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ + .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ + .gpio2 = GPIO_MODE_NONE, /* NOT USED */ + .gpio3 = GPIO_MODE_NONE, /* NOT USED */ + .gpio4 = GPIO_MODE_NONE, /* NOT USED */ + .gpio5 = GPIO_MODE_GPIO, /* INTH# */ + .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */ + .gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */ + .gpio8 = GPIO_MODE_NONE, /* NOT USED */ + .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */ + .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */ + .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */ + .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */ + .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */ + .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */ + .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */ + .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */ + .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */ + .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */ + .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */ + .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */ + .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */ + .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */ + .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */ + .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */ + .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */ + .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */ + .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */ + .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */ + .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */ + .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */ + .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + + .gpio19 = GPIO_DIR_OUTPUT, + + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_OUTPUT, + + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + + .gpio19 = GPIO_LEVEL_LOW, + + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ + .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ + .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ + .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ + .gpio36 = GPIO_MODE_NONE, /* NOT USED */ + .gpio37 = GPIO_MODE_NONE, /* NOT USED */ + .gpio38 = GPIO_MODE_NONE, /* NOT USED */ + .gpio39 = GPIO_MODE_NONE, /* NOT USED */ + .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */ + .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */ + .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ + .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ + .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ + .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ + .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ + .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ + .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ + .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ + .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ + .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */ + .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ + .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */ + .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */ + .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ + .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ + .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ + .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ + .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */ + .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ + .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + + .gpio51 = GPIO_DIR_OUTPUT, + + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + + .gpio57 = GPIO_DIR_INPUT, + + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_LOW, + + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, + + .gpio51 = GPIO_LEVEL_HIGH, + + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + + .gpio57 = GPIO_LEVEL_LOW, + + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ + .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ + .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ + .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */ + .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ + .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ + .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ + .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */ + .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */ + .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */ + .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ + .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * direction configured. + */ + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + /* + * Note: Only gpio configured as "gpio" or "none" need to have the + * level set. + */ + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h deleted file mode 100644 index 7fffe8b..0000000 --- a/src/mainboard/google/stout/gpio.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef STOUT_GPIO_H -#define STOUT_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */ - .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */ - .gpio2 = GPIO_MODE_NONE, /* NOT USED */ - .gpio3 = GPIO_MODE_NONE, /* NOT USED */ - .gpio4 = GPIO_MODE_NONE, /* NOT USED */ - .gpio5 = GPIO_MODE_GPIO, /* INTH# */ - .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */ - .gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */ - .gpio8 = GPIO_MODE_NONE, /* NOT USED */ - .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */ - .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */ - .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */ - .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */ - .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */ - .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */ - .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */ - .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */ - .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */ - .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */ - .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */ - .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */ - .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */ - .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */ - .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */ - .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */ - .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */ - .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */ - .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */ - .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */ - .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */ - .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */ - .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_OUTPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_OUTPUT, - - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_OUTPUT, - .gpio17 = GPIO_DIR_OUTPUT, - - .gpio19 = GPIO_DIR_OUTPUT, - - .gpio21 = GPIO_DIR_OUTPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_OUTPUT, - - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_LOW, - - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_LOW, - - .gpio19 = GPIO_LEVEL_LOW, - - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_LOW, - .gpio23 = GPIO_LEVEL_LOW, - - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_HIGH, - .gpio29 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */ - .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ - .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ - .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ - .gpio36 = GPIO_MODE_NONE, /* NOT USED */ - .gpio37 = GPIO_MODE_NONE, /* NOT USED */ - .gpio38 = GPIO_MODE_NONE, /* NOT USED */ - .gpio39 = GPIO_MODE_NONE, /* NOT USED */ - .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */ - .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */ - .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ - .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ - .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ - .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ - .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ - .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ - .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ - .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ - .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ - .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */ - .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ - .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */ - .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */ - .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ - .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ - .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ - .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ - .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */ - .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ - .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_OUTPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_INPUT, - - .gpio51 = GPIO_DIR_OUTPUT, - - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - - .gpio57 = GPIO_DIR_INPUT, - - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_HIGH, - .gpio35 = GPIO_LEVEL_HIGH, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_HIGH, - .gpio41 = GPIO_LEVEL_LOW, - - .gpio48 = GPIO_LEVEL_LOW, - .gpio49 = GPIO_LEVEL_HIGH, - - .gpio51 = GPIO_LEVEL_HIGH, - - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_LOW, - - .gpio57 = GPIO_LEVEL_LOW, - - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */ - .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */ - .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */ - .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */ - .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ - .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ - .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ - .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */ - .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */ - .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */ - .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ - .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. - */ - .gpio64 = GPIO_DIR_OUTPUT, - .gpio65 = GPIO_DIR_OUTPUT, - .gpio66 = GPIO_DIR_OUTPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_OUTPUT, - .gpio70 = GPIO_DIR_OUTPUT, - .gpio71 = GPIO_DIR_OUTPUT, - .gpio72 = GPIO_DIR_OUTPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - /* - * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. - */ - .gpio64 = GPIO_LEVEL_HIGH, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_HIGH, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_HIGH, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, - .gpio72 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 99979e9..d7046a3 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -29,11 +29,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" #include <bootmode.h> #include <tpm.h> #include <cbfs.h> diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index c29b1001..b3bf53f 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -15,3 +15,4 @@ romstage-y += chromeos.c ramstage-y += chromeos.c +romstage-y += gpio.c diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c new file mode 100644 index 0000000..37b2430 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/gpio.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EMERALDLAKE2_GPIO_H +#define EMERALDLAKE2_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio48 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h deleted file mode 100644 index 37b2430..0000000 --- a/src/mainboard/intel/emeraldlake2/gpio.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef EMERALDLAKE2_GPIO_H -#define EMERALDLAKE2_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio3 = GPIO_MODE_GPIO, - .gpio5 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_GPIO, - .gpio12 = GPIO_MODE_GPIO, - .gpio15 = GPIO_MODE_GPIO, - .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, - .gpio48 = GPIO_MODE_GPIO, - .gpio57 = GPIO_MODE_GPIO, - .gpio60 = GPIO_MODE_GPIO, -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio48 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; - -#endif diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 145526a..8528bff 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -30,12 +30,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> #include <tpm.h> -#include "gpio.h" #define SIO_PORT 0x164e diff --git a/src/mainboard/kontron/ktqm77/gpio.c b/src/mainboard/kontron/ktqm77/gpio.c new file mode 100644 index 0000000..a6c3960 --- /dev/null +++ b/src/mainboard/kontron/ktqm77/gpio.c @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef KTQM77_GPIO_H +#define KTQM77_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +/* + * TODO: Investigate somehow... Current values are taken from a running + * system with vendor supplied firmware. + */ + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio1 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio2 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio3 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio4 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio5 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio6 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio7 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio8 = GPIO_MODE_GPIO, /* Unknown Output LOW*/ + .gpio9 = GPIO_MODE_NATIVE, /* Native - OC5# pin */ + .gpio10 = GPIO_MODE_NATIVE, /* Native - OC6# pin */ + .gpio11 = GPIO_MODE_NATIVE, /* Native - SMBALERT# pin */ + .gpio12 = GPIO_MODE_NATIVE, /* Native - LAN_PHY_PWR_CTRL */ + .gpio13 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio14 = GPIO_MODE_NATIVE, /* Native - OC7# pin */ + .gpio15 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio16 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio17 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin */ + .gpio19 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio20 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio21 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio22 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio23 = GPIO_MODE_NATIVE, /* Native - LDRQ1# pin */ + .gpio24 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio25 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio26 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ4# pin */ + .gpio27 = GPIO_MODE_GPIO, /* Unknown Input */ /* Vendor supplied DSDT sets this conditionally + when going to suspend (S3, S4, S5). */ + .gpio28 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio29 = GPIO_MODE_NATIVE, /* Native - SLP_LAN# pin, forced by soft strap */ + .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# pin */ + .gpio31 = GPIO_MODE_NATIVE /* Native - ACPRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio1 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio2 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio3 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio4 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio5 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio6 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio7 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio8 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio9 = GPIO_DIR_INPUT, /* Native */ + .gpio10 = GPIO_DIR_INPUT, /* Native */ + .gpio11 = GPIO_DIR_INPUT, /* Native */ + .gpio12 = GPIO_DIR_INPUT, /* Native */ + .gpio13 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio14 = GPIO_DIR_INPUT, /* Native */ + .gpio15 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio16 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio17 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio18 = GPIO_DIR_INPUT, /* Native */ + .gpio19 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio20 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio21 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio22 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio23 = GPIO_DIR_INPUT, /* Native */ + .gpio24 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio25 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio26 = GPIO_DIR_INPUT, /* Native */ + .gpio27 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio28 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio29 = GPIO_DIR_INPUT, /* Native */ + .gpio30 = GPIO_DIR_INPUT, /* Native */ + .gpio31 = GPIO_DIR_INPUT, /* Native */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio1 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio2 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio3 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio4 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio5 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio6 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio7 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio8 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio9 = GPIO_LEVEL_LOW, /* Native */ + .gpio10 = GPIO_LEVEL_LOW, /* Native */ + .gpio11 = GPIO_LEVEL_LOW, /* Native */ + .gpio12 = GPIO_LEVEL_LOW, /* Native */ + .gpio13 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio14 = GPIO_LEVEL_LOW, /* Native */ + .gpio15 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio16 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio17 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio18 = GPIO_LEVEL_LOW, /* Native */ + .gpio19 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio20 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio21 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio22 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio23 = GPIO_LEVEL_LOW, /* Native */ + .gpio24 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio25 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio26 = GPIO_LEVEL_LOW, /* Native */ + .gpio27 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio28 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio29 = GPIO_LEVEL_LOW, /* Native */ + .gpio30 = GPIO_LEVEL_LOW, /* Native */ + .gpio31 = GPIO_LEVEL_LOW, /* Native */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* Native - CLKRUN# pin */ + .gpio33 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio34 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio35 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio36 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio37 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio38 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio39 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio40 = GPIO_MODE_NATIVE, /* Native - OC1# pin */ + .gpio41 = GPIO_MODE_NATIVE, /* Native - OC2# pin */ + .gpio42 = GPIO_MODE_NATIVE, /* Native - OC3# pin */ + .gpio43 = GPIO_MODE_NATIVE, /* Native - OC4# pin */ + .gpio44 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ5# pin */ + .gpio45 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ6# pin */ + .gpio46 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ7# pin */ + .gpio47 = GPIO_MODE_NATIVE, /* Native - PEG_A_CLKRQ# pin */ + .gpio48 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio49 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio50 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio51 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio52 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio53 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio54 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio55 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio56 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio57 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio58 = GPIO_MODE_NATIVE, /* Native - SML1CLK */ + .gpio59 = GPIO_MODE_NATIVE, /* Native - OC0# pin */ + .gpio60 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ + .gpio61 = GPIO_MODE_NATIVE, /* Native - SUS_STAT# pin*/ + .gpio62 = GPIO_MODE_NATIVE, /* Native - SUSCLK */ + .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5# */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, /* Native */ + .gpio33 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio34 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio35 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio36 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio37 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio38 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio39 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio40 = GPIO_DIR_INPUT, /* Native */ + .gpio41 = GPIO_DIR_INPUT, /* Native */ + .gpio42 = GPIO_DIR_INPUT, /* Native */ + .gpio43 = GPIO_DIR_INPUT, /* Native */ + .gpio44 = GPIO_DIR_INPUT, /* Native */ + .gpio45 = GPIO_DIR_INPUT, /* Native */ + .gpio46 = GPIO_DIR_INPUT, /* Native */ + .gpio47 = GPIO_DIR_INPUT, /* Native */ + .gpio48 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio49 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio50 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio51 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio52 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio53 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio54 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio55 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio56 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio57 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio58 = GPIO_DIR_INPUT, /* Native */ + .gpio59 = GPIO_DIR_INPUT, /* Native */ + .gpio60 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ + .gpio61 = GPIO_DIR_INPUT, /* Native */ + .gpio62 = GPIO_DIR_INPUT, /* Native */ + .gpio63 = GPIO_DIR_INPUT, /* Native */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, /* Native */ + .gpio33 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio34 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio35 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio36 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio37 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio38 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio39 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio40 = GPIO_LEVEL_LOW, /* Native */ + .gpio41 = GPIO_LEVEL_LOW, /* Native */ + .gpio42 = GPIO_LEVEL_LOW, /* Native */ + .gpio43 = GPIO_LEVEL_LOW, /* Native */ + .gpio44 = GPIO_LEVEL_LOW, /* Native */ + .gpio45 = GPIO_LEVEL_LOW, /* Native */ + .gpio46 = GPIO_LEVEL_LOW, /* Native */ + .gpio47 = GPIO_LEVEL_LOW, /* Native */ + .gpio48 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio49 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio50 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio51 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio52 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio53 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio54 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio55 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio56 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio57 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio58 = GPIO_LEVEL_LOW, /* Native */ + .gpio59 = GPIO_LEVEL_LOW, /* Native */ + .gpio60 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ + .gpio61 = GPIO_LEVEL_LOW, /* Native */ + .gpio62 = GPIO_LEVEL_LOW, /* Native */ + .gpio63 = GPIO_LEVEL_LOW, /* Native */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio65 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio66 = GPIO_MODE_GPIO, /* Unknown Output LOW */ + .gpio67 = GPIO_MODE_NATIVE, /* Native - CLKOUTFLEX3 */ + .gpio68 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio69 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio70 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio71 = GPIO_MODE_GPIO, /* Unknown Input */ + .gpio72 = GPIO_MODE_NATIVE, /* Native - nothing on mobile */ + .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# pin */ + .gpio74 = GPIO_MODE_NATIVE, /* Native - SML1ALERT#/PCHHOT# pin */ + .gpio75 = GPIO_MODE_NATIVE, /* Native - SML1DATA */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio65 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ + .gpio67 = GPIO_DIR_INPUT, /* Native */ + .gpio68 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio69 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio70 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio71 = GPIO_DIR_INPUT, /* Unknown Input */ + .gpio72 = GPIO_DIR_INPUT, /* Native */ + .gpio73 = GPIO_DIR_INPUT, /* Native */ + .gpio74 = GPIO_DIR_INPUT, /* Native */ + .gpio75 = GPIO_DIR_INPUT, /* Native */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio65 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio66 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ + .gpio67 = GPIO_LEVEL_LOW, /* Native */ + .gpio68 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio69 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio70 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio71 = GPIO_LEVEL_LOW, /* Unknown Input */ + .gpio72 = GPIO_LEVEL_LOW, /* Native */ + .gpio73 = GPIO_LEVEL_LOW, /* Native */ + .gpio74 = GPIO_LEVEL_LOW, /* Native */ + .gpio75 = GPIO_LEVEL_LOW, /* Native */ +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/kontron/ktqm77/gpio.h b/src/mainboard/kontron/ktqm77/gpio.h deleted file mode 100644 index a6c3960..0000000 --- a/src/mainboard/kontron/ktqm77/gpio.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef KTQM77_GPIO_H -#define KTQM77_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -/* - * TODO: Investigate somehow... Current values are taken from a running - * system with vendor supplied firmware. - */ - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio1 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio2 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio3 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio4 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio5 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio6 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio7 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio8 = GPIO_MODE_GPIO, /* Unknown Output LOW*/ - .gpio9 = GPIO_MODE_NATIVE, /* Native - OC5# pin */ - .gpio10 = GPIO_MODE_NATIVE, /* Native - OC6# pin */ - .gpio11 = GPIO_MODE_NATIVE, /* Native - SMBALERT# pin */ - .gpio12 = GPIO_MODE_NATIVE, /* Native - LAN_PHY_PWR_CTRL */ - .gpio13 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio14 = GPIO_MODE_NATIVE, /* Native - OC7# pin */ - .gpio15 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio16 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio17 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin */ - .gpio19 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio20 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio21 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio22 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio23 = GPIO_MODE_NATIVE, /* Native - LDRQ1# pin */ - .gpio24 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio25 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio26 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ4# pin */ - .gpio27 = GPIO_MODE_GPIO, /* Unknown Input */ /* Vendor supplied DSDT sets this conditionally - when going to suspend (S3, S4, S5). */ - .gpio28 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio29 = GPIO_MODE_NATIVE, /* Native - SLP_LAN# pin, forced by soft strap */ - .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# pin */ - .gpio31 = GPIO_MODE_NATIVE /* Native - ACPRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio1 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio2 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio3 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio4 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio5 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio6 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio7 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio8 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio9 = GPIO_DIR_INPUT, /* Native */ - .gpio10 = GPIO_DIR_INPUT, /* Native */ - .gpio11 = GPIO_DIR_INPUT, /* Native */ - .gpio12 = GPIO_DIR_INPUT, /* Native */ - .gpio13 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio14 = GPIO_DIR_INPUT, /* Native */ - .gpio15 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio16 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio17 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio18 = GPIO_DIR_INPUT, /* Native */ - .gpio19 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio20 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio21 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio22 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio23 = GPIO_DIR_INPUT, /* Native */ - .gpio24 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio25 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio26 = GPIO_DIR_INPUT, /* Native */ - .gpio27 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio28 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio29 = GPIO_DIR_INPUT, /* Native */ - .gpio30 = GPIO_DIR_INPUT, /* Native */ - .gpio31 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio1 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio2 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio3 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio4 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio5 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio6 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio7 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio8 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio9 = GPIO_LEVEL_LOW, /* Native */ - .gpio10 = GPIO_LEVEL_LOW, /* Native */ - .gpio11 = GPIO_LEVEL_LOW, /* Native */ - .gpio12 = GPIO_LEVEL_LOW, /* Native */ - .gpio13 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio14 = GPIO_LEVEL_LOW, /* Native */ - .gpio15 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio16 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio17 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio18 = GPIO_LEVEL_LOW, /* Native */ - .gpio19 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio20 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio21 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio22 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio23 = GPIO_LEVEL_LOW, /* Native */ - .gpio24 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio25 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio26 = GPIO_LEVEL_LOW, /* Native */ - .gpio27 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio28 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio29 = GPIO_LEVEL_LOW, /* Native */ - .gpio30 = GPIO_LEVEL_LOW, /* Native */ - .gpio31 = GPIO_LEVEL_LOW, /* Native */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* Native - CLKRUN# pin */ - .gpio33 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio34 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio35 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio36 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio37 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio38 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio39 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio40 = GPIO_MODE_NATIVE, /* Native - OC1# pin */ - .gpio41 = GPIO_MODE_NATIVE, /* Native - OC2# pin */ - .gpio42 = GPIO_MODE_NATIVE, /* Native - OC3# pin */ - .gpio43 = GPIO_MODE_NATIVE, /* Native - OC4# pin */ - .gpio44 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ5# pin */ - .gpio45 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ6# pin */ - .gpio46 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ7# pin */ - .gpio47 = GPIO_MODE_NATIVE, /* Native - PEG_A_CLKRQ# pin */ - .gpio48 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio49 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio50 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio51 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio52 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio53 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio54 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio55 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio56 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio57 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio58 = GPIO_MODE_NATIVE, /* Native - SML1CLK */ - .gpio59 = GPIO_MODE_NATIVE, /* Native - OC0# pin */ - .gpio60 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ - .gpio61 = GPIO_MODE_NATIVE, /* Native - SUS_STAT# pin*/ - .gpio62 = GPIO_MODE_NATIVE, /* Native - SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5# */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, /* Native */ - .gpio33 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio34 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio35 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio36 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio37 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio38 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio39 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio40 = GPIO_DIR_INPUT, /* Native */ - .gpio41 = GPIO_DIR_INPUT, /* Native */ - .gpio42 = GPIO_DIR_INPUT, /* Native */ - .gpio43 = GPIO_DIR_INPUT, /* Native */ - .gpio44 = GPIO_DIR_INPUT, /* Native */ - .gpio45 = GPIO_DIR_INPUT, /* Native */ - .gpio46 = GPIO_DIR_INPUT, /* Native */ - .gpio47 = GPIO_DIR_INPUT, /* Native */ - .gpio48 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio49 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio50 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio51 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio52 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio53 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio54 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio55 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio56 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio57 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio58 = GPIO_DIR_INPUT, /* Native */ - .gpio59 = GPIO_DIR_INPUT, /* Native */ - .gpio60 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */ - .gpio61 = GPIO_DIR_INPUT, /* Native */ - .gpio62 = GPIO_DIR_INPUT, /* Native */ - .gpio63 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, /* Native */ - .gpio33 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio34 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio35 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio36 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio37 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio38 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio39 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio40 = GPIO_LEVEL_LOW, /* Native */ - .gpio41 = GPIO_LEVEL_LOW, /* Native */ - .gpio42 = GPIO_LEVEL_LOW, /* Native */ - .gpio43 = GPIO_LEVEL_LOW, /* Native */ - .gpio44 = GPIO_LEVEL_LOW, /* Native */ - .gpio45 = GPIO_LEVEL_LOW, /* Native */ - .gpio46 = GPIO_LEVEL_LOW, /* Native */ - .gpio47 = GPIO_LEVEL_LOW, /* Native */ - .gpio48 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio49 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio50 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio51 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio52 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio53 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio54 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio55 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio56 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio57 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio58 = GPIO_LEVEL_LOW, /* Native */ - .gpio59 = GPIO_LEVEL_LOW, /* Native */ - .gpio60 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */ - .gpio61 = GPIO_LEVEL_LOW, /* Native */ - .gpio62 = GPIO_LEVEL_LOW, /* Native */ - .gpio63 = GPIO_LEVEL_LOW, /* Native */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio65 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio66 = GPIO_MODE_GPIO, /* Unknown Output LOW */ - .gpio67 = GPIO_MODE_NATIVE, /* Native - CLKOUTFLEX3 */ - .gpio68 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio69 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio70 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio71 = GPIO_MODE_GPIO, /* Unknown Input */ - .gpio72 = GPIO_MODE_NATIVE, /* Native - nothing on mobile */ - .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# pin */ - .gpio74 = GPIO_MODE_NATIVE, /* Native - SML1ALERT#/PCHHOT# pin */ - .gpio75 = GPIO_MODE_NATIVE, /* Native - SML1DATA */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio65 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */ - .gpio67 = GPIO_DIR_INPUT, /* Native */ - .gpio68 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio69 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio70 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio71 = GPIO_DIR_INPUT, /* Unknown Input */ - .gpio72 = GPIO_DIR_INPUT, /* Native */ - .gpio73 = GPIO_DIR_INPUT, /* Native */ - .gpio74 = GPIO_DIR_INPUT, /* Native */ - .gpio75 = GPIO_DIR_INPUT, /* Native */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio65 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio66 = GPIO_LEVEL_LOW, /* Unknown Output LOW */ - .gpio67 = GPIO_LEVEL_LOW, /* Native */ - .gpio68 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio69 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio70 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio71 = GPIO_LEVEL_LOW, /* Unknown Input */ - .gpio72 = GPIO_LEVEL_LOW, /* Native */ - .gpio73 = GPIO_LEVEL_LOW, /* Native */ - .gpio74 = GPIO_LEVEL_LOW, /* Native */ - .gpio75 = GPIO_LEVEL_LOW, /* Native */ -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; -#endif diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 197b460..8f3f900 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -29,11 +29,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include "gpio.h" void pch_enable_lpc(void) { diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index d83f26d..26526c9 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -27,3 +27,4 @@ $(SPD_BIN): cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := spd +romstage-y += gpio.c diff --git a/src/mainboard/samsung/lumpy/gpio.c b/src/mainboard/samsung/lumpy/gpio.c new file mode 100644 index 0000000..e5737bb --- /dev/null +++ b/src/mainboard/samsung/lumpy/gpio.c @@ -0,0 +1,332 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LUMPY_GPIO_H +#define LUMPY_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +/* + * GPIO SET 1 includes GPIO0 to GPIO31 + */ + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ + .gpio1 = GPIO_MODE_GPIO, /* KBC3_EXTSMI# */ + .gpio2 = GPIO_MODE_NATIVE, /* CHP3_ALSINT# (Light Sensor) */ + .gpio3 = GPIO_MODE_NATIVE, /* CHP3_TP_INT# (Trackpad) */ + .gpio4 = GPIO_MODE_NONE, + .gpio5 = GPIO_MODE_GPIO, /* SIM3_CARD_DET# */ + .gpio6 = GPIO_MODE_NONE, + .gpio7 = GPIO_MODE_GPIO, /* KBC3_RUNSCI# */ + .gpio8 = GPIO_MODE_GPIO, /* CHP3_INTELBT_OFF# */ + .gpio9 = GPIO_MODE_NONE, + .gpio10 = GPIO_MODE_NONE, + .gpio11 = GPIO_MODE_GPIO, /* CHP3_TP_INT# (Trackpad wake) */ + .gpio12 = GPIO_MODE_NONE, + .gpio13 = GPIO_MODE_GPIO, /* CHP3_DEBUG13 */ + .gpio14 = GPIO_MODE_GPIO, /* KBC3_WAKESCI# */ + .gpio15 = GPIO_MODE_NONE, + .gpio16 = GPIO_MODE_NONE, + .gpio17 = GPIO_MODE_GPIO, /* KBC3_DVP_MODE */ + .gpio18 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ1# */ + .gpio19 = GPIO_MODE_NONE, + .gpio20 = GPIO_MODE_NONE, + .gpio21 = GPIO_MODE_GPIO, /* LCD3_SIZE */ + .gpio22 = GPIO_MODE_GPIO, /* CHP3_BIOS_CRISIS# */ + .gpio23 = GPIO_MODE_NONE, + .gpio24 = GPIO_MODE_GPIO, /* KBC3_SPI_WP# */ + .gpio25 = GPIO_MODE_NONE, + .gpio26 = GPIO_MODE_NATIVE, /* LAN3_CLKREQ# */ + .gpio27 = GPIO_MODE_NONE, + .gpio28 = GPIO_MODE_NONE, + .gpio29 = GPIO_MODE_NONE, + .gpio30 = GPIO_MODE_NATIVE, /* CHP3_SUSWARN# */ + .gpio31 = GPIO_MODE_NATIVE, /* KBC3_AC_PRESENT */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_NO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_NO_INVERT, +}; + +/* + * GPIO SET 2 includes GPIO32 to GPIO63 + */ + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ + .gpio33 = GPIO_MODE_GPIO, /* Onboard Memory Capacity */ + .gpio34 = GPIO_MODE_NONE, + .gpio35 = GPIO_MODE_GPIO, /* CHP3_WLAN_OFF# */ + .gpio36 = GPIO_MODE_NONE, + .gpio37 = GPIO_MODE_GPIO, /* CHP3_FDI_OVRVLTG */ + .gpio38 = GPIO_MODE_GPIO, /* CHP3_3G_OFF# */ + .gpio39 = GPIO_MODE_NONE, + .gpio40 = GPIO_MODE_NATIVE, /* USB3_OC1# */ + .gpio41 = GPIO_MODE_GPIO, /* Onboard Memory Revision */ + .gpio42 = GPIO_MODE_GPIO, /* CHP3_REC_MODE# */ + .gpio43 = GPIO_MODE_GPIO, /* CHP3_HSPA_PWRON# */ + .gpio44 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL2# */ + .gpio45 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL3# */ + .gpio46 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG1_CTL2# */ + .gpio47 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE0 */ + .gpio48 = GPIO_MODE_GPIO, /* CHP3_BT_OFF# */ + .gpio49 = GPIO_MODE_GPIO, /* Onboard Memory Vendor */ + .gpio50 = GPIO_MODE_NONE, + .gpio51 = GPIO_MODE_NONE, + .gpio52 = GPIO_MODE_NONE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NONE, + .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR */ + .gpio56 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE1 */ + .gpio57 = GPIO_MODE_GPIO, /* CHP3_DEBUG10 */ + .gpio58 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMCLK# */ + .gpio59 = GPIO_MODE_NATIVE, /* USB3_OC0# */ + .gpio60 = GPIO_MODE_GPIO, /* CHP3_DRAMRST_GATE */ + .gpio61 = GPIO_MODE_NATIVE, /* CHP3_SUSSTAT# */ + .gpio62 = GPIO_MODE_NATIVE, /* CHP3_SUSCLK */ + .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, /* Enable WLAN */ + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, /* Enable 3G */ + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB0 SDP */ + .gpio45 = GPIO_LEVEL_LOW, /* CTL3=0 for USB0 SDP */ + .gpio46 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB1 SDP */ + .gpio47 = GPIO_LEVEL_HIGH, /* Enable USB0 */ + .gpio48 = GPIO_LEVEL_LOW, /* Disable Bluetooth */ + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, /* Enable USB1 */ + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +/* + * GPIO SET 3 includes GPIO64 to GPIO75 + */ + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NONE, + .gpio65 = GPIO_MODE_NONE, + .gpio66 = GPIO_MODE_NONE, + .gpio67 = GPIO_MODE_NONE, + .gpio68 = GPIO_MODE_NONE, + .gpio69 = GPIO_MODE_GPIO, /* PEX3_WWAN_DET# */ + .gpio70 = GPIO_MODE_GPIO, /* CHP3_WLAN_RST# */ + .gpio71 = GPIO_MODE_GPIO, /* CHP3_WLAN_PWRON */ + .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# (pullup) */ + .gpio73 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG1_CTL3# */ + .gpio74 = GPIO_MODE_NONE, + .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, /* WLAN out of reset */ + .gpio71 = GPIO_LEVEL_HIGH, /* WLAN power on */ + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_LOW, /* USB1 CTL3=0 for SDP */ + .gpio74 = GPIO_LEVEL_LOW, + .gpio75 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio38 = GPIO_RESET_RSMRST, + .gpio43 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/samsung/lumpy/gpio.h b/src/mainboard/samsung/lumpy/gpio.h deleted file mode 100644 index e5737bb..0000000 --- a/src/mainboard/samsung/lumpy/gpio.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LUMPY_GPIO_H -#define LUMPY_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -/* - * GPIO SET 1 includes GPIO0 to GPIO31 - */ - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ - .gpio1 = GPIO_MODE_GPIO, /* KBC3_EXTSMI# */ - .gpio2 = GPIO_MODE_NATIVE, /* CHP3_ALSINT# (Light Sensor) */ - .gpio3 = GPIO_MODE_NATIVE, /* CHP3_TP_INT# (Trackpad) */ - .gpio4 = GPIO_MODE_NONE, - .gpio5 = GPIO_MODE_GPIO, /* SIM3_CARD_DET# */ - .gpio6 = GPIO_MODE_NONE, - .gpio7 = GPIO_MODE_GPIO, /* KBC3_RUNSCI# */ - .gpio8 = GPIO_MODE_GPIO, /* CHP3_INTELBT_OFF# */ - .gpio9 = GPIO_MODE_NONE, - .gpio10 = GPIO_MODE_NONE, - .gpio11 = GPIO_MODE_GPIO, /* CHP3_TP_INT# (Trackpad wake) */ - .gpio12 = GPIO_MODE_NONE, - .gpio13 = GPIO_MODE_GPIO, /* CHP3_DEBUG13 */ - .gpio14 = GPIO_MODE_GPIO, /* KBC3_WAKESCI# */ - .gpio15 = GPIO_MODE_NONE, - .gpio16 = GPIO_MODE_NONE, - .gpio17 = GPIO_MODE_GPIO, /* KBC3_DVP_MODE */ - .gpio18 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ1# */ - .gpio19 = GPIO_MODE_NONE, - .gpio20 = GPIO_MODE_NONE, - .gpio21 = GPIO_MODE_GPIO, /* LCD3_SIZE */ - .gpio22 = GPIO_MODE_GPIO, /* CHP3_BIOS_CRISIS# */ - .gpio23 = GPIO_MODE_NONE, - .gpio24 = GPIO_MODE_GPIO, /* KBC3_SPI_WP# */ - .gpio25 = GPIO_MODE_NONE, - .gpio26 = GPIO_MODE_NATIVE, /* LAN3_CLKREQ# */ - .gpio27 = GPIO_MODE_NONE, - .gpio28 = GPIO_MODE_NONE, - .gpio29 = GPIO_MODE_NONE, - .gpio30 = GPIO_MODE_NATIVE, /* CHP3_SUSWARN# */ - .gpio31 = GPIO_MODE_NATIVE, /* KBC3_AC_PRESENT */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_LOW, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_LOW, - .gpio9 = GPIO_LEVEL_LOW, - .gpio10 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_LOW, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - .gpio14 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_LOW, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_LOW, - .gpio30 = GPIO_LEVEL_LOW, - .gpio31 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio0 = GPIO_NO_INVERT, - .gpio1 = GPIO_INVERT, - .gpio2 = GPIO_INVERT, - .gpio3 = GPIO_INVERT, - .gpio4 = GPIO_NO_INVERT, - .gpio5 = GPIO_INVERT, - .gpio6 = GPIO_NO_INVERT, - .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_NO_INVERT, - .gpio9 = GPIO_NO_INVERT, - .gpio10 = GPIO_NO_INVERT, - .gpio11 = GPIO_INVERT, - .gpio12 = GPIO_NO_INVERT, - .gpio13 = GPIO_NO_INVERT, - .gpio14 = GPIO_INVERT, - .gpio15 = GPIO_NO_INVERT, -}; - -/* - * GPIO SET 2 includes GPIO32 to GPIO63 - */ - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ - .gpio33 = GPIO_MODE_GPIO, /* Onboard Memory Capacity */ - .gpio34 = GPIO_MODE_NONE, - .gpio35 = GPIO_MODE_GPIO, /* CHP3_WLAN_OFF# */ - .gpio36 = GPIO_MODE_NONE, - .gpio37 = GPIO_MODE_GPIO, /* CHP3_FDI_OVRVLTG */ - .gpio38 = GPIO_MODE_GPIO, /* CHP3_3G_OFF# */ - .gpio39 = GPIO_MODE_NONE, - .gpio40 = GPIO_MODE_NATIVE, /* USB3_OC1# */ - .gpio41 = GPIO_MODE_GPIO, /* Onboard Memory Revision */ - .gpio42 = GPIO_MODE_GPIO, /* CHP3_REC_MODE# */ - .gpio43 = GPIO_MODE_GPIO, /* CHP3_HSPA_PWRON# */ - .gpio44 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL2# */ - .gpio45 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL3# */ - .gpio46 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG1_CTL2# */ - .gpio47 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE0 */ - .gpio48 = GPIO_MODE_GPIO, /* CHP3_BT_OFF# */ - .gpio49 = GPIO_MODE_GPIO, /* Onboard Memory Vendor */ - .gpio50 = GPIO_MODE_NONE, - .gpio51 = GPIO_MODE_NONE, - .gpio52 = GPIO_MODE_NONE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NONE, - .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR */ - .gpio56 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE1 */ - .gpio57 = GPIO_MODE_GPIO, /* CHP3_DEBUG10 */ - .gpio58 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMCLK# */ - .gpio59 = GPIO_MODE_NATIVE, /* USB3_OC0# */ - .gpio60 = GPIO_MODE_GPIO, /* CHP3_DRAMRST_GATE */ - .gpio61 = GPIO_MODE_NATIVE, /* CHP3_SUSSTAT# */ - .gpio62 = GPIO_MODE_NATIVE, /* CHP3_SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_OUTPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_OUTPUT, - .gpio44 = GPIO_DIR_OUTPUT, - .gpio45 = GPIO_DIR_OUTPUT, - .gpio46 = GPIO_DIR_OUTPUT, - .gpio47 = GPIO_DIR_OUTPUT, - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_INPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_INPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_INPUT, - .gpio56 = GPIO_DIR_OUTPUT, - .gpio57 = GPIO_DIR_OUTPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_INPUT, - .gpio62 = GPIO_DIR_INPUT, - .gpio63 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_HIGH, /* Enable WLAN */ - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_HIGH, /* Enable 3G */ - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_LOW, - .gpio41 = GPIO_LEVEL_LOW, - .gpio42 = GPIO_LEVEL_LOW, - .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB0 SDP */ - .gpio45 = GPIO_LEVEL_LOW, /* CTL3=0 for USB0 SDP */ - .gpio46 = GPIO_LEVEL_HIGH, /* CTL2=1 for USB1 SDP */ - .gpio47 = GPIO_LEVEL_HIGH, /* Enable USB0 */ - .gpio48 = GPIO_LEVEL_LOW, /* Disable Bluetooth */ - .gpio49 = GPIO_LEVEL_LOW, - .gpio50 = GPIO_LEVEL_LOW, - .gpio51 = GPIO_LEVEL_LOW, - .gpio52 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_LOW, - .gpio54 = GPIO_LEVEL_LOW, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_HIGH, /* Enable USB1 */ - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_LOW, - .gpio59 = GPIO_LEVEL_LOW, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, -}; - -/* - * GPIO SET 3 includes GPIO64 to GPIO75 - */ - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NONE, - .gpio65 = GPIO_MODE_NONE, - .gpio66 = GPIO_MODE_NONE, - .gpio67 = GPIO_MODE_NONE, - .gpio68 = GPIO_MODE_NONE, - .gpio69 = GPIO_MODE_GPIO, /* PEX3_WWAN_DET# */ - .gpio70 = GPIO_MODE_GPIO, /* CHP3_WLAN_RST# */ - .gpio71 = GPIO_MODE_GPIO, /* CHP3_WLAN_PWRON */ - .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# (pullup) */ - .gpio73 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG1_CTL3# */ - .gpio74 = GPIO_MODE_NONE, - .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_OUTPUT, - .gpio71 = GPIO_DIR_OUTPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_OUTPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_LOW, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_HIGH, /* WLAN out of reset */ - .gpio71 = GPIO_LEVEL_HIGH, /* WLAN power on */ - .gpio72 = GPIO_LEVEL_LOW, - .gpio73 = GPIO_LEVEL_LOW, /* USB1 CTL3=0 for SDP */ - .gpio74 = GPIO_LEVEL_LOW, - .gpio75 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_set2 pch_gpio_set2_reset = { - .gpio38 = GPIO_RESET_RSMRST, - .gpio43 = GPIO_RESET_RSMRST, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - .reset = &pch_gpio_set2_reset, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; - -#endif diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index b91573b..791afe9 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,12 +32,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> #include "option_table.h" -#include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index c29b1001..b3bf53f 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -15,3 +15,4 @@ romstage-y += chromeos.c ramstage-y += chromeos.c +romstage-y += gpio.c diff --git a/src/mainboard/samsung/stumpy/gpio.c b/src/mainboard/samsung/stumpy/gpio.c new file mode 100644 index 0000000..1371155 --- /dev/null +++ b/src/mainboard/samsung/stumpy/gpio.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STUMPY_GPIO_H +#define STUMPY_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +/* + * GPIO SET 1 includes GPIO0 to GPIO31 + */ + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ + .gpio1 = GPIO_MODE_GPIO, /* SIO3_EXTSMI# */ + .gpio2 = GPIO_MODE_NONE, + .gpio3 = GPIO_MODE_NONE, + .gpio4 = GPIO_MODE_NONE, + .gpio5 = GPIO_MODE_NONE, + .gpio6 = GPIO_MODE_NONE, + .gpio7 = GPIO_MODE_NONE, + .gpio8 = GPIO_MODE_GPIO, /* CHP3_INTELBT_OFF# */ + .gpio9 = GPIO_MODE_NATIVE, /* USB_OC13# */ + .gpio10 = GPIO_MODE_NATIVE, /* USB_OC12# */ + .gpio11 = GPIO_MODE_NONE, + .gpio12 = GPIO_MODE_NONE, + .gpio13 = GPIO_MODE_GPIO, /* CHP3_DEBUG13 */ + .gpio14 = GPIO_MODE_GPIO, /* SIO3_WAKESCI# */ + .gpio15 = GPIO_MODE_NONE, + .gpio16 = GPIO_MODE_NONE, + .gpio17 = GPIO_MODE_GPIO, /* KBC3_DVP_MODE */ + .gpio18 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ1# */ + .gpio19 = GPIO_MODE_NONE, + .gpio20 = GPIO_MODE_NONE, + .gpio21 = GPIO_MODE_NONE, + .gpio22 = GPIO_MODE_GPIO, /* CHP3_BIOS_CRISIS# */ + .gpio23 = GPIO_MODE_NONE, + .gpio24 = GPIO_MODE_NONE, + .gpio25 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ3# */ + .gpio26 = GPIO_MODE_NATIVE, /* LAN3_CLKREQ# */ + .gpio27 = GPIO_MODE_NONE, + .gpio28 = GPIO_MODE_NONE, + .gpio29 = GPIO_MODE_NONE, + .gpio30 = GPIO_MODE_NATIVE, /* CHP3_SUSWARN# */ + .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT (pullup) */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_LOW, +}; + +/* + * GPIO SET 2 includes GPIO32 to GPIO63 + */ + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ + .gpio33 = GPIO_MODE_NONE, + .gpio34 = GPIO_MODE_NONE, + .gpio35 = GPIO_MODE_GPIO, /* CHP3_WLAN_OFF# */ + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, /* CHP3_FDI_OVRVLTG */ + .gpio38 = GPIO_MODE_NONE, + .gpio39 = GPIO_MODE_NONE, + .gpio40 = GPIO_MODE_NATIVE, /* USB3_OC1# */ + .gpio41 = GPIO_MODE_NATIVE, /* USB3_OC4# */ + .gpio42 = GPIO_MODE_GPIO, /* CHP3_REC_MODE# */ + .gpio43 = GPIO_MODE_NATIVE, /* USB3_OC8# */ + .gpio44 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL2# */ + .gpio45 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL3# */ + .gpio46 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG4_CTL2# */ + .gpio47 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE0 */ + .gpio48 = GPIO_MODE_GPIO, /* CHP3_BT_OFF# */ + .gpio49 = GPIO_MODE_NONE, + .gpio50 = GPIO_MODE_NONE, + .gpio51 = GPIO_MODE_NONE, + .gpio52 = GPIO_MODE_NONE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NONE, + .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR */ + .gpio56 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE4 */ + .gpio57 = GPIO_MODE_GPIO, /* CHP3_DEBUG10 */ + .gpio58 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMCLK# */ + .gpio59 = GPIO_MODE_NATIVE, /* USB3_OC0# */ + .gpio60 = GPIO_MODE_GPIO, /* CHP3_DRAMRST_GATE */ + .gpio61 = GPIO_MODE_NONE, + .gpio62 = GPIO_MODE_NATIVE, /* CHP3_SUSCLK */ + .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio47 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_LOW, + .gpio59 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +/* + * GPIO SET 3 includes GPIO64 to GPIO75 + */ + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, /* CLK3_SIO48 */ + .gpio65 = GPIO_MODE_NONE, + .gpio66 = GPIO_MODE_NONE, + .gpio67 = GPIO_MODE_NONE, + .gpio68 = GPIO_MODE_GPIO, /* CHP3_SPI_WP */ + .gpio69 = GPIO_MODE_NONE, + .gpio70 = GPIO_MODE_NONE, + .gpio71 = GPIO_MODE_NONE, + .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# (pullup) */ + .gpio73 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG4_CTL3# */ + .gpio74 = GPIO_MODE_NONE, + .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_LOW, + .gpio75 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/samsung/stumpy/gpio.h b/src/mainboard/samsung/stumpy/gpio.h deleted file mode 100644 index 1371155..0000000 --- a/src/mainboard/samsung/stumpy/gpio.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef STUMPY_GPIO_H -#define STUMPY_GPIO_H - -#include "southbridge/intel/bd82x6x/gpio.h" - -/* - * GPIO SET 1 includes GPIO0 to GPIO31 - */ - -const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* CHP3_SERDBG */ - .gpio1 = GPIO_MODE_GPIO, /* SIO3_EXTSMI# */ - .gpio2 = GPIO_MODE_NONE, - .gpio3 = GPIO_MODE_NONE, - .gpio4 = GPIO_MODE_NONE, - .gpio5 = GPIO_MODE_NONE, - .gpio6 = GPIO_MODE_NONE, - .gpio7 = GPIO_MODE_NONE, - .gpio8 = GPIO_MODE_GPIO, /* CHP3_INTELBT_OFF# */ - .gpio9 = GPIO_MODE_NATIVE, /* USB_OC13# */ - .gpio10 = GPIO_MODE_NATIVE, /* USB_OC12# */ - .gpio11 = GPIO_MODE_NONE, - .gpio12 = GPIO_MODE_NONE, - .gpio13 = GPIO_MODE_GPIO, /* CHP3_DEBUG13 */ - .gpio14 = GPIO_MODE_GPIO, /* SIO3_WAKESCI# */ - .gpio15 = GPIO_MODE_NONE, - .gpio16 = GPIO_MODE_NONE, - .gpio17 = GPIO_MODE_GPIO, /* KBC3_DVP_MODE */ - .gpio18 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ1# */ - .gpio19 = GPIO_MODE_NONE, - .gpio20 = GPIO_MODE_NONE, - .gpio21 = GPIO_MODE_NONE, - .gpio22 = GPIO_MODE_GPIO, /* CHP3_BIOS_CRISIS# */ - .gpio23 = GPIO_MODE_NONE, - .gpio24 = GPIO_MODE_NONE, - .gpio25 = GPIO_MODE_NATIVE, /* MIN3_CLKREQ3# */ - .gpio26 = GPIO_MODE_NATIVE, /* LAN3_CLKREQ# */ - .gpio27 = GPIO_MODE_NONE, - .gpio28 = GPIO_MODE_NONE, - .gpio29 = GPIO_MODE_NONE, - .gpio30 = GPIO_MODE_NATIVE, /* CHP3_SUSWARN# */ - .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT (pullup) */ -}; - -const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_OUTPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_OUTPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_INPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_INPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_INPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_LOW, - .gpio1 = GPIO_LEVEL_LOW, - .gpio2 = GPIO_LEVEL_LOW, - .gpio3 = GPIO_LEVEL_LOW, - .gpio4 = GPIO_LEVEL_LOW, - .gpio5 = GPIO_LEVEL_LOW, - .gpio6 = GPIO_LEVEL_LOW, - .gpio7 = GPIO_LEVEL_LOW, - .gpio8 = GPIO_LEVEL_HIGH, - .gpio9 = GPIO_LEVEL_LOW, - .gpio10 = GPIO_LEVEL_LOW, - .gpio11 = GPIO_LEVEL_LOW, - .gpio12 = GPIO_LEVEL_LOW, - .gpio13 = GPIO_LEVEL_LOW, - .gpio14 = GPIO_LEVEL_LOW, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_LOW, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_LOW, - .gpio20 = GPIO_LEVEL_LOW, - .gpio21 = GPIO_LEVEL_LOW, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_LOW, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_LOW, - .gpio30 = GPIO_LEVEL_LOW, - .gpio31 = GPIO_LEVEL_LOW, -}; - -/* - * GPIO SET 2 includes GPIO32 to GPIO63 - */ - -const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_NATIVE, /* PCI3_CLKRUN# */ - .gpio33 = GPIO_MODE_NONE, - .gpio34 = GPIO_MODE_NONE, - .gpio35 = GPIO_MODE_GPIO, /* CHP3_WLAN_OFF# */ - .gpio36 = GPIO_MODE_GPIO, - .gpio37 = GPIO_MODE_GPIO, /* CHP3_FDI_OVRVLTG */ - .gpio38 = GPIO_MODE_NONE, - .gpio39 = GPIO_MODE_NONE, - .gpio40 = GPIO_MODE_NATIVE, /* USB3_OC1# */ - .gpio41 = GPIO_MODE_NATIVE, /* USB3_OC4# */ - .gpio42 = GPIO_MODE_GPIO, /* CHP3_REC_MODE# */ - .gpio43 = GPIO_MODE_NATIVE, /* USB3_OC8# */ - .gpio44 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL2# */ - .gpio45 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG0_CTL3# */ - .gpio46 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG4_CTL2# */ - .gpio47 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE0 */ - .gpio48 = GPIO_MODE_GPIO, /* CHP3_BT_OFF# */ - .gpio49 = GPIO_MODE_NONE, - .gpio50 = GPIO_MODE_NONE, - .gpio51 = GPIO_MODE_NONE, - .gpio52 = GPIO_MODE_NONE, - .gpio53 = GPIO_MODE_NATIVE, - .gpio54 = GPIO_MODE_NONE, - .gpio55 = GPIO_MODE_GPIO, /* STP_A16OVR */ - .gpio56 = GPIO_MODE_GPIO, /* CHP3_CHG_ENABLE4 */ - .gpio57 = GPIO_MODE_GPIO, /* CHP3_DEBUG10 */ - .gpio58 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMCLK# */ - .gpio59 = GPIO_MODE_NATIVE, /* USB3_OC0# */ - .gpio60 = GPIO_MODE_GPIO, /* CHP3_DRAMRST_GATE */ - .gpio61 = GPIO_MODE_NONE, - .gpio62 = GPIO_MODE_NATIVE, /* CHP3_SUSCLK */ - .gpio63 = GPIO_MODE_NATIVE, /* CHP3_SLPS5# */ -}; - -const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_OUTPUT, - .gpio45 = GPIO_DIR_OUTPUT, - .gpio46 = GPIO_DIR_OUTPUT, - .gpio47 = GPIO_DIR_OUTPUT, - .gpio48 = GPIO_DIR_OUTPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_INPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_INPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_INPUT, - .gpio56 = GPIO_DIR_OUTPUT, - .gpio57 = GPIO_DIR_OUTPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio60 = GPIO_DIR_OUTPUT, - .gpio61 = GPIO_DIR_INPUT, - .gpio62 = GPIO_DIR_INPUT, - .gpio63 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_LOW, - .gpio33 = GPIO_LEVEL_LOW, - .gpio34 = GPIO_LEVEL_LOW, - .gpio35 = GPIO_LEVEL_HIGH, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_LOW, - .gpio39 = GPIO_LEVEL_LOW, - .gpio40 = GPIO_LEVEL_LOW, - .gpio41 = GPIO_LEVEL_LOW, - .gpio42 = GPIO_LEVEL_LOW, - .gpio43 = GPIO_LEVEL_LOW, - .gpio44 = GPIO_LEVEL_HIGH, - .gpio45 = GPIO_LEVEL_LOW, - .gpio46 = GPIO_LEVEL_HIGH, - .gpio47 = GPIO_LEVEL_HIGH, - .gpio48 = GPIO_LEVEL_HIGH, - .gpio49 = GPIO_LEVEL_LOW, - .gpio50 = GPIO_LEVEL_LOW, - .gpio51 = GPIO_LEVEL_LOW, - .gpio52 = GPIO_LEVEL_LOW, - .gpio53 = GPIO_LEVEL_LOW, - .gpio54 = GPIO_LEVEL_LOW, - .gpio55 = GPIO_LEVEL_LOW, - .gpio56 = GPIO_LEVEL_HIGH, - .gpio57 = GPIO_LEVEL_LOW, - .gpio58 = GPIO_LEVEL_LOW, - .gpio59 = GPIO_LEVEL_LOW, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_LOW, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_LOW, -}; - -/* - * GPIO SET 3 includes GPIO64 to GPIO75 - */ - -const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NATIVE, /* CLK3_SIO48 */ - .gpio65 = GPIO_MODE_NONE, - .gpio66 = GPIO_MODE_NONE, - .gpio67 = GPIO_MODE_NONE, - .gpio68 = GPIO_MODE_GPIO, /* CHP3_SPI_WP */ - .gpio69 = GPIO_MODE_NONE, - .gpio70 = GPIO_MODE_NONE, - .gpio71 = GPIO_MODE_NONE, - .gpio72 = GPIO_MODE_NATIVE, /* BATLOW# (pullup) */ - .gpio73 = GPIO_MODE_GPIO, /* CHP3_SMRT_CHG4_CTL3# */ - .gpio74 = GPIO_MODE_NONE, - .gpio75 = GPIO_MODE_NATIVE, /* SIO3_THERM_SMDATA# */ -}; - -const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, - .gpio65 = GPIO_DIR_INPUT, - .gpio66 = GPIO_DIR_INPUT, - .gpio67 = GPIO_DIR_INPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_OUTPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_LOW, - .gpio65 = GPIO_LEVEL_LOW, - .gpio66 = GPIO_LEVEL_LOW, - .gpio67 = GPIO_LEVEL_LOW, - .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_LOW, - .gpio71 = GPIO_LEVEL_LOW, - .gpio72 = GPIO_LEVEL_LOW, - .gpio73 = GPIO_LEVEL_LOW, - .gpio74 = GPIO_LEVEL_LOW, - .gpio75 = GPIO_LEVEL_LOW, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; - -#endif diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 2caf23e..87528af 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -32,12 +32,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> #include <tpm.h> -#include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif

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coreboot-gerrit February 2016