Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13120
-gerrit
commit 803f2c4af4b800c5ff1bcc36afb1cbaf71140f95
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Thu Jan 21 13:28:43 2016 -0800
include/bootblock_common.h: Provide common prototype for main()
For the common bootblock, main() is implemented in lib/, but the
prototype for main() was available from arch-specific headers.
Note that we cannot remove the prototype from the arch-specific
headers at this point, as they are needed for other stages. This is
not currently an issue, since the main() signatures are identical.
Change-Id: I436b830538cc3d9a079859bfb560fb2bad9b842a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/include/bootblock_common.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h
index 1acbef4..0f7dfae 100644
--- a/src/include/bootblock_common.h
+++ b/src/include/bootblock_common.h
@@ -16,6 +16,9 @@
#ifndef __BOOTBLOCK_COMMON_H
#define __BOOTBLOCK_COMMON_H
+/* The bootblock main() function */
+void main(void);
+
/* These are defined as weak no-ops that can be overridden by mainboard/SoC. */
void bootblock_mainboard_early_init(void);
void bootblock_mainboard_init(void);
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13674
-gerrit
commit 0d48c1645fdb13e122e5d1e17c1c40d19523b66b
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Feb 10 16:06:00 2016 -0700
util/kconfig: Ignore extra symbols in configs instead of failing
When updating an old .config file that has a symbol that has been
removed from the current Kconfig tree, kconfig will generate a warning
and fail to save the updated file. This is incredibly annoying, and
not the goal when trying to eliminate Kconfig warnings.
Instead of generating a warning, just print a message that it's being
ignored. This will remove the offending symbol, while allowing the
updated config file to be saved.
Split the change from 1 line to 3 lines to keep it at 80 characters.
Change-Id: I09d5775c9ed14bde80077b51b862a7f41bee098a
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/kconfig/confdata.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c
index e582463..436d735 100644
--- a/util/kconfig/confdata.c
+++ b/util/kconfig/confdata.c
@@ -362,7 +362,9 @@ load:
if (def == S_DEF_USER) {
sym = sym_find(line + strlen(CONFIG_));
if (!sym) {
- conf_warning("trying to assign non-existent symbol %s", line + strlen(CONFIG_));
+ conf_message(
+ "ignoring nonexistent symbol %s",
+ line + strlen(CONFIG_));
sym_add_change_count(1);
goto setsym;
}
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13677
-gerrit
commit 82b8daa981d94326e300b182f302c892001dbd88
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Feb 10 17:47:03 2016 -0800
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.
Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/mainboard/intel/apollolake_rvp/Makefile.inc | 2 +-
src/mainboard/intel/apollolake_rvp/bootblock.c | 31 +++++++++++
src/soc/intel/apollolake/Kconfig | 12 +++++
src/soc/intel/apollolake/Makefile.inc | 5 ++
src/soc/intel/apollolake/bootblock/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/include/soc/cpu.h | 24 +++++++++
src/soc/intel/apollolake/include/soc/northbridge.h | 26 +++++++++
src/soc/intel/apollolake/include/soc/pci_devs.h | 38 ++++++++++++++
src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++++
src/soc/intel/apollolake/placeholders.c | 14 +++++
src/soc/intel/apollolake/tsc_freq.c | 20 +++++++
src/soc/intel/apollolake/uart_early.c | 61 ++++++++++++++++++++++
12 files changed, 290 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc
index a48936e..8501868 100644
--- a/src/mainboard/intel/apollolake_rvp/Makefile.inc
+++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc
@@ -1 +1 @@
-# Nothing yet here
+bootblock-y += bootblock.c
diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c
new file mode 100644
index 0000000..63dca24
--- /dev/null
+++ b/src/mainboard/intel/apollolake_rvp/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/uart.h>
+
+static struct pad_config aplk_rvp_gpios[] = {
+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/
+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/
+};
+
+void bootblock_mainboard_init(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios));
+ lpss_console_uart_init();
+ console_init();
+ }
+}
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index e39fc9c..dcfbad6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -32,6 +32,13 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select SOC_INTEL_COMMON
select UDELAY_TSC
+ select CONSOLE_SERIAL
+ select BOOTBLOCK_CONSOLE
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"
@@ -63,4 +70,9 @@ config CPU_ADDR_BITS
int
default 36
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL
+ hex "MMIO base address for UART"
+ default 0xde000000
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index dccbc69..17b1357 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -8,11 +8,16 @@ subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/cache_as_ram.S
+bootblock-y += bootblock/bootblock.c
bootblock-y += gpio.c
bootblock-y += placeholders.c
+bootblock-y += tsc_freq.c
+bootblock-y += uart_early.c
romstage-y += placeholders.c
romstage-y += gpio.c
+romstage-y += uart_early.c
+
smm-y += placeholders.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
new file mode 100644
index 0000000..b1bf91e
--- /dev/null
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <bootblock_common.h>
+#include <device/pci.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
+#include <soc/uart.h>
+
+void bootblock_soc_init(void)
+{
+ device_t dev = NB_DEV_ROOT;
+
+ /* Set PCI Express BAR */
+ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
+
+ dev = P2SB_DEV;
+ /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_COMMAND, 0x6);
+}
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
new file mode 100644
index 0000000..bee58b2
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_CPU_H_
+#define _SOC_APOLLOLAKE_CPU_H_
+
+#include <cpu/x86/msr.h>
+
+#define CPUID_APOLLOLAKE_A0 0x506c8
+
+#define MSR_PLATFORM_INFO 0xce
+
+#define BASE_CLOCK_MHZ 100
+
+#endif /* _SOC_APOLLOLAKE_CPU_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
new file mode 100644
index 0000000..4a071cb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define PCIEX_SIZE (256 * MiB)
+
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+
+#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
new file mode 100644
index 0000000..5578977
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -0,0 +1,38 @@
+#ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_
+#define _SOC_APOLLOLAKE_PCI_DEVS_H_
+
+#include <rules.h>
+
+#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
+#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
+
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
+#else
+#include <arch/io.h>
+#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
+#endif
+
+/* North bridge devices */
+#define NB_DEV_SLOT_ROOT 0x00
+#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
+#define NB_DEV_ROOT _NB_DEV(ROOT)
+
+/* LPSS UART */
+#define LPSS_DEV_SLOT_UART 0x18
+#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
+#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1)
+#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2)
+#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3)
+#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0)
+#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1)
+#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
+#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+
+#define P2SB_DEV PCI_DEV(0, 0xd, 0)
+#define PMC_DEV PCI_DEV(0, 0xd, 1)
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
new file mode 100644
index 0000000..fd535fb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_UART_H_
+#define _SOC_APOLLOLAKE_UART_H_
+
+/* Clock is 100MHz * (M / N).*/
+#define UART_CLK 0x200
+# define UART_CLK_UPDATE (1 << 31)
+# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16)
+# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1)
+# define UART_CLK_EN (1 << 0)
+#define UART_RESET 0x204
+# define UART_RESET_DMA_EN (1 << 2)
+# define UART_RESET_UART_EN (3 << 0)
+
+void lpss_console_uart_init(void);
+
+#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c
index 3a818eb..825ebd4 100644
--- a/src/soc/intel/apollolake/placeholders.c
+++ b/src/soc/intel/apollolake/placeholders.c
@@ -2,6 +2,8 @@
#include <cpu/x86/smm.h>
#include <delay.h>
#include <rules.h>
+#include <console/uart.h>
+
void *cbmem_top(void)
{
@@ -17,3 +19,15 @@ void init_timer(void)
{
}
#endif
+
+#if ENV_RAMSTAGE
+/* we do not have uart driver for ramstage yet, so we put dummies */
+uintptr_t uart_platform_base(int idx)
+{
+ return 0;
+}
+unsigned int uart_platform_refclk(void)
+{
+ return 0;
+}
+#endif
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
new file mode 100644
index 0000000..b6320ed
--- /dev/null
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <soc/cpu.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+ return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+}
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
new file mode 100644
index 0000000..b94bf4d
--- /dev/null
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <soc/uart.h>
+#include <soc/pci_devs.h>
+
+static void lpss_uart_write(uint16_t reg, uint32_t val)
+{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg;
+ write32((void *)base, val);
+}
+
+void lpss_console_uart_init(void)
+{
+ uint32_t clk_sel;
+ device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
+ if(CONFIG_UART_FOR_CONSOLE > 2)
+ return;
+
+ /* Enable BAR0 for the UART -- this is where the 8250 registers hide */
+ pci_write_config32(uart, PCI_BASE_ADDRESS_0,
+ CONFIG_CONSOLE_UART_BASE_ADDRESS);
+
+ /* Enable memory access and bus master */
+ pci_write_config32(uart, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Take UART out of reset */
+ lpss_uart_write(UART_RESET, UART_RESET_UART_EN);
+
+ /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
+ clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a);
+ /* Set M and N divisor inputs and enable clock */
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE);
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN);
+
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ /* That's within 0.5% of the actual value we've set earlier */
+ return 115200 * 16;
+}
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13302
-gerrit
commit 2532ef41514b990571a1bacb1b15ca8c3b4bee86
Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com>
Date: Wed Oct 7 11:06:14 2015 -0700
cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well
This is needed in a follow-on patch to enable udelay() handling on
apollolake, which is a dependency for the console code.
Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com>
---
src/cpu/x86/tsc/Makefile.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc
index bbebda9..7e2eab2 100644
--- a/src/cpu/x86/tsc/Makefile.inc
+++ b/src/cpu/x86/tsc/Makefile.inc
@@ -1,3 +1,4 @@
+bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13669
-gerrit
commit 10b35c0a4efc0e303a85dfd3fd646b71ac944d93
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 10:52:47 2016 -0600
lib/coreboot_table: add function to allow arch code to add records
Add lb_arch_add_records() to allow the architecture code to
generically hook into the coreboot table generation.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed lb_arch_add_records() is
called when a strong symbol is provided.
Change-Id: I7c69c0ff0801392bbcf5aef586a48388b624afd4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/include/boot/coreboot_tables.h | 3 +++
src/lib/coreboot_table.c | 5 +++++
2 files changed, 8 insertions(+)
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index ff942f1..34183a0 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -22,6 +22,9 @@ void lb_board(struct lb_header *header);
/* Define this in soc or fsp driver to add specific table entries. */
void lb_framebuffer(struct lb_header *header);
+/* Allow arch to add records. */
+void lb_arch_add_records(struct lb_header *header);
+
/*
* Function to retrieve MAC address(es) from the VPD and store them in the
* coreboot table.
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 86f22c9..cc336c2 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -389,6 +389,8 @@ static void lb_record_version_timestamp(struct lb_header *header)
void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ }
+void __attribute__((weak)) lb_arch_add_records(struct lb_header *header) { }
+
static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
{
struct lb_record *rec;
@@ -540,6 +542,9 @@ unsigned long write_coreboot_table(
lb_boot_media_params(head);
+ /* Add architecture records. */
+ lb_arch_add_records(head);
+
/* Add all cbmem entries into the coreboot tables. */
cbmem_add_records_to_cbtable(head);
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13670
-gerrit
commit 24fb1c9047a9ea6775104063a557c230c4c312b9
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 10:56:06 2016 -0600
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/arch/x86/cpu.c | 23 +++++++++++++++++++++++
src/commonlib/include/commonlib/coreboot_tables.h | 8 ++++++++
2 files changed, 31 insertions(+)
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index d46e591..cba105a 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
+#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <arch/io.h>
@@ -18,6 +19,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
+#include <cpu/x86/tsc.h>
#include <arch/cpu.h>
#include <device/path.h>
#include <device/device.h>
@@ -287,3 +289,24 @@ void cpu_initialize(unsigned int index)
return;
}
+
+void lb_arch_add_records(struct lb_header *header)
+{
+ uint32_t freq_khz;
+ struct lb_tsc_info *tsc_info;
+
+ /* Don't advertise a TSC rate unless it's constant. */
+ if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ return;
+
+ freq_khz = tsc_freq_mhz() * 1000;
+
+ /* No use exposing a TSC frequency that is zero. */
+ if (freq_khz == 0)
+ return;
+
+ tsc_info = (void *)lb_new_record(header);
+ tsc_info->tag = LB_TAG_TSC_INFO;
+ tsc_info->size = sizeof(*tsc_info);
+ tsc_info->freq_khz = freq_khz;
+}
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 43adb09..5c28791 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -335,6 +335,14 @@ struct lb_cbmem_entry {
uint32_t id;
};
+#define LB_TAG_TSC_INFO 0x0032
+struct lb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13671
-gerrit
commit aeb317e4448b77a54af518e416a7879413b635b5
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 11:01:49 2016 -0600
libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSC
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information
exported in the coreboot tables as the cpu_khz frequency. That
allows get_cpu_speed() not to be called which currently relies
on the 8254 PIT. As certain x86 platforms allow that device
to be optional or turned off for power saving reasons, allow
a path where get_cpu_speed() is no longer called. Additionally,
this approach also allows the libpayload to not duplicate logic
that already exists in coreboot.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Confirmed in payload TSC frequency is honored instead of
using get_cpu_speed().
Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
payloads/libpayload/arch/x86/sysinfo.c | 11 +++++++----
payloads/libpayload/include/coreboot_tables.h | 8 ++++++++
payloads/libpayload/libc/coreboot.c | 18 ++++++++++++++++++
3 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c
index c3336b8..ddd6550 100644
--- a/payloads/libpayload/arch/x86/sysinfo.c
+++ b/payloads/libpayload/arch/x86/sysinfo.c
@@ -32,12 +32,14 @@
#include <coreboot_tables.h>
#include <multiboot_tables.h>
+#define CPU_KHZ_DEFAULT 200
+
/**
* This is a global structure that is used through the library - we set it
* up initially with some dummy values - hopefully they will be overridden.
*/
struct sysinfo_t lib_sysinfo = {
- .cpu_khz = 200,
+ .cpu_khz = CPU_KHZ_DEFAULT,
#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
.ser_ioport = CONFIG_LP_SERIAL_IOBASE,
#else
@@ -49,9 +51,6 @@ int lib_get_sysinfo(void)
{
int ret;
- /* Get the CPU speed (for delays). */
- lib_sysinfo.cpu_khz = get_cpu_speed();
-
#if IS_ENABLED(CONFIG_LP_MULTIBOOT)
/* Get the information from the multiboot tables,
* if they exist */
@@ -63,6 +62,10 @@ int lib_get_sysinfo(void)
ret = get_coreboot_info(&lib_sysinfo);
+ /* Get the CPU speed (for delays) if not set from the default value. */
+ if (lib_sysinfo.cpu_khz == CPU_KHZ_DEFAULT)
+ lib_sysinfo.cpu_khz = get_cpu_speed();
+
if (!lib_sysinfo.n_memranges) {
/* If we can't get a good memory range, use the default. */
lib_sysinfo.n_memranges = 2;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 24cbf45..276f25f 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -268,6 +268,14 @@ struct cb_boot_media_params {
uint64_t boot_media_size;
};
+#define CB_TAG_TSC_INFO 0x0032
+struct cb_tsc_info {
+ uint32_t tag;
+ uint32_t size;
+
+ uint32_t freq_khz;
+};
+
#define CB_TAG_SERIALNO 0x002a
#define CB_MAX_SERIALNO_LENGTH 32
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 3e248e1..3abd610 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -231,6 +231,19 @@ static void cb_parse_boot_media_params(unsigned char *ptr,
info->boot_media_size = bmp->boot_media_size;
}
+#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC)
+static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
+{
+ const struct cb_tsc_info *tsc_info = ptr;
+
+ if (tsc_info->freq_khz == 0)
+ return;
+
+ /* Honor the TSC frequency passed to the payload. */
+ info->cpu_khz = tsc_info->freq_khz;
+}
+#endif
+
int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
{
struct cb_header *header;
@@ -386,6 +399,11 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_BOOT_MEDIA_PARAMS:
cb_parse_boot_media_params(ptr, info);
break;
+#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC)
+ case CB_TAG_TSC_INFO:
+ cb_parse_tsc_info(ptr, info);
+ break;
+#endif
default:
cb_parse_arch_specific(rec, info);
break;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13675
-gerrit
commit 3f402352da1d2cda6ab1215be2b6d9a764c56f6b
Author: Patrick Georgi <pgeorgi(a)google.com>
Date: Thu Feb 11 00:09:30 2016 +0100
git modules: rename git submodules to avoid hierarchies
Having a git module named "3rdparty" and another one in
"3rdparty/chrome-ec" led to git failures when the latter was initialized
before the former (because of git being stupid, but then it says so on
the box, right?)
Rename modules so there's no such hierarchy (3rdparty ->
3rdparty/blobs). While at it, also rename the culprit to match the path
name (3rdparty/chrome-ec to 3rdparty/chromeec).
git will resolve this on the next git submodule update invocation (eg.
the next coreboot build).
Change-Id: Ief79074d73abeefff36a47b2e58ac6b1c047e3a7
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
.gitmodules | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/.gitmodules b/.gitmodules
index b8f28cd..ad6b899 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,4 +1,4 @@
-[submodule "3rdparty"]
+[submodule "3rdparty/blobs"]
path = 3rdparty/blobs
url = ../blobs.git
update = none
@@ -12,6 +12,6 @@
[submodule "arm-trusted-firmware"]
path = 3rdparty/arm-trusted-firmware
url = ../arm-trusted-firmware.git
-[submodule "3rdparty/chrome-ec"]
+[submodule "3rdparty/chromeec"]
path = 3rdparty/chromeec
url = ../chrome-ec.git
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13674
-gerrit
commit d72db51039ecc97a27fdb4aebdb354b96f9f8ea2
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Feb 10 16:06:00 2016 -0700
util/kconfig: Ignore extra symbols in configs instead of failing
When updating an old .config file that has a symbol that has been
removed from the current Kconfig tree, kconfig will generate a warning
and fail to save the updated file. This is incredibly annoying, and
not the goal when trying to eliminate Kconfig warnings.
Instead of generating a warning, just print a message that it's being
ignored. This will remove the offending symbol, while allowing the
updated config file to be saved.
Split the file from 1 line to 3 lines to keep it at 80 characters.
Change-Id: I09d5775c9ed14bde80077b51b862a7f41bee098a
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/kconfig/confdata.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c
index e582463..436d735 100644
--- a/util/kconfig/confdata.c
+++ b/util/kconfig/confdata.c
@@ -362,7 +362,9 @@ load:
if (def == S_DEF_USER) {
sym = sym_find(line + strlen(CONFIG_));
if (!sym) {
- conf_warning("trying to assign non-existent symbol %s", line + strlen(CONFIG_));
+ conf_message(
+ "ignoring nonexistent symbol %s",
+ line + strlen(CONFIG_));
sym_add_change_count(1);
goto setsym;
}