the following patch was just integrated into master:
commit 59ff3400b0e90f8ec4dfbf361862e5dfe0a25285
Author: Martin Roth <martinroth(a)google.com>
Date: Tue Feb 9 09:06:46 2016 -0700
Kconfig: Move defaults for CBFS_SIZE
We want the question for CBFS size to be next to the rom size in the
mainboard directory, but that doesn't seem to work for how people
want to set the defaults. Instead of having the list of exceptions
to the size, just set the defaults at the end of kconfig.
- Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into
the chipset Kconfigs (gm45, nehalem, sandybridge, x4x)
- Override the default for HAVE_INTEL_FIRMWARE on skylake.
- Move the HAVE_INTEL_FIRMWARE default setting into the firmware
Kconfig file
- Move the location of the default CBFS_SIZE=ROM_SIZE to the end of
the top level kconfig file, while leaving the question where it is.
Test=rebuild Kconfig files before and after the change, verify that
they are how they were intended to be.
Note: the Skylake boards actually changed value, because they were
picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the
0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after
the HAVE_INTEL_FIRMWARE default. Affected boards were:
Google chell, glados, & lars and Intel kunimitsu.
Change-Id: I2963a7a7eab037955558d401f5573533674a664f
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/13645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/13645 for details.
-gerrit
the following patch was just integrated into master:
commit a3e4833e5d30a904319811f420a7896675bfb12b
Author: Ben Gardner <gardner.ben(a)gmail.com>
Date: Mon Feb 8 12:18:09 2016 -0600
intel/fsp1_0: Allow the MRC cache to live in a FMAP region
The new option CONFIG_MRC_CACHE_FMAP will cause fastboot_cache.c to
look in the FMAP for a region named "RW_MRC_CACHE" and prevents adding
a CBFS file named "mrc.cache".
Tested on a fsp_baytail-based board.
Change-Id: I248f469c7e3447ac4ec7be32229fbb5584cfd2ed
Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13632
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: York Yang <york.yang(a)intel.com>
See https://review.coreboot.org/13632 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13556
-gerrit
commit 379a1bfa986befc13cfb6de5329f2eedb3d1fc8a
Author: Martin Roth <martinroth(a)google.com>
Date: Tue Feb 2 09:43:12 2016 -0700
lint: Make sure site-local isn't committed to coreboot repo
Change-Id: I1dc9469e3d001fe0d5b0517d45679b056586b5b3
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/lint/lint-stable-013-site-local | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/util/lint/lint-stable-013-site-local b/util/lint/lint-stable-013-site-local
new file mode 100755
index 0000000..43c4542
--- /dev/null
+++ b/util/lint/lint-stable-013-site-local
@@ -0,0 +1,29 @@
+#!/bin/sh
+# This file is part of the coreboot project.
+#
+# Copyright 2016 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# DESCR: Verify that site-local is not in the coreboot repository
+#
+# Because site-local is intended for local use only, it should never be
+# pushed to coreboot.org. Even for committing it for local use, it's
+# recommended that it be kept in a separate repository, and pulled in
+# as a git submodule.
+
+LC_ALL=C export LC_ALL
+
+if [ -n "$(command -v git)" ] && [ -e ".git" ]; then
+ if [ -n "$(git ls-files site-local/*)" ]; then
+ echo "Error: site-local must be kept separate from the coreboot repository."
+ fi
+fi
the following patch was just integrated into master:
commit b19425b46b0eb24e9b9cd6403d1fbeb68615b66e
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue Feb 9 18:27:37 2016 +0100
google/veyron_speedy: remove extraneous file
veyron_speedy was deduplicated as sub-board into google/veyron, so the
addition of chromeos.fmd (identical btw) wasn't useful.
Change-Id: Ic4eb6f5fefb0812cae1b9c0475e3a296d7fa65b6
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/13646 for details.
-gerrit
the following patch was just integrated into master:
commit 6b881b24a31e1fd8ee34d5e41f9600dc277d6ca7
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue Feb 9 14:01:08 2016 +0100
google/chromeos: backup -> back up
See discussion on https://review.coreboot.org/13600 and
https://review.coreboot.org/13601
Change-Id: Ia8274b0b296d6b398f75c0d91a6fded4c5f57e10
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13643
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/13643 for details.
-gerrit
the following patch was just integrated into master:
commit aaa3b4a0d73500aa62fefed744ec0b29d67c54d2
Author: Patrick Georgi <pgeorgi(a)google.com>
Date: Wed Feb 10 00:20:55 2016 +0100
gitconfig: Fix make gitconfig if USE_BLOBS is disabled
We tested for the presence of .git/modules/3rdparty, which always exists
now because of .git/modules/3rdparty/chrome-ec. Test for .../hooks
instead since that's the actual location for the later activities.
Change-Id: Id5de9f850413c2bc3525faa6cc549641304c3d47
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
Reviewed-on: https://review.coreboot.org/13650
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13650 for details.
-gerrit
the following patch was just integrated into master:
commit 8e68aff51ccb14d06db43c755f4f7ca89747d6ae
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Feb 8 11:48:26 2016 +0100
buildgcc: enable multilib for gcc
Make the gcc build system create multiple libgcc.a instances for
different ABIs.
Change-Id: I1c888bf751bf43566da8927ed0aedb53857363bf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13625 for details.
-gerrit
the following patch was just integrated into master:
commit 3834520ba1da2587e0e4bcdcc447b110314cb2ee
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Feb 1 19:47:10 2016 -0800
arch/arm64: Use correct SPSR.DAIF mask for BL31 and payload
The PSTATE mask bits for Debug exceptions, external Aborts, Interrupts
and Fast interrupts are usually best left unset: under normal
circumstances none of those exceptions should occur in firmware, and if
they do it's better to get a crash close to the code that caused it
(rather than much later when the kernel first unmasks them). For this
reason arm64_cpu_init unmasks them right after boot. However, the EL2
payload was still running with all mask bits set, which this patch
fixes.
BL31, on the other hand, explicitly wants to be entered with all masks
set (see calling convention in docs/firmware-design.md), which we had
previously not been doing. It doesn't seem to make a difference at the
moment, but since it's explicitly specified we should probably comply.
BRANCH=None
BUG=None
TEST=Booted Oak, confirmed with raw_read_daif() in payload that mask
bits are now cleared.
Change-Id: I04406da4c435ae7d44e2592c41f9807934bbc802
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 6ba55bc23fbde962d91c87dc0f982437572a69a8
Original-Change-Id: Ic5fbdd4e1cd7933c8b0c7c5fe72eac2022c9553c
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325056
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13596 for details.
-gerrit
the following patch was just integrated into master:
commit 372d0ff1d12b23f3c724f7c35fa57e4858dc0db6
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Jan 26 19:17:53 2016 -0800
arch/arm64: mmu: Spot check TTB memory attributes
On ARM64, the memory type for accessing page table descriptors during
address translation is governed by the Translation Control Register
(TCR). When the MMU code accesses the same descriptors to change page
mappings, it uses the standard memory type rules (defined by the page
table descriptor for the page that contains that table, or 'device' if
the MMU is off).
Accessing the same memory with different memory types can lead to all
kinds of fun and hard to debug effects. In particular, if the TCR says
"cacheable" and the page tables say "uncacheable", page table walks will
pull stale entries into the cache and later mmu_config_range() calls
will write directly to memory, bypassing those cache lines. This means
the translations will not get updated even after a TLB flush, and later
cache flushes/evictions may write the stale entries back to memory.
Since page table configuration is currently always done from SoC code,
we can't generally ensure that the TTB is always mapped as cacheable.
We can however save developers of future SoCs a lot of headaches and
time by spot checking the attributes when the MMU gets enabled, as this
patch does.
BRANCH=None
BUG=None
TEST=Booted Oak. Manually tested get_pte() with a few addresses.
Change-Id: I3afd29dece848c4b5f759ce2f00ca2b7433374da
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: f3947f4bb0abf4466006d5e3a962bbcb8919b12d
Original-Change-Id: I1008883e5ed4cc37d30cae5777a60287d3d01af0
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323862
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13595 for details.
-gerrit
Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13668
-gerrit
commit 1a071ded147a77ef6a1fce45202737378e355e6a
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Feb 9 23:10:17 2016 -0800
tegra132/pistachio: Increase romstage size in memlayout.ld
These SoCs have come within a kilobyte of their romstage limit, so let's
expand that a little to make room for future core code contributions.
(In the Tegra case just by copying the layout from Tegra210, because
why not? Keeps things simple.)
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug
and Urara.
Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 6 +++---
src/soc/nvidia/tegra132/include/soc/memlayout.ld | 16 ++++++++--------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index c84de40..a9800a5 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -36,9 +36,9 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 40K)
- VBOOT2_WORK(0x1a00f000, 12K)
- PRERAM_CBFS_CACHE(0x1a012000, 56K)
+ ROMSTAGE(0x1a005000, 60K)
+ VBOOT2_WORK(0x1a014000, 12K)
+ PRERAM_CBFS_CACHE(0x1a017000, 56K)
SRAM_END(0x1a066000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
index e3d221e..a8f8a34 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
@@ -29,17 +29,17 @@ SECTIONS
{
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
- PRERAM_CBFS_CACHE(0x40002000, 72K)
- VBOOT2_WORK(0x40014000, 12K)
+ PRERAM_CBFS_CACHE(0x40002000, 36K)
+ VBOOT2_WORK(0x4000B000, 12K)
#if ENV_ARM64
- STACK(0x40017000, 3K)
+ STACK(0x4000E000, 3K)
#else /* AVP gets a separate stack to avoid any chance of handoff races. */
- STACK(0x40017C00, 3K)
+ STACK(0x4000EC00, 3K)
#endif
- TIMESTAMP(0x40018800, 2K)
- BOOTBLOCK(0x40019000, 22K)
- VERSTAGE(0x4001e800, 55K)
- ROMSTAGE(0x4002c400, 77K)
+ TIMESTAMP(0x4000F800, 2K)
+ BOOTBLOCK(0x40010000, 28K)
+ VERSTAGE(0x40017000, 64K)
+ ROMSTAGE(0x40027000, 100K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)