Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13677
-gerrit
commit 2022c88c3754ce9c0d7097703555ccb425489fe9
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Feb 10 17:47:03 2016 -0800
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.
Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/mainboard/intel/apollolake_rvp/Makefile.inc | 2 +-
src/mainboard/intel/apollolake_rvp/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/Kconfig | 12 +++++
src/soc/intel/apollolake/Makefile.inc | 6 +++
src/soc/intel/apollolake/bootblock/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/include/soc/bootblock.h | 2 +
src/soc/intel/apollolake/include/soc/cpu.h | 24 +++++++++
src/soc/intel/apollolake/include/soc/northbridge.h | 26 +++++++++
src/soc/intel/apollolake/include/soc/pci_devs.h | 40 ++++++++++++++
src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++++
src/soc/intel/apollolake/placeholders.c | 15 ++++++
src/soc/intel/apollolake/tsc_freq.c | 20 +++++++
src/soc/intel/apollolake/uart_early.c | 61 ++++++++++++++++++++++
13 files changed, 295 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc
index a48936e..8501868 100644
--- a/src/mainboard/intel/apollolake_rvp/Makefile.inc
+++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc
@@ -1 +1 @@
-# Nothing yet here
+bootblock-y += bootblock.c
diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c
new file mode 100644
index 0000000..c1b7d41
--- /dev/null
+++ b/src/mainboard/intel/apollolake_rvp/bootblock.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/uart.h>
+
+static struct pad_config aplk_rvp_gpios[] = {
+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/
+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios));
+ lpss_console_uart_init();
+ }
+}
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index e39fc9c..dcfbad6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -32,6 +32,13 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select SOC_INTEL_COMMON
select UDELAY_TSC
+ select CONSOLE_SERIAL
+ select BOOTBLOCK_CONSOLE
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"
@@ -63,4 +70,9 @@ config CPU_ADDR_BITS
int
default 36
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL
+ hex "MMIO base address for UART"
+ default 0xde000000
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e58be86..7f8beb0 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,14 +9,20 @@ subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
+bootblock-y += bootblock/bootblock.c
bootblock-y += gpio.c
bootblock-y += placeholders.c
+bootblock-y += tsc_freq.c
+bootblock-y += uart_early.c
romstage-y += placeholders.c
romstage-y += gpio.c
+romstage-y += uart_early.c
+
smm-y += placeholders.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
+ramstage-y += uart_early.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 44e04e6..dc84c02 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -1,4 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <bootblock_common.h>
+#include <device/pci.h>
#include <soc/bootblock.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
+
void bootblock_c_entry(void)
{
+ device_t dev = NB_DEV_ROOT;
+
+ /* Set PCI Express BAR */
+ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
+
+ dev = P2SB_DEV;
+ /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ /* Call lib/bootblock.c main */
+ main();
}
diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h
index 7c323d4..23cfdc4 100644
--- a/src/soc/intel/apollolake/include/soc/bootblock.h
+++ b/src/soc/intel/apollolake/include/soc/bootblock.h
@@ -1,4 +1,6 @@
#ifndef _SOC_APOLLOLAKE_BOOTBLOCK_H_
#define _SOC_APOLLOLAKE_BOOTBLOCK_H_
void bootblock_c_entry(void);
+/* provide prototype for lib/bootblock.c main as workaround */
+void main(void);
#endif
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
new file mode 100644
index 0000000..bee58b2
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_CPU_H_
+#define _SOC_APOLLOLAKE_CPU_H_
+
+#include <cpu/x86/msr.h>
+
+#define CPUID_APOLLOLAKE_A0 0x506c8
+
+#define MSR_PLATFORM_INFO 0xce
+
+#define BASE_CLOCK_MHZ 100
+
+#endif /* _SOC_APOLLOLAKE_CPU_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
new file mode 100644
index 0000000..4a071cb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define PCIEX_SIZE (256 * MiB)
+
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+
+#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
new file mode 100644
index 0000000..3116389
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -0,0 +1,40 @@
+#ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_
+#define _SOC_APOLLOLAKE_PCI_DEVS_H_
+
+#include <rules.h>
+
+#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
+
+
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
+#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
+#else
+#include <arch/io.h>
+#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
+#endif
+
+/* North bridge devices */
+#define NB_DEV_SLOT_ROOT 0x00
+#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
+#define NB_DEV_ROOT _NB_DEV(ROOT)
+
+/* LPSS UART */
+#define LPSS_DEV_SLOT_UART 0x18
+#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
+#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1)
+#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2)
+#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3)
+#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0)
+#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1)
+#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
+#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+
+#define P2SB_DEV PCI_DEV(0, 0xd, 0)
+#define PMC_DEV PCI_DEV(0, 0xd, 1)
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
new file mode 100644
index 0000000..fd535fb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_UART_H_
+#define _SOC_APOLLOLAKE_UART_H_
+
+/* Clock is 100MHz * (M / N).*/
+#define UART_CLK 0x200
+# define UART_CLK_UPDATE (1 << 31)
+# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16)
+# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1)
+# define UART_CLK_EN (1 << 0)
+#define UART_RESET 0x204
+# define UART_RESET_DMA_EN (1 << 2)
+# define UART_RESET_UART_EN (3 << 0)
+
+void lpss_console_uart_init(void);
+
+#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c
index 3a818eb..691ee6a 100644
--- a/src/soc/intel/apollolake/placeholders.c
+++ b/src/soc/intel/apollolake/placeholders.c
@@ -2,6 +2,8 @@
#include <cpu/x86/smm.h>
#include <delay.h>
#include <rules.h>
+#include <console/uart.h>
+
void *cbmem_top(void)
{
@@ -17,3 +19,16 @@ void init_timer(void)
{
}
#endif
+#ifdef dfd
+#if ENV_RAMSTAGE
+/* we do not have uart driver for ramstage yet, so we put dummies */
+uintptr_t uart_platform_base(int idx)
+{
+ return 0;
+}
+unsigned int uart_platform_refclk(void)
+{
+ return 0;
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
new file mode 100644
index 0000000..b6320ed
--- /dev/null
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <soc/cpu.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+ return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+}
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
new file mode 100644
index 0000000..b94bf4d
--- /dev/null
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <soc/uart.h>
+#include <soc/pci_devs.h>
+
+static void lpss_uart_write(uint16_t reg, uint32_t val)
+{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg;
+ write32((void *)base, val);
+}
+
+void lpss_console_uart_init(void)
+{
+ uint32_t clk_sel;
+ device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
+ if(CONFIG_UART_FOR_CONSOLE > 2)
+ return;
+
+ /* Enable BAR0 for the UART -- this is where the 8250 registers hide */
+ pci_write_config32(uart, PCI_BASE_ADDRESS_0,
+ CONFIG_CONSOLE_UART_BASE_ADDRESS);
+
+ /* Enable memory access and bus master */
+ pci_write_config32(uart, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Take UART out of reset */
+ lpss_uart_write(UART_RESET, UART_RESET_UART_EN);
+
+ /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
+ clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a);
+ /* Set M and N divisor inputs and enable clock */
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE);
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN);
+
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ /* That's within 0.5% of the actual value we've set earlier */
+ return 115200 * 16;
+}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13672
-gerrit
commit dd821745830ef0bb1122f9e253615051421b878c
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Feb 10 18:07:52 2016 +0100
util/cbfstool: Improve heuristic for cbfs header pointer protection
cbfstool has a routine to deal with old images that may encourage it to
overwrite the master header. That routine is triggered for
"cbfstool add-master-header" prepared images even though these are not
at risk, and - worse - destroys the chain structure (through a negative
file length), so avoid touching such images.
Change-Id: I9d0bbe3e6300b9b9f3e50347737d1850f83ddad8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/cbfstool/cbfs_image.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 314ea57..95e6f42 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -110,11 +110,18 @@ static int cbfs_fix_legacy_size(struct cbfs_image *image, char *hdr_loc)
// A bug in old cbfstool may produce extra few bytes (by alignment) and
// cause cbfstool to overwrite things after free space -- which is
// usually CBFS header on x86. We need to workaround that.
+ // Except when we run across a file that contains the actual header,
+ // in which case this image is a safe, new-style
+ // `cbfstool add-master-header` based image.
struct cbfs_file *entry, *first = NULL, *last = NULL;
for (first = entry = cbfs_find_first_entry(image);
entry && cbfs_is_valid_entry(image, entry);
entry = cbfs_find_next_entry(image, entry)) {
+ /* Is the header guarded by a CBFS file entry? Then exit */
+ if (((char *)entry) + ntohl(entry->offset) == hdr_loc) {
+ return 0;
+ }
last = entry;
}
if ((char *)first < (char *)hdr_loc &&
the following patch was just integrated into master:
commit c52d4f5745bde9e9d0dedc761ae3c0566aa5e2e1
Author: Ruilin Hao <rlhao(a)marvell.com>
Date: Thu Dec 10 00:36:10 2015 -0800
util/marvell: Add Marvell doimage utility and dependency in relevant Makefile
- Add the doimage sources in util/marvell
- Add dependency in root makefile
- Add dependency in makefile for armada38x soc
BUG=chrome-os-partner:47462
TEST=emerge-cyclone coreboot
BRANCH=tot
Change-Id: I81b30e0865cbd619a41659c3f2819ad3bafc5f24
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 4b2a990150580e0b879a346ed8b71b3765b66bab
Original-Change-Id: I7e89b5e96206fde97ce69c296850122fd6c858f9
Original-Signed-off-by: Kefei Yao <kfyao(a)marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/318046
Original-Commit-Ready: Kan Yan <kyan(a)google.com>
Original-Tested-by: Kan Yan <kyan(a)google.com>
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Reviewed-by: Kan Yan <kyan(a)google.com>
Original-Reviewed-by: Yuji Sasaki <sasakiy(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13137
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/13137 for details.
-gerrit
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13684
-gerrit
commit 347f1b7485bb10513aea7eb5d85df90f7d964ba5
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Thu Feb 11 08:36:50 2016 +0100
device/pci_rom: Rename missleading ON_DEVICE_ROM_RUN
The Kconfig option ON_DEVICE_ROM_RUN suggest that PCI option roms
are runned, but in fact it only controls the loading
of PCI based option roms.
At the moment coreboot only executes Option Roms if they are
VGA Options Roms and the VGA Option Rom execution flag is enabled.
Setting ON_DEVICE_ROM_RUN with VGA Option Rom execution disabled
has no effect.
Clarify that this flag controls the loading behaviour and not the
execution behaviour.
Change-Id: Ie3e503cb145f9b7ce613755e60ac0f6c00f2bcdb
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
src/device/Kconfig | 6 +++---
src/device/pci_rom.c | 10 ++++------
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 0113545..70a362f 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -84,13 +84,13 @@ config ALWAYS_LOAD_OPROM
are needed for the kernel's display driver to know how a piece of
hardware is configured to be used.
-config ON_DEVICE_ROM_RUN
- bool "Run Option ROMs on PCI devices"
+config ON_DEVICE_ROM_LOAD
+ bool "Load Option ROMs on PCI devices"
default n if PAYLOAD_SEABIOS
default y if !PAYLOAD_SEABIOS
depends on PCI
help
- Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
+ Load Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
If disabled, only Option ROMs stored in CBFS will be executed by
coreboot. If you are concerned about security, you might want to
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index ad6c7e4..8366fea 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -52,6 +52,10 @@ struct rom_header *pci_rom_probe(struct device *dev)
if (rom_header) {
printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
dev_path(dev), rom_header);
+ } else if (!IS_ENABLED(CONFIG_ON_DEVICE_ROM_LOAD)) {
+ printk(BIOS_DEBUG, "PCI Option ROM loading disabled "
+ "for %s\n", dev_path(dev));
+ return NULL;
} else {
uintptr_t rom_address;
@@ -70,15 +74,9 @@ struct rom_header *pci_rom_probe(struct device *dev)
rom_address|PCI_ROM_ADDRESS_ENABLE);
}
-#if CONFIG_ON_DEVICE_ROM_RUN
printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n",
dev_path(dev), (unsigned long)rom_address);
rom_header = (struct rom_header *)rom_address;
-#else
- printk(BIOS_DEBUG, "Option ROM execution disabled "
- "for %s\n", dev_path(dev));
- return NULL;
-#endif
}
printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "