the following patch was just integrated into master:
commit 9f428137b75031d5cd6a88dc9c5c2a8237acde28
Author: Patrick Georgi <pgeorgi(a)google.com>
Date: Thu Feb 11 00:09:30 2016 +0100
git modules: rename git submodules to avoid hierarchies
Having a git module named "3rdparty" and another one in
"3rdparty/chrome-ec" led to git failures when the latter was initialized
before the former (because of git being stupid, but then it says so on
the box, right?)
Rename modules so there's no such hierarchy (3rdparty ->
3rdparty/blobs). While at it, also rename the culprit to match the path
name (3rdparty/chrome-ec to 3rdparty/chromeec).
git will resolve this on the next git submodule update invocation (eg.
the next coreboot build).
Change-Id: Ief79074d73abeefff36a47b2e58ac6b1c047e3a7
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
Reviewed-on: https://review.coreboot.org/13675
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/13675 for details.
-gerrit
the following patch was just integrated into master:
commit 1509c908aa14f591ef21cf9c38f97094b4a14c4d
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Feb 10 22:27:42 2016 +0100
3rdparty/chromeec: fix build with paths containing "@"
Move submodule forward to a newer upstream master to fix the build on
paths containing "@", as can happen on jenkins.
Change-Id: Ie74012725c379909d5bf631f9cc9969106ca52b8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13673
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13673 for details.
-gerrit
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13677
-gerrit
commit 32efb1433b0449d6e82338f54fe5ecd393381937
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Feb 10 17:47:03 2016 -0800
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.
Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/mainboard/intel/apollolake_rvp/Makefile.inc | 2 +-
src/mainboard/intel/apollolake_rvp/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/Kconfig | 12 +++++
src/soc/intel/apollolake/Makefile.inc | 6 +++
src/soc/intel/apollolake/bootblock/bootblock.c | 30 ++++++++++-
src/soc/intel/apollolake/include/soc/bootblock.h | 2 +
src/soc/intel/apollolake/include/soc/cpu.h | 24 +++++++++
src/soc/intel/apollolake/include/soc/northbridge.h | 26 +++++++++
src/soc/intel/apollolake/include/soc/pci_devs.h | 40 ++++++++++++++
src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++++
src/soc/intel/apollolake/tsc_freq.c | 20 +++++++
src/soc/intel/apollolake/uart_early.c | 61 ++++++++++++++++++++++
12 files changed, 279 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc
index a48936e..8501868 100644
--- a/src/mainboard/intel/apollolake_rvp/Makefile.inc
+++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc
@@ -1 +1 @@
-# Nothing yet here
+bootblock-y += bootblock.c
diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c
new file mode 100644
index 0000000..c1b7d41
--- /dev/null
+++ b/src/mainboard/intel/apollolake_rvp/bootblock.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/uart.h>
+
+static struct pad_config aplk_rvp_gpios[] = {
+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/
+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios));
+ lpss_console_uart_init();
+ }
+}
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index e39fc9c..dcfbad6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -32,6 +32,13 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select SOC_INTEL_COMMON
select UDELAY_TSC
+ select CONSOLE_SERIAL
+ select BOOTBLOCK_CONSOLE
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"
@@ -63,4 +70,9 @@ config CPU_ADDR_BITS
int
default 36
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL
+ hex "MMIO base address for UART"
+ default 0xde000000
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e58be86..7f8beb0 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,14 +9,20 @@ subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
+bootblock-y += bootblock/bootblock.c
bootblock-y += gpio.c
bootblock-y += placeholders.c
+bootblock-y += tsc_freq.c
+bootblock-y += uart_early.c
romstage-y += placeholders.c
romstage-y += gpio.c
+romstage-y += uart_early.c
+
smm-y += placeholders.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
+ramstage-y += uart_early.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index dc0b183..d3a78e1 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -1,6 +1,34 @@
-#include <soc/bootblock.h>
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
#include <arch/cpu.h>
+#include <bootblock_common.h>
+#include <device/pci.h>
+#include <soc/bootblock.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
void asmlinkage bootblock_c_entry(void)
{
+ device_t dev = NB_DEV_ROOT;
+
+ /* Set PCI Express BAR */
+ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
+
+ dev = P2SB_DEV;
+ /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ /* Call lib/bootblock.c main */
+ main();
}
diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h
index 933c7fe..655188b 100644
--- a/src/soc/intel/apollolake/include/soc/bootblock.h
+++ b/src/soc/intel/apollolake/include/soc/bootblock.h
@@ -3,4 +3,6 @@
#include <arch/cpu.h>
void asmlinkage bootblock_c_entry(void);
+/* provide prototype for lib/bootblock.c main as workaround */
+void main(void);
#endif
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
new file mode 100644
index 0000000..bee58b2
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_CPU_H_
+#define _SOC_APOLLOLAKE_CPU_H_
+
+#include <cpu/x86/msr.h>
+
+#define CPUID_APOLLOLAKE_A0 0x506c8
+
+#define MSR_PLATFORM_INFO 0xce
+
+#define BASE_CLOCK_MHZ 100
+
+#endif /* _SOC_APOLLOLAKE_CPU_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
new file mode 100644
index 0000000..4a071cb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define PCIEX_SIZE (256 * MiB)
+
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+
+#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
new file mode 100644
index 0000000..3116389
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -0,0 +1,40 @@
+#ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_
+#define _SOC_APOLLOLAKE_PCI_DEVS_H_
+
+#include <rules.h>
+
+#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
+
+
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
+#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
+#else
+#include <arch/io.h>
+#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
+#endif
+
+/* North bridge devices */
+#define NB_DEV_SLOT_ROOT 0x00
+#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
+#define NB_DEV_ROOT _NB_DEV(ROOT)
+
+/* LPSS UART */
+#define LPSS_DEV_SLOT_UART 0x18
+#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
+#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1)
+#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2)
+#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3)
+#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0)
+#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1)
+#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
+#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+
+#define P2SB_DEV PCI_DEV(0, 0xd, 0)
+#define PMC_DEV PCI_DEV(0, 0xd, 1)
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
new file mode 100644
index 0000000..fd535fb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_UART_H_
+#define _SOC_APOLLOLAKE_UART_H_
+
+/* Clock is 100MHz * (M / N).*/
+#define UART_CLK 0x200
+# define UART_CLK_UPDATE (1 << 31)
+# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16)
+# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1)
+# define UART_CLK_EN (1 << 0)
+#define UART_RESET 0x204
+# define UART_RESET_DMA_EN (1 << 2)
+# define UART_RESET_UART_EN (3 << 0)
+
+void lpss_console_uart_init(void);
+
+#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
new file mode 100644
index 0000000..b6320ed
--- /dev/null
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <soc/cpu.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+ return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+}
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
new file mode 100644
index 0000000..d3b1d80
--- /dev/null
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <soc/uart.h>
+#include <soc/pci_devs.h>
+
+static void lpss_uart_write(uint16_t reg, uint32_t val)
+{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg;
+ write32((void *)base, val);
+}
+
+void lpss_console_uart_init(void)
+{
+ uint32_t clk_sel;
+ device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
+ if (CONFIG_UART_FOR_CONSOLE > 2)
+ return;
+
+ /* Enable BAR0 for the UART -- this is where the 8250 registers hide */
+ pci_write_config32(uart, PCI_BASE_ADDRESS_0,
+ CONFIG_CONSOLE_UART_BASE_ADDRESS);
+
+ /* Enable memory access and bus master */
+ pci_write_config32(uart, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Take UART out of reset */
+ lpss_uart_write(UART_RESET, UART_RESET_UART_EN);
+
+ /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
+ clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a);
+ /* Set M and N divisor inputs and enable clock */
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE);
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN);
+
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ /* That's within 0.5% of the actual value we've set earlier */
+ return 115200 * 16;
+}
Yves Roth (yves.r.roth(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13287
-gerrit
commit b4ff4f6dc34a29aa8d0bbe8211ea749631acfbca
Author: Damien Roth <yves.r.roth(a)gmail.com>
Date: Mon Jan 18 12:57:11 2016 -0700
cpu/allwinner: Update license headers
These licence headers were not compliant with the coreboot standard.
Change-Id: I85bb5f971ab1f8ac3e9589f712370fbf09716b67
Signed-off-by: Damien Roth <yves.r.roth(a)gmail.com>
---
src/cpu/allwinner/a10/bootblock.c | 16 ++++++++++++++--
src/cpu/allwinner/a10/bootblock_media.c | 16 ++++++++++++++--
src/cpu/allwinner/a10/cbmem.c | 16 ++++++++++++++--
src/cpu/allwinner/a10/chip.h | 16 ++++++++++++++--
src/cpu/allwinner/a10/clock.c | 15 +++++++++++++--
src/cpu/allwinner/a10/clock.h | 15 +++++++++++++--
src/cpu/allwinner/a10/cpu.c | 16 ++++++++++++++--
src/cpu/allwinner/a10/dramc.h | 21 ++++++++++++++++-----
src/cpu/allwinner/a10/gpio.c | 15 +++++++++++++--
src/cpu/allwinner/a10/gpio.h | 14 ++++++++++++--
src/cpu/allwinner/a10/memmap.h | 15 +++++++++++++--
src/cpu/allwinner/a10/monotonic_timer.c | 16 ++++++++++++++--
src/cpu/allwinner/a10/pinmux.c | 17 +++++++++++++++--
src/cpu/allwinner/a10/ram_segs.h | 16 ++++++++++++++--
src/cpu/allwinner/a10/raminit.c | 21 ++++++++++++++++-----
src/cpu/allwinner/a10/timer.c | 16 ++++++++++++++--
src/cpu/allwinner/a10/timer.h | 15 +++++++++++++--
src/cpu/allwinner/a10/twi.c | 19 +++++++++++++++----
src/cpu/allwinner/a10/twi.h | 15 +++++++++++++--
src/cpu/allwinner/a10/uart.c | 17 +++++++++++++++--
src/cpu/allwinner/a10/uart.h | 16 ++++++++++++++--
src/cpu/allwinner/a10/uart_console.c | 15 +++++++++++++--
22 files changed, 306 insertions(+), 52 deletions(-)
diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c
index 808982c..471104b 100644
--- a/src/cpu/allwinner/a10/bootblock.c
+++ b/src/cpu/allwinner/a10/bootblock.c
@@ -1,9 +1,21 @@
/*
- * Allwinner A10 bootblock initialization
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Allwinner A10 bootblock initialization
+ *
*/
#include <types.h>
diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c
index 17c6039..c89cac0 100644
--- a/src/cpu/allwinner/a10/bootblock_media.c
+++ b/src/cpu/allwinner/a10/bootblock_media.c
@@ -1,8 +1,20 @@
/*
- * CBFS accessors for bootblock stage.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * CBFS accessors for bootblock stage.
+ *
*/
#include <boot_device.h>
#include <console/console.h>
diff --git a/src/cpu/allwinner/a10/cbmem.c b/src/cpu/allwinner/a10/cbmem.c
index e051f06..a4c563a 100644
--- a/src/cpu/allwinner/a10/cbmem.c
+++ b/src/cpu/allwinner/a10/cbmem.c
@@ -1,8 +1,20 @@
/*
- * Provides cbmem utilities for romstage and ramstage
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Provides cbmem utilities for romstage and ramstage
+ *
*/
#include "ram_segs.h"
diff --git a/src/cpu/allwinner/a10/chip.h b/src/cpu/allwinner/a10/chip.h
index 16f60c0..af419ea 100644
--- a/src/cpu/allwinner/a10/chip.h
+++ b/src/cpu/allwinner/a10/chip.h
@@ -1,8 +1,20 @@
/*
- * Allwinnwer A10 devicetree config struct
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Allwinnwer A10 devicetree config struct
+ *
*/
#include <types.h>
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index c22b242..ae50e06 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -1,8 +1,19 @@
/*
- * Helpers for clock control and gating on Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Helpers for clock control and gating on Allwinner CPUs
*/
#include "clock.h"
diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h
index 0a9cfd6..d1729a3 100644
--- a/src/cpu/allwinner/a10/clock.h
+++ b/src/cpu/allwinner/a10/clock.h
@@ -1,10 +1,21 @@
/*
- * Definitions for clock control and gating on Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007-2011 Allwinner Technology Co., Ltd.
* Tom Cubie <tangliang(a)allwinnertech.com>
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License. or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Definitions for clock control and gating on Allwinner CPUs
*/
#ifndef CPU_ALLWINNER_A10_CLOCK_H
diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c
index c2cbc2f..60b93be 100644
--- a/src/cpu/allwinner/a10/cpu.c
+++ b/src/cpu/allwinner/a10/cpu.c
@@ -1,8 +1,20 @@
/*
- * Ramstage initialization for Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Ramstage initialization for Allwinner CPUs
+ *
*/
#include <console/console.h>
diff --git a/src/cpu/allwinner/a10/dramc.h b/src/cpu/allwinner/a10/dramc.h
index 7d44d83..fe50acd 100644
--- a/src/cpu/allwinner/a10/dramc.h
+++ b/src/cpu/allwinner/a10/dramc.h
@@ -1,14 +1,25 @@
/*
- * Allwinner A10 platform dram register definition.
- *
- * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
- * and earlier U-Boot Allwiner A10 SPL work
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007-2012 Allwinner Technology Co., Ltd.
* Berg Xing <bergxing(a)allwinnertech.com>
* Tom Cubie <tangliang(a)allwinnertech.com>
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Allwinner A10 platform dram register definition.
+ *
+ * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
+ * and earlier U-Boot Allwiner A10 SPL work
*/
#ifndef CPU_ALLWINNER_A10_DRAMC_H
diff --git a/src/cpu/allwinner/a10/gpio.c b/src/cpu/allwinner/a10/gpio.c
index 95854e5..1614c5f 100644
--- a/src/cpu/allwinner/a10/gpio.c
+++ b/src/cpu/allwinner/a10/gpio.c
@@ -1,8 +1,19 @@
/*
- * Basic GPIO helpers for Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Basic GPIO helpers for Allwinner CPUs
*/
#include "gpio.h"
diff --git a/src/cpu/allwinner/a10/gpio.h b/src/cpu/allwinner/a10/gpio.h
index b20d759..8d95074 100644
--- a/src/cpu/allwinner/a10/gpio.h
+++ b/src/cpu/allwinner/a10/gpio.h
@@ -1,8 +1,18 @@
/*
- * Definitions for GPIO and pin multiplexing on Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Definitions for GPIO and pin multiplexing on Allwinner CPUs
*/
#ifndef __CPU_ALLWINNER_A10_PINMUX_H
diff --git a/src/cpu/allwinner/a10/memmap.h b/src/cpu/allwinner/a10/memmap.h
index 78d81dc..2c02ec8 100644
--- a/src/cpu/allwinner/a10/memmap.h
+++ b/src/cpu/allwinner/a10/memmap.h
@@ -1,10 +1,21 @@
/*
- * Memory map definitions for Allwinner A10 CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007-2011 Allwinner Technology Co., Ltd.
* Tom Cubie <tangliang(a)allwinnertech.com>
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Memory map definitions for Allwinner A10 CPUs
*/
#ifndef CPU_ALLWINNER_A10_MEMMAP_H
diff --git a/src/cpu/allwinner/a10/monotonic_timer.c b/src/cpu/allwinner/a10/monotonic_timer.c
index 16d478a..479dee9 100644
--- a/src/cpu/allwinner/a10/monotonic_timer.c
+++ b/src/cpu/allwinner/a10/monotonic_timer.c
@@ -1,8 +1,20 @@
/*
- * Placeholder for code to come (needed to complete build)
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the Licenseor (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Placeholder for code to come (needed to complete build)
+ *
*/
#include <timer.h>
diff --git a/src/cpu/allwinner/a10/pinmux.c b/src/cpu/allwinner/a10/pinmux.c
index f5ed19a..b8bf607 100644
--- a/src/cpu/allwinner/a10/pinmux.c
+++ b/src/cpu/allwinner/a10/pinmux.c
@@ -1,8 +1,21 @@
/*
- * Helpers to multiplex and configure pins on Allwinner SoCs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Helpers to multiplex and configure pins on Allwinner SoCs
+ *
*/
#include "gpio.h"
diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h
index 26944e4..fa3684f 100644
--- a/src/cpu/allwinner/a10/ram_segs.h
+++ b/src/cpu/allwinner/a10/ram_segs.h
@@ -1,8 +1,20 @@
/*
- * How we use DRAM on Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * How we use DRAM on Allwinner CPUs
*/
#include <config.h>
diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c
index 28fd408..e917e6e 100644
--- a/src/cpu/allwinner/a10/raminit.c
+++ b/src/cpu/allwinner/a10/raminit.c
@@ -1,8 +1,5 @@
/*
- * Allwinner A10 DRAM controller initialization
- *
- * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
- * and earlier U-Boot Allwiner A10 SPL work
+ * This file is part of the coreboot project.
*
* Copyright (C) 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net>
* Copyright (C) 2013 Luke Kenneth Casson Leighton <lkcl(a)lkcl.net>
@@ -10,7 +7,21 @@
* Berg Xing <bergxing(a)allwinnertech.com>
* Tom Cubie <tangliang(a)allwinnertech.com>
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Allwinner A10 DRAM controller initialization
+ *
+ * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
+ * and earlier U-Boot Allwiner A10 SPL work
*/
#include "clock.h"
diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c
index 5082114..3eacf54 100644
--- a/src/cpu/allwinner/a10/timer.c
+++ b/src/cpu/allwinner/a10/timer.c
@@ -1,8 +1,20 @@
/*
- * Timer control and delays for Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Timer control and delays for Allwinner CPUs
+ *
*/
#include "timer.h"
diff --git a/src/cpu/allwinner/a10/timer.h b/src/cpu/allwinner/a10/timer.h
index cb12753..7e10f2f 100644
--- a/src/cpu/allwinner/a10/timer.h
+++ b/src/cpu/allwinner/a10/timer.h
@@ -1,10 +1,21 @@
/*
- * Definitions for timer control on Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007-2011 Allwinner Technology Co., Ltd.
* Tom Cubie <tangliang(a)allwinnertech.com>
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Definitions for timer control on Allwinner CPUs
*/
#ifndef CPU_ALLWINNER_A10_TIMER_H
diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c
index f780721..69e08ca 100644
--- a/src/cpu/allwinner/a10/twi.c
+++ b/src/cpu/allwinner/a10/twi.c
@@ -1,12 +1,23 @@
/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net>
+ * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
* Setup helpers for Two Wire Interface (TWI) (I²C) Allwinner CPUs
*
* Only functionality for I²C master is provided.
* Largely based on the uboot-sunxi code.
- *
- * Copyright (C) 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net>
- * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
*/
#include "memmap.h"
diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h
index 3dbb302..a8ebdf3 100644
--- a/src/cpu/allwinner/a10/twi.h
+++ b/src/cpu/allwinner/a10/twi.h
@@ -1,8 +1,19 @@
/*
- * Definitions Two Wire Interface (TWI) (I²C) Allwinner CPUs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Definitions Two Wire Interface (TWI) (I²C) Allwinner CPUs
*/
#ifndef CPU_ALLWINNER_A10_TWI_H
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
index 3c02867..b976d30 100644
--- a/src/cpu/allwinner/a10/uart.c
+++ b/src/cpu/allwinner/a10/uart.c
@@ -1,8 +1,21 @@
/*
- * Uart setup helpers for Allwinner SoCs
+ * This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Uart setup helpers for Allwinner SoCs
+ *
+ *
*/
#include "uart.h"
diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h
index aa94362..a5ed2a9 100644
--- a/src/cpu/allwinner/a10/uart.h
+++ b/src/cpu/allwinner/a10/uart.h
@@ -1,4 +1,18 @@
/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
* Definitions for UART on Allwinner CPUs
*
* The UART on the A10 seems to be 8250-compatible, however, this has not been
@@ -6,8 +20,6 @@
* have to re-implement it ARM-style for the time being. The register
* definitions are present in <uart7250.h>, and are not redefined here.
*
- * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
*/
#ifndef CPU_ALLWINNER_A10_UART_H
diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c
index 35bff79..64c2a4f 100644
--- a/src/cpu/allwinner/a10/uart_console.c
+++ b/src/cpu/allwinner/a10/uart_console.c
@@ -1,9 +1,20 @@
/*
- * Glue to UART code to enable serial console
+ * This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
- * Subject to the GNU GPL v2, or (at your option) any later version.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Glue to UART code to enable serial console
*/
#include <types.h>
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13677
-gerrit
commit 39c2c3b2cf008be51dd2ab2069065446337c4220
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Feb 10 17:47:03 2016 -0800
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.
Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/mainboard/intel/apollolake_rvp/Makefile.inc | 2 +-
src/mainboard/intel/apollolake_rvp/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/Kconfig | 12 +++++
src/soc/intel/apollolake/Makefile.inc | 6 +++
src/soc/intel/apollolake/bootblock/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/include/soc/bootblock.h | 4 ++
src/soc/intel/apollolake/include/soc/cpu.h | 24 +++++++++
src/soc/intel/apollolake/include/soc/northbridge.h | 26 +++++++++
src/soc/intel/apollolake/include/soc/pci_devs.h | 40 ++++++++++++++
src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++++
src/soc/intel/apollolake/tsc_freq.c | 20 +++++++
src/soc/intel/apollolake/uart_early.c | 61 ++++++++++++++++++++++
12 files changed, 282 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc
index a48936e..8501868 100644
--- a/src/mainboard/intel/apollolake_rvp/Makefile.inc
+++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc
@@ -1 +1 @@
-# Nothing yet here
+bootblock-y += bootblock.c
diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c
new file mode 100644
index 0000000..c1b7d41
--- /dev/null
+++ b/src/mainboard/intel/apollolake_rvp/bootblock.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/uart.h>
+
+static struct pad_config aplk_rvp_gpios[] = {
+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/
+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios));
+ lpss_console_uart_init();
+ }
+}
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index e39fc9c..dcfbad6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -32,6 +32,13 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select SOC_INTEL_COMMON
select UDELAY_TSC
+ select CONSOLE_SERIAL
+ select BOOTBLOCK_CONSOLE
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"
@@ -63,4 +70,9 @@ config CPU_ADDR_BITS
int
default 36
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL
+ hex "MMIO base address for UART"
+ default 0xde000000
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e58be86..7f8beb0 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,14 +9,20 @@ subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
+bootblock-y += bootblock/bootblock.c
bootblock-y += gpio.c
bootblock-y += placeholders.c
+bootblock-y += tsc_freq.c
+bootblock-y += uart_early.c
romstage-y += placeholders.c
romstage-y += gpio.c
+romstage-y += uart_early.c
+
smm-y += placeholders.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
+ramstage-y += uart_early.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index a5f3beb..d3a78e1 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -1,4 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <arch/cpu.h>
+#include <bootblock_common.h>
+#include <device/pci.h>
#include <soc/bootblock.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
+
void asmlinkage bootblock_c_entry(void)
{
+ device_t dev = NB_DEV_ROOT;
+
+ /* Set PCI Express BAR */
+ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
+
+ dev = P2SB_DEV;
+ /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ /* Call lib/bootblock.c main */
+ main();
}
diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h
index 1cf9b70..655188b 100644
--- a/src/soc/intel/apollolake/include/soc/bootblock.h
+++ b/src/soc/intel/apollolake/include/soc/bootblock.h
@@ -1,4 +1,8 @@
#ifndef _SOC_APOLLOLAKE_BOOTBLOCK_H_
#define _SOC_APOLLOLAKE_BOOTBLOCK_H_
+#include <arch/cpu.h>
+
void asmlinkage bootblock_c_entry(void);
+/* provide prototype for lib/bootblock.c main as workaround */
+void main(void);
#endif
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
new file mode 100644
index 0000000..bee58b2
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_CPU_H_
+#define _SOC_APOLLOLAKE_CPU_H_
+
+#include <cpu/x86/msr.h>
+
+#define CPUID_APOLLOLAKE_A0 0x506c8
+
+#define MSR_PLATFORM_INFO 0xce
+
+#define BASE_CLOCK_MHZ 100
+
+#endif /* _SOC_APOLLOLAKE_CPU_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
new file mode 100644
index 0000000..4a071cb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define PCIEX_SIZE (256 * MiB)
+
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+
+#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
new file mode 100644
index 0000000..3116389
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -0,0 +1,40 @@
+#ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_
+#define _SOC_APOLLOLAKE_PCI_DEVS_H_
+
+#include <rules.h>
+
+#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
+
+
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
+#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
+#else
+#include <arch/io.h>
+#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
+#endif
+
+/* North bridge devices */
+#define NB_DEV_SLOT_ROOT 0x00
+#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
+#define NB_DEV_ROOT _NB_DEV(ROOT)
+
+/* LPSS UART */
+#define LPSS_DEV_SLOT_UART 0x18
+#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
+#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1)
+#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2)
+#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3)
+#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0)
+#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1)
+#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
+#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+
+#define P2SB_DEV PCI_DEV(0, 0xd, 0)
+#define PMC_DEV PCI_DEV(0, 0xd, 1)
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
new file mode 100644
index 0000000..fd535fb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_UART_H_
+#define _SOC_APOLLOLAKE_UART_H_
+
+/* Clock is 100MHz * (M / N).*/
+#define UART_CLK 0x200
+# define UART_CLK_UPDATE (1 << 31)
+# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16)
+# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1)
+# define UART_CLK_EN (1 << 0)
+#define UART_RESET 0x204
+# define UART_RESET_DMA_EN (1 << 2)
+# define UART_RESET_UART_EN (3 << 0)
+
+void lpss_console_uart_init(void);
+
+#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
new file mode 100644
index 0000000..b6320ed
--- /dev/null
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <soc/cpu.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+ return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+}
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
new file mode 100644
index 0000000..d3b1d80
--- /dev/null
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <soc/uart.h>
+#include <soc/pci_devs.h>
+
+static void lpss_uart_write(uint16_t reg, uint32_t val)
+{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg;
+ write32((void *)base, val);
+}
+
+void lpss_console_uart_init(void)
+{
+ uint32_t clk_sel;
+ device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
+ if (CONFIG_UART_FOR_CONSOLE > 2)
+ return;
+
+ /* Enable BAR0 for the UART -- this is where the 8250 registers hide */
+ pci_write_config32(uart, PCI_BASE_ADDRESS_0,
+ CONFIG_CONSOLE_UART_BASE_ADDRESS);
+
+ /* Enable memory access and bus master */
+ pci_write_config32(uart, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Take UART out of reset */
+ lpss_uart_write(UART_RESET, UART_RESET_UART_EN);
+
+ /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
+ clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a);
+ /* Set M and N divisor inputs and enable clock */
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE);
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN);
+
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ /* That's within 0.5% of the actual value we've set earlier */
+ return 115200 * 16;
+}
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13677
-gerrit
commit 3739b2470f4558ffb131d29a1121b678c4eb80fc
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Feb 10 17:47:03 2016 -0800
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.
Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/mainboard/intel/apollolake_rvp/Makefile.inc | 2 +-
src/mainboard/intel/apollolake_rvp/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/Kconfig | 12 +++++
src/soc/intel/apollolake/Makefile.inc | 6 +++
src/soc/intel/apollolake/bootblock/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/include/soc/bootblock.h | 4 ++
src/soc/intel/apollolake/include/soc/cpu.h | 24 +++++++++
src/soc/intel/apollolake/include/soc/northbridge.h | 26 +++++++++
src/soc/intel/apollolake/include/soc/pci_devs.h | 40 ++++++++++++++
src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++++
src/soc/intel/apollolake/placeholders.c | 2 +
src/soc/intel/apollolake/tsc_freq.c | 20 +++++++
src/soc/intel/apollolake/uart_early.c | 61 ++++++++++++++++++++++
13 files changed, 284 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc
index a48936e..8501868 100644
--- a/src/mainboard/intel/apollolake_rvp/Makefile.inc
+++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc
@@ -1 +1 @@
-# Nothing yet here
+bootblock-y += bootblock.c
diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c
new file mode 100644
index 0000000..c1b7d41
--- /dev/null
+++ b/src/mainboard/intel/apollolake_rvp/bootblock.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/uart.h>
+
+static struct pad_config aplk_rvp_gpios[] = {
+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/
+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios));
+ lpss_console_uart_init();
+ }
+}
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index e39fc9c..dcfbad6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -32,6 +32,13 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select SOC_INTEL_COMMON
select UDELAY_TSC
+ select CONSOLE_SERIAL
+ select BOOTBLOCK_CONSOLE
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"
@@ -63,4 +70,9 @@ config CPU_ADDR_BITS
int
default 36
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL
+ hex "MMIO base address for UART"
+ default 0xde000000
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e58be86..7f8beb0 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,14 +9,20 @@ subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
+bootblock-y += bootblock/bootblock.c
bootblock-y += gpio.c
bootblock-y += placeholders.c
+bootblock-y += tsc_freq.c
+bootblock-y += uart_early.c
romstage-y += placeholders.c
romstage-y += gpio.c
+romstage-y += uart_early.c
+
smm-y += placeholders.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
+ramstage-y += uart_early.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index a5f3beb..d3a78e1 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -1,4 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <arch/cpu.h>
+#include <bootblock_common.h>
+#include <device/pci.h>
#include <soc/bootblock.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
+
void asmlinkage bootblock_c_entry(void)
{
+ device_t dev = NB_DEV_ROOT;
+
+ /* Set PCI Express BAR */
+ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
+
+ dev = P2SB_DEV;
+ /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ /* Call lib/bootblock.c main */
+ main();
}
diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h
index 1cf9b70..655188b 100644
--- a/src/soc/intel/apollolake/include/soc/bootblock.h
+++ b/src/soc/intel/apollolake/include/soc/bootblock.h
@@ -1,4 +1,8 @@
#ifndef _SOC_APOLLOLAKE_BOOTBLOCK_H_
#define _SOC_APOLLOLAKE_BOOTBLOCK_H_
+#include <arch/cpu.h>
+
void asmlinkage bootblock_c_entry(void);
+/* provide prototype for lib/bootblock.c main as workaround */
+void main(void);
#endif
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
new file mode 100644
index 0000000..bee58b2
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_CPU_H_
+#define _SOC_APOLLOLAKE_CPU_H_
+
+#include <cpu/x86/msr.h>
+
+#define CPUID_APOLLOLAKE_A0 0x506c8
+
+#define MSR_PLATFORM_INFO 0xce
+
+#define BASE_CLOCK_MHZ 100
+
+#endif /* _SOC_APOLLOLAKE_CPU_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
new file mode 100644
index 0000000..4a071cb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define PCIEX_SIZE (256 * MiB)
+
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+
+#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
new file mode 100644
index 0000000..3116389
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -0,0 +1,40 @@
+#ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_
+#define _SOC_APOLLOLAKE_PCI_DEVS_H_
+
+#include <rules.h>
+
+#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
+
+
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
+#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
+#else
+#include <arch/io.h>
+#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
+#endif
+
+/* North bridge devices */
+#define NB_DEV_SLOT_ROOT 0x00
+#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
+#define NB_DEV_ROOT _NB_DEV(ROOT)
+
+/* LPSS UART */
+#define LPSS_DEV_SLOT_UART 0x18
+#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
+#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1)
+#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2)
+#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3)
+#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0)
+#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1)
+#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
+#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+
+#define P2SB_DEV PCI_DEV(0, 0xd, 0)
+#define PMC_DEV PCI_DEV(0, 0xd, 1)
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
new file mode 100644
index 0000000..fd535fb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_UART_H_
+#define _SOC_APOLLOLAKE_UART_H_
+
+/* Clock is 100MHz * (M / N).*/
+#define UART_CLK 0x200
+# define UART_CLK_UPDATE (1 << 31)
+# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16)
+# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1)
+# define UART_CLK_EN (1 << 0)
+#define UART_RESET 0x204
+# define UART_RESET_DMA_EN (1 << 2)
+# define UART_RESET_UART_EN (3 << 0)
+
+void lpss_console_uart_init(void);
+
+#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c
index 3a818eb..9913af9 100644
--- a/src/soc/intel/apollolake/placeholders.c
+++ b/src/soc/intel/apollolake/placeholders.c
@@ -2,6 +2,8 @@
#include <cpu/x86/smm.h>
#include <delay.h>
#include <rules.h>
+#include <console/uart.h>
+
void *cbmem_top(void)
{
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
new file mode 100644
index 0000000..b6320ed
--- /dev/null
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <soc/cpu.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+ return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+}
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
new file mode 100644
index 0000000..d3b1d80
--- /dev/null
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <soc/uart.h>
+#include <soc/pci_devs.h>
+
+static void lpss_uart_write(uint16_t reg, uint32_t val)
+{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg;
+ write32((void *)base, val);
+}
+
+void lpss_console_uart_init(void)
+{
+ uint32_t clk_sel;
+ device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
+ if (CONFIG_UART_FOR_CONSOLE > 2)
+ return;
+
+ /* Enable BAR0 for the UART -- this is where the 8250 registers hide */
+ pci_write_config32(uart, PCI_BASE_ADDRESS_0,
+ CONFIG_CONSOLE_UART_BASE_ADDRESS);
+
+ /* Enable memory access and bus master */
+ pci_write_config32(uart, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Take UART out of reset */
+ lpss_uart_write(UART_RESET, UART_RESET_UART_EN);
+
+ /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
+ clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a);
+ /* Set M and N divisor inputs and enable clock */
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE);
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN);
+
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ /* That's within 0.5% of the actual value we've set earlier */
+ return 115200 * 16;
+}
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13677
-gerrit
commit 8b2e56c4b7ae3d72e492f9392d0ffd8568997eba
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Wed Feb 10 17:47:03 2016 -0800
soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.
Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/mainboard/intel/apollolake_rvp/Makefile.inc | 2 +-
src/mainboard/intel/apollolake_rvp/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/Kconfig | 12 +++++
src/soc/intel/apollolake/Makefile.inc | 6 +++
src/soc/intel/apollolake/bootblock/bootblock.c | 30 +++++++++++
src/soc/intel/apollolake/include/soc/bootblock.h | 4 ++
src/soc/intel/apollolake/include/soc/cpu.h | 24 +++++++++
src/soc/intel/apollolake/include/soc/northbridge.h | 26 +++++++++
src/soc/intel/apollolake/include/soc/pci_devs.h | 40 ++++++++++++++
src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++++
src/soc/intel/apollolake/placeholders.c | 15 ++++++
src/soc/intel/apollolake/tsc_freq.c | 20 +++++++
src/soc/intel/apollolake/uart_early.c | 61 ++++++++++++++++++++++
13 files changed, 297 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc
index a48936e..8501868 100644
--- a/src/mainboard/intel/apollolake_rvp/Makefile.inc
+++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc
@@ -1 +1 @@
-# Nothing yet here
+bootblock-y += bootblock.c
diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c
new file mode 100644
index 0000000..c1b7d41
--- /dev/null
+++ b/src/mainboard/intel/apollolake_rvp/bootblock.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/uart.h>
+
+static struct pad_config aplk_rvp_gpios[] = {
+ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/
+ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios));
+ lpss_console_uart_init();
+ }
+}
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index e39fc9c..dcfbad6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -32,6 +32,13 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select SOC_INTEL_COMMON
select UDELAY_TSC
+ select CONSOLE_SERIAL
+ select BOOTBLOCK_CONSOLE
+ select TSC_CONSTANT_RATE
+ select UDELAY_TSC
+ select TSC_CONSTANT_RATE
+ select NO_UART_ON_SUPERIO
+ select DRIVERS_UART_8250MEM_32
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"
@@ -63,4 +70,9 @@ config CPU_ADDR_BITS
int
default 36
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL
+ hex "MMIO base address for UART"
+ default 0xde000000
+
endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e58be86..7f8beb0 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,14 +9,20 @@ subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cache_as_ram.S
+bootblock-y += bootblock/bootblock.c
bootblock-y += gpio.c
bootblock-y += placeholders.c
+bootblock-y += tsc_freq.c
+bootblock-y += uart_early.c
romstage-y += placeholders.c
romstage-y += gpio.c
+romstage-y += uart_early.c
+
smm-y += placeholders.c
ramstage-y += placeholders.c
ramstage-y += gpio.c
+ramstage-y += uart_early.c
CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index a5f3beb..d3a78e1 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -1,4 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <arch/cpu.h>
+#include <bootblock_common.h>
+#include <device/pci.h>
#include <soc/bootblock.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
+
void asmlinkage bootblock_c_entry(void)
{
+ device_t dev = NB_DEV_ROOT;
+
+ /* Set PCI Express BAR */
+ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
+
+ dev = P2SB_DEV;
+ /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ /* Call lib/bootblock.c main */
+ main();
}
diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h
index 1cf9b70..655188b 100644
--- a/src/soc/intel/apollolake/include/soc/bootblock.h
+++ b/src/soc/intel/apollolake/include/soc/bootblock.h
@@ -1,4 +1,8 @@
#ifndef _SOC_APOLLOLAKE_BOOTBLOCK_H_
#define _SOC_APOLLOLAKE_BOOTBLOCK_H_
+#include <arch/cpu.h>
+
void asmlinkage bootblock_c_entry(void);
+/* provide prototype for lib/bootblock.c main as workaround */
+void main(void);
#endif
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
new file mode 100644
index 0000000..bee58b2
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_CPU_H_
+#define _SOC_APOLLOLAKE_CPU_H_
+
+#include <cpu/x86/msr.h>
+
+#define CPUID_APOLLOLAKE_A0 0x506c8
+
+#define MSR_PLATFORM_INFO 0xce
+
+#define BASE_CLOCK_MHZ 100
+
+#endif /* _SOC_APOLLOLAKE_CPU_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
new file mode 100644
index 0000000..4a071cb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define PCIEX_SIZE (256 * MiB)
+
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+
+#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
new file mode 100644
index 0000000..3116389
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -0,0 +1,40 @@
+#ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_
+#define _SOC_APOLLOLAKE_PCI_DEVS_H_
+
+#include <rules.h>
+
+#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
+
+
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
+#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
+#else
+#include <arch/io.h>
+#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
+#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
+#endif
+
+/* North bridge devices */
+#define NB_DEV_SLOT_ROOT 0x00
+#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
+#define NB_DEV_ROOT _NB_DEV(ROOT)
+
+/* LPSS UART */
+#define LPSS_DEV_SLOT_UART 0x18
+#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
+#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1)
+#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2)
+#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3)
+#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0)
+#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1)
+#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
+#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+
+#define P2SB_DEV PCI_DEV(0, 0xd, 0)
+#define PMC_DEV PCI_DEV(0, 0xd, 1)
+
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
new file mode 100644
index 0000000..fd535fb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_UART_H_
+#define _SOC_APOLLOLAKE_UART_H_
+
+/* Clock is 100MHz * (M / N).*/
+#define UART_CLK 0x200
+# define UART_CLK_UPDATE (1 << 31)
+# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16)
+# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1)
+# define UART_CLK_EN (1 << 0)
+#define UART_RESET 0x204
+# define UART_RESET_DMA_EN (1 << 2)
+# define UART_RESET_UART_EN (3 << 0)
+
+void lpss_console_uart_init(void);
+
+#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c
index 3a818eb..691ee6a 100644
--- a/src/soc/intel/apollolake/placeholders.c
+++ b/src/soc/intel/apollolake/placeholders.c
@@ -2,6 +2,8 @@
#include <cpu/x86/smm.h>
#include <delay.h>
#include <rules.h>
+#include <console/uart.h>
+
void *cbmem_top(void)
{
@@ -17,3 +19,16 @@ void init_timer(void)
{
}
#endif
+#ifdef dfd
+#if ENV_RAMSTAGE
+/* we do not have uart driver for ramstage yet, so we put dummies */
+uintptr_t uart_platform_base(int idx)
+{
+ return 0;
+}
+unsigned int uart_platform_refclk(void)
+{
+ return 0;
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
new file mode 100644
index 0000000..b6320ed
--- /dev/null
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <soc/cpu.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+ return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+}
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
new file mode 100644
index 0000000..d3b1d80
--- /dev/null
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <soc/uart.h>
+#include <soc/pci_devs.h>
+
+static void lpss_uart_write(uint16_t reg, uint32_t val)
+{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg;
+ write32((void *)base, val);
+}
+
+void lpss_console_uart_init(void)
+{
+ uint32_t clk_sel;
+ device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
+ if (CONFIG_UART_FOR_CONSOLE > 2)
+ return;
+
+ /* Enable BAR0 for the UART -- this is where the 8250 registers hide */
+ pci_write_config32(uart, PCI_BASE_ADDRESS_0,
+ CONFIG_CONSOLE_UART_BASE_ADDRESS);
+
+ /* Enable memory access and bus master */
+ pci_write_config32(uart, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Take UART out of reset */
+ lpss_uart_write(UART_RESET, UART_RESET_UART_EN);
+
+ /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
+ clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a);
+ /* Set M and N divisor inputs and enable clock */
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE);
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN);
+
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ /* That's within 0.5% of the actual value we've set earlier */
+ return 115200 * 16;
+}