the following patch was just integrated into master:
commit ae4b8540807ca60b7fdb3916325b70663048ac54
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 22:56:24 2016 -0600
lib/prog_loaders.c: remove arch/stages.h include
There's no delcaration used. Remove the include.
Change-Id: I6fa7de6362ca0e92f0d5a7d07f3a224b9f77f709
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13679
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/13679 for details.
-gerrit
the following patch was just integrated into master:
commit ae3f3024d9ef60c6e12d9b49b2fd955939616504
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Feb 10 22:54:07 2016 -0600
arch: remove stage_exit()
It's no longer used. Remove it.
Change-Id: Id6f4084ab9d671e94f0eee76bf36fad9a174ef14
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/13678 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13690
-gerrit
commit 93a55892ab95cd54733c922f33d09be8299f2ddc
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Feb 10 17:10:05 2016 -0800
skylake: Enable DDI-A 4-lane support if GOP does not execute
This change will allow the kernel to use 4-lane eDP connections
if the GOP driver does not execute and set this bit. If GOP
has executed (everyone but Chrome OS verified mode) the link will
already be up and this will do nothing.
BUG=chrome-os-partner:50197
BRANCH=glados
TEST=boot on chell and ensure 4
Change-Id: I9e2328b00db84f26b9bd03220b8ac0bd5f64cfbf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: cff83e18ce9936c8d507f93c8443b7056c62e844
Original-Change-Id: I3f1e5d78b91eb0e4a23fcc196aff0edadc252a0c
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327251
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/igd.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index b87467f..4bb597c 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -62,6 +62,23 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
static void igd_init(struct device *dev)
{
+ u32 ddi_buf_ctl;
+
+ gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!gtt_res || !gtt_res->base)
+ return;
+
+ /*
+ * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
+ * This will allow the kernel to use 4-lane eDP links properly
+ * if the VBIOS or GOP driver does not execute.
+ */
+ ddi_buf_ctl = gtt_read(DDI_BUF_CTL_A);
+ if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
+ ddi_buf_ctl |= DDI_A_4_LANES;
+ gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
+ }
+
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
return;
@@ -70,10 +87,6 @@ static void igd_init(struct device *dev)
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
- gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (!gtt_res || !gtt_res->base)
- return;
-
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
#if IS_ENABLED(CONFIG_CHROMEOS)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13689
-gerrit
commit 59deef4ce5b8cd4eec4db47bb9fe04bef0ecaf58
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Feb 8 16:08:15 2016 -0800
skylake: acpi: Make GRXS method serialized
This method creates a named object and should be serialized to avoid
a compiler warning from recent iasl releases.
BUG=chrome-os-partner:40635
BRANCH=glados
TEST=emerge-chell coreboot with no iasl warnings
Change-Id: If54df4eca8849a8d278816712164b30a775a41ca
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9aa8c5627276be08bf0dc3d0f4b9b7bd3f40c227
Original-Change-Id: Ieb05525503bf61c9922677484aba5479856a3f35
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326843
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/acpi/gpio.asl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl
index d305e91..c9116d0 100644
--- a/src/soc/intel/skylake/acpi/gpio.asl
+++ b/src/soc/intel/skylake/acpi/gpio.asl
@@ -102,7 +102,7 @@ Method (GADD, 1, NotSerialized)
* Get GPIO Value
* Arg0 - GPIO Number
*/
-Method (GRXS, 1, NotSerialized)
+Method (GRXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13688
-gerrit
commit 7370d5431cb3a587bb678c20c09e978209949da8
Author: robbie zhang <robbie.zhang(a)intel.com>
Date: Wed Feb 10 11:40:11 2016 -0800
Intel common: add microcode loading to romstage before fspmemoryinit
The intend is to seek upgraded microcode in RW section and load it
before Fsp memoryinit, to ensure any goodness in the microcode update,
especially related to memory configuration, can be applied earlier.
BUG=chrome-os-partner:50132
BRANCH=glados
TEST=Built and boot on kunimintus. Verified microcode gets reloaded.
Boot time impact is very minor.
CQ-DEPEND=CL:327170
Change-Id: I1a5df1d1efa25fb256743dca6a661c828263ec7c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: d7f700c1876e53194748d1d1c66637b9419b7086
Original-Change-Id: I7083ec6305af9e14a57d7b0cb1bd800cd9e22f44
Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327193
Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/drivers/intel/fsp1_1/romstage.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 7466575..d53712e 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -22,6 +22,7 @@
#include <boardid.h>
#include <console/console.h>
#include <cbmem.h>
+#include <cpu/intel/microcode.h>
#include <cpu/x86/mtrr.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
@@ -49,6 +50,9 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
timestamp_add_now(TS_START_ROMSTAGE);
+ /* Load microcode before ram init */
+ intel_update_microcode_from_cbfs();
+
memset(&pei_data, 0, sizeof(pei_data));
/* Display parameters */
Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13652
-gerrit
commit 483390cc79fa015696056794eef2d4cdd0ee5ca3
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Feb 9 16:09:15 2016 -0800
timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig
This patch generalizes the approach previously used for ARM32
TTB_SUBTABLES to "auto-detect" whether a certain region was defined in
memlayout.ld. This allows us to get rid of the explicit Kconfig for the
TIMESTAMP region, reducing configuration redundancy and avoiding
confusion when setting up future boards.
(Removing armv4/bootblock_simple.c because it references this Kconfig
and it is a dead file that I just forgot to remove in CL:12076.)
BRANCH=None
BUG=None
TEST=Booted Oak and confirmed that all pre-RAM timestamps are still
there. Built Nyan and Falco.
Change-Id: I557a4b263018511d17baa4177963130a97ea310a
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
src/Kconfig | 8 ------
src/arch/arm/armv4/bootblock_simple.c | 47 -----------------------------------
src/arch/arm/armv7/mmu.c | 7 ++----
src/arch/x86/car.ld | 2 --
src/include/symbols.h | 7 ++++++
src/lib/bootblock.c | 7 +++++-
src/lib/timestamp.c | 39 ++++++++++++++++++-----------
src/soc/broadcom/cygnus/Kconfig | 1 -
src/soc/intel/braswell/Kconfig | 1 -
src/soc/intel/skylake/Kconfig | 1 -
src/soc/mediatek/mt8173/Kconfig | 1 -
src/soc/nvidia/tegra132/Kconfig | 1 -
src/soc/nvidia/tegra210/Kconfig | 1 -
src/soc/qualcomm/ipq806x/Kconfig | 1 -
src/soc/rockchip/rk3288/Kconfig | 1 -
15 files changed, 40 insertions(+), 85 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 7f13b62..a1e487f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -198,14 +198,6 @@ config COLLECT_TIMESTAMPS
Make coreboot create a table of timer-ID/timer-value pairs to
allow measuring time spent at different phases of the boot process.
-config HAS_PRECBMEM_TIMESTAMP_REGION
- bool "Timestamp region exists for pre-cbmem timestamps"
- default y if ARCH_ROMSTAGE_X86_32 && CACHE_AS_RAM
- help
- A separate region is maintained to allow storing of timestamps before
- cbmem comes up. This is useful for storing timestamps across different
- stage boundaries.
-
config USE_BLOBS
bool "Allow use of binary-only repository"
default n
diff --git a/src/arch/arm/armv4/bootblock_simple.c b/src/arch/arm/armv4/bootblock_simple.c
deleted file mode 100644
index 85f486e..0000000
--- a/src/arch/arm/armv4/bootblock_simple.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2010 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <bootblock_common.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <timestamp.h>
-
-__attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ }
-__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ }
-__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ }
-
-void main(void)
-{
- init_timer();
- if (IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION))
- timestamp_init(timestamp_get());
-
- bootblock_mainboard_early_init();
-
- if (CONFIG_BOOTBLOCK_CONSOLE) {
- console_init();
- exception_init();
- }
-
- bootblock_soc_init();
- bootblock_mainboard_init();
-
- run_romstage();
-}
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 8c2f78c..2cf90e7 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -118,11 +118,8 @@ typedef uint32_t pte_t;
static pte_t *const ttb_buff = (void *)_ttb;
-/* Not all boards want to use subtables and declare them in memlayout.ld. This
- * outputs two 0x00000000 symbols if they don't, making _ttb_subtables_size 0.
- * (I would like to explicitly assign them to 0 here, but that triggers
- * https://sourceware.org/bugzilla/show_bug.cgi?id=1038 in GNU as.) */
-asm (".weak _ttb_subtables, _ettb_subtables");
+/* Not all boards want to use subtables and declare them in memlayout.ld. */
+DECLARE_OPTIONAL_REGION(ttb_subtables);
static struct {
pte_t value;
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index f29a465..d19e613 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -42,9 +42,7 @@
* backing store once cbmem comes online. Therefore, this data needs
* to reside in the migrated area (between _car_data_start and
* _car_data_end). */
-#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION)
TIMESTAMP(., 0x100)
-#endif
/* _car_global_start and _car_global_end provide symbols to per-stage
* variables that are not shared like the timestamp and the pre-ram
* cbmem console. This is useful for clearing this area on a per-stage
diff --git a/src/include/symbols.h b/src/include/symbols.h
index 4276176..a36392f 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -84,4 +84,11 @@ extern u8 _framebuffer[];
extern u8 _eframebuffer[];
#define _framebuffer_size (_eframebuffer - _framebuffer)
+/* Put this into a .c file accessing a linker script region to mark that region
+ * as "optional". If it is defined in memlayout.ld (or anywhere else), the
+ * values from that definition will be used. If not, start, end and size will
+ * all evaluate to 0. (We can't explicitly assign the symbols to 0 in the
+ * assembly due to https://sourceware.org/bugzilla/show_bug.cgi?id=1038.) */
+#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name )
+
#endif /* __SYMBOLS_H */
diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c
index d7d0bb5..4a36a58 100644
--- a/src/lib/bootblock.c
+++ b/src/lib/bootblock.c
@@ -19,8 +19,11 @@
#include <console/console.h>
#include <delay.h>
#include <program_loading.h>
+#include <symbols.h>
#include <timestamp.h>
+DECLARE_OPTIONAL_REGION(timestamp);
+
__attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ }
__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ }
__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ }
@@ -28,7 +31,9 @@ __attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ }
void main(void)
{
init_timer();
- if (IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION))
+
+ /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */
+ if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)
timestamp_init(timestamp_get());
bootblock_mainboard_early_init();
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index 2850fb7..ae84c4f 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -38,8 +38,10 @@ struct __attribute__((__packed__)) timestamp_cache {
struct timestamp_entry entries[MAX_BSS_TIMESTAMP_CACHE];
};
-#if (IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) && defined(__PRE_RAM__))
-#define USE_TIMESTAMP_REGION 1
+DECLARE_OPTIONAL_REGION(timestamp);
+
+#if defined(__PRE_RAM__)
+#define USE_TIMESTAMP_REGION (_timestamp_size > 0)
#else
#define USE_TIMESTAMP_REGION 0
#endif
@@ -254,21 +256,30 @@ static void timestamp_sync_cache_to_cbmem(int is_recovery)
/*
* There's no need to worry about the base_time fields being out of
- * sync because the following configurations are used/supported:
+ * sync because only the following configurations are used/supported:
+ *
+ * 1. Timestamps get initialized before ramstage, which implies
+ * CONFIG_EARLY_CBMEM_INIT and CBMEM initialization in romstage.
+ * This requires the board to define a TIMESTAMP() region in its
+ * memlayout.ld (default on x86). The base_time from timestamp_init()
+ * (usually called from bootblock.c on most non-x86 boards) persists
+ * in that region until it gets synced to CBMEM in romstage.
+ * In ramstage, the BSS cache's base_time will be 0 until the second
+ * sync, which will adjust the timestamps in there to the correct
+ * base_time (from CBMEM) with the timestamp_add_table_entry() below.
*
- * 1. CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION is enabled. This
- * implies CONFIG_EARLY_CBMEM_INIT so once cbmem comes
- * online we sync the timestamps to the cbmem storage while
- * running in romstage. In ramstage the cbmem area is
- * recovered and utilized.
+ * 2. Timestamps only get initialized in ramstage *and*
+ * CONFIG_LATE_CBMEM_INIT is set. main() will call timestamp_init()
+ * very early (before any timestamps get logged) to set a base_time
+ * in the BSS cache, which will later get synced over to CBMEM.
*
- * 2. CONFIG_LATE_CBMEM_INIT (!CONFIG_EARLY_CBMEM_INIT) is
- * being used. That means the only cache that exists is
- * in ramstage. Once cbmem comes online in ramstage those
- * values are sync'd over.
+ * If you try to initialize timestamps before ramstage but don't define
+ * a TIMESTAMP region, all operations will fail (safely), and coreboot
+ * will behave as if timestamps only get initialized in ramstage.
*
- * Any other combinations will result in inconsistent base_time
- * values including bizarre timestamp values.
+ * If CONFIG_EARLY_CBMEM_INIT is set but timestamps only get
+ * initialized in ramstage, the base_time from timestamp_init() will
+ * get ignored and all timestamps will be 0-based.
*/
for (i = 0; i < ts_cache_table->num_entries; i++) {
struct timestamp_entry *tse = &ts_cache_table->entries[i];
diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig
index 8cafc4b..d4c34c9 100644
--- a/src/soc/broadcom/cygnus/Kconfig
+++ b/src/soc/broadcom/cygnus/Kconfig
@@ -24,7 +24,6 @@ config SOC_BROADCOM_CYGNUS
select GENERIC_UDELAY
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
- select HAS_PRECBMEM_TIMESTAMP_REGION
select GENERIC_GPIO_LIB
if SOC_BROADCOM_CYGNUS
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index a64505e..053aa29 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -17,7 +17,6 @@ config CPU_SPECIFIC_OPTIONS
select COLLECT_TIMESTAMPS
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
- select HAS_PRECBMEM_TIMESTAMP_REGION
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
select HAVE_HARD_RESET
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index c0ce9ad..302b575 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS
select COLLECT_TIMESTAMPS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select GENERIC_GPIO_LIB
- select HAS_PRECBMEM_TIMESTAMP_REGION
select HAVE_HARD_RESET
select HAVE_INTEL_FIRMWARE
select HAVE_MONOTONIC_TIMER
diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig
index d8f1116..ed1c4da 100644
--- a/src/soc/mediatek/mt8173/Kconfig
+++ b/src/soc/mediatek/mt8173/Kconfig
@@ -11,7 +11,6 @@ config SOC_MEDIATEK_MT8173
select SPI_ATOMIC_SEQUENCING if SPI_FLASH
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
- select HAS_PRECBMEM_TIMESTAMP_REGION
select GENERIC_GPIO_LIB
select HAVE_HARD_RESET
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index 04d5783..502e7c4 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -13,7 +13,6 @@ config SOC_NVIDIA_TEGRA132
select HAVE_HARD_RESET
select HAVE_UART_SPECIAL
select GENERIC_GPIO_LIB
- select HAS_PRECBMEM_TIMESTAMP_REGION
if SOC_NVIDIA_TEGRA132
diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig
index 5273d81..2601c70 100644
--- a/src/soc/nvidia/tegra210/Kconfig
+++ b/src/soc/nvidia/tegra210/Kconfig
@@ -13,7 +13,6 @@ config SOC_NVIDIA_TEGRA210
select HAVE_HARD_RESET
select HAVE_UART_SPECIAL
select ARM64_USE_ARM_TRUSTED_FIRMWARE
- select HAS_PRECBMEM_TIMESTAMP_REGION
select GENERIC_GPIO_LIB
if SOC_NVIDIA_TEGRA210
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index dd60d63..aeb59ff 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -6,7 +6,6 @@ config SOC_QC_IPQ806X
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select BOOTBLOCK_CONSOLE
- select HAS_PRECBMEM_TIMESTAMP_REGION
select HAVE_UART_SPECIAL
select SPI_ATOMIC_SEQUENCING
select GENERIC_GPIO_LIB
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 65e6dc3..0f39f75 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -20,7 +20,6 @@ config SOC_ROCKCHIP_RK3288
select ARCH_VERSTAGE_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
- select HAS_PRECBMEM_TIMESTAMP_REGION
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
select HAVE_UART_SPECIAL
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13687
-gerrit
commit cf1838c25fae064e5c2734b6baf8ea37827d1165
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Thu Feb 11 22:04:55 2016 +0100
kconfig: make oldconfig work "non-strict"
oldconfig is regularly used to clean up templates that sometimes contain
duplicates or old symbols.
Since it cleans up the config, it doesn't need to fail on issues.
Change-Id: Ife0e9e3b9bfdde1eb6be0e2e38e81b9042cb7950
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/kconfig/Makefile | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile
index a7d3855..ffd5253 100644
--- a/util/kconfig/Makefile
+++ b/util/kconfig/Makefile
@@ -34,8 +34,10 @@ config: $(objk)/conf
nconfig: $(objk)/nconf
$< $(Kconfig)
+# Disable strict mode because oldconfig is typically used to clean up
+# templates and the like. The second invocation should already have sane data.
oldconfig: $(objk)/conf
- $< --$@ $(Kconfig)
+ KCONFIG_STRICT= $< --$@ $(Kconfig)
$< --silentoldconfig $(Kconfig)
silentoldconfig: $(objk)/conf
the following patch was just integrated into master:
commit 69d20c45ecd8d224f1e9cf785f4fa441feb6e0a3
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Feb 8 19:48:11 2016 -0800
timestamp: Bump CBMEM timestamp count, make full use of pre-RAM regions
Since we're reaching the timestamp limit on certain platforms (both for
the pre-RAM cache and the final CBMEM region), this patch increases the
amount of space for both. In the pre-RAM case, it achieves this by
always utilizing the full size of the TIMESTAMP() region allocated in
memlayout.ld, rather than arbitrarily limiting it to some constant.
BRANCH=None
BUG=None
TEST=Booted Oak and confirmed that I can once again see all pre-RAM
timestamps after picking in the LZ4 patch series.
Change-Id: Iabb075a48d8d1e3e1811afeaad5ab47e7846c972
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13651
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/13651 for details.
-gerrit