coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: group serial console options into one Kconfig
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13790 -gerrit commit 027121284f893cec6c15c9a28a61e59d9a5a925b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:49:07 2016 -0600 soc/intel/apollolake: group serial console options into one Kconfig Add SOC_UART_DEBUG which does all the appropriate selection of the dependent Kconfig options for seral console. Also provide a default option of it being turned off instead of always selected. Change-Id: I1a6dba9c0072a17859c8f389709afe6fe3b04fac Signed-off-by: Aaron Durbin <adurbin(a)chormium.org> --- src/soc/intel/apollolake/Kconfig | 13 +++++++++---- src/soc/intel/apollolake/Makefile.inc | 6 +++--- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bb0cc20..c32b80f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,13 +32,9 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON select UDELAY_TSC - select CONSOLE_SERIAL - select BOOTBLOCK_CONSOLE select TSC_CONSTANT_RATE select UDELAY_TSC select TSC_CONSTANT_RATE - select NO_UART_ON_SUPERIO - select DRIVERS_UART_8250MEM_32 config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address" @@ -75,6 +71,15 @@ config CONSOLE_UART_BASE_ADDRESS hex "MMIO base address for UART" default 0xde000000 +config SOC_UART_DEBUG + bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." + default n + select CONSOLE_SERIAL + select BOOTBLOCK_CONSOLE + select DRIVERS_UART + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7f8beb0..76fa4c7 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -13,16 +13,16 @@ bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c bootblock-y += placeholders.c bootblock-y += tsc_freq.c -bootblock-y += uart_early.c +bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += placeholders.c romstage-y += gpio.c -romstage-y += uart_early.c +romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c -ramstage-y += uart_early.c +ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include

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Patch set updated for coreboot: lib/bootblock: provide SoC callback parity with mainboard
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13791 -gerrit commit e26e503c932a301f8077058e2a5a2ebbef257fc0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:56:00 2016 -0600 lib/bootblock: provide SoC callback parity with mainboard There was no 'early' call into the SoC code prior to console getting initialized. Not having this enforces the mainboard to drive the setup of the console which typically just ends up calling into the SoC codde. Provide a SoC early init call to handle this without having to duplicate the same code in mainboards utilizing the same SoC. Change-Id: Ia233dc3ae89a77df284d6d5cf5b2b051ad3be089 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootblock_common.h | 7 ++++++- src/lib/bootblock.c | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index c8156d0..2cecc3b 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -18,9 +18,14 @@ #include <main_decl.h> -/* These are defined as weak no-ops that can be overridden by mainboard/SoC. */ +/* + * These are defined as weak no-ops that can be overridden by mainboard/SoC. + * The 'early' variants are called prior to console initialization. Also, the + * SoC functions are called prior to the mainboard fucntions. + */ void bootblock_mainboard_early_init(void); void bootblock_mainboard_init(void); +void bootblock_soc_early_init(void); void bootblock_soc_init(void); #endif /* __BOOTBLOCK_COMMON_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 4a36a58..658eea4 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -25,6 +25,7 @@ DECLARE_OPTIONAL_REGION(timestamp); __attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ } +__attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } @@ -36,6 +37,7 @@ void main(void) if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0) timestamp_init(timestamp_get()); + bootblock_soc_early_init(); bootblock_mainboard_early_init(); if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {

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Patch set updated for coreboot: soc/intel/appollolake: fix comment in gpio_defs.h
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13789 -gerrit commit 2ae617bd2061fb8abc806844d3e242c2f3ad8155 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 12:59:20 2016 -0600 soc/intel/appollolake: fix comment in gpio_defs.h GPIO_187 is the beginning of the Northwest community pads. Change-Id: I5565ecf534530144e80c65d886db11b53f38f935 Signed-off-by Aaron Durbin <adurbin(a)chormium.org> --- src/soc/intel/apollolake/include/soc/gpio_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 6a9863d..50f1fc2 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -147,7 +147,7 @@ #define SVID0_DATA 76 #define SVID0_CLK 77 -/* North community pads */ +/* Northwest community pads */ #define GPIO_187 78 #define GPIO_188 79 #define GPIO_189 80

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Patch set updated for coreboot: soc/intel/apollolake: implement bootblock_soc_early_init()
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13793 -gerrit commit 94ff5beae39e8b5b907d8acdfe04b8191d5746b7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:02:58 2016 -0600 soc/intel/apollolake: implement bootblock_soc_early_init() Provide a bootblock_soc_early_init() to that takes care of initializing the UART on behalf of the mainboard when serial console is enabled. Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/bootblock/bootblock.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 5007613..4ea3f70 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -17,6 +17,7 @@ #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <soc/uart.h> void asmlinkage bootblock_c_entry(void) { @@ -42,3 +43,10 @@ void platform_prog_run(struct prog *prog) msr.lo |= (1 << 8); wrmsr(MSR_POWER_MISC, msr); } + +void bootblock_soc_early_init(void) +{ + /* Prepare UART for serial console. */ + if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) + soc_console_uart_init(); +}

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Patch set updated for coreboot: soc/intel/apollolake: provide function to setup uart pads and controller
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13792 -gerrit commit ded793f38641b45a0a4d59a42cfa314b6be8ba27 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:00:03 2016 -0600 soc/intel/apollolake: provide function to setup uart pads and controller Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option. Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/include/soc/uart.h | 3 +++ src/soc/intel/apollolake/uart_early.c | 32 ++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h index fd535fb..16f09b1 100644 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -25,4 +25,7 @@ void lpss_console_uart_init(void); +/* Initialize the console UART including the pads for the configured UART. */ +void soc_console_uart_init(void); + #endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index d3b1d80..4ee4a38 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -22,12 +22,21 @@ static void lpss_uart_write(uint16_t reg, uint32_t val) write32((void *)base, val); } +static inline int invalid_uart_for_console(void) +{ + /* There are actually only 2 UARTS, and they are named UART1 and + * UART2. They live at pci functions 1 and 2 respectively. */ + if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1) + return 1; + return 0; +} + void lpss_console_uart_init(void) { uint32_t clk_sel; device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); - if (CONFIG_UART_FOR_CONSOLE > 2) + if (invalid_uart_for_console()) return; /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ @@ -59,3 +68,24 @@ unsigned int uart_platform_refclk(void) /* That's within 0.5% of the actual value we've set earlier */ return 115200 * 16; } + +static const struct pad_config uart_gpios[] = { + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ +}; + +void soc_console_uart_init(void) +{ + /* Get a 0-based pad index. See invalid_uart_for_console() above. */ + const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; + + if (invalid_uart_for_console()) + return; + + /* Configure the 2 pads per UART. */ + gpio_configure_pads(&uart_gpios[pad_index * 2], 2); + + lpss_console_uart_init(); +}

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init()
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13794 -gerrit commit 72ce464ec5af45ce8c29d10a62bfca2d38b56de6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:05:04 2016 -0600 mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init() Now that the SoC is configuring the UART pads there's no need to implement bootblock_mainboard_early_init(). Remove it and bootblock.c. Change-Id: I2ae7ea38351733e1c9757cde20b79e1d19d0c1e5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 - src/mainboard/intel/apollolake_rvp/bootblock.c | 30 ------------------------- 2 files changed, 31 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc index 8501868..e69de29 100644 --- a/src/mainboard/intel/apollolake_rvp/Makefile.inc +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -1 +0,0 @@ -bootblock-y += bootblock.c diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c deleted file mode 100644 index c1b7d41..0000000 --- a/src/mainboard/intel/apollolake_rvp/bootblock.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <bootblock_common.h> -#include <console/console.h> -#include <soc/gpio.h> -#include <soc/gpio_defs.h> -#include <soc/uart.h> - -static struct pad_config aplk_rvp_gpios[] = { - PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/ -}; - -void bootblock_mainboard_early_init(void) -{ - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { - gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios)); - lpss_console_uart_init(); - } -}

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New patch to review for coreboot: mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init()
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13794 -gerrit commit 1bc2ffc79f0ce361034e478fd111a47e97c128cb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:05:04 2016 -0600 mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init() Now that the SoC is configuring the UART pads there's no need to implement bootblock_mainboard_early_init(). Remove it and bootblock.c. Change-Id: I2ae7ea38351733e1c9757cde20b79e1d19d0c1e5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 - src/mainboard/intel/apollolake_rvp/bootblock.c | 30 ------------------------- 2 files changed, 31 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc index 8501868..e69de29 100644 --- a/src/mainboard/intel/apollolake_rvp/Makefile.inc +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -1 +0,0 @@ -bootblock-y += bootblock.c diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c deleted file mode 100644 index c1b7d41..0000000 --- a/src/mainboard/intel/apollolake_rvp/bootblock.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <bootblock_common.h> -#include <console/console.h> -#include <soc/gpio.h> -#include <soc/gpio_defs.h> -#include <soc/uart.h> - -static struct pad_config aplk_rvp_gpios[] = { - PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/ -}; - -void bootblock_mainboard_early_init(void) -{ - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { - gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios)); - lpss_console_uart_init(); - } -}

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New patch to review for coreboot: soc/intel/apollolake: implement bootblock_soc_early_init()
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13793 -gerrit commit 7c422a5993badaa504781fee320960890855f09f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:02:58 2016 -0600 soc/intel/apollolake: implement bootblock_soc_early_init() Provide a bootblock_soc_early_init() to that takes care of initializing the UART on behalf of the mainboard when serial console is enabled. Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/bootblock/bootblock.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 5007613..4ea3f70 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -17,6 +17,7 @@ #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <soc/uart.h> void asmlinkage bootblock_c_entry(void) { @@ -42,3 +43,10 @@ void platform_prog_run(struct prog *prog) msr.lo |= (1 << 8); wrmsr(MSR_POWER_MISC, msr); } + +void bootblock_soc_early_init(void) +{ + /* Prepare UART for serial console. */ + if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) + soc_console_uart_init(); +}

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New patch to review for coreboot: soc/intel/apollolake: provide function to setup uart pads and controller
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13792 -gerrit commit 94595ced304cc18453b098d81b0c20ef530f4c45 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:00:03 2016 -0600 soc/intel/apollolake: provide function to setup uart pads and controller Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option. Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/include/soc/uart.h | 3 +++ src/soc/intel/apollolake/uart_early.c | 32 ++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h index fd535fb..16f09b1 100644 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -25,4 +25,7 @@ void lpss_console_uart_init(void); +/* Initialize the console UART including the pads for the configured UART. */ +void soc_console_uart_init(void); + #endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index d3b1d80..4ee4a38 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -22,12 +22,21 @@ static void lpss_uart_write(uint16_t reg, uint32_t val) write32((void *)base, val); } +static inline int invalid_uart_for_console(void) +{ + /* There are actually only 2 UARTS, and they are named UART1 and + * UART2. They live at pci functions 1 and 2 respectively. */ + if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1) + return 1; + return 0; +} + void lpss_console_uart_init(void) { uint32_t clk_sel; device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); - if (CONFIG_UART_FOR_CONSOLE > 2) + if (invalid_uart_for_console()) return; /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ @@ -59,3 +68,24 @@ unsigned int uart_platform_refclk(void) /* That's within 0.5% of the actual value we've set earlier */ return 115200 * 16; } + +static const struct pad_config uart_gpios[] = { + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ +}; + +void soc_console_uart_init(void) +{ + /* Get a 0-based pad index. See invalid_uart_for_console() above. */ + const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; + + if (invalid_uart_for_console()) + return; + + /* Configure the 2 pads per UART. */ + gpio_configure_pads(&uart_gpios[pad_index * 2], 2); + + lpss_console_uart_init(); +}

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New patch to review for coreboot: lib/bootblock: provide SoC callback parity with mainboard
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13791 -gerrit commit 5c343acb083d9c01ae2b3548ebd6407334bd8224 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:56:00 2016 -0600 lib/bootblock: provide SoC callback parity with mainboard There was no 'early' call into the SoC code prior to console getting initialized. Not having this enforces the mainboard to drive the setup of the console which typically just ends up calling into the SoC codde. Provide a SoC early init call to handle this without having to duplicate the same code in mainboards utilizing the same SoC. Change-Id: Ia233dc3ae89a77df284d6d5cf5b2b051ad3be089 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootblock_common.h | 7 ++++++- src/lib/bootblock.c | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index c8156d0..2cecc3b 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -18,9 +18,14 @@ #include <main_decl.h> -/* These are defined as weak no-ops that can be overridden by mainboard/SoC. */ +/* + * These are defined as weak no-ops that can be overridden by mainboard/SoC. + * The 'early' variants are called prior to console initialization. Also, the + * SoC functions are called prior to the mainboard fucntions. + */ void bootblock_mainboard_early_init(void); void bootblock_mainboard_init(void); +void bootblock_soc_early_init(void); void bootblock_soc_init(void); #endif /* __BOOTBLOCK_COMMON_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 4a36a58..658eea4 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -25,6 +25,7 @@ DECLARE_OPTIONAL_REGION(timestamp); __attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ } +__attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } @@ -36,6 +37,7 @@ void main(void) if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0) timestamp_init(timestamp_get()); + bootblock_soc_early_init(); bootblock_mainboard_early_init(); if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {

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coreboot-gerrit February 2016