coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: fsp_baytrail: Fix a possible hanging DisplayPort
by Werner Zeh 25 Feb '16

25 Feb '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13743 -gerrit commit ebc83881ef5f4920d8c4640001965ab0f549e289 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Feb 19 10:50:38 2016 +0100 fsp_baytrail: Fix a possible hanging DisplayPort On some devices it can happen that DisplayPort TX lanes do not work properly if the power gate setup is omitted. If that happens, DisplayPort training will fail and therefore DisplayPort channel will not work. Both ports are affected. It seems that not every CPU shows this effect and those that are affected tend to fail more often in a cold environment. With this fix a board that originally shows this failure was running for over 1000 power cycles without issues. Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Kconfig | 8 +++ src/soc/intel/fsp_baytrail/Makefile.inc | 2 + src/soc/intel/fsp_baytrail/gfx.c | 118 ++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 506e731..b30d52f 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -96,6 +96,14 @@ config VGA_BIOS_FILE string default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS +config FSP_BAYTRAIL_GFX_INIT + default n + bool + help + Enabling this option will activate graphics init code. With this init, + the graphic power gate registers will be initialized before + VBIOS is executed. + config CPU_MICROCODE_HEADER_FILES string default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 79fc7eb..41672e6 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -3,6 +3,7 @@ # # Copyright (C) 2010 Google Inc. # Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2016 Siemens AG # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -54,6 +55,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c +ramstage-(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c new file mode 100644 index 0000000..4d3737d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/gfx.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright 2016 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> +#include <stdlib.h> + +#include <soc/gfx.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +#define GFX_TIMEOUT 100000 /* 100ms */ + +static const struct reg_script gpu_pre_vbios_script[] = { + /* Make sure GFX is bus master with MMIO access */ + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + /* Display */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, + GFX_TIMEOUT), + /* Tx/Rx Lanes */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, + GFX_TIMEOUT), + /* Common Lane */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, + GFX_TIMEOUT), + /* Ungating Tx only */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, + GFX_TIMEOUT), + /* Ungating Common Lane only */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, + GFX_TIMEOUT), + /* Ungating Display */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, + GFX_TIMEOUT), + REG_SCRIPT_END +}; + +static const struct reg_script gfx_post_vbios_script[] = { + /* Deassert Render Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), + /* Deassert Media Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), + /* Set Lock bits */ + REG_PCI_RMW32(GGC, 0xffffffff, 1), + REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), + REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), + REG_SCRIPT_END +}; + +static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +{ + reg_script_run_on_dev(dev, ops); +} + +static void gfx_pre_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); + gfx_run_script(dev, gpu_pre_vbios_script); +} + +static void gfx_post_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); + gfx_run_script(dev, gfx_post_vbios_script); +} + +static void gfx_init(device_t dev) +{ + /* Pre VBIOS Init */ + gfx_pre_vbios_init(dev); + + /* Run VBIOS */ + pci_dev_init(dev); + + /* Post VBIOS Init */ + gfx_post_vbios_init(dev); +} + +static struct device_operations gfx_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gfx_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver gfx_driver __pci_driver = { + .ops = &gfx_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = GFX_DEVID, +};

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Patch set updated for coreboot: mc_tcu3: Enable graphic init code
by Werner Zeh 25 Feb '16

25 Feb '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13774 -gerrit commit d17350ef6c7ec04e7f0cfd2ba0ec05e5a54f887a Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Feb 24 07:35:17 2016 +0100 mc_tcu3: Enable graphic init code The used Baytrail-M SoC on TCU3 tend to have issues with DisplayPort if the graphic power gate is not set up in coreboot. To avoid this error, use the graphic init code on this board. Change-Id: I973bbaa7d86c1ede1f2884b3a08ccb31f7d85087 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 1b62045..d7ff867 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_FSP_BAYTRAIL_MD select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES + select FSP_BAYTRAIL_GFX_INIT config MAINBOARD_DIR string

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Patch merged into coreboot/master: cbfs: Fix compiler error for gcc versions < 4.6
by gerrit＠coreboot.org 25 Feb '16

25 Feb '16

the following patch was just integrated into master: commit 116485a6343c24452f491fc67a342ddfe0f3a167 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Feb 24 08:50:37 2016 +0100 cbfs: Fix compiler error for gcc versions < 4.6 The missing braces for access to a union member cause an error on gcc versions < 4.6. Change-Id: I7de14a6d89219f5376f4f969adecfe8014a5a9d8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/13776 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13776 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: group serial console options into one Kconfig
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13790 -gerrit commit ef1ea438c45ac76237e4dde0e941cfd88a2c646a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:49:07 2016 -0600 soc/intel/apollolake: group serial console options into one Kconfig Add SOC_UART_DEBUG which does all the appropriate selection of the dependent Kconfig options for seral console. Also provide a default option of it being turned off instead of always selected. Change-Id: I1a6dba9c0072a17859c8f389709afe6fe3b04fac Signed-off-by: Aaron Durbin <adurbin(a)chormium.org> --- src/soc/intel/apollolake/Kconfig | 13 +++++++++---- src/soc/intel/apollolake/Makefile.inc | 6 +++--- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bb0cc20..c32b80f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,13 +32,9 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON select UDELAY_TSC - select CONSOLE_SERIAL - select BOOTBLOCK_CONSOLE select TSC_CONSTANT_RATE select UDELAY_TSC select TSC_CONSTANT_RATE - select NO_UART_ON_SUPERIO - select DRIVERS_UART_8250MEM_32 config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address" @@ -75,6 +71,15 @@ config CONSOLE_UART_BASE_ADDRESS hex "MMIO base address for UART" default 0xde000000 +config SOC_UART_DEBUG + bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." + default n + select CONSOLE_SERIAL + select BOOTBLOCK_CONSOLE + select DRIVERS_UART + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7f8beb0..76fa4c7 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -13,16 +13,16 @@ bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c bootblock-y += placeholders.c bootblock-y += tsc_freq.c -bootblock-y += uart_early.c +bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += placeholders.c romstage-y += gpio.c -romstage-y += uart_early.c +romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c -ramstage-y += uart_early.c +ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include

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Patch set updated for coreboot: lib/bootblock: provide SoC callback parity with mainboard
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13791 -gerrit commit 8aa41f29c9b5c78de5da853ea6839973448b2107 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:56:00 2016 -0600 lib/bootblock: provide SoC callback parity with mainboard There was no 'early' call into the SoC code prior to console getting initialized. Not having this enforces the mainboard to drive the setup of the console which typically just ends up calling into the SoC code. Provide a SoC early init call to handle this without having to duplicate the same code in mainboards utilizing the same SoC. Change-Id: Ia233dc3ae89a77df284d6d5cf5b2b051ad3be089 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/bootblock_common.h | 7 ++++++- src/lib/bootblock.c | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index c8156d0..2cecc3b 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -18,9 +18,14 @@ #include <main_decl.h> -/* These are defined as weak no-ops that can be overridden by mainboard/SoC. */ +/* + * These are defined as weak no-ops that can be overridden by mainboard/SoC. + * The 'early' variants are called prior to console initialization. Also, the + * SoC functions are called prior to the mainboard fucntions. + */ void bootblock_mainboard_early_init(void); void bootblock_mainboard_init(void); +void bootblock_soc_early_init(void); void bootblock_soc_init(void); #endif /* __BOOTBLOCK_COMMON_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 4a36a58..658eea4 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -25,6 +25,7 @@ DECLARE_OPTIONAL_REGION(timestamp); __attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ } +__attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } @@ -36,6 +37,7 @@ void main(void) if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0) timestamp_init(timestamp_get()); + bootblock_soc_early_init(); bootblock_mainboard_early_init(); if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {

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Patch set updated for coreboot: lib/memrange: avoid shadow object declarations
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13788 -gerrit commit 66c17bc825fcb02fff97cec9ea0b95b19908b0f7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:49:25 2016 -0600 lib/memrange: avoid shadow object declarations Fix an error where a variable named 'free' was shadowing the function 'free'. src/lib/memrange.c:293:73: error: declaration of 'free' shadows a global declaration [-Werror=shadow] Change-Id: Ie57194b392f8f00ed4fd5c76dab27299b00ae293 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/memrange.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/lib/memrange.c b/src/lib/memrange.c index cc75e01..489b562 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -290,7 +290,7 @@ void memranges_add_resources(struct memranges *ranges, memranges_add_resources_filter(ranges, mask, match, tag, NULL); } -void memranges_init_empty(struct memranges *ranges, struct range_entry *free, +void memranges_init_empty(struct memranges *ranges, struct range_entry *to_free, size_t num_free) { size_t i; @@ -299,7 +299,7 @@ void memranges_init_empty(struct memranges *ranges, struct range_entry *free, ranges->free_list = NULL; for (i = 0; i < num_free; i++) - range_entry_link(&ranges->free_list, &free[i]); + range_entry_link(&ranges->free_list, &to_free[i]); } void memranges_init(struct memranges *ranges,

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Patch set updated for coreboot: soc/intel/appollolake: fix comment in gpio_defs.h
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13789 -gerrit commit 2f806daeedad7a2c76f77debfed3a40e232680a6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 12:59:20 2016 -0600 soc/intel/appollolake: fix comment in gpio_defs.h GPIO_187 is the beginning of the Northwest community pads. Change-Id: I5565ecf534530144e80c65d886db11b53f38f935 Signed-off-by Aaron Durbin <adurbin(a)chormium.org> --- src/soc/intel/apollolake/include/soc/gpio_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 6a9863d..50f1fc2 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -147,7 +147,7 @@ #define SVID0_DATA 76 #define SVID0_CLK 77 -/* North community pads */ +/* Northwest community pads */ #define GPIO_187 78 #define GPIO_188 79 #define GPIO_189 80

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Patch set updated for coreboot: soc/intel/apollolake: implement bootblock_soc_early_init()
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13793 -gerrit commit 5d93d5cfb6d7538ee5844e6174fd295fe205e13a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:02:58 2016 -0600 soc/intel/apollolake: implement bootblock_soc_early_init() Provide a bootblock_soc_early_init() to that takes care of initializing the UART on behalf of the mainboard when serial console is enabled. Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/bootblock/bootblock.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 5007613..4ea3f70 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -17,6 +17,7 @@ #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <soc/uart.h> void asmlinkage bootblock_c_entry(void) { @@ -42,3 +43,10 @@ void platform_prog_run(struct prog *prog) msr.lo |= (1 << 8); wrmsr(MSR_POWER_MISC, msr); } + +void bootblock_soc_early_init(void) +{ + /* Prepare UART for serial console. */ + if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) + soc_console_uart_init(); +}

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Patch set updated for coreboot: soc/intel/apollolake: provide function to setup uart pads and controller
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13792 -gerrit commit 10dc144fe4dfc00c382802063d03c8f8e6acce33 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:00:03 2016 -0600 soc/intel/apollolake: provide function to setup uart pads and controller Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option. Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/include/soc/uart.h | 3 +++ src/soc/intel/apollolake/uart_early.c | 32 ++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h index fd535fb..16f09b1 100644 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -25,4 +25,7 @@ void lpss_console_uart_init(void); +/* Initialize the console UART including the pads for the configured UART. */ +void soc_console_uart_init(void); + #endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index d3b1d80..4ee4a38 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -22,12 +22,21 @@ static void lpss_uart_write(uint16_t reg, uint32_t val) write32((void *)base, val); } +static inline int invalid_uart_for_console(void) +{ + /* There are actually only 2 UARTS, and they are named UART1 and + * UART2. They live at pci functions 1 and 2 respectively. */ + if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1) + return 1; + return 0; +} + void lpss_console_uart_init(void) { uint32_t clk_sel; device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); - if (CONFIG_UART_FOR_CONSOLE > 2) + if (invalid_uart_for_console()) return; /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ @@ -59,3 +68,24 @@ unsigned int uart_platform_refclk(void) /* That's within 0.5% of the actual value we've set earlier */ return 115200 * 16; } + +static const struct pad_config uart_gpios[] = { + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ +}; + +void soc_console_uart_init(void) +{ + /* Get a 0-based pad index. See invalid_uart_for_console() above. */ + const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; + + if (invalid_uart_for_console()) + return; + + /* Configure the 2 pads per UART. */ + gpio_configure_pads(&uart_gpios[pad_index * 2], 2); + + lpss_console_uart_init(); +}

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init()
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13794 -gerrit commit 398b1924053564d279821290d645525c1c4a880f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:05:04 2016 -0600 mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init() Now that the SoC is configuring the UART pads there's no need to implement bootblock_mainboard_early_init(). Remove it and bootblock.c. Change-Id: I2ae7ea38351733e1c9757cde20b79e1d19d0c1e5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 - src/mainboard/intel/apollolake_rvp/bootblock.c | 30 ------------------------- 2 files changed, 31 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc index 8501868..e69de29 100644 --- a/src/mainboard/intel/apollolake_rvp/Makefile.inc +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -1 +0,0 @@ -bootblock-y += bootblock.c diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c deleted file mode 100644 index c1b7d41..0000000 --- a/src/mainboard/intel/apollolake_rvp/bootblock.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <bootblock_common.h> -#include <console/console.h> -#include <soc/gpio.h> -#include <soc/gpio_defs.h> -#include <soc/uart.h> - -static struct pad_config aplk_rvp_gpios[] = { - PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/ -}; - -void bootblock_mainboard_early_init(void) -{ - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { - gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios)); - lpss_console_uart_init(); - } -}

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coreboot-gerrit February 2016