coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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1305 discussions

New patch to review for coreboot: x86/Makefile.inc: Fix redundant addition of memlayout.ld in bootblock
by Furquan Shaikh 24 Feb '16

24 Feb '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13777 -gerrit commit 80d01c88be6ca03c2afa036fedfa488b086bdbfc Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Feb 24 09:42:16 2016 -0800 x86/Makefile.inc: Fix redundant addition of memlayout.ld in bootblock For C_ENVIRONMENT_BOOTBLOCK, memlayout.ld is added by call to early_x86_stage. Remove redundant addition of memlayout.ld in this case. Change-Id: Ibb5ce690ac4e63f7ff5063d5bd04daeeb731e4d7 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/arch/x86/Makefile.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 56e2ad0..01fa81e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,7 +113,6 @@ $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) bootblock-y += bootblock_crt0.S -bootblock-y += memlayout.ld ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386))

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Patch merged into coreboot/master: Documentation/Intel: Add minimal APCI and TempRamExit documentation
by gerrit＠coreboot.org 24 Feb '16

24 Feb '16

the following patch was just integrated into master: commit bf08da27d56f12e9176fc419f39b4951cd46a8f2 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Feb 20 17:48:35 2016 -0800 Documentation/Intel: Add minimal APCI and TempRamExit documentation Update the documentation to add the minimal ACPI support. Also add TempRamExit entry to the FSP features table. TEST=None Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13757 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13757 for details. -gerrit

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Patch set updated for coreboot: cbfs: Fix compiler error for gcc versions < 4.6
by Werner Zeh 24 Feb '16

24 Feb '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13776 -gerrit commit 86ae5e468390662cedca53fc80b6a14e8187abf8 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Feb 24 08:50:37 2016 +0100 cbfs: Fix compiler error for gcc versions < 4.6 The missing braces for access to a union member cause an error on gcc versions < 4.6. Change-Id: I7de14a6d89219f5376f4f969adecfe8014a5a9d8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/commonlib/lz4_wrapper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c index ea7b90d..7699cc8 100644 --- a/src/commonlib/lz4_wrapper.c +++ b/src/commonlib/lz4_wrapper.c @@ -149,7 +149,7 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) } while (1) { - struct lz4_block_header b = { .raw = read_le32(in) }; + struct lz4_block_header b = { { .raw = read_le32(in) } }; in += sizeof(struct lz4_block_header); if ((size_t)(in - src) + b.size > srcn)

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New patch to review for coreboot: cbfs: Fix compiler error for gcc version < 4.6
by Werner Zeh 24 Feb '16

24 Feb '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13776 -gerrit commit f6bb7de901a1d2373d2550863356f7c64cddee72 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Feb 24 08:50:37 2016 +0100 cbfs: Fix compiler error for gcc version < 4.6 The missing braces for access to a union member causes an error on gcc versions < 4.6. Change-Id: I7de14a6d89219f5376f4f969adecfe8014a5a9d8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/commonlib/lz4_wrapper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c index ea7b90d..7699cc8 100644 --- a/src/commonlib/lz4_wrapper.c +++ b/src/commonlib/lz4_wrapper.c @@ -149,7 +149,7 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) } while (1) { - struct lz4_block_header b = { .raw = read_le32(in) }; + struct lz4_block_header b = { { .raw = read_le32(in) } }; in += sizeof(struct lz4_block_header); if ((size_t)(in - src) + b.size > srcn)

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New patch to review for coreboot: northbridge/intel: add missing #include guards
by Iru Cai 24 Feb '16

24 Feb '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13775 -gerrit commit 46fde717d9aeafef6e392d6b3ab54ed9b803d78b Author: Iru Cai <mytbk920423(a)gmail.com> Date: Wed Feb 24 15:03:58 2016 +0800 northbridge/intel: add missing #include guards Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/northbridge/intel/i945/chip.h | 5 +++++ src/northbridge/intel/nehalem/chip.h | 5 +++++ src/northbridge/intel/sandybridge/chip.h | 5 +++++ src/northbridge/intel/sandybridge/gma.h | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 52925ff..446af72 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_I945_CHIP_H +#define NORTHBRIDGE_INTEL_I945_CHIP_H + #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { @@ -6,3 +9,5 @@ struct northbridge_intel_i945_config { int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index 5598022..caf9819 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H +#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -39,3 +42,5 @@ struct northbridge_intel_nehalem_config { struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index b04f95e..5effc0d 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H +#define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -45,3 +48,5 @@ struct northbridge_intel_sandybridge_config { struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 8381863..0832468 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H +#define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H + /* mailbox 0: header */ typedef struct { u8 signature[16]; @@ -114,3 +117,5 @@ struct i915_gpu_controller_info; int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u8 *mmio, u32 lfb); + +#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */

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New patch to review for coreboot: mc_tcu3: Enable graphic init code
by Werner Zeh 24 Feb '16

24 Feb '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13774 -gerrit commit 64a6769406f513df197e415a0678b8ad07f7e6e3 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Feb 24 07:35:17 2016 +0100 mc_tcu3: Enable graphic init code The used Baytrail-M SoC on TCU3 tend to have issues with DisplayPort if the graphic power gate is not set up in coreboot. To avoid this error, use the graphic init code on this board. Change-Id: I973bbaa7d86c1ede1f2884b3a08ccb31f7d85087 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 1b62045..d7ff867 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_FSP_BAYTRAIL_MD select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES + select FSP_BAYTRAIL_GFX_INIT config MAINBOARD_DIR string

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Patch set updated for coreboot: fsp_baytrail: Fix a possible hanging DisplayPort
by Werner Zeh 24 Feb '16

24 Feb '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13743 -gerrit commit 5450936205d62eb240811ed1efa17a1b4fc2a752 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Feb 19 10:50:38 2016 +0100 fsp_baytrail: Fix a possible hanging DisplayPort On some devices it can happen that DisplayPort TX lanes do not work properly if the power gate setup is omitted. If that happens, DisplayPort training will fail and therefore DisplayPort channel will not work. Both ports are affected. It seems that not every CPU shows this effect and those that are affected tend to fail more often in cold environment. With this fix a board that originally shows this failure very often was running for over 1000 power cycles without issues. Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Kconfig | 8 +++ src/soc/intel/fsp_baytrail/Makefile.inc | 2 + src/soc/intel/fsp_baytrail/gfx.c | 118 ++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 506e731..b30d52f 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -96,6 +96,14 @@ config VGA_BIOS_FILE string default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS +config FSP_BAYTRAIL_GFX_INIT + default n + bool + help + Enabling this option will activate graphics init code. With this init, + the graphic power gate registers will be initialized before + VBIOS is executed. + config CPU_MICROCODE_HEADER_FILES string default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 79fc7eb..41672e6 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -3,6 +3,7 @@ # # Copyright (C) 2010 Google Inc. # Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2016 Siemens AG # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -54,6 +55,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c +ramstage-(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c new file mode 100644 index 0000000..4d3737d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/gfx.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright 2016 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> +#include <stdlib.h> + +#include <soc/gfx.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +#define GFX_TIMEOUT 100000 /* 100ms */ + +static const struct reg_script gpu_pre_vbios_script[] = { + /* Make sure GFX is bus master with MMIO access */ + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + /* Display */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, + GFX_TIMEOUT), + /* Tx/Rx Lanes */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, + GFX_TIMEOUT), + /* Common Lane */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, + GFX_TIMEOUT), + /* Ungating Tx only */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, + GFX_TIMEOUT), + /* Ungating Common Lane only */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, + GFX_TIMEOUT), + /* Ungating Display */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, + GFX_TIMEOUT), + REG_SCRIPT_END +}; + +static const struct reg_script gfx_post_vbios_script[] = { + /* Deassert Render Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), + /* Deassert Media Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), + /* Set Lock bits */ + REG_PCI_RMW32(GGC, 0xffffffff, 1), + REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), + REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), + REG_SCRIPT_END +}; + +static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +{ + reg_script_run_on_dev(dev, ops); +} + +static void gfx_pre_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); + gfx_run_script(dev, gpu_pre_vbios_script); +} + +static void gfx_post_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); + gfx_run_script(dev, gfx_post_vbios_script); +} + +static void gfx_init(device_t dev) +{ + /* Pre VBIOS Init */ + gfx_pre_vbios_init(dev); + + /* Run VBIOS */ + pci_dev_init(dev); + + /* Post VBIOS Init */ + gfx_post_vbios_init(dev); +} + +static struct device_operations gfx_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gfx_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver gfx_driver __pci_driver = { + .ops = &gfx_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = GFX_DEVID, +};

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Patch set updated for coreboot: kbuild: clean up drivers/
by Stefan Reinauer 24 Feb '16

24 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/9941 -gerrit commit 7435322233a8bf9b8852886491fe3c2130f77462 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Feb 23 15:26:42 2016 -0800 kbuild: clean up drivers/ Try to reorder drivers to fit src/drivers/[X]/[Y]/ scheme Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I815db91fcddc88ef6561fb0ed9651e7a505725d6 --- Makefile.inc | 4 +- src/Kconfig | 2 + src/drivers/aspeed/Kconfig | 2 - src/drivers/aspeed/Makefile.inc | 1 - src/drivers/ati/Kconfig | 1 - src/drivers/ati/Makefile.inc | 1 - src/drivers/dec/21143/Makefile.inc | 4 + src/drivers/dec/Kconfig | 1 - src/drivers/dec/Makefile.inc | 1 - src/drivers/emulation/Kconfig | 1 - src/drivers/emulation/Makefile.inc | 1 - src/drivers/generic/Kconfig | 2 - src/drivers/generic/Makefile.inc | 2 - src/drivers/i2c/Kconfig | 12 - src/drivers/i2c/Makefile.inc | 12 - src/drivers/ics/Kconfig | 1 - src/drivers/ics/Makefile.inc | 1 - src/drivers/intel/Kconfig | 18 -- src/drivers/intel/Makefile.inc | 5 - src/drivers/intel/fsp1_0/Makefile.inc | 3 + src/drivers/intel/fsp1_1/Makefile.inc | 4 + src/drivers/intel/i210/Makefile.inc | 6 +- src/drivers/maxim/Kconfig | 16 -- src/drivers/maxim/Makefile.inc | 16 -- src/drivers/parade/Kconfig | 16 -- src/drivers/parade/Makefile.inc | 16 -- src/drivers/pc80/Kconfig | 26 -- src/drivers/pc80/Makefile.inc | 24 -- src/drivers/pc80/i8254.c | 51 ---- src/drivers/pc80/i8259.c | 138 ----------- src/drivers/pc80/isa-dma.c | 44 ---- src/drivers/pc80/keyboard.c | 381 ----------------------------- src/drivers/pc80/mc146818rtc.c | 397 ------------------------------ src/drivers/pc80/mc146818rtc_early.c | 103 -------- src/drivers/pc80/pc/Kconfig | 18 ++ src/drivers/pc80/pc/Makefile.inc | 11 + src/drivers/pc80/pc/i8254.c | 51 ++++ src/drivers/pc80/pc/i8259.c | 139 +++++++++++ src/drivers/pc80/pc/isa-dma.c | 44 ++++ src/drivers/pc80/pc/keyboard.c | 387 ++++++++++++++++++++++++++++++ src/drivers/pc80/pc/ps2_controller.asl | 46 ++++ src/drivers/pc80/pc/spkmodem.c | 126 ++++++++++ src/drivers/pc80/pc/udelay_io.c | 14 ++ src/drivers/pc80/ps2_controller.asl | 46 ---- src/drivers/pc80/rtc/Kconfig | 4 + src/drivers/pc80/rtc/Makefile.inc | 15 ++ src/drivers/pc80/rtc/mc146818rtc.c | 400 +++++++++++++++++++++++++++++++ src/drivers/pc80/rtc/mc146818rtc_early.c | 104 ++++++++ src/drivers/pc80/spkmodem.c | 124 ---------- src/drivers/pc80/tpm/Makefile.inc | 4 + src/drivers/pc80/udelay_io.c | 13 - src/drivers/pc80/vga/Makefile.inc | 4 + src/drivers/ricoh/Kconfig | 1 - src/drivers/sil/Kconfig | 1 - src/drivers/sil/Makefile.inc | 1 - src/drivers/ti/Kconfig | 17 -- src/drivers/ti/Makefile.inc | 18 -- src/drivers/xgi/Kconfig | 2 - src/drivers/xgi/Makefile.inc | 1 - src/drivers/xpowers/Kconfig | 1 - src/drivers/xpowers/Makefile.inc | 1 - src/drivers/xpowers/axp209/Makefile.inc | 10 +- src/include/pc80/mc146818rtc.h | 2 +- 63 files changed, 1396 insertions(+), 1522 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 1889128..c3bb1e7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -69,7 +69,9 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs build_complete subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) -subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode +subdirs-y += src/superio +subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) +subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom subdirs-y += util/futility util/marvell subdirs-y += $(wildcard src/arch/*) diff --git a/src/Kconfig b/src/Kconfig index 3def65b..0fa1397 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -432,6 +432,7 @@ source "src/superio/*/Kconfig" comment "Embedded Controllers" source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" +# FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" source "src/southbridge/intel/common/firmware/Kconfig" @@ -445,6 +446,7 @@ source "src/device/Kconfig" menu "Generic Drivers" source "src/drivers/*/Kconfig" +source "src/drivers/*/*/Kconfig" endmenu config RTC diff --git a/src/drivers/aspeed/Kconfig b/src/drivers/aspeed/Kconfig deleted file mode 100644 index 3b0238b..0000000 --- a/src/drivers/aspeed/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -source src/drivers/aspeed/common/Kconfig -source src/drivers/aspeed/ast2050/Kconfig diff --git a/src/drivers/aspeed/Makefile.inc b/src/drivers/aspeed/Makefile.inc deleted file mode 100644 index 2553464..0000000 --- a/src/drivers/aspeed/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += common ast2050 diff --git a/src/drivers/ati/Kconfig b/src/drivers/ati/Kconfig deleted file mode 100644 index f1ea32c..0000000 --- a/src/drivers/ati/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/ati/ragexl/Kconfig diff --git a/src/drivers/ati/Makefile.inc b/src/drivers/ati/Makefile.inc deleted file mode 100644 index 15b5dfc..0000000 --- a/src/drivers/ati/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += ragexl diff --git a/src/drivers/dec/21143/Makefile.inc b/src/drivers/dec/21143/Makefile.inc index e99dfad..b7382e4 100644 --- a/src/drivers/dec/21143/Makefile.inc +++ b/src/drivers/dec/21143/Makefile.inc @@ -1 +1,5 @@ +ifeq ($(CONFIG_DRIVERS_DEC_21143),y) + ramstage-y += 21143.c + +endif diff --git a/src/drivers/dec/Kconfig b/src/drivers/dec/Kconfig deleted file mode 100644 index c9dfe64..0000000 --- a/src/drivers/dec/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/dec/21143/Kconfig diff --git a/src/drivers/dec/Makefile.inc b/src/drivers/dec/Makefile.inc deleted file mode 100644 index 196c424..0000000 --- a/src/drivers/dec/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_DRIVERS_DEC_21143) += 21143 diff --git a/src/drivers/emulation/Kconfig b/src/drivers/emulation/Kconfig deleted file mode 100644 index df8d4ff..0000000 --- a/src/drivers/emulation/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/emulation/qemu/Kconfig diff --git a/src/drivers/emulation/Makefile.inc b/src/drivers/emulation/Makefile.inc deleted file mode 100644 index c1c92cd..0000000 --- a/src/drivers/emulation/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += qemu diff --git a/src/drivers/generic/Kconfig b/src/drivers/generic/Kconfig deleted file mode 100644 index 3317fd1..0000000 --- a/src/drivers/generic/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -source src/drivers/generic/generic/Kconfig -source src/drivers/generic/ioapic/Kconfig diff --git a/src/drivers/generic/Makefile.inc b/src/drivers/generic/Makefile.inc deleted file mode 100644 index a099a31..0000000 --- a/src/drivers/generic/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -subdirs-y += generic -subdirs-y += ioapic diff --git a/src/drivers/i2c/Kconfig b/src/drivers/i2c/Kconfig deleted file mode 100644 index 2831c3f..0000000 --- a/src/drivers/i2c/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -source src/drivers/i2c/adm1026/Kconfig -source src/drivers/i2c/adm1027/Kconfig -source src/drivers/i2c/adt7463/Kconfig -source src/drivers/i2c/at24rf08c/Kconfig -source src/drivers/i2c/i2cmux/Kconfig -source src/drivers/i2c/i2cmux2/Kconfig -source src/drivers/i2c/lm63/Kconfig -source src/drivers/i2c/rtd2132/Kconfig -source src/drivers/i2c/tpm/Kconfig -source src/drivers/i2c/w83793/Kconfig -source src/drivers/i2c/w83795/Kconfig -source src/drivers/i2c/ww_ring/Kconfig diff --git a/src/drivers/i2c/Makefile.inc b/src/drivers/i2c/Makefile.inc deleted file mode 100644 index c69dc02..0000000 --- a/src/drivers/i2c/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -subdirs-y += adm1026 -subdirs-y += adm1027 -subdirs-y += adt7463 -subdirs-y += at24rf08c -subdirs-y += i2cmux -subdirs-y += i2cmux2 -subdirs-y += lm63 -subdirs-y += rtd2132 -subdirs-y += tpm -subdirs-y += w83793 -subdirs-y += w83795 -subdirs-y += ww_ring diff --git a/src/drivers/ics/Kconfig b/src/drivers/ics/Kconfig deleted file mode 100644 index 0a0ba66..0000000 --- a/src/drivers/ics/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/ics/954309/Kconfig diff --git a/src/drivers/ics/Makefile.inc b/src/drivers/ics/Makefile.inc deleted file mode 100644 index 39cc90b..0000000 --- a/src/drivers/ics/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_DRIVERS_ICS_954309) += 954309 diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig deleted file mode 100644 index 19986f4..0000000 --- a/src/drivers/intel/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -source src/drivers/intel/fsp1_1/Kconfig -source src/drivers/intel/gma/Kconfig -source src/drivers/intel/i210/Kconfig diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc deleted file mode 100644 index e54f07b..0000000 --- a/src/drivers/intel/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -subdirs-y += gma -subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi -subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0 -subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1 -subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index ea8f61e..4ff1068 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +ifeq ($(CONFIG_PLATFORM_USES_FSP1_0),y) + ramstage-y += fsp_util.c hob.c romstage-y += fsp_util.c hob.c @@ -44,3 +46,4 @@ mrc.cache-type := mrc_cache endif endif +endif diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index f101cc4..3f214cb 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. # +ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) + verstage-y += car.c verstage-y += fsp_util.c verstage-y += verstage.c @@ -53,3 +55,5 @@ fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) fsp.bin-position := $(CONFIG_FSP_LOC) fsp.bin-type := fsp endif + +endif diff --git a/src/drivers/intel/i210/Makefile.inc b/src/drivers/intel/i210/Makefile.inc index a1f15de..a696022 100644 --- a/src/drivers/intel/i210/Makefile.inc +++ b/src/drivers/intel/i210/Makefile.inc @@ -1 +1,5 @@ -ramstage-y += i210.c \ No newline at end of file +ifeq ($(CONFIG_DRIVER_INTEL_I210),y) + +ramstage-y += i210.c + +endif diff --git a/src/drivers/maxim/Kconfig b/src/drivers/maxim/Kconfig deleted file mode 100644 index 4dc9b60..0000000 --- a/src/drivers/maxim/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 The Chromium OS Authors. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -source src/drivers/maxim/max77686/Kconfig diff --git a/src/drivers/maxim/Makefile.inc b/src/drivers/maxim/Makefile.inc deleted file mode 100644 index 2fc011d..0000000 --- a/src/drivers/maxim/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 The Chromium OS Authors. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-$(CONFIG_DRIVER_MAXIM_MAX77686) += max77686/ diff --git a/src/drivers/parade/Kconfig b/src/drivers/parade/Kconfig deleted file mode 100644 index be80bb8..0000000 --- a/src/drivers/parade/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -source src/drivers/parade/ps8625/Kconfig diff --git a/src/drivers/parade/Makefile.inc b/src/drivers/parade/Makefile.inc deleted file mode 100644 index 0470763..0000000 --- a/src/drivers/parade/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-$(CONFIG_DRIVER_PARADE_PS8625) += ps8625/ diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 18c626c..4a703b0 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -1,27 +1 @@ -# Might be removed (alongside with the PS/2 init code) once payloads -# reliably support PS/2 init themselves. -if PC80_SYSTEM - -config DRIVERS_PS2_KEYBOARD - bool "PS/2 keyboard init" - default n - help - Enable this option to initialize PS/2 keyboards found connected - to the PS/2 port. - - Some payloads (eg, filo) require this option. Other payloads - (eg, GRUB 2, SeaBIOS, Linux) do not require it. - Initializing a PS/2 keyboard can take several hundred milliseconds. - - If you know you will only use a payload which does not require - this option, then you can say N here to speed up boot time. - Otherwise say Y. - -config DRIVERS_MC146818 - bool - default y if ARCH_X86 - select RTC - source src/drivers/pc80/tpm/Kconfig - -endif diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc deleted file mode 100644 index 0788cc7..0000000 --- a/src/drivers/pc80/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -ifeq ($(CONFIG_ARCH_X86),y) - -romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c -ramstage-y += isa-dma.c -ramstage-y += i8254.c -ramstage-y += i8259.c -ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c -ramstage-y += keyboard.c -ramstage-$(CONFIG_SPKMODEM) += spkmodem.c - -romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c - -romstage-$(CONFIG_SPKMODEM) += spkmodem.c - -subdirs-y += tpm vga - -cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default -cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool -cmos.default-type = 0xaa - -smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c - -endif diff --git a/src/drivers/pc80/i8254.c b/src/drivers/pc80/i8254.c deleted file mode 100644 index 5851ec0..0000000 --- a/src/drivers/pc80/i8254.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <pc80/i8254.h> -#include <console/console.h> - -/* Initialize i8254 timers */ - -void setup_i8254(void) -{ - /* Timer 0 (taken from biosemu) */ - outb(TIMER0_SEL | WORD_ACCESS | MODE3 | BINARY_COUNT, TIMER_MODE_PORT); - outb(0x00, TIMER0_PORT); - outb(0x00, TIMER0_PORT); - - /* Timer 1 */ - outb(TIMER1_SEL | LOBYTE_ACCESS | MODE3 | BINARY_COUNT, - TIMER_MODE_PORT); - outb(0x12, TIMER1_PORT); -} - -#if CONFIG_UDELAY_TIMER2 -static void load_timer2(unsigned int ticks) -{ - /* Set up the timer gate, turn off the speaker */ - outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); - outb(TIMER2_SEL | WORD_ACCESS | MODE0 | BINARY_COUNT, TIMER_MODE_PORT); - outb(ticks & 0xFF, TIMER2_PORT); - outb(ticks >> 8, TIMER2_PORT); -} - -void udelay(int usecs) -{ - load_timer2((usecs * TICKS_PER_MS) / 1000); - while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) - ; -} -#endif diff --git a/src/drivers/pc80/i8259.c b/src/drivers/pc80/i8259.c deleted file mode 100644 index 1cb49b1..0000000 --- a/src/drivers/pc80/i8259.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <pc80/i8259.h> -#include <console/console.h> - -/* Read the current PIC IRQ mask */ -u16 pic_read_irq_mask(void) -{ - u16 mask; - int i; - - mask = inb(MASTER_PIC_OCW1) | (inb(SLAVE_PIC_OCW1) << 8); - - printk(BIOS_DEBUG, "8259 PIC: OCW1 IRQ Mask: 0x%x\n", mask); - printk(BIOS_SPEW, "\tEnabled IRQs (0 = Unmasked, 1 = Masked off):\n" - "\t\tMaster\t\tSlave\n"); - for(i = 0; i <= 7; i++) { - printk(BIOS_SPEW, "\t\tIRQ%X: %x\t\tIRQ%X: %x\n", - i, (mask >> i) & 1, i + 8, (mask >> (i + 8)) & 1); - } - return mask; -} - -/* - * Write an IRQ mask to the PIC: - * IRQA is bit 0xA in the 16 bit bitmask (OCW1) - */ -void pic_write_irq_mask(u16 mask) -{ - outb(mask, MASTER_PIC_OCW1); - outb(mask >> 8, SLAVE_PIC_OCW1); -} - -/* - * The PIC IRQs default to masked off - * Allow specific IRQs to be enabled (1) - * or disabled by (0) the user - */ -void pic_irq_enable(u8 int_num, u8 mask) -{ - pic_write_irq_mask(pic_read_irq_mask() & ~(mask << int_num)); - pic_read_irq_mask(); -} - -void setup_i8259(void) -{ - /* A write to ICW1 starts the Interrupt Controller Initialization - * Sequence. This implicitly causes the following to happen: - * - Interrupt Mask register is cleared - * - Priority 7 is assigned to IRQ7 input - * - Slave mode address is set to 7 - * - Special mask mode is cleared - * - * We send the initialization sequence to both the master and - * slave i8259 controller. - */ - outb(ICW_SELECT|IC4, MASTER_PIC_ICW1); - outb(ICW_SELECT|IC4, SLAVE_PIC_ICW1); - - /* Now the interrupt controller expects us to write to ICW2. */ - outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2); - outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2); - - /* Now the interrupt controller expects us to write to ICW3. - * - * The normal scenario is to set up cascading on IRQ2 on the master - * i8259 and assign the slave ID 2 to the slave i8259. - */ - outb(CASCADED_PIC, MASTER_PIC_ICW3); - outb(SLAVE_ID, SLAVE_PIC_ICW3); - - /* Now the interrupt controller expects us to write to ICW4. - * - * We switch both i8259 to microprocessor mode because they're - * operating as part of an x86 architecture based chipset - */ - outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2); - outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2); - - /* Now clear the interrupts through OCW1. - * First we mask off all interrupts on the slave interrupt controller - * then we mask off all interrupts but interrupt 2 on the master - * controller. This way the cascading stays alive. - */ - outb(ALL_IRQS, SLAVE_PIC_OCW1); - outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1); -} - -/** - * @brief Configure IRQ triggering in the i8259 compatible Interrupt Controller. - * - * Switch a certain interrupt to be level / edge triggered. - * - * @param int_num legacy interrupt number (3-7, 9-15) - * @param is_level_triggered 1 for level triggered interrupt, 0 for edge - * triggered interrupt - */ -void i8259_configure_irq_trigger(int int_num, int is_level_triggered) -{ - u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8); - - if (is_level_triggered) - int_bits |= (1 << int_num); - else - int_bits &= ~(1 << int_num); - - /* Write new values */ - outb((u8)(int_bits & 0xff), ELCR1); - outb((u8)(int_bits >> 8), ELCR2); - -#ifdef PARANOID_IRQ_TRIGGERS - /* Try reading back the new values. This seems like an error but is not ... */ - if (inb(ELCR1) != (int_bits & 0xff)) { - printk(BIOS_ERR, "%s: lower order bits are wrong: want 0x%x, got 0x%x\n", - __func__, (int_bits & 0xff), inb(ELCR1)); - } - - if (inb(ELCR2) != (int_bits >> 8)) { - printk(BIOS_ERR, "%s: higher order bits are wrong: want 0x%x, got 0x%x\n", - __func__, (int_bits>>8), inb(ELCR2)); - } -#endif -} diff --git a/src/drivers/pc80/isa-dma.c b/src/drivers/pc80/isa-dma.c deleted file mode 100644 index b64f125..0000000 --- a/src/drivers/pc80/isa-dma.c +++ /dev/null @@ -1,44 +0,0 @@ -#include <arch/io.h> -#include <pc80/isa-dma.h> - -/* DMA controller registers */ -#define DMA1_CMD_REG 0x08 /* command register (w) */ -#define DMA1_STAT_REG 0x08 /* status register (r) */ -#define DMA1_REQ_REG 0x09 /* request register (w) */ -#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ -#define DMA1_MODE_REG 0x0B /* mode register (w) */ -#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ -#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ -#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ -#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ -#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ - -#define DMA2_CMD_REG 0xD0 /* command register (w) */ -#define DMA2_STAT_REG 0xD0 /* status register (r) */ -#define DMA2_REQ_REG 0xD2 /* request register (w) */ -#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ -#define DMA2_MODE_REG 0xD6 /* mode register (w) */ -#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ -#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ -#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ -#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ -#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ - -#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ -#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ -#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ - -#define DMA_AUTOINIT 0x10 - - -void isa_dma_init(void) -{ - /* slave at 0x00 - 0x0f */ - /* master at 0xc0 - 0xdf */ - /* 0x80 - 0x8f DMA page registers */ - /* DMA: 0x00, 0x02, 0x4, 0x06 base address for DMA channel */ - outb(0, DMA1_RESET_REG); - outb(0, DMA2_RESET_REG); - outb(DMA_MODE_CASCADE, DMA2_MODE_REG); - outb(0, DMA2_MASK_REG); -} diff --git a/src/drivers/pc80/keyboard.c b/src/drivers/pc80/keyboard.c deleted file mode 100644 index 56b1fce..0000000 --- a/src/drivers/pc80/keyboard.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Raptor Engineering - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2003 Ollie Lo <ollielo(a)hotmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <pc80/keyboard.h> -#include <device/device.h> -#include <arch/io.h> -#include <delay.h> -#include <types.h> -#include <arch/acpi.h> - -#define KBD_DATA 0x60 -#define KBD_COMMAND 0x64 -#define KBD_STATUS 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) - -// Keyboard Controller Commands -#define KBC_CMD_READ_COMMAND 0x20 // Read command byte -#define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte -#define KBC_CMD_AUX_ENABLE 0xA8 // Auxiliary Interface enable -#define KBC_CMD_AUX_TEST 0xA9 // Auxiliary Interface test -#define KBC_CMD_SELF_TEST 0xAA // Controller self-test -#define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test - -/* The Keyboard controller command byte - * BIT | Description - * ----+------------------------------------------------------- - * 7 | reserved, must be zero - * 6 | XT Translation, (1 = on, 0 = off) - * 5 | Disable Mouse Port (1 = disable, 0 = enable) - * 4 | Disable Keyboard Port (1 = disable, 0 = enable) - * 3 | reserved, must be zero - * 2 | System Flag (1 = self-test passed. DO NOT SET TO ZERO) - * 1 | Mouse Port Interrupts (1 = enable, 0 = disable) - * 0 | Keyboard Port Interrupts (1 = enable, 0 = disable) - */ - -// Keyboard Controller Replies -#define KBC_REPLY_SELFTEST_OK 0x55 // controller self-test succeeded - -// -// Keyboard Replies -// -#define KBD_REPLY_POR 0xAA // Power on reset -#define KBD_REPLY_ACK 0xFA // Command ACK -#define KBD_REPLY_RESEND 0xFE // Command NACK, send command again - -/* Wait 400ms for keyboard controller answers */ -#define KBC_TIMEOUT_IN_MS 400 - -static int kbc_input_buffer_empty(void) -{ - u32 timeout; - for (timeout = KBC_TIMEOUT_IN_MS; - timeout && (inb(KBD_STATUS) & KBD_IBF); timeout--) - mdelay(1); - - if (!timeout) - printk(BIOS_WARNING, - "Unexpected Keyboard controller input buffer full\n"); - return !!timeout; -} - -static int kbc_output_buffer_full(void) -{ - u32 timeout; - for (timeout = KBC_TIMEOUT_IN_MS; - timeout && ((inb(KBD_STATUS) & KBD_OBF) == 0); timeout--) - mdelay(1); - - if (!timeout) - printk(BIOS_INFO, - "Keyboard controller output buffer result timeout\n"); - return !!timeout; -} - -static int kbc_cleanup_buffers(void) -{ - u32 timeout; - for (timeout = KBC_TIMEOUT_IN_MS; - timeout && (inb(KBD_STATUS) & (KBD_OBF | KBD_IBF)); timeout--) { - mdelay(1); - inb(KBD_DATA); - } - - if (!timeout) { - printk(BIOS_ERR, - "Couldn't cleanup the keyboard controller buffers\n"); - printk(BIOS_ERR, "Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n", - KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA)); - } - - return !!timeout; -} - -static enum cb_err kbc_self_test(uint8_t probe_aux, uint8_t *aux_probe_result) -{ - uint8_t self_test; - uint8_t byte; - - /* Set initial aux probe output value */ - if (aux_probe_result) - *aux_probe_result = 0; - - /* Clean up any junk that might have been in the KBC. - * Both input and output buffers must be empty. - */ - if (!kbc_cleanup_buffers()) - return CB_KBD_CONTROLLER_FAILURE; - - /* reset/self test 8042 - send cmd 0xAA */ - outb(KBC_CMD_SELF_TEST, KBD_COMMAND); - - if (!kbc_output_buffer_full()) { - /* There probably is no keyboard controller. */ - printk(BIOS_ERR, "Could not reset keyboard controller.\n"); - return CB_KBD_CONTROLLER_FAILURE; - } - - /* read self-test result, 0x55 is returned in the output buffer */ - self_test = inb(KBD_DATA); - - if (self_test != 0x55) { - printk(BIOS_ERR, "Keyboard Controller self-test failed: 0x%x\n", - self_test); - return CB_KBD_CONTROLLER_FAILURE; - } - - /* ensure the buffers are empty */ - kbc_cleanup_buffers(); - - /* keyboard interface test */ - outb(KBC_CMD_KBD_TEST, KBD_COMMAND); - - if (!kbc_output_buffer_full()) { - printk(BIOS_ERR, "Keyboard Interface test timed out.\n"); - return CB_KBD_CONTROLLER_FAILURE; - } - - /* read test result, 0x00 should be returned in case of no failures */ - self_test = inb(KBD_DATA); - - if (self_test != 0x00) { - printk(BIOS_ERR, "Keyboard Interface test failed: 0x%x\n", - self_test); - return CB_KBD_INTERFACE_FAILURE; - } - - if (probe_aux) { - /* aux interface detect */ - outb(KBC_CMD_AUX_ENABLE, KBD_COMMAND); - if (!kbc_input_buffer_empty()) { - printk(BIOS_ERR, "Timeout waiting for controller during aux enable.\n"); - return CB_KBD_CONTROLLER_FAILURE; - } - outb(KBC_CMD_READ_COMMAND, KBD_COMMAND); - if (!kbc_output_buffer_full()) { - printk(BIOS_ERR, "Timeout waiting for controller during aux probe.\n"); - return CB_KBD_CONTROLLER_FAILURE; - } - - byte = inb(KBD_DATA); - if (!(byte & (0x1 << 5))) { - printk(BIOS_DEBUG, "PS/2 auxiliary channel detected...\n"); - - /* auxiliary interface test */ - outb(KBC_CMD_AUX_TEST, KBD_COMMAND); - - if (!kbc_output_buffer_full()) { - printk(BIOS_ERR, "Auxiliary channel probe timed out.\n"); - goto aux_failure; - } - - /* read test result, 0x00 should be returned in case of no failures */ - self_test = inb(KBD_DATA); - - if (self_test != 0x00) { - printk(BIOS_ERR, "No device detected on auxiliary channel: 0x%x\n", - self_test); - goto aux_failure; - } - - printk(BIOS_DEBUG, "PS/2 device detected on auxiliary channel\n"); - if (aux_probe_result) - *aux_probe_result = 1; - } - } - -aux_failure: - - return CB_SUCCESS; -} - -static u8 send_keyboard(u8 command) -{ - u8 regval = 0; - u8 resend = 10; - - do { - if (!kbc_input_buffer_empty()) - return 0; - outb(command, KBD_DATA); - /* the reset command takes much longer then normal commands and - * even worse, some keyboards do send the ACK _after_ doing the - * reset */ - if (command == 0xFF) { - u8 retries; - for (retries = 9; retries && !kbc_output_buffer_full(); - retries--) ; - } - if (!kbc_output_buffer_full()) { - printk(BIOS_ERR, - "Could not send keyboard command %02x\n", - command); - return 0; - } - regval = inb(KBD_DATA); - --resend; - } while (regval == KBD_REPLY_RESEND && resend > 0); - - return regval; -} - -uint8_t pc_keyboard_init(uint8_t probe_aux) -{ - u8 retries; - u8 regval; - enum cb_err err; - uint8_t aux_dev_detected; - - if (!CONFIG_DRIVERS_PS2_KEYBOARD) - return 0; - - if (acpi_is_wakeup_s3()) - return 0; - - printk(BIOS_DEBUG, "Keyboard init...\n"); - - /* Run a keyboard controller self-test */ - err = kbc_self_test(probe_aux, &aux_dev_detected); - /* Ignore iterface failure as it's non-fatal. */ - if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) - return 0; - - /* Enable keyboard interface - No IRQ */ - if (!kbc_input_buffer_empty()) - return 0; - outb(0x60, KBD_COMMAND); - if (!kbc_input_buffer_empty()) - return 0; - outb(0x20, KBD_DATA); /* send cmd: enable keyboard */ - if (!kbc_input_buffer_empty()) { - printk(BIOS_INFO, "Timeout while enabling keyboard\n"); - return 0; - } - - /* clean up any junk that might have been in the keyboard */ - if (!kbc_cleanup_buffers()) - return 0; - - /* reset keyboard and self test (keyboard side) */ - regval = send_keyboard(0xFF); - if (regval == KBD_REPLY_RESEND) { - /* keeps sending RESENDs, probably no keyboard. */ - printk(BIOS_INFO, "No PS/2 keyboard detected.\n"); - return 0; - } - - if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, "Keyboard reset failed ACK: 0x%x\n", regval); - return 0; - } - - /* the reset command takes some time, so wait a little longer */ - for (retries = 9; retries && !kbc_output_buffer_full(); retries--) ; - - if (!kbc_output_buffer_full()) { - printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n"); - return 0; - } - - regval = inb(KBD_DATA); - if (regval != 0xAA) { - printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", - regval); - return 0; - } - - /* - * The following set scancode stuff is what normal BIOS do. It could be - * argued that coreboot shouldn't set the scan code..... - */ - - /* disable the keyboard */ - regval = send_keyboard(0xF5); - if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, "Keyboard disable failed ACK: 0x%x\n", regval); - return 0; - } - - /* Set scancode command */ - regval = send_keyboard(0xF0); - if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", - regval); - return 0; - } - /* Set scancode mode 2 */ - regval = send_keyboard(0x02); - if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, - "Keyboard set scancode mode failed ACK: 0x%x\n", regval); - return 0; - } - - /* All is well - enable keyboard interface */ - if (!kbc_input_buffer_empty()) - return 0; - outb(0x60, KBD_COMMAND); - if (!kbc_input_buffer_empty()) - return 0; - outb(0x65, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ - if (!kbc_input_buffer_empty()) { - printk(BIOS_ERR, "Timeout during keyboard enable\n"); - return 0; - } - - /* enable the keyboard */ - regval = send_keyboard(0xF4); - if (regval != KBD_REPLY_ACK) { - printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval); - return 0; - } - - printk(BIOS_DEBUG, "PS/2 keyboard initialized on primary channel\n"); - - return aux_dev_detected; -} - -/* - * Support PS/2 mode - oddball SIOs(KBC) need this setup - * Not well documented. Google - 0xcb keyboard controller - * This is called before pc_keyboard_init(). - */ -void set_kbc_ps2_mode(void) -{ - enum cb_err err; - - /* Run a keyboard controller self-test */ - err = kbc_self_test(0, NULL); - /* Ignore iterface failure as it's non-fatal. */ - if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) - return; - - /* Support PS/2 mode */ - if (!kbc_input_buffer_empty()) - return; - outb(0xcb, KBD_COMMAND); - - if (!kbc_input_buffer_empty()) - return; - outb(0x01, KBD_DATA); - - kbc_cleanup_buffers(); -} diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c deleted file mode 100644 index 6c39f81..0000000 --- a/src/drivers/pc80/mc146818rtc.c +++ /dev/null @@ -1,397 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <bcd.h> -#include <stdint.h> -#include <version.h> -#include <console/console.h> -#include <pc80/mc146818rtc.h> -#include <boot/coreboot_tables.h> -#include <rtc.h> -#include <string.h> -#include <cbfs.h> - -/* There's no way around this include guard. option_table.h is autogenerated */ -#if CONFIG_USE_OPTION_TABLE -#include "option_table.h" -#else -#define LB_CKS_RANGE_START 0 -#define LB_CKS_RANGE_END 0 -#define LB_CKS_LOC 0 -#endif - -#include <smp/spinlock.h> - -#if (defined(__PRE_RAM__) && \ -IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)) - #define LOCK_NVRAM_CBFS_SPINLOCK spin_lock(romstage_nvram_cbfs_lock()); - #define UNLOCK_NVRAM_CBFS_SPINLOCK spin_unlock(romstage_nvram_cbfs_lock()); -#else - #define LOCK_NVRAM_CBFS_SPINLOCK - #define UNLOCK_NVRAM_CBFS_SPINLOCK -#endif - -static void cmos_reset_date(void) -{ - /* Now setup a default date equals to the build date */ - struct rtc_time time = { - .sec = 0, - .min = 0, - .hour = 1, - .mday = bcd2bin(coreboot_build_date.day), - .mon = bcd2bin(coreboot_build_date.month), - .year = (bcd2bin(coreboot_build_date.century) * 100) + - bcd2bin(coreboot_build_date.year), - .wday = bcd2bin(coreboot_build_date.weekday) - }; - rtc_set(&time); -} - -static int cmos_checksum_valid(int range_start, int range_end, int cks_loc) -{ - if (IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) - return 1; - - int i; - u16 sum, old_sum; - sum = 0; - for (i = range_start; i <= range_end; i++) - sum += cmos_read(i); - old_sum = ((cmos_read(cks_loc) << 8) | cmos_read(cks_loc + 1)) & - 0x0ffff; - return sum == old_sum; -} - -static void cmos_set_checksum(int range_start, int range_end, int cks_loc) -{ - int i; - u16 sum; - sum = 0; - for (i = range_start; i <= range_end; i++) - sum += cmos_read(i); - cmos_write(((sum >> 8) & 0x0ff), cks_loc); - cmos_write(((sum >> 0) & 0x0ff), cks_loc + 1); -} - -#define RTC_CONTROL_DEFAULT (RTC_24H) -#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) - -#ifndef __SMM__ -void cmos_init(bool invalid) -{ - bool cmos_invalid = invalid; - bool checksum_invalid = false; - bool clear_cmos; - size_t i; - uint8_t x; - -#ifndef __PRE_RAM__ - /* - * Avoid clearing pending interrupts and resetting the RTC control - * register in the resume path because the Linux kernel relies on - * this to know if it should restart the RTC timer queue if the wake - * was due to the RTC alarm. - */ - if (acpi_is_wakeup_s3()) - return; -#endif /* __PRE_RAM__ */ - - printk(BIOS_DEBUG, "RTC Init\n"); - - if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { - /* See if there has been a CMOS power problem. */ - x = cmos_read(RTC_VALID); - cmos_invalid = !(x & RTC_VRT); - - /* See if there is a CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, - PC_CKS_RANGE_END, PC_CKS_LOC); - - clear_cmos = false; - } else { - clear_cmos = true; - } - - if (invalid || cmos_invalid || checksum_invalid) { - if (clear_cmos) { - cmos_write(0, 0x01); - cmos_write(0, 0x03); - cmos_write(0, 0x05); - for (i = 10; i < 128; i++) - cmos_write(0, i); - } - - if (cmos_invalid) - cmos_reset_date(); - - printk(BIOS_WARNING, "RTC:%s%s%s%s\n", - invalid ? " Clear requested":"", - cmos_invalid ? " Power Problem":"", - checksum_invalid ? " Checksum invalid":"", - clear_cmos ? " zeroing cmos":""); - } - - /* Setup the real time clock */ - cmos_write(RTC_CONTROL_DEFAULT, RTC_CONTROL); - /* Setup the frequency it operates at */ - cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT); - /* Ensure all reserved bits are 0 in register D */ - cmos_write(RTC_VRT, RTC_VALID); - - if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { - /* See if there is a LB CMOS checksum error */ - checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, - LB_CKS_RANGE_END,LB_CKS_LOC); - if (checksum_invalid) - printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); - - /* Make certain we have a valid checksum */ - cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); - } - - /* Clear any pending interrupts */ - cmos_read(RTC_INTR_FLAGS); -} -#endif /* __SMM__ */ - - -/* - * This routine returns the value of the requested bits. - * input bit = bit count from the beginning of the cmos image - * length = number of bits to include in the value - * ret = a character pointer to where the value is to be returned - * returns CB_SUCCESS = successful, cb_err code if an error occurred - */ -static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, - void *vret) -{ - unsigned char *ret; - unsigned long byte,byte_bit; - unsigned long i; - unsigned char uchar; - - /* - * The table is checked when it is built to ensure all - * values are valid. - */ - ret = vret; - byte = bit / 8; /* find the byte where the data starts */ - byte_bit = bit % 8; /* find the bit in the byte where the data starts */ - if (length < 9) { /* one byte or less */ - uchar = cmos_read(byte); /* load the byte */ - uchar >>= byte_bit; /* shift the bits to byte align */ - /* clear unspecified bits */ - ret[0] = uchar & ((1 << length) - 1); - } else { /* more that one byte so transfer the whole bytes */ - for (i = 0; length; i++, length -= 8, byte++) { - /* load the byte */ - ret[i] = cmos_read(byte); - } - } - return CB_SUCCESS; -} - -enum cb_err get_option(void *dest, const char *name) -{ - struct cmos_option_table *ct; - struct cmos_entries *ce; - size_t namelen; - int found = 0; - - if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) - return CB_CMOS_OTABLE_DISABLED; - - LOCK_NVRAM_CBFS_SPINLOCK - - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - - /* find the requested entry record */ - ct = cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK - return CB_CMOS_LAYOUT_NOT_FOUND; - } - ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length); - for(; ce->tag == LB_TAG_OPTION; - ce = (struct cmos_entries*)((unsigned char *)ce + ce->size)) { - if (memcmp(ce->name, name, namelen) == 0) { - found = 1; - break; - } - } - if (!found) { - printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - UNLOCK_NVRAM_CBFS_SPINLOCK - return CB_CMOS_OPTION_NOT_FOUND; - } - - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK - return CB_CMOS_ACCESS_ERROR; - } - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - UNLOCK_NVRAM_CBFS_SPINLOCK - return CB_CMOS_CHECKSUM_INVALID; - } - UNLOCK_NVRAM_CBFS_SPINLOCK - return CB_SUCCESS; -} - -static enum cb_err set_cmos_value(unsigned long bit, unsigned long length, - void *vret) -{ - unsigned char *ret; - unsigned long byte,byte_bit; - unsigned long i; - unsigned char uchar, mask; - unsigned int chksum_update_needed = 0; - - ret = vret; - byte = bit / 8; /* find the byte where the data starts */ - byte_bit = bit % 8; /* find the bit where the data starts */ - if (length <= 8) { /* one byte or less */ - mask = (1 << length) - 1; - mask <<= byte_bit; - - uchar = cmos_read(byte); - uchar &= ~mask; - uchar |= (ret[0] << byte_bit); - cmos_write(uchar, byte); - if (byte >= LB_CKS_RANGE_START && byte <= LB_CKS_RANGE_END) - chksum_update_needed = 1; - } else { /* more that one byte so transfer the whole bytes */ - if (byte_bit || length % 8) - return CB_ERR_ARG; - - for (i = 0; length; i++, length -= 8, byte++) - cmos_write(ret[i], byte); - if (byte >= LB_CKS_RANGE_START && - byte <= LB_CKS_RANGE_END) - chksum_update_needed = 1; - } - - if (chksum_update_needed) { - cmos_set_checksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END, - LB_CKS_LOC); - } - return CB_SUCCESS; -} - - -enum cb_err set_option(const char *name, void *value) -{ - struct cmos_option_table *ct; - struct cmos_entries *ce; - unsigned long length; - size_t namelen; - int found = 0; - - if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) - return CB_CMOS_OTABLE_DISABLED; - - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - - /* find the requested entry record */ - ct = cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); - if (!ct) { - printk(BIOS_ERR, "cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length); - for(; ce->tag == LB_TAG_OPTION; - ce = (struct cmos_entries*)((unsigned char *)ce + ce->size)) { - if (memcmp(ce->name, name, namelen) == 0) { - found = 1; - break; - } - } - if (!found) { - printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - return CB_CMOS_OPTION_NOT_FOUND; - } - - length = ce->length; - if (ce->config == 's') { - length = MAX(strlen((const char *)value) * 8, ce->length - 8); - /* make sure the string is null terminated */ - if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) - return (CB_CMOS_ACCESS_ERROR); - } - - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) - return (CB_CMOS_ACCESS_ERROR); - - return CB_SUCCESS; -} - -/* - * If the CMOS is cleared, the rtc_reg has the invalid date. That - * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need - * to make sure the date is valid. - */ -void cmos_check_update_date() -{ - u8 year, century; - - /* Assume hardware always supports RTC_CLK_ALTCENTURY. */ - century = cmos_read(RTC_CLK_ALTCENTURY); - year = cmos_read(RTC_CLK_YEAR); - - /* - * TODO: If century is 0xFF, 100% that the cmos is cleared. - * Other than that, so far rtc_year is the only entry to check - * if the date is valid. - */ - if (century > 0x99 || year > 0x99) /* Invalid date */ - cmos_reset_date(); -} - -int rtc_set(const struct rtc_time *time){ - cmos_write(bin2bcd(time->sec), RTC_CLK_SECOND); - cmos_write(bin2bcd(time->min), RTC_CLK_MINUTE); - cmos_write(bin2bcd(time->hour), RTC_CLK_HOUR); - cmos_write(bin2bcd(time->mday), RTC_CLK_DAYOFMONTH); - cmos_write(bin2bcd(time->mon), RTC_CLK_MONTH); - cmos_write(bin2bcd(time->year % 100), RTC_CLK_YEAR); - /* Same assumption as above: We always have RTC_CLK_ALTCENTURY */ - cmos_write(bin2bcd(time->year / 100), RTC_CLK_ALTCENTURY); - cmos_write(bin2bcd(time->wday + 1), RTC_CLK_DAYOFWEEK); - return 0; -} - -int rtc_get(struct rtc_time *time) -{ - time->sec = bcd2bin(cmos_read(RTC_CLK_SECOND)); - time->min = bcd2bin(cmos_read(RTC_CLK_MINUTE)); - time->hour = bcd2bin(cmos_read(RTC_CLK_HOUR)); - time->mday = bcd2bin(cmos_read(RTC_CLK_DAYOFMONTH)); - time->mon = bcd2bin(cmos_read(RTC_CLK_MONTH)); - time->year = bcd2bin(cmos_read(RTC_CLK_YEAR)); - /* Same assumption as above: We always have RTC_CLK_ALTCENTURY */ - time->year += bcd2bin(cmos_read(RTC_CLK_ALTCENTURY)) * 100; - time->wday = bcd2bin(cmos_read(RTC_CLK_DAYOFWEEK)) - 1; - return 0; -} diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c deleted file mode 100644 index 3ff5d4f..0000000 --- a/src/drivers/pc80/mc146818rtc_early.c +++ /dev/null @@ -1,103 +0,0 @@ -#include <stdint.h> -#include <pc80/mc146818rtc.h> -#include <fallback.h> -#if CONFIG_USE_OPTION_TABLE -#include "option_table.h" -#endif - -#if CONFIG_MAX_REBOOT_CNT > 15 -#error "CONFIG_MAX_REBOOT_CNT too high" -#endif - -static int cmos_error(void) -{ - unsigned char reg_d; - /* See if the cmos error condition has been flagged */ - reg_d = cmos_read(RTC_REG_D); - return (reg_d & RTC_VRT) == 0; -} - -static int cmos_chksum_valid(void) -{ -#if CONFIG_USE_OPTION_TABLE - unsigned char addr; - u16 sum, old_sum; - sum = 0; - /* Compute the cmos checksum */ - for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { - sum += cmos_read(addr); - } - - /* Read the stored checksum */ - old_sum = cmos_read(LB_CKS_LOC) << 8; - old_sum |= cmos_read(LB_CKS_LOC+1); - - return sum == old_sum; -#else - return 0; -#endif -} - -static inline __attribute__((unused)) int boot_count(uint8_t rtc_byte) -{ - return rtc_byte >> 4; -} - -static inline __attribute__((unused)) uint8_t increment_boot_count(uint8_t rtc_byte) -{ - return rtc_byte + (1 << 4); -} - -static inline __attribute__((unused)) uint8_t boot_set_fallback(uint8_t rtc_byte) -{ - return rtc_byte & ~RTC_BOOT_NORMAL; -} - -static inline __attribute__((unused)) int boot_use_normal(uint8_t rtc_byte) -{ - return rtc_byte & RTC_BOOT_NORMAL; -} - -static inline __attribute__((unused)) int do_normal_boot(void) -{ - unsigned char byte; - - if (cmos_error() || !cmos_chksum_valid()) { - /* Invalid CMOS checksum detected! - * Force fallback boot... - */ - byte = cmos_read(RTC_BOOT_BYTE); - byte &= boot_set_fallback(byte) & 0x0f; - byte |= 0xf << 4; - cmos_write(byte, RTC_BOOT_BYTE); - } - - /* The RTC_BOOT_BYTE is now o.k. see where to go. */ - byte = cmos_read(RTC_BOOT_BYTE); - - /* Are we attempting to boot normally? */ - if (boot_use_normal(byte)) { - /* Are we already at the max count? */ - if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT) - byte = increment_boot_count(byte); - else - byte = boot_set_fallback(byte); - } - - /* Save the boot byte */ - cmos_write(byte, RTC_BOOT_BYTE); - - /* Return selected code path for this boot attempt */ - return boot_use_normal(byte); -} - -unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) -{ -#if CONFIG_USE_OPTION_TABLE - unsigned byte; - byte = cmos_read(start/8); - return (byte >> (start & 7U)) & ((1U << size) - 1U); -#else - return def; -#endif -} diff --git a/src/drivers/pc80/pc/Kconfig b/src/drivers/pc80/pc/Kconfig new file mode 100644 index 0000000..c44cf91 --- /dev/null +++ b/src/drivers/pc80/pc/Kconfig @@ -0,0 +1,18 @@ +# Might be removed (alongside with the PS/2 init code) once payloads +# reliably support PS/2 init themselves. + +config DRIVERS_PS2_KEYBOARD + bool "PS/2 keyboard init" + default n + depends on PC80_SYSTEM + help + Enable this option to initialize PS/2 keyboards found connected + to the PS/2 port. + + Some payloads (eg, filo) require this option. Other payloads + (eg, GRUB 2, SeaBIOS, Linux) do not require it. + Initializing a PS/2 keyboard can take several hundred milliseconds. + + If you know you will only use a payload which does not require + this option, then you can say N here to speed up boot time. + Otherwise say Y. diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc new file mode 100644 index 0000000..550ca12 --- /dev/null +++ b/src/drivers/pc80/pc/Makefile.inc @@ -0,0 +1,11 @@ +ifeq ($(CONFIG_ARCH_X86),y) + +ramstage-y += isa-dma.c +ramstage-y += i8254.c +ramstage-y += i8259.c +ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c +ramstage-y += keyboard.c +ramstage-$(CONFIG_SPKMODEM) += spkmodem.c +romstage-$(CONFIG_SPKMODEM) += spkmodem.c + +endif diff --git a/src/drivers/pc80/pc/i8254.c b/src/drivers/pc80/pc/i8254.c new file mode 100644 index 0000000..5851ec0 --- /dev/null +++ b/src/drivers/pc80/pc/i8254.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <pc80/i8254.h> +#include <console/console.h> + +/* Initialize i8254 timers */ + +void setup_i8254(void) +{ + /* Timer 0 (taken from biosemu) */ + outb(TIMER0_SEL | WORD_ACCESS | MODE3 | BINARY_COUNT, TIMER_MODE_PORT); + outb(0x00, TIMER0_PORT); + outb(0x00, TIMER0_PORT); + + /* Timer 1 */ + outb(TIMER1_SEL | LOBYTE_ACCESS | MODE3 | BINARY_COUNT, + TIMER_MODE_PORT); + outb(0x12, TIMER1_PORT); +} + +#if CONFIG_UDELAY_TIMER2 +static void load_timer2(unsigned int ticks) +{ + /* Set up the timer gate, turn off the speaker */ + outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); + outb(TIMER2_SEL | WORD_ACCESS | MODE0 | BINARY_COUNT, TIMER_MODE_PORT); + outb(ticks & 0xFF, TIMER2_PORT); + outb(ticks >> 8, TIMER2_PORT); +} + +void udelay(int usecs) +{ + load_timer2((usecs * TICKS_PER_MS) / 1000); + while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) + ; +} +#endif diff --git a/src/drivers/pc80/pc/i8259.c b/src/drivers/pc80/pc/i8259.c new file mode 100644 index 0000000..4261d5b --- /dev/null +++ b/src/drivers/pc80/pc/i8259.c @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <pc80/i8259.h> +#include <console/console.h> + +/* Read the current PIC IRQ mask */ +u16 pic_read_irq_mask(void) +{ + u16 mask; + int i; + + mask = inb(MASTER_PIC_OCW1) | (inb(SLAVE_PIC_OCW1) << 8); + + printk(BIOS_DEBUG, "8259 PIC: OCW1 IRQ Mask: 0x%x\n", mask); + printk(BIOS_SPEW, "\tEnabled IRQs (0 = Unmasked, 1 = Masked off):\n" + "\t\tMaster\t\tSlave\n"); + for (i = 0; i <= 7; i++) { + printk(BIOS_SPEW, "\t\tIRQ%X: %x\t\tIRQ%X: %x\n", + i, (mask >> i) & 1, i + 8, (mask >> (i + 8)) & 1); + } + return mask; +} + +/* + * Write an IRQ mask to the PIC: + * IRQA is bit 0xA in the 16 bit bitmask (OCW1) + */ +void pic_write_irq_mask(u16 mask) +{ + outb(mask, MASTER_PIC_OCW1); + outb(mask >> 8, SLAVE_PIC_OCW1); +} + +/* + * The PIC IRQs default to masked off + * Allow specific IRQs to be enabled (1) + * or disabled by (0) the user + */ +void pic_irq_enable(u8 int_num, u8 mask) +{ + pic_write_irq_mask(pic_read_irq_mask() & ~(mask << int_num)); + pic_read_irq_mask(); +} + +void setup_i8259(void) +{ + /* A write to ICW1 starts the Interrupt Controller Initialization + * Sequence. This implicitly causes the following to happen: + * - Interrupt Mask register is cleared + * - Priority 7 is assigned to IRQ7 input + * - Slave mode address is set to 7 + * - Special mask mode is cleared + * + * We send the initialization sequence to both the master and + * slave i8259 controller. + */ + outb(ICW_SELECT|IC4, MASTER_PIC_ICW1); + outb(ICW_SELECT|IC4, SLAVE_PIC_ICW1); + + /* Now the interrupt controller expects us to write to ICW2. */ + outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2); + outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2); + + /* Now the interrupt controller expects us to write to ICW3. + * + * The normal scenario is to set up cascading on IRQ2 on the master + * i8259 and assign the slave ID 2 to the slave i8259. + */ + outb(CASCADED_PIC, MASTER_PIC_ICW3); + outb(SLAVE_ID, SLAVE_PIC_ICW3); + + /* Now the interrupt controller expects us to write to ICW4. + * + * We switch both i8259 to microprocessor mode because they're + * operating as part of an x86 architecture based chipset + */ + outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2); + outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2); + + /* Now clear the interrupts through OCW1. + * First we mask off all interrupts on the slave interrupt controller + * then we mask off all interrupts but interrupt 2 on the master + * controller. This way the cascading stays alive. + */ + outb(ALL_IRQS, SLAVE_PIC_OCW1); + outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1); +} + +/** + * @brief Configure IRQ triggering in the i8259 compatible Interrupt Controller. + * + * Switch a certain interrupt to be level / edge triggered. + * + * @param int_num legacy interrupt number (3-7, 9-15) + * @param is_level_triggered 1 for level triggered interrupt, 0 for edge + * triggered interrupt + */ +void i8259_configure_irq_trigger(int int_num, int is_level_triggered) +{ + u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8); + + if (is_level_triggered) + int_bits |= (1 << int_num); + else + int_bits &= ~(1 << int_num); + + /* Write new values */ + outb((u8)(int_bits & 0xff), ELCR1); + outb((u8)(int_bits >> 8), ELCR2); + +#ifdef PARANOID_IRQ_TRIGGERS + /* Try reading back the new values. This seems like an error + * but it is not. */ + if (inb(ELCR1) != (int_bits & 0xff)) { + printk(BIOS_ERR, "%s: lower order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (int_bits & 0xff), inb(ELCR1)); + } + + if (inb(ELCR2) != (int_bits >> 8)) { + printk(BIOS_ERR, "%s: higher order bits are wrong: want 0x%x, got 0x%x\n", + __func__, (int_bits>>8), inb(ELCR2)); + } +#endif +} diff --git a/src/drivers/pc80/pc/isa-dma.c b/src/drivers/pc80/pc/isa-dma.c new file mode 100644 index 0000000..b64f125 --- /dev/null +++ b/src/drivers/pc80/pc/isa-dma.c @@ -0,0 +1,44 @@ +#include <arch/io.h> +#include <pc80/isa-dma.h> + +/* DMA controller registers */ +#define DMA1_CMD_REG 0x08 /* command register (w) */ +#define DMA1_STAT_REG 0x08 /* status register (r) */ +#define DMA1_REQ_REG 0x09 /* request register (w) */ +#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ +#define DMA1_MODE_REG 0x0B /* mode register (w) */ +#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ +#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ +#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ +#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ +#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ + +#define DMA2_CMD_REG 0xD0 /* command register (w) */ +#define DMA2_STAT_REG 0xD0 /* status register (r) */ +#define DMA2_REQ_REG 0xD2 /* request register (w) */ +#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ +#define DMA2_MODE_REG 0xD6 /* mode register (w) */ +#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ +#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ +#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ +#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ +#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ + +#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ +#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ +#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ + +#define DMA_AUTOINIT 0x10 + + +void isa_dma_init(void) +{ + /* slave at 0x00 - 0x0f */ + /* master at 0xc0 - 0xdf */ + /* 0x80 - 0x8f DMA page registers */ + /* DMA: 0x00, 0x02, 0x4, 0x06 base address for DMA channel */ + outb(0, DMA1_RESET_REG); + outb(0, DMA2_RESET_REG); + outb(DMA_MODE_CASCADE, DMA2_MODE_REG); + outb(0, DMA2_MASK_REG); +} diff --git a/src/drivers/pc80/pc/keyboard.c b/src/drivers/pc80/pc/keyboard.c new file mode 100644 index 0000000..415dbd1 --- /dev/null +++ b/src/drivers/pc80/pc/keyboard.c @@ -0,0 +1,387 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Raptor Engineering + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2003 Ollie Lo <ollielo(a)hotmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <pc80/keyboard.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <types.h> +#include <arch/acpi.h> + +#define KBD_DATA 0x60 +#define KBD_COMMAND 0x64 +#define KBD_STATUS 0x64 +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) + +// Keyboard Controller Commands +#define KBC_CMD_READ_COMMAND 0x20 // Read command byte +#define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte +#define KBC_CMD_AUX_ENABLE 0xA8 // Auxiliary Interface enable +#define KBC_CMD_AUX_TEST 0xA9 // Auxiliary Interface test +#define KBC_CMD_SELF_TEST 0xAA // Controller self-test +#define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test + +/* The Keyboard controller command byte + * BIT | Description + * ----+------------------------------------------------------- + * 7 | reserved, must be zero + * 6 | XT Translation, (1 = on, 0 = off) + * 5 | Disable Mouse Port (1 = disable, 0 = enable) + * 4 | Disable Keyboard Port (1 = disable, 0 = enable) + * 3 | reserved, must be zero + * 2 | System Flag (1 = self-test passed. DO NOT SET TO ZERO) + * 1 | Mouse Port Interrupts (1 = enable, 0 = disable) + * 0 | Keyboard Port Interrupts (1 = enable, 0 = disable) + */ + +// Keyboard Controller Replies +#define KBC_REPLY_SELFTEST_OK 0x55 // controller self-test succeeded + +// +// Keyboard Replies +// +#define KBD_REPLY_POR 0xAA // Power on reset +#define KBD_REPLY_ACK 0xFA // Command ACK +#define KBD_REPLY_RESEND 0xFE // Command NACK, send command again + +/* Wait 400ms for keyboard controller answers */ +#define KBC_TIMEOUT_IN_MS 400 + +static int kbc_input_buffer_empty(void) +{ + u32 timeout; + + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && (inb(KBD_STATUS) & KBD_IBF); timeout--) + mdelay(1); + + if (!timeout) + printk(BIOS_WARNING, + "Unexpected Keyboard controller input buffer full\n"); + return !!timeout; +} + +static int kbc_output_buffer_full(void) +{ + u32 timeout; + + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && ((inb(KBD_STATUS) & KBD_OBF) == 0); timeout--) + mdelay(1); + + if (!timeout) + printk(BIOS_INFO, + "Keyboard controller output buffer result timeout\n"); + return !!timeout; +} + +static int kbc_cleanup_buffers(void) +{ + u32 timeout; + + for (timeout = KBC_TIMEOUT_IN_MS; + timeout && (inb(KBD_STATUS) & (KBD_OBF | KBD_IBF)); timeout--) { + mdelay(1); + inb(KBD_DATA); + } + + if (!timeout) { + printk(BIOS_ERR, + "Couldn't cleanup the keyboard controller buffers\n"); + printk(BIOS_ERR, "Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n", + KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA)); + } + + return !!timeout; +} + +static enum cb_err kbc_self_test(uint8_t probe_aux, uint8_t *aux_probe_result) +{ + uint8_t self_test; + uint8_t byte; + + /* Set initial aux probe output value */ + if (aux_probe_result) + *aux_probe_result = 0; + + /* Clean up any junk that might have been in the KBC. + * Both input and output buffers must be empty. + */ + if (!kbc_cleanup_buffers()) + return CB_KBD_CONTROLLER_FAILURE; + + /* reset/self test 8042 - send cmd 0xAA */ + outb(KBC_CMD_SELF_TEST, KBD_COMMAND); + + if (!kbc_output_buffer_full()) { + /* There probably is no keyboard controller. */ + printk(BIOS_ERR, "Could not reset keyboard controller.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + + /* read self-test result, 0x55 is returned in the output buffer */ + self_test = inb(KBD_DATA); + + if (self_test != 0x55) { + printk(BIOS_ERR, "Keyboard Controller self-test failed: 0x%x\n", + self_test); + return CB_KBD_CONTROLLER_FAILURE; + } + + /* ensure the buffers are empty */ + kbc_cleanup_buffers(); + + /* keyboard interface test */ + outb(KBC_CMD_KBD_TEST, KBD_COMMAND); + + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Keyboard Interface test timed out.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + + /* read test result, 0x00 should be returned in case of no failures */ + self_test = inb(KBD_DATA); + + if (self_test != 0x00) { + printk(BIOS_ERR, "Keyboard Interface test failed: 0x%x\n", + self_test); + return CB_KBD_INTERFACE_FAILURE; + } + + if (probe_aux) { + /* aux interface detect */ + outb(KBC_CMD_AUX_ENABLE, KBD_COMMAND); + if (!kbc_input_buffer_empty()) { + printk(BIOS_ERR, "Timeout waiting for controller during aux enable.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + outb(KBC_CMD_READ_COMMAND, KBD_COMMAND); + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Timeout waiting for controller during aux probe.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + + byte = inb(KBD_DATA); + if (!(byte & (0x1 << 5))) { + printk(BIOS_DEBUG, "PS/2 auxiliary channel detected...\n"); + + /* auxiliary interface test */ + outb(KBC_CMD_AUX_TEST, KBD_COMMAND); + + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Auxiliary channel probe timed out.\n"); + goto aux_failure; + } + + /* read test result, 0x00 should be returned in case of no failures */ + self_test = inb(KBD_DATA); + + if (self_test != 0x00) { + printk(BIOS_ERR, "No device detected on auxiliary channel: 0x%x\n", + self_test); + goto aux_failure; + } + + printk(BIOS_DEBUG, "PS/2 device detected on auxiliary channel\n"); + if (aux_probe_result) + *aux_probe_result = 1; + } + } + +aux_failure: + + return CB_SUCCESS; +} + +static u8 send_keyboard(u8 command) +{ + u8 regval = 0; + u8 resend = 10; + + do { + if (!kbc_input_buffer_empty()) + return 0; + outb(command, KBD_DATA); + /* the reset command takes much longer then normal commands and + * even worse, some keyboards do send the ACK _after_ doing the + * reset */ + if (command == 0xFF) { + u8 retries; + + for (retries = 9; retries && !kbc_output_buffer_full(); + retries--) + ; + } + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, + "Could not send keyboard command %02x\n", + command); + return 0; + } + regval = inb(KBD_DATA); + --resend; + } while (regval == KBD_REPLY_RESEND && resend > 0); + + return regval; +} + +uint8_t pc_keyboard_init(uint8_t probe_aux) +{ + u8 retries; + u8 regval; + enum cb_err err; + uint8_t aux_dev_detected; + + if (!CONFIG_DRIVERS_PS2_KEYBOARD) + return 0; + + if (acpi_is_wakeup_s3()) + return 0; + + printk(BIOS_DEBUG, "Keyboard init...\n"); + + /* Run a keyboard controller self-test */ + err = kbc_self_test(probe_aux, &aux_dev_detected); + /* Ignore iterface failure as it's non-fatal. */ + if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) + return 0; + + /* Enable keyboard interface - No IRQ */ + if (!kbc_input_buffer_empty()) + return 0; + outb(0x60, KBD_COMMAND); + if (!kbc_input_buffer_empty()) + return 0; + outb(0x20, KBD_DATA); /* send cmd: enable keyboard */ + if (!kbc_input_buffer_empty()) { + printk(BIOS_INFO, "Timeout while enabling keyboard\n"); + return 0; + } + + /* clean up any junk that might have been in the keyboard */ + if (!kbc_cleanup_buffers()) + return 0; + + /* reset keyboard and self test (keyboard side) */ + regval = send_keyboard(0xFF); + if (regval == KBD_REPLY_RESEND) { + /* keeps sending RESENDs, probably no keyboard. */ + printk(BIOS_INFO, "No PS/2 keyboard detected.\n"); + return 0; + } + + if (regval != KBD_REPLY_ACK) { + printk(BIOS_ERR, "Keyboard reset failed ACK: 0x%x\n", regval); + return 0; + } + + /* the reset command takes some time, so wait a little longer */ + for (retries = 9; retries && !kbc_output_buffer_full(); retries--) + ; + + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n"); + return 0; + } + + regval = inb(KBD_DATA); + if (regval != 0xAA) { + printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", + regval); + return 0; + } + + /* + * The following set scancode stuff is what normal BIOS do. It could be + * argued that coreboot shouldn't set the scan code..... + */ + + /* disable the keyboard */ + regval = send_keyboard(0xF5); + if (regval != KBD_REPLY_ACK) { + printk(BIOS_ERR, "Keyboard disable failed ACK: 0x%x\n", regval); + return 0; + } + + /* Set scancode command */ + regval = send_keyboard(0xF0); + if (regval != KBD_REPLY_ACK) { + printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", + regval); + return 0; + } + /* Set scancode mode 2 */ + regval = send_keyboard(0x02); + if (regval != KBD_REPLY_ACK) { + printk(BIOS_ERR, + "Keyboard set scancode mode failed ACK: 0x%x\n", regval); + return 0; + } + + /* All is well - enable keyboard interface */ + if (!kbc_input_buffer_empty()) + return 0; + outb(0x60, KBD_COMMAND); + if (!kbc_input_buffer_empty()) + return 0; + outb(0x65, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ + if (!kbc_input_buffer_empty()) { + printk(BIOS_ERR, "Timeout during keyboard enable\n"); + return 0; + } + + /* enable the keyboard */ + regval = send_keyboard(0xF4); + if (regval != KBD_REPLY_ACK) { + printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval); + return 0; + } + + printk(BIOS_DEBUG, "PS/2 keyboard initialized on primary channel\n"); + + return aux_dev_detected; +} + +/* + * Support PS/2 mode - oddball SIOs(KBC) need this setup + * Not well documented. Google - 0xcb keyboard controller + * This is called before pc_keyboard_init(). + */ +void set_kbc_ps2_mode(void) +{ + enum cb_err err; + + /* Run a keyboard controller self-test */ + err = kbc_self_test(0, NULL); + /* Ignore iterface failure as it's non-fatal. */ + if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) + return; + + /* Support PS/2 mode */ + if (!kbc_input_buffer_empty()) + return; + outb(0xcb, KBD_COMMAND); + + if (!kbc_input_buffer_empty()) + return; + outb(0x01, KBD_DATA); + + kbc_cleanup_buffers(); +} diff --git a/src/drivers/pc80/pc/ps2_controller.asl b/src/drivers/pc80/pc/ps2_controller.asl new file mode 100644 index 0000000..a4984cf --- /dev/null +++ b/src/drivers/pc80/pc/ps2_controller.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + Return (0xf) + } + } diff --git a/src/drivers/pc80/pc/spkmodem.c b/src/drivers/pc80/pc/spkmodem.c new file mode 100644 index 0000000..df66f6f --- /dev/null +++ b/src/drivers/pc80/pc/spkmodem.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/io.h> +#include <console/spkmodem.h> +#include <cpu/x86/tsc.h> + +#define SPEAKER_PIT_FREQUENCY 0x1234dd + + +enum { + PIT_COUNTER_0 = 0x40, + PIT_COUNTER_1 = 0x41, + PIT_COUNTER_2 = 0x42, + PIT_CTRL = 0x43, + PIT_SPEAKER_PORT = 0x61, +}; + + +enum { + PIT_SPK_TMR2 = 0x01, + PIT_SPK_DATA = 0x02, + PIT_SPK_TMR2_LATCH = 0x20 +}; + +enum { + PIT_CTRL_SELECT_MASK = 0xc0, + PIT_CTRL_SELECT_0 = 0x00, + PIT_CTRL_SELECT_1 = 0x40, + PIT_CTRL_SELECT_2 = 0x80, + + PIT_CTRL_READLOAD_MASK = 0x30, + PIT_CTRL_COUNTER_LATCH = 0x00, + PIT_CTRL_READLOAD_LSB = 0x10, + PIT_CTRL_READLOAD_MSB = 0x20, + PIT_CTRL_READLOAD_WORD = 0x30, + + PIT_CTRL_MODE_MASK = 0x0e, + PIT_CTRL_INTR_ON_TERM = 0x00, + PIT_CTRL_PROGR_ONE_SHOT = 0x02, + + PIT_CTRL_RATE_GEN = 0x04, + + PIT_CTRL_SQUAREWAVE_GEN = 0x06, + PIT_CTRL_SOFTSTROBE = 0x08, + + PIT_CTRL_HARDSTROBE = 0x0a, + + + PIT_CTRL_COUNT_MASK = 0x01, + PIT_CTRL_COUNT_BINARY = 0x00, + PIT_CTRL_COUNT_BCD = 0x01 +}; + + +static void +make_tone(uint16_t freq_count, unsigned int duration) +{ + outb(PIT_CTRL_SELECT_2 + | PIT_CTRL_READLOAD_WORD + | PIT_CTRL_SQUAREWAVE_GEN + | PIT_CTRL_COUNT_BINARY, PIT_CTRL); + + outb(freq_count & 0xff, PIT_COUNTER_2); + + outb((freq_count >> 8) & 0xff, PIT_COUNTER_2); + + outb(inb(PIT_SPEAKER_PORT) + | PIT_SPK_TMR2 | PIT_SPK_DATA, + PIT_SPEAKER_PORT); + + for (; duration; duration--) { + unsigned short counter, previous_counter = 0xffff; + + while (1) { + counter = inb(PIT_COUNTER_2); + counter |= ((uint16_t)inb(PIT_COUNTER_2)) << 8; + if (counter > previous_counter) { + previous_counter = counter; + break; + } + previous_counter = counter; + } + } +} + +void spkmodem_tx_byte(unsigned char c) +{ + int i; + + make_tone(SPEAKER_PIT_FREQUENCY / 200, 4); + for (i = 7; i >= 0; i--) { + if ((c >> i) & 1) + make_tone(SPEAKER_PIT_FREQUENCY / 2000, 20); + else + make_tone(SPEAKER_PIT_FREQUENCY / 4000, 40); + make_tone(SPEAKER_PIT_FREQUENCY / 1000, 10); + } + make_tone(SPEAKER_PIT_FREQUENCY / 200, 0); +} + +void spkmodem_init(void) +{ + /* Some cards need time to come online. + * Output some message to get it started. + */ + spkmodem_tx_byte('S'); + spkmodem_tx_byte('P'); + spkmodem_tx_byte('K'); + spkmodem_tx_byte('\r'); + spkmodem_tx_byte('\n'); +} diff --git a/src/drivers/pc80/pc/udelay_io.c b/src/drivers/pc80/pc/udelay_io.c new file mode 100644 index 0000000..3305e4c --- /dev/null +++ b/src/drivers/pc80/pc/udelay_io.c @@ -0,0 +1,14 @@ +#include <arch/io.h> +#include <delay.h> + +void init_timer(void) +{ +} + +void udelay(unsigned usecs) +{ + int i; + + for (i = 0; i < usecs; i++) + inb(0x80); +} diff --git a/src/drivers/pc80/ps2_controller.asl b/src/drivers/pc80/ps2_controller.asl deleted file mode 100644 index a4984cf..0000000 --- a/src/drivers/pc80/ps2_controller.asl +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - Device (PS2K) // Keyboard - { - Name(_HID, EISAID("PNP0303")) - Name(_CID, EISAID("PNP030B")) - - Name(_CRS, ResourceTemplate() - { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) - IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 - }) - - Method (_STA, 0) - { - Return (0xf) - } - } - - Device (PS2M) // Mouse - { - Name(_HID, EISAID("PNP0F13")) - Name(_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 - }) - - Method(_STA, 0) - { - Return (0xf) - } - } diff --git a/src/drivers/pc80/rtc/Kconfig b/src/drivers/pc80/rtc/Kconfig new file mode 100644 index 0000000..350863e --- /dev/null +++ b/src/drivers/pc80/rtc/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_MC146818 + bool + default y if ARCH_X86 + depends on PC80_SYSTEM diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc new file mode 100644 index 0000000..d3b3344 --- /dev/null +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_ARCH_X86),y) + +romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c +romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c + +ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_early.c +ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c + +cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default +cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool +cmos.default-type = 0xaa + +smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c + +endif diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c new file mode 100644 index 0000000..7f98be2 --- /dev/null +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -0,0 +1,400 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <bcd.h> +#include <stdint.h> +#include <version.h> +#include <console/console.h> +#include <pc80/mc146818rtc.h> +#include <boot/coreboot_tables.h> +#include <rtc.h> +#include <string.h> +#include <cbfs.h> + +/* There's no way around this include guard. option_table.h is autogenerated */ +#if CONFIG_USE_OPTION_TABLE +#include "option_table.h" +#else +#define LB_CKS_RANGE_START 0 +#define LB_CKS_RANGE_END 0 +#define LB_CKS_LOC 0 +#endif + +#include <smp/spinlock.h> + +#if (defined(__PRE_RAM__) && \ +IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)) + #define LOCK_NVRAM_CBFS_SPINLOCK() spin_lock(romstage_nvram_cbfs_lock()) + #define UNLOCK_NVRAM_CBFS_SPINLOCK() spin_unlock(romstage_nvram_cbfs_lock()) +#else + #define LOCK_NVRAM_CBFS_SPINLOCK() { } + #define UNLOCK_NVRAM_CBFS_SPINLOCK() { } +#endif + +static void cmos_reset_date(void) +{ + /* Now setup a default date equals to the build date */ + struct rtc_time time = { + .sec = 0, + .min = 0, + .hour = 1, + .mday = bcd2bin(coreboot_build_date.day), + .mon = bcd2bin(coreboot_build_date.month), + .year = (bcd2bin(coreboot_build_date.century) * 100) + + bcd2bin(coreboot_build_date.year), + .wday = bcd2bin(coreboot_build_date.weekday) + }; + rtc_set(&time); +} + +static int cmos_checksum_valid(int range_start, int range_end, int cks_loc) +{ + int i; + u16 sum, old_sum; + + if (IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) + return 1; + + sum = 0; + for (i = range_start; i <= range_end; i++) + sum += cmos_read(i); + old_sum = ((cmos_read(cks_loc) << 8) | cmos_read(cks_loc + 1)) & + 0x0ffff; + return sum == old_sum; +} + +static void cmos_set_checksum(int range_start, int range_end, int cks_loc) +{ + int i; + u16 sum; + + sum = 0; + for (i = range_start; i <= range_end; i++) + sum += cmos_read(i); + cmos_write(((sum >> 8) & 0x0ff), cks_loc); + cmos_write(((sum >> 0) & 0x0ff), cks_loc + 1); +} + +#define RTC_CONTROL_DEFAULT (RTC_24H) +#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) + +#ifndef __SMM__ +void cmos_init(bool invalid) +{ + bool cmos_invalid = invalid; + bool checksum_invalid = false; + bool clear_cmos; + size_t i; + uint8_t x; + +#ifndef __PRE_RAM__ + /* + * Avoid clearing pending interrupts and resetting the RTC control + * register in the resume path because the Linux kernel relies on + * this to know if it should restart the RTC timer queue if the wake + * was due to the RTC alarm. + */ + if (acpi_is_wakeup_s3()) + return; +#endif /* __PRE_RAM__ */ + + printk(BIOS_DEBUG, "RTC Init\n"); + + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + /* See if there has been a CMOS power problem. */ + x = cmos_read(RTC_VALID); + cmos_invalid = !(x & RTC_VRT); + + /* See if there is a CMOS checksum error */ + checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, + PC_CKS_RANGE_END, PC_CKS_LOC); + + clear_cmos = false; + } else { + clear_cmos = true; + } + + if (invalid || cmos_invalid || checksum_invalid) { + if (clear_cmos) { + cmos_write(0, 0x01); + cmos_write(0, 0x03); + cmos_write(0, 0x05); + for (i = 10; i < 128; i++) + cmos_write(0, i); + } + + if (cmos_invalid) + cmos_reset_date(); + + printk(BIOS_WARNING, "RTC:%s%s%s%s\n", + invalid ? " Clear requested":"", + cmos_invalid ? " Power Problem":"", + checksum_invalid ? " Checksum invalid":"", + clear_cmos ? " zeroing cmos":""); + } + + /* Setup the real time clock */ + cmos_write(RTC_CONTROL_DEFAULT, RTC_CONTROL); + /* Setup the frequency it operates at */ + cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT); + /* Ensure all reserved bits are 0 in register D */ + cmos_write(RTC_VRT, RTC_VALID); + + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { + /* See if there is a LB CMOS checksum error */ + checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START, + LB_CKS_RANGE_END, LB_CKS_LOC); + if (checksum_invalid) + printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); + + /* Make certain we have a valid checksum */ + cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC); + } + + /* Clear any pending interrupts */ + cmos_read(RTC_INTR_FLAGS); +} +#endif /* __SMM__ */ + + +/* + * This routine returns the value of the requested bits. + * input bit = bit count from the beginning of the cmos image + * length = number of bits to include in the value + * ret = a character pointer to where the value is to be returned + * returns CB_SUCCESS = successful, cb_err code if an error occurred + */ +static enum cb_err get_cmos_value(unsigned long bit, unsigned long length, + void *vret) +{ + unsigned char *ret; + unsigned long byte, byte_bit; + unsigned long i; + unsigned char uchar; + + /* + * The table is checked when it is built to ensure all + * values are valid. + */ + ret = vret; + byte = bit / 8; /* find the byte where the data starts */ + byte_bit = bit % 8; /* find the bit in the byte where the data starts */ + if (length < 9) { /* one byte or less */ + uchar = cmos_read(byte); /* load the byte */ + uchar >>= byte_bit; /* shift the bits to byte align */ + /* clear unspecified bits */ + ret[0] = uchar & ((1 << length) - 1); + } else { /* more that one byte so transfer the whole bytes */ + for (i = 0; length; i++, length -= 8, byte++) { + /* load the byte */ + ret[i] = cmos_read(byte); + } + } + return CB_SUCCESS; +} + +enum cb_err get_option(void *dest, const char *name) +{ + struct cmos_option_table *ct; + struct cmos_entries *ce; + size_t namelen; + int found = 0; + + if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + + LOCK_NVRAM_CBFS_SPINLOCK(); + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + /* find the requested entry record */ + ct = cbfs_boot_map_with_leak("cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT, NULL); + if (!ct) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " \ + "Options are disabled\n"); + + UNLOCK_NVRAM_CBFS_SPINLOCK(); + return CB_CMOS_LAYOUT_NOT_FOUND; + } + ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); + for (; ce->tag == LB_TAG_OPTION; + ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { + if (memcmp(ce->name, name, namelen) == 0) { + found = 1; + break; + } + } + if (!found) { + printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); + UNLOCK_NVRAM_CBFS_SPINLOCK(); + return CB_CMOS_OPTION_NOT_FOUND; + } + + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { + UNLOCK_NVRAM_CBFS_SPINLOCK(); + return CB_CMOS_ACCESS_ERROR; + } + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { + UNLOCK_NVRAM_CBFS_SPINLOCK(); + return CB_CMOS_CHECKSUM_INVALID; + } + UNLOCK_NVRAM_CBFS_SPINLOCK(); + return CB_SUCCESS; +} + +static enum cb_err set_cmos_value(unsigned long bit, unsigned long length, + void *vret) +{ + unsigned char *ret; + unsigned long byte, byte_bit; + unsigned long i; + unsigned char uchar, mask; + unsigned int chksum_update_needed = 0; + + ret = vret; + byte = bit / 8; /* find the byte where the data starts */ + byte_bit = bit % 8; /* find the bit where the data starts */ + if (length <= 8) { /* one byte or less */ + mask = (1 << length) - 1; + mask <<= byte_bit; + + uchar = cmos_read(byte); + uchar &= ~mask; + uchar |= (ret[0] << byte_bit); + cmos_write(uchar, byte); + if (byte >= LB_CKS_RANGE_START && byte <= LB_CKS_RANGE_END) + chksum_update_needed = 1; + } else { /* more that one byte so transfer the whole bytes */ + if (byte_bit || length % 8) + return CB_ERR_ARG; + + for (i = 0; length; i++, length -= 8, byte++) + cmos_write(ret[i], byte); + if (byte >= LB_CKS_RANGE_START && + byte <= LB_CKS_RANGE_END) + chksum_update_needed = 1; + } + + if (chksum_update_needed) { + cmos_set_checksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END, + LB_CKS_LOC); + } + return CB_SUCCESS; +} + + +enum cb_err set_option(const char *name, void *value) +{ + struct cmos_option_table *ct; + struct cmos_entries *ce; + unsigned long length; + size_t namelen; + int found = 0; + + if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + /* find the requested entry record */ + ct = cbfs_boot_map_with_leak("cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT, NULL); + if (!ct) { + printk(BIOS_ERR, "cmos_layout.bin could not be found. " \ + "Options are disabled\n"); + return CB_CMOS_LAYOUT_NOT_FOUND; + } + ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); + for (; ce->tag == LB_TAG_OPTION; + ce = (struct cmos_entries *)((unsigned char *)ce + ce->size)) { + if (memcmp(ce->name, name, namelen) == 0) { + found = 1; + break; + } + } + if (!found) { + printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); + return CB_CMOS_OPTION_NOT_FOUND; + } + + length = ce->length; + if (ce->config == 's') { + length = MAX(strlen((const char *)value) * 8, ce->length - 8); + /* make sure the string is null terminated */ + if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) + != CB_SUCCESS) + return CB_CMOS_ACCESS_ERROR; + } + + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) + return CB_CMOS_ACCESS_ERROR; + + return CB_SUCCESS; +} + +/* + * If the CMOS is cleared, the rtc_reg has the invalid date. That + * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need + * to make sure the date is valid. + */ +void cmos_check_update_date(void) +{ + u8 year, century; + + /* Assume hardware always supports RTC_CLK_ALTCENTURY. */ + century = cmos_read(RTC_CLK_ALTCENTURY); + year = cmos_read(RTC_CLK_YEAR); + + /* + * TODO: If century is 0xFF, 100% that the cmos is cleared. + * Other than that, so far rtc_year is the only entry to check + * if the date is valid. + */ + if (century > 0x99 || year > 0x99) /* Invalid date */ + cmos_reset_date(); +} + +int rtc_set(const struct rtc_time *time) +{ + cmos_write(bin2bcd(time->sec), RTC_CLK_SECOND); + cmos_write(bin2bcd(time->min), RTC_CLK_MINUTE); + cmos_write(bin2bcd(time->hour), RTC_CLK_HOUR); + cmos_write(bin2bcd(time->mday), RTC_CLK_DAYOFMONTH); + cmos_write(bin2bcd(time->mon), RTC_CLK_MONTH); + cmos_write(bin2bcd(time->year % 100), RTC_CLK_YEAR); + /* Same assumption as above: We always have RTC_CLK_ALTCENTURY */ + cmos_write(bin2bcd(time->year / 100), RTC_CLK_ALTCENTURY); + cmos_write(bin2bcd(time->wday + 1), RTC_CLK_DAYOFWEEK); + return 0; +} + +int rtc_get(struct rtc_time *time) +{ + time->sec = bcd2bin(cmos_read(RTC_CLK_SECOND)); + time->min = bcd2bin(cmos_read(RTC_CLK_MINUTE)); + time->hour = bcd2bin(cmos_read(RTC_CLK_HOUR)); + time->mday = bcd2bin(cmos_read(RTC_CLK_DAYOFMONTH)); + time->mon = bcd2bin(cmos_read(RTC_CLK_MONTH)); + time->year = bcd2bin(cmos_read(RTC_CLK_YEAR)); + /* Same assumption as above: We always have RTC_CLK_ALTCENTURY */ + time->year += bcd2bin(cmos_read(RTC_CLK_ALTCENTURY)) * 100; + time->wday = bcd2bin(cmos_read(RTC_CLK_DAYOFWEEK)) - 1; + return 0; +} diff --git a/src/drivers/pc80/rtc/mc146818rtc_early.c b/src/drivers/pc80/rtc/mc146818rtc_early.c new file mode 100644 index 0000000..8bebc42 --- /dev/null +++ b/src/drivers/pc80/rtc/mc146818rtc_early.c @@ -0,0 +1,104 @@ +#include <stdint.h> +#include <pc80/mc146818rtc.h> +#include <fallback.h> +#if CONFIG_USE_OPTION_TABLE +#include "option_table.h" +#endif + +#if CONFIG_MAX_REBOOT_CNT > 15 +#error "CONFIG_MAX_REBOOT_CNT too high" +#endif + +static int cmos_error(void) +{ + unsigned char reg_d; + /* See if the cmos error condition has been flagged */ + reg_d = cmos_read(RTC_REG_D); + return (reg_d & RTC_VRT) == 0; +} + +static int cmos_chksum_valid(void) +{ +#if CONFIG_USE_OPTION_TABLE + unsigned char addr; + u16 sum, old_sum; + + sum = 0; + /* Compute the cmos checksum */ + for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) + sum += cmos_read(addr); + + /* Read the stored checksum */ + old_sum = cmos_read(LB_CKS_LOC) << 8; + old_sum |= cmos_read(LB_CKS_LOC+1); + + return sum == old_sum; +#else + return 0; +#endif +} + +static inline __attribute__((unused)) int boot_count(uint8_t rtc_byte) +{ + return rtc_byte >> 4; +} + +static inline __attribute__((unused)) uint8_t increment_boot_count(uint8_t rtc_byte) +{ + return rtc_byte + (1 << 4); +} + +static inline __attribute__((unused)) uint8_t boot_set_fallback(uint8_t rtc_byte) +{ + return rtc_byte & ~RTC_BOOT_NORMAL; +} + +static inline __attribute__((unused)) int boot_use_normal(uint8_t rtc_byte) +{ + return rtc_byte & RTC_BOOT_NORMAL; +} + +static inline __attribute__((unused)) int do_normal_boot(void) +{ + unsigned char byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* Invalid CMOS checksum detected! + * Force fallback boot... + */ + byte = cmos_read(RTC_BOOT_BYTE); + byte &= boot_set_fallback(byte) & 0x0f; + byte |= 0xf << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } + + /* The RTC_BOOT_BYTE is now o.k. see where to go. */ + byte = cmos_read(RTC_BOOT_BYTE); + + /* Are we attempting to boot normally? */ + if (boot_use_normal(byte)) { + /* Are we already at the max count? */ + if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT) + byte = increment_boot_count(byte); + else + byte = boot_set_fallback(byte); + } + + /* Save the boot byte */ + cmos_write(byte, RTC_BOOT_BYTE); + + /* Return selected code path for this boot attempt */ + return boot_use_normal(byte); +} + +unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) +{ +#if CONFIG_USE_OPTION_TABLE + unsigned byte; + + byte = cmos_read(start/8); + return (byte >> (start & 7U)) & ((1U << size) - 1U); +#else + return def; +#endif +} diff --git a/src/drivers/pc80/spkmodem.c b/src/drivers/pc80/spkmodem.c deleted file mode 100644 index fe57e62..0000000 --- a/src/drivers/pc80/spkmodem.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/io.h> -#include <console/spkmodem.h> -#include <cpu/x86/tsc.h> - -#define SPEAKER_PIT_FREQUENCY 0x1234dd - - -enum { - PIT_COUNTER_0 = 0x40, - PIT_COUNTER_1 = 0x41, - PIT_COUNTER_2 = 0x42, - PIT_CTRL = 0x43, - PIT_SPEAKER_PORT = 0x61, -}; - - -enum { - PIT_SPK_TMR2 = 0x01, - PIT_SPK_DATA = 0x02, - PIT_SPK_TMR2_LATCH = 0x20 -}; - -enum { - PIT_CTRL_SELECT_MASK = 0xc0, - PIT_CTRL_SELECT_0 = 0x00, - PIT_CTRL_SELECT_1 = 0x40, - PIT_CTRL_SELECT_2 = 0x80, - - PIT_CTRL_READLOAD_MASK= 0x30, - PIT_CTRL_COUNTER_LATCH = 0x00, - PIT_CTRL_READLOAD_LSB = 0x10, - PIT_CTRL_READLOAD_MSB = 0x20, - PIT_CTRL_READLOAD_WORD = 0x30, - - PIT_CTRL_MODE_MASK = 0x0e, - PIT_CTRL_INTR_ON_TERM = 0x00, - PIT_CTRL_PROGR_ONE_SHOT = 0x02, - - PIT_CTRL_RATE_GEN = 0x04, - - PIT_CTRL_SQUAREWAVE_GEN = 0x06, - PIT_CTRL_SOFTSTROBE = 0x08, - - PIT_CTRL_HARDSTROBE = 0x0a, - - - PIT_CTRL_COUNT_MASK = 0x01, - PIT_CTRL_COUNT_BINARY = 0x00, - PIT_CTRL_COUNT_BCD = 0x01 -}; - - -static void -make_tone (uint16_t freq_count, unsigned int duration) -{ - outb (PIT_CTRL_SELECT_2 - | PIT_CTRL_READLOAD_WORD - | PIT_CTRL_SQUAREWAVE_GEN - | PIT_CTRL_COUNT_BINARY, PIT_CTRL); - - outb (freq_count & 0xff, PIT_COUNTER_2); - - outb ((freq_count >> 8) & 0xff, PIT_COUNTER_2); - - outb (inb (PIT_SPEAKER_PORT) - | PIT_SPK_TMR2 | PIT_SPK_DATA, - PIT_SPEAKER_PORT); - - for (; duration; duration--) { - unsigned short counter, previous_counter = 0xffff; - while (1) { - counter = inb (PIT_COUNTER_2); - counter |= ((uint16_t) inb (PIT_COUNTER_2)) << 8; - if (counter > previous_counter) - { - previous_counter = counter; - break; - } - previous_counter = counter; - } - } -} - -void spkmodem_tx_byte(unsigned char c) -{ - int i; - - make_tone (SPEAKER_PIT_FREQUENCY / 200, 4); - for (i = 7; i >= 0; i--) { - if ((c >> i) & 1) - make_tone (SPEAKER_PIT_FREQUENCY / 2000, 20); - else - make_tone (SPEAKER_PIT_FREQUENCY / 4000, 40); - make_tone (SPEAKER_PIT_FREQUENCY / 1000, 10); - } - make_tone (SPEAKER_PIT_FREQUENCY / 200, 0); -} - -void spkmodem_init(void) -{ - /* Some cards need time to come online. Output some message to get it started. */ - spkmodem_tx_byte('S'); - spkmodem_tx_byte('P'); - spkmodem_tx_byte('K'); - spkmodem_tx_byte('\r'); - spkmodem_tx_byte('\n'); -} diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc index 697842f..0068ff1 100644 --- a/src/drivers/pc80/tpm/Makefile.inc +++ b/src/drivers/pc80/tpm/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_ARCH_X86),y) + verstage-$(CONFIG_LPC_TPM) += tpm.c romstage-$(CONFIG_LPC_TPM) += tpm.c ramstage-$(CONFIG_LPC_TPM) += tpm.c romstage-$(CONFIG_LPC_TPM) += romstage.c + +endif diff --git a/src/drivers/pc80/udelay_io.c b/src/drivers/pc80/udelay_io.c deleted file mode 100644 index 1cdc673..0000000 --- a/src/drivers/pc80/udelay_io.c +++ /dev/null @@ -1,13 +0,0 @@ -#include <arch/io.h> -#include <delay.h> - -void init_timer(void) -{ -} - -void udelay(unsigned usecs) -{ - int i; - for(i = 0; i < usecs; i++) - inb(0x80); -} diff --git a/src/drivers/pc80/vga/Makefile.inc b/src/drivers/pc80/vga/Makefile.inc index d4b726a..3e31de1 100644 --- a/src/drivers/pc80/vga/Makefile.inc +++ b/src/drivers/pc80/vga/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_ARCH_X86),y) + ramstage-$(CONFIG_VGA) += vga_io.c ramstage-$(CONFIG_VGA) += vga_palette.c ramstage-$(CONFIG_VGA) += vga_font_8x16.c ramstage-$(CONFIG_VGA) += vga.c + +endif diff --git a/src/drivers/ricoh/Kconfig b/src/drivers/ricoh/Kconfig deleted file mode 100644 index 6b05142..0000000 --- a/src/drivers/ricoh/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/ricoh/rce822/Kconfig diff --git a/src/drivers/sil/Kconfig b/src/drivers/sil/Kconfig deleted file mode 100644 index 69f53d9..0000000 --- a/src/drivers/sil/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source "src/drivers/sil/3114/Kconfig" diff --git a/src/drivers/sil/Makefile.inc b/src/drivers/sil/Makefile.inc deleted file mode 100644 index 6826fc2..0000000 --- a/src/drivers/sil/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += 3114 diff --git a/src/drivers/ti/Kconfig b/src/drivers/ti/Kconfig deleted file mode 100644 index 7c5ace9..0000000 --- a/src/drivers/ti/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 The Chromium OS Authors. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -source src/drivers/ti/tps65090/Kconfig -source src/drivers/ti/tps65913/Kconfig diff --git a/src/drivers/ti/Makefile.inc b/src/drivers/ti/Makefile.inc deleted file mode 100644 index 8c6e62c..0000000 --- a/src/drivers/ti/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 The Chromium OS Authors. -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-$(CONFIG_DRIVER_TI_TPS65090) += tps65090/ -subdirs-$(CONFIG_DRIVERS_TI_TPS65913) += tps65913/ diff --git a/src/drivers/xgi/Kconfig b/src/drivers/xgi/Kconfig deleted file mode 100644 index dea25ea..0000000 --- a/src/drivers/xgi/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -source src/drivers/xgi/common/Kconfig -source src/drivers/xgi/z9s/Kconfig diff --git a/src/drivers/xgi/Makefile.inc b/src/drivers/xgi/Makefile.inc deleted file mode 100644 index ce83d7a..0000000 --- a/src/drivers/xgi/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += common z9s \ No newline at end of file diff --git a/src/drivers/xpowers/Kconfig b/src/drivers/xpowers/Kconfig deleted file mode 100644 index 3ac2748..0000000 --- a/src/drivers/xpowers/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/xpowers/axp209/Kconfig diff --git a/src/drivers/xpowers/Makefile.inc b/src/drivers/xpowers/Makefile.inc deleted file mode 100644 index ef6dffc..0000000 --- a/src/drivers/xpowers/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209 diff --git a/src/drivers/xpowers/axp209/Makefile.inc b/src/drivers/xpowers/axp209/Makefile.inc index 5ac691e..e08a8e2 100644 --- a/src/drivers/xpowers/axp209/Makefile.inc +++ b/src/drivers/xpowers/axp209/Makefile.inc @@ -1,3 +1,7 @@ -bootblock-$(CONFIG_DRIVER_XPOWERS_AXP209_BOOTBLOCK) += axp209.c -romstage-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209.c -ramstage-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209.c +ifeq ($(CONFIG_DRIVER_XPOWERS_AXP209),y) + +bootblock-$(CONFIG_DRIVER_XPOWERS_AXP209_BOOTBLOCK) += axp209.c +romstage-y += axp209.c +ramstage-y += axp209.c + +endif diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 38f2ad0..f5630c5 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -179,7 +179,7 @@ enum cb_err get_option(void *dest, const char *name); unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); #else /* defined(__ROMCC__) */ -#include <drivers/pc80/mc146818rtc_early.c> +#include <drivers/pc80/rtc/mc146818rtc_early.c> #endif /* !defined(__ROMCC__) */ #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))

1 0

Patch set updated for coreboot: Some timer cleanups
by Stefan Reinauer 24 Feb '16

24 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10011 -gerrit commit 7c5091a942e23344b3035b7234140ab52136802c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 27 13:38:50 2015 -0700 Some timer cleanups Clean up the usage of UDELAY_IO Change-Id: Ic6915743b7c948a57478744777fdbc31163c48f6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/via/c7/Kconfig | 4 +++- src/drivers/pc80/pc/Makefile.inc | 1 + src/mainboard/abit/be6-ii_v2_0/Kconfig | 2 +- src/mainboard/abit/be6-ii_v2_0/romstage.c | 1 - src/mainboard/asus/mew-am/romstage.c | 1 - src/mainboard/asus/mew-vm/romstage.c | 1 - src/mainboard/asus/p2b-f/romstage.c | 1 - src/mainboard/emulation/qemu-i440fx/romstage.c | 1 - src/mainboard/jetway/j7f2/romstage.c | 1 - src/mainboard/via/vt8454c/romstage.c | 1 - 10 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig index 3507713..b71178d 100644 --- a/src/cpu/via/c7/Kconfig +++ b/src/cpu/via/c7/Kconfig @@ -9,7 +9,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select UDELAY_TSC + # Missing tsc_freq_mhz and TSC_CONSTANT_RATE + #select UDELAY_TSC + select UDELAY_IO select MMX select SSE2 diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 550ca12..b7eda19 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_ARCH_X86),y) ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c +romstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c diff --git a/src/mainboard/abit/be6-ii_v2_0/Kconfig b/src/mainboard/abit/be6-ii_v2_0/Kconfig index b5eaff6..bc375ab 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Kconfig +++ b/src/mainboard/abit/be6-ii_v2_0/Kconfig @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE - select UDELAY_TSC + select UDELAY_IO select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 08c4b4d..e38d846 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 7a79416..ec9091e 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index ad5d001..f52413c 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -24,7 +24,6 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index aa350f0..521ddbd 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index f16f8dd..d03c8ab 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <timestamp.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 3c4835f..42aaa0c 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/fintek/common/fintek.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index caf8f61..f93b09a 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -23,7 +23,6 @@ #include <lib.h> #include <northbridge/via/cx700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" #include <delay.h> #include "northbridge/via/cx700/early_smbus.c" #include "lib/debug.c"

1 0

Patch set updated for coreboot: cpu/x86: Kconfig cleanups
by Stefan Reinauer 24 Feb '16

24 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10012 -gerrit commit 367fcfa3fbdb6edef89cd4a7709bee65ee7db83d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 27 13:40:16 2015 -0700 cpu/x86: Kconfig cleanups Sort some Kconfig options Change-Id: I25ea327ed151e18ccb5d13626d44925d2a253d08 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/x86/Kconfig | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 94225a3..d8f338d 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,7 +1,16 @@ +# TODO These two options look too similar config PARALLEL_CPU_INIT bool default n +config PARALLEL_MP + def_bool n + help + This option uses common MP infrastructure for bringing up APs + in parallel. It additionally provides a more flexible mechanism + for sequencing the steps of bringing up the APs. + + config UDELAY_IO bool default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 @@ -39,11 +48,14 @@ config TSC_MONOTONIC_TIMER help Expose monotonic time using the TSC. -config UDELAY_TIMER2 +# This option is used in code but never selected. +config TSC_CALIBRATE_WITH_IO bool + depends on UDELAY_TSC default n -config TSC_CALIBRATE_WITH_IO +# This option is used in code but never selected. +config UDELAY_TIMER2 bool default n @@ -121,13 +133,6 @@ config PLATFORM_USES_FSP1_0 Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) 1.0 for initialization. -config PARALLEL_MP - def_bool n - help - This option uses common MP infrastructure for bringing up APs - in parallel. It additionally provides a more flexible mechanism - for sequencing the steps of bringing up the APs. - config BACKUP_DEFAULT_SMM_REGION def_bool n help

1 0

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