coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

1 participants
1226 discussions

New patch to review for coreboot: UDC: Correct cleaning out memory for string descriptors
by Patrick Georgi 29 Jun '15

29 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10687 -gerrit commit fd47b009b7be90465ba2bc389964204cfccbd7d8 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 23 12:33:53 2015 -0700 UDC: Correct cleaning out memory for string descriptors BUG=chrome-os-partner:41687 BRANCH=None TEST=Compiles successfully and fastboot devices reports correct serial number even after re-connection. Change-Id: I4741a5d6333523eb47c27b4a20c4ef3f1e853d76 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6249b1e35391550d788f56a7b3e7a49ae19f0c93 Original-Change-Id: I1348c33f354d11e3c29ccd9da9948cfbeb60aa9e Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281192 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/drivers/udc/udc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/udc/udc.c b/payloads/libpayload/drivers/udc/udc.c index 01aa4b1..834a891 100644 --- a/payloads/libpayload/drivers/udc/udc.c +++ b/payloads/libpayload/drivers/udc/udc.c @@ -350,7 +350,7 @@ static int setup_ep0(struct usbdev_ctrl *this, dev_req_t *dr) int d_len = s_len * 2; uint8_t *data = dma_malloc(d_len + 2); - memset(data, 0, d_len); + memset(data, 0, d_len + 2); data[0] = d_len + 2; // length data[1] = 0x03; // string descriptor int i;

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New patch to review for coreboot: udc/chipidea: Allow force_shutdown of connection
by Patrick Georgi 29 Jun '15

29 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10686 -gerrit commit e7b19e58e11cda3c43176a509a62127cd6cd85e3 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jun 22 16:07:51 2015 -0700 udc/chipidea: Allow force_shutdown of connection Allow force shutdown operation of the connection in case where the cable is disconnected and reconnected back. BUG=chrome-os-partner:41687 BRANCH=None TEST=Compiles successfully and fastboot works fine even with reconnection of cable Change-Id: I8eb1217b4a9ad6ce8a2a40db329eca1930eda089 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3d7ab65c459caa4ec526b99a1aee1a31e9cb80da Original-Change-Id: I354c44e0ed2211cb2c4c1ae653d201b7d15ea932 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281066 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- payloads/libpayload/drivers/udc/chipidea.c | 21 ++++++++++++++------- payloads/libpayload/include/udc/udc.h | 9 +++++++++ 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c index 16a42e4..20267ed 100644 --- a/payloads/libpayload/drivers/udc/chipidea.c +++ b/payloads/libpayload/drivers/udc/chipidea.c @@ -413,6 +413,18 @@ static int chipidea_poll(struct usbdev_ctrl *this) return 1; } +static void chipidea_force_shutdown(struct usbdev_ctrl *this) +{ + struct chipidea_pdata *p = CI_PDATA(this); + writel(0xffffffff, &p->opreg->epflush); + writel(USBCMD_8MICRO | USBCMD_RST, &p->opreg->usbcmd); + writel(0, &p->opreg->usbmode); + writel(USBCMD_8MICRO, &p->opreg->usbcmd); + free(p->qhlist); + free(p); + free(this); +} + static void chipidea_shutdown(struct usbdev_ctrl *this) { struct chipidea_pdata *p = CI_PDATA(this); @@ -426,13 +438,7 @@ static void chipidea_shutdown(struct usbdev_ctrl *this) if (!SIMPLEQ_EMPTY(&p->job_queue[i][j])) is_empty = 0; } - writel(0xffffffff, &p->opreg->epflush); - writel(USBCMD_8MICRO | USBCMD_RST, &p->opreg->usbcmd); - writel(0, &p->opreg->usbmode); - writel(USBCMD_8MICRO, &p->opreg->usbcmd); - free(p->qhlist); - free(p); - free(this); + chipidea_force_shutdown(this); } static void chipidea_set_address(struct usbdev_ctrl *this, int address) @@ -491,6 +497,7 @@ struct usbdev_ctrl *chipidea_init(device_descriptor_t *dd) ctrl->add_gadget = udc_add_gadget; ctrl->add_strings = udc_add_strings; ctrl->enqueue_packet = chipidea_enqueue_packet; + ctrl->force_shutdown = chipidea_force_shutdown; ctrl->shutdown = chipidea_shutdown; ctrl->set_address = chipidea_set_address; ctrl->stall = chipidea_stall; diff --git a/payloads/libpayload/include/udc/udc.h b/payloads/libpayload/include/udc/udc.h index 99cbb1b..5180177 100644 --- a/payloads/libpayload/include/udc/udc.h +++ b/payloads/libpayload/include/udc/udc.h @@ -140,6 +140,15 @@ struct usbdev_ctrl { */ void (*stall)(struct usbdev_ctrl *, uint8_t ep, int in_dir, int set); + /** + * Disable controller and deallocate data structures. + */ + void (*force_shutdown)(struct usbdev_ctrl *this); + + /** + * Let queues run out, then disable controller and deallocate data + * structures. + */ void (*shutdown)(struct usbdev_ctrl *this); /**

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New patch to review for coreboot: veyron_danger: Update SDMMC power on/off code for v2
by Patrick Georgi 29 Jun '15

29 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10685 -gerrit commit 105d11fd07fbfc9347ebdac6e49c131c8c13f394 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jun 3 15:27:07 2015 -0700 veyron_danger: Update SDMMC power on/off code for v2 This re-factors SDMMC power on/off to make corrections and take differences between board versions into account. To avoid similar- but-different case switch statements in romstage.c and mainboard.c, power on/off functions for SDMMC are split into their own .c file. BUG=none BRANCH=none TEST=built and booted of micro-SD card on Danger v2 Change-Id: Ib3069c35ceff1ff98b49579a6298681c1390beee Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: eecfee4a5dd39073b5f966a25991a594b3c4b519 Original-Change-Id: Id86ae7f40687e843ffc4e7769309d4678ad54f49 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280853 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_danger/Makefile.inc | 2 ++ src/mainboard/google/veyron_danger/board.h | 2 ++ src/mainboard/google/veyron_danger/mainboard.c | 4 +-- src/mainboard/google/veyron_danger/romstage.c | 6 ---- src/mainboard/google/veyron_danger/sdmmc.c | 45 +++++++++++++++++++++++++ 5 files changed, 50 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/veyron_danger/Makefile.inc b/src/mainboard/google/veyron_danger/Makefile.inc index a027c6d..1d312c3 100644 --- a/src/mainboard/google/veyron_danger/Makefile.inc +++ b/src/mainboard/google/veyron_danger/Makefile.inc @@ -27,6 +27,7 @@ verstage-y += reset.c romstage-y += boardid.c romstage-y += romstage.c +romstage-y += sdmmc.c romstage-y += sdram_configs.c romstage-y += reset.c @@ -34,6 +35,7 @@ ramstage-y += boardid.c ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c +ramstage-y += sdmmc.c bootblock-y += memlayout.ld verstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron_danger/board.h b/src/mainboard/google/veyron_danger/board.h index 8f62078..aa703c2 100644 --- a/src/mainboard/google/veyron_danger/board.h +++ b/src/mainboard/google/veyron_danger/board.h @@ -27,6 +27,8 @@ #define GPIO_RESET GPIO(0, B, 5) #define GPIO_LCDC_BL GPIO(7, A, 7) +void sdmmc_power_off(void); +void sdmmc_power_on(void); void setup_chromeos_gpios(void); #endif /* __MAINBOARD_GOOGLE_VEYRON_DANGER_BOARD_H */ diff --git a/src/mainboard/google/veyron_danger/mainboard.c b/src/mainboard/google/veyron_danger/mainboard.c index 621d347..7b06742 100644 --- a/src/mainboard/google/veyron_danger/mainboard.c +++ b/src/mainboard/google/veyron_danger/mainboard.c @@ -55,9 +55,7 @@ static void configure_sdmmc(void) /* use sdmmc0 io, disable JTAG function */ write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12)); - /* Note: these power rail definitions are copied in romstage.c */ - rk808_configure_ldo(4, 3300); /* VCCIO_SD */ - rk808_configure_ldo(5, 3300); /* VCC33_SD */ + sdmmc_power_on(); gpio_input(GPIO(7, A, 5)); /* SDMMC_DET_L */ } diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 68ab661..80d9081 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -78,12 +78,6 @@ static void configure_l2ctlr(void) write_l2ctlr(l2ctlr); } -static void sdmmc_power_off(void) -{ - rk808_configure_ldo(4, 0); /* VCCIO_SD */ - rk808_configure_ldo(5, 0); /* VCC33_SD */ -} - void main(void) { #if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/mainboard/google/veyron_danger/sdmmc.c b/src/mainboard/google/veyron_danger/sdmmc.c new file mode 100644 index 0000000..b60f2e6 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdmmc.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "board.h" + +#include <soc/rk808.h> + +static void sdmmc_power(int enable) +{ + switch (board_id()) { + case 0: + /* VCC33_SD is tied to VCC33_SYS and is always on */ + break; + default: + rk808_configure_ldo(4, enable ? 3300 : 0); /* VCC33_SD_LDO */ + rk808_configure_ldo(5, enable ? 3300 : 0); /* VCCIO_SD */ + break; + } +} + +void sdmmc_power_off(void) +{ + sdmmc_power(0); +} + +void sdmmc_power_on(void) +{ + sdmmc_power(1); +}

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New patch to review for coreboot: veyron_danger: Add basic HDMI support
by Patrick Georgi 29 Jun '15

29 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10684 -gerrit commit aefd000d570b43962a20963c6521821962301029 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jun 3 17:00:32 2015 -0700 veyron_danger: Add basic HDMI support This adds a configure_hdmi() function that drives the HDMI enable output high and configures the iomux. We'll add EDP/HDMI auto-detection in an upcoming patch. BUG=none BRANCH=none TEST=set vop_mode to 1 in Danger's devicetree.cb and saw dev mode screen output to HDMI display. Change-Id: I2a208059fee74d436b5a5bedbc677bc59525f935 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 721f326319f727afcf73a0c21d20d26cb463ad71 Original-Change-Id: I139d39749963d4121aaeec0c3da37d825ffa94ac Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280849 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_danger/mainboard.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_danger/mainboard.c b/src/mainboard/google/veyron_danger/mainboard.c index 175ff33..621d347 100644 --- a/src/mainboard/google/veyron_danger/mainboard.c +++ b/src/mainboard/google/veyron_danger/mainboard.c @@ -104,9 +104,27 @@ static void configure_vop(void) gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */ gpio_output(GPIO_LCDC_BL, 0); + rk808_configure_switch(1, 1); /* VCC33_LCD */ +} + +static void configure_hdmi(void) +{ rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */ rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */ - rk808_configure_switch(1, 1); /* VCC33_LCD */ + + /* set POWER_HDMI_EN */ + switch (board_id()) { + case 0: + gpio_output(GPIO(7, A, 2), 1); + break; + default: + gpio_output(GPIO(5, C, 3), 1); + break; + } + + /* HDMI I2C */ + write32(&rk3288_grf->iomux_i2c5sda, IOMUX_HDMI_EDP_I2C_SDA); + write32(&rk3288_grf->iomux_i2c5scl, IOMUX_HDMI_EDP_I2C_SCL); } static void mainboard_init(device_t dev) @@ -118,6 +136,7 @@ static void mainboard_init(device_t dev) configure_emmc(); configure_codec(); configure_vop(); + configure_hdmi(); elog_init(); elog_add_watchdog_reset();

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Patch merged into coreboot/master: intel raminit: check correct registers in channel_test
by gerrit＠coreboot.org 28 Jun '15

28 Jun '15

the following patch was just integrated into master: commit 4275ff86fa09ad725b082d4387d75c78888bbda5 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Jun 25 19:32:28 2015 +0200 intel raminit: check correct registers in channel_test Found while doing code review. No actual problem was observed. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Verify byte-lane error count registers 0 to 7 instead of verifying byte-lane error count register 0 eight times in a row. Change-Id: Ife6ac6558b2f65ad947870cde5f15d90560ce6d9 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: http://review.coreboot.org/10664 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10664 for details. -gerrit

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Patch merged into coreboot/master: intel raminit: properly handle DDR3 DIMMs with address mirroring
by gerrit＠coreboot.org 28 Jun '15

28 Jun '15

the following patch was just integrated into master: commit 3247916d1105a33a1c93be415e3bcded785c86cf Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Jun 24 19:14:53 2015 +0200 intel raminit: properly handle DDR3 DIMMs with address mirroring Issue observed: DDR3 DIMM with address mirroring enabled doesn't work when placed in slot 1 and slot 0 is empty. It does work when placed in slot 0 and slot 1 is empty. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H * Kingston KVR1066D3N7/4G (address mirroring enabled DIMM) Problem description: The address mirror enable bit is slot-swapped in the DIMM mapping code, but none of the remaining code is aware of DIMM mapping. Removing the code, that is swapping the mirror enable bit, results in the correct behaviour. The DIMM is now working in every slot. Change-Id: I7a51bbc8d156209449fd67c954930835814a40ee Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: http://review.coreboot.org/10652 Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10652 for details. -gerrit

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New patch to review for coreboot: amd/.../hudson: Warn if HUDSON_FWM_POSITION is not inside CBFS
by Martin Roth 28 Jun '15

28 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10683 -gerrit commit fbc0a6598e81dac9410aa384f1a720034e4f41cd Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 28 14:12:29 2015 -0600 amd/.../hudson: Warn if HUDSON_FWM_POSITION is not inside CBFS Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS. This can be extended to other Kconfig values for CBFS. Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 5 +++++ src/southbridge/amd/pi/hudson/Makefile.inc | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 85e5596..3f46464 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -37,10 +37,15 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c HUDSON_FWM_POS_CALC=$(shell let y="0xffffffff - ($(CONFIG_COREBOOT_ROMSIZE_KB) * 1024) + 1 + 0x20000" ; printf "%u\n" $$y) HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) +HUDSON_FWM_INSIDE_CBFS=$(shell let y="$(CBFS_BASE_ADDRESS) < $(HUDSON_FWM_POSITION)" ; printf "%u\n" $$y) ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) $(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) endif +ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) +$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) +endif + #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index f56f3dc..106d72b 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -60,10 +60,14 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c HUDSON_FWM_POS_CALC=$(shell let y="0xffffffff - ($(CONFIG_COREBOOT_ROMSIZE_KB) * 1024) + 1 + 0x20000" ; printf "%u\n" $$y) HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) +HUDSON_FWM_INSIDE_CBFS=$(shell let y="$(CBFS_BASE_ADDRESS) < $(HUDSON_FWM_POSITION)" ; printf "%u\n" $$y) ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) $(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) endif +ifneq ($(HUDSON_FWM_INSIDE_CBFS), 1) +$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION ($(HUDSON_FWM_POSITION)) is outside of CBFS area ($(CBFS_BASE_ADDRESS) to 4294967295) ##### ) +endif CBFS_HEADER_SIZE=0x40 #assume the cbfs header is less than $(CBFS_HEADER_SIZE) bytes.

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New patch to review for coreboot: Calculate HUDSON_FWM_POSITION and display warning on mismatch
by Martin Roth 28 Jun '15

28 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10682 -gerrit commit f001eba1d2886c6b872edb2671908528c8b96caf Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 28 14:06:23 2015 -0600 Calculate HUDSON_FWM_POSITION and display warning on mismatch This patch calculates the address where the chipset firmware descriptor should be located and compares it against the actual value from Kconfig. If the two don't match, it puts up a warning. This could probably replace the config variable completely, but I wanted to see how other people felt before doing that. I seem to recall that the value used to be calculated, so I figure that there must be a reason it's done this way at this point. If we do want to keep the Kconfig setting, this patch could also be modified to just verify that the HUDSON_FWM_POSITION is inside the ROM space. Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 5 +++++ src/southbridge/amd/pi/hudson/Makefile.inc | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index ea86a32..85e5596 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -34,8 +34,13 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | # +-----------+---------------+----------------+------------+ # EC ROM should be 64K aligned. + +HUDSON_FWM_POS_CALC=$(shell let y="0xffffffff - ($(CONFIG_COREBOOT_ROMSIZE_KB) * 1024) + 1 + 0x20000" ; printf "%u\n" $$y) HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) +ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) +$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) +endif #assume the cbfs header is less than 128 bytes. ROMSIG_SIZE=16 ifeq ($(CONFIG_HUDSON_XHCI_FWM), y) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 235ce1e..f56f3dc 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -58,7 +58,12 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # # EC ROM should be 64K aligned. +HUDSON_FWM_POS_CALC=$(shell let y="0xffffffff - ($(CONFIG_COREBOOT_ROMSIZE_KB) * 1024) + 1 + 0x20000" ; printf "%u\n" $$y) HUDSON_FWM_POSITION=$(shell printf %u $(CONFIG_HUDSON_FWM_POSITION)) + +ifneq ($(HUDSON_FWM_POS_CALC), $(HUDSON_FWM_POSITION)) +$(warning ##### WARNING: CONFIG_HUDSON_FWM_POSITION does not match calculated firmware position $(HUDSON_FWM_POS_CALC) != $(HUDSON_FWM_POSITION) ##### ) +endif CBFS_HEADER_SIZE=0x40 #assume the cbfs header is less than $(CBFS_HEADER_SIZE) bytes.

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New patch to review for coreboot: Makefile.inc: Add CBFS_BASE_ADDRESS variable for later comparison
by Martin Roth 28 Jun '15

28 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10681 -gerrit commit 509c29a36d6833430d11cc90cd96fd684559dd36 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 28 13:49:16 2015 -0600 Makefile.inc: Add CBFS_BASE_ADDRESS variable for later comparison The CBFS_BASE_ADDRESS can be compared against values used with cbfstool to generate warnings. This can help cut down on mistakes and debug time. This is pretty global, so I put this at the top level. Change-Id: I149007dd637661f799a0f2cdb079d11df726ca86 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 2f1fe82..f827383 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -41,6 +41,10 @@ export objcbfs := $(obj)/cbfs/$(call strip_quotes,$(CONFIG_CBFS_PREFIX)) ## file under src/ are placed and built under $(objgenerated) export objgenerated := $(obj)/generated +## Calculate the base address of CBFS for later comparisons +CBFS_BASE_ADDRESS=$(shell let y="0xffffffff - $(CONFIG_CBFS_SIZE) + 1" ; \ + printf "%u\n" $$y) + ####################################################################### # root rule to resolve if in build mode (ie. configuration exists) real-target: $(obj)/config.h coreboot

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New patch to review for coreboot: southbridge/amd/pi/hudson: Fix HUDSON_DISABLE_IMC kconfig warning
by Martin Roth 28 Jun '15

28 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10680 -gerrit commit de7e582c408f345a382544438afe223a322883ba Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jun 28 09:44:31 2015 -0600 southbridge/amd/pi/hudson: Fix HUDSON_DISABLE_IMC kconfig warning Platforms selecting the HUDSON_DISABLE_IMC symbol were showing the warning: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_AMD_AGESA_BINARY_PI) selects HUDSON_DISABLE_IMC which has unmet direct dependencies (SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN) By moving the definition of the symbol outside of the if block and removing the default n, we can get rid of the warning without changing the value for any platform. Change-Id: I5c1bdfbcf3c5c44ee05b8c5e679f6854d784d8dc Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/southbridge/amd/pi/hudson/Kconfig | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 36716fa..237183a 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -35,6 +35,9 @@ config SOUTHBRIDGE_AMD_PI_KERN select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET +config HUDSON_DISABLE_IMC + bool + if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN config BOOTBLOCK_SOUTHBRIDGE_INIT @@ -65,10 +68,6 @@ config HUDSON_XHCI_FWM help Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 -config HUDSON_DISABLE_IMC - bool - default n - config HUDSON_IMC_FWM bool "Add IMC firmware" depends on !HUDSON_DISABLE_IMC

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coreboot-gerrit June 2015