coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

1 participants
1226 discussions

New patch to review for coreboot: Update crossgcc Makefile for new buildgcc arguments
by Martin Roth 28 Jun '15

28 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10679 -gerrit commit cf8b83147387d52ddef48d577e3f67225d39b5db Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 27 19:09:05 2015 -0600 Update crossgcc Makefile for new buildgcc arguments - IASL was split out of the gcc builds, so needs a target of its own. - Add clang build target - Update the build-ARCH targets as buildgcc -G no longer builds gcc. - Rework all the targets to use common targets to call buildgcc - Split the tempfile clean from the regular clean - Change the 'all' target to leave the tempfiles until all architectures are built so that if one fails and needs a rebuild, it doesn't have to start from scratch. - Add add an all_without_gdb target - Add clang build to all Change-Id: I4ff720eab6d9b72d00757fd2b632e6d9a6c25aa3 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/crossgcc/Makefile | 77 +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 55 insertions(+), 22 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index ae9177c..b4b0223 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,56 +1,89 @@ -all: build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv +# if no architecture is specified, set a default +BUILD_PLATFORM ?= i386-elf +all: + $(MAKE) BUILDGCC_OPTIONS=-t build-i386 build-x64 build-armv7a build-mips build-riscv build-aarch64 \ + build_clang + $(MAKE) clean_tempfiles + +all_without_gdb: + $(MAKE) BUILDGCC_OPTIONS=-t build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \ + build-mips-without-gdb build-riscv-without-gdb build-aarch64-without-gdb build_clang + $(MAKE) clean_tempfiles + +build_tools: build_gcc build_iasl build_gdb + +build_tools_without_gdb: build_gcc build_iasl + +########################################################### +### targets to do buildgcc builds + +build_gcc: + bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(BUILDJOBS),-j $(BUILDJOBS)) $(BUILDGCC_OPTIONS) + +build_gdb: + bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(BUILDJOBS),-j $(BUILDJOBS)) $(BUILDGCC_OPTIONS) + +build_iasl: + bash ./buildgcc -P iasl $(if $(BUILDJOBS),-j $(BUILDJOBS)) $(BUILDGCC_OPTIONS) + +build_clang: + bash ./buildgcc -P clang $(if $(BUILDJOBS),-j $(BUILDJOBS)) $(BUILDGCC_OPTIONS) + +########################################################### +### Build with GDB ### build-i386: - bash ./buildgcc -G -p i386-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools BUILD_PLATFORM=i386-elf build-x64: - bash ./buildgcc -G -p x86_64-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools BUILD_PLATFORM=x86_64-elf build-armv7a: - bash ./buildgcc -G -p armv7a-eabi $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools BUILD_PLATFORM=armv7a-eabi build-aarch64: - bash ./buildgcc -G -p aarch64-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools BUILD_PLATFORM=aarch64-elf build-mips: - bash ./buildgcc -G -p mipsel-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools BUILD_PLATFORM=mipsel-elf build-riscv: - bash ./buildgcc -G -p riscv-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools BUILD_PLATFORM=riscv-elf -.PHONY: build-i386-without-gdb +########################################################### +### Build without GDB build-i386-without-gdb: - bash ./buildgcc -p i386-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=i386-elf -.PHONY: build-x64-without-gdb build-x64-without-gdb: - bash ./buildgcc -p x86_64-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=x86_64-elf -.PHONY: build-armv7a-without-gdb build-armv7a-without-gdb: - bash ./buildgcc -p armv7a-eabi $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=armv7a-eabi -.PHONY: build-aarch64-without-gdb build-aarch64-without-gdb: - bash ./buildgcc -p aarch64-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=aarch64-elf -.PHONY: build-mips-without-gdb build-mips-without-gdb: - bash ./buildgcc -p mipsel-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=mipsel-elf -.PHONY: build-riscv-without-gdb build-riscv-without-gdb: - bash ./buildgcc -p riscv-elf $(if $(BUILDJOBS),-j $(BUILDJOBS)) + @$(MAKE) build_tools_without_gdb BUILD_PLATFORM=riscv-elf -clean: - rm -rf xgcc +clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* rm -rf llvm-* clang-tools-* cfe-* compiler-rt-* rm -rf acpica-* rm -rf gdb-* +clean: clean_tempfiles + rm -rf xgcc + distclean: clean rm -rf tarballs -.PHONY: all build clean distclean +.PHONY: build_gcc build_iasl build_gdb build_tools build_tools_without_gdb \ + build-i386-without-gdb build-x64-without-gdb build-armv7a-without-gdb \ + build-aarch64-without-gdb build-mips-without-gdb build-riscv-without-gdb \ + all build clean distclean clean_tempfiles all_without_gdb

1 0

Patch set updated for coreboot: Move baytrail & fsp_baytrail to the common IFD interface.
by Martin Roth 27 Jun '15

27 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10647 -gerrit commit 1bf6336defad7eea5d83df00b1b6706c72dacd05 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jun 23 19:59:30 2015 -0600 Move baytrail & fsp_baytrail to the common IFD interface. - Add the common/firmware subdir to the baytrail & fsp_baytrail makefiles and remove the code it replaces. - Update baytrail & fsp_baytrail Kconfigs to use the common code. - Update the IFD Kconfig help and prompts for the TXE vs ME. - Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail platforms have their own defaults. Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 3 +- src/mainboard/intel/bakersport_fsp/Kconfig | 8 ---- src/mainboard/intel/bayleybay_fsp/Kconfig | 8 ---- src/mainboard/intel/minnowmax/Kconfig | 8 ---- src/mainboard/siemens/mc_tcu3/Kconfig | 4 -- src/soc/intel/baytrail/Kconfig | 58 +-------------------------- src/soc/intel/baytrail/Makefile.inc | 37 +---------------- src/soc/intel/fsp_baytrail/Kconfig | 29 +------------- src/soc/intel/fsp_baytrail/Makefile.inc | 30 +------------- src/southbridge/intel/common/firmware/Kconfig | 14 ++++--- 10 files changed, 13 insertions(+), 186 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 94b3508..269f7d2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -342,9 +342,8 @@ config CBFS_SIZE NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \ - NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \ + NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \ SOC_INTEL_BROADWELL - default 0x200000 if SOC_INTEL_FSP_BAYTRAIL default ROM_SIZE help This is the part of the ROM actually managed by CBFS, located at the diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index 7f5513a..c382bac 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -34,14 +34,6 @@ config MAINBOARD_DIR string default "intel/bayleybay_fsp" -config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Bakersport CRB (FSP)" diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 3048126..a5c7605 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -34,14 +34,6 @@ config MAINBOARD_DIR string default "intel/bayleybay_fsp" -config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Bayley Bay CRB (FSP)" diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 66825c6..636972f 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -33,14 +33,6 @@ config MAINBOARD_DIR string default "intel/minnowmax" -config INCLUDE_ME - bool - default n - -config LOCK_MANAGEMENT_ENGINE - bool - default n - config MAINBOARD_PART_NUMBER string default "Minnow Max" diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 6d01e82..9eb396b 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -37,10 +37,6 @@ config MAINBOARD_DIR string default "siemens/mc_tcu3" -config INCLUDE_ME - bool - default n - config MAINBOARD_PART_NUMBER string default "MC_TCU3 (FSP)" diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 2764efb..5754c15 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select SOC_INTEL_COMMON + select HAVE_INTEL_FIRMWARE config BOOTBLOCK_CPU_INIT string @@ -153,63 +154,6 @@ config ENABLE_BUILTIN_COM1 configure the pads and enable it. This serial port can be used for the debug console. -config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" - default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty/blobs repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. - -config ME_BIN_PATH - string "Path to management engine firmware" - depends on HAVE_ME_BIN - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" - -config HAVE_IFD_BIN - bool - default y - -config BUILD_WITH_FAKE_IFD - bool "Build with a fake IFD" - default y if !HAVE_IFD_BIN - help - If you don't have an Intel Firmware Descriptor (ifd.bin) for your - board, you can select this option and coreboot will build without it. - Though, the resulting coreboot.rom will not contain all parts required - to get coreboot running on your board. You can however write only the - BIOS section to your board's flash ROM and keep the other sections - untouched. Unfortunately the current version of flashrom doesn't - support this yet. But there is a patch pending [1]. - - WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. - - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html - -config IFD_BIOS_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_ME_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_PLATFORM_SECTION - depends on BUILD_WITH_FAKE_IFD - string - default "" - -config IFD_BIN_PATH - string "Path to intel firmware descriptor" - depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" - config HAVE_REFCODE_BLOB depends on ARCH_X86 bool "An external reference code blob should be put into cbfs." diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 78e2da6..7417526 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../southbridge/intel/common/firmware ramstage-y += memmap.c romstage-y += memmap.c @@ -56,40 +57,6 @@ ramstage-y += placeholders.c CPPFLAGS_common += -Isrc/soc/intel/baytrail/include -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -INTERMEDIATE:=baytrail_add_me - -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) -IFD_BIN_PATH := $(objgenerated)/ifdfake.bin -IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ - $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ - $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) -else -IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) -endif - -baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf "\n** WARNING **\n" - printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" - printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" - printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" - $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) -endif - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(IFD_BIN_PATH) \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 -ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(CONFIG_ME_BIN_PATH) \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - # If an MRC file is an ELF file determine the entry address and first loadable # section offset in the file. Subtract the offset from the entry address to # determine the final location. @@ -102,6 +69,4 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) mrc.bin-type := mrc -PHONY += baytrail_add_me - endif diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 95d45da..d51a238 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS + select HAVE_INTEL_FIRMWARE config SOC_INTEL_FSP_BAYTRAIL_MD bool @@ -94,34 +95,6 @@ config CPU_MICROCODE_CBFS_LOC hex default 0xfff10040 -config INCLUDE_ME - bool "Include the TXE" - default n - help - Build the TXE and descriptor.bin into the ROM image. If you want to use a - descriptor.bin and TXE file from the previous ROM image, you may not want - to build it in here. - -config ME_PATH - string "Path to ME" - depends on INCLUDE_ME - help - The path of the TXE and Descriptor files. - -config LOCK_MANAGEMENT_ENGINE - bool "Lock TXE section" - default n - depends on INCLUDE_ME - help - The Intel Trusted Execution Engine supports preventing write accesses - from the host to the Management Engine section in the firmware - descriptor. If the ME section is locked, it can only be overwritten - with an external SPI flash programmer. You will want this if you - want to increase security of your ROM image once you are sure - that the ME firmware is no longer going to change. - - If unsure, say N. - config ENABLE_BUILTIN_COM1 bool "Enable built-in legacy Serial Port" help diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 92a1fbd..45ea3e4 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -30,6 +30,7 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../lib/fsp subdirs-y += fsp +subdirs-y += ../../../southbridge/intel/common/firmware ramstage-y += memmap.c romstage-y += memmap.c @@ -62,33 +63,4 @@ ramstage-y += i2c.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp -# Run an intermediate step when producing coreboot.rom -# that adds additional components to the final firmware -# image outside of CBFS -ifeq ($(CONFIG_INCLUDE_ME),y) -ifneq ($(CONFIG_ME_PATH),) -INTERMEDIATE:=baytrail_add_txe - -baytrail_add_txe: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" - dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \ - of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 - printf " IFDTOOL txe.bin -> coreboot.pre\n" - $(objutil)/ifdtool/ifdtool \ - -i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/txe.bin \ - $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -endif - -endif -endif - endif diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 71434ac..8ad1fed 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -38,15 +38,17 @@ config IFD_BIN_PATH depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" + bool "Add Intel ME/TXE firmware" depends on HAVE_IFD_BIN help The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty/blobs repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. + for an integrated controller. This might be called the Management + Engine (ME), the Trusted Execution Engine (TXE) or something else + depending on the chip. This firmware might or might not be available + in coreboot's 3rdparty/blobs repository. If it is not and if you don't + have access to the firmware from elsewhere, you can still build + coreboot without it. In this case however, you'll have to make sure + that you don't overwrite your ME/TXE firmware on your flash ROM. config ME_BIN_PATH string "Path to management engine firmware"

1 0

Patch set updated for coreboot: ifdfake: Add prompts and help for the regions in Kconfig
by Martin Roth 27 Jun '15

27 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10649 -gerrit commit eeb8242dc0b642709bd4f005466643a65786dc99 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jun 23 21:49:56 2015 -0600 ifdfake: Add prompts and help for the regions in Kconfig Update the ifdfake region questions in Kconfig with help descriptions and prompts to allow values to be entered and not just use pre-defined default values. Change-Id: Ifdffadc3d74ec49492c2ded66623a1be6945425f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/southbridge/intel/common/firmware/Kconfig | 31 +++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 2767c0e..092d273 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -74,23 +74,46 @@ config BUILD_WITH_FAKE_IFD config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD - string + string "BIOS Region Starting:Ending addresses within the ROM" default "" + help + The BIOS region is typically the size of the CBFS area, and is located + at the end of the ROM space. + + For an 8MB ROM with a 3MB CBFS area, this would look like: + 0x00500000:0x007fffff config IFD_ME_SECTION depends on BUILD_WITH_FAKE_IFD - string + string "ME/TXE Region Starting:Ending addresses within the ROM" default "" + help + The ME/TXE region typically starts at around 0x1000 and often fills the + ROM space not used by CBFS. + + For an 8MB ROM with a 3MB CBFS area, this might look like: + 0x00001000:0x004fffff config IFD_GBE_SECTION depends on BUILD_WITH_FAKE_IFD - string + string "GBE Region Starting:Ending addresses within the ROM" default "" + help + The Gigabit Ethernet ROM region is used when an Intel NIC is built into + the Southbridge/SOC and the platform uses this device instead of an external + PCIe NIC. It will be located between the ME/TXE and the BIOS region. + + Leave this empty if you're unsure. config IFD_PLATFORM_SECTION depends on BUILD_WITH_FAKE_IFD - string + string "Platform Region Starting:Ending addresses within the Rom" default "" + help + The Platform region is used for platform specific data. + It will be located between the ME/TXE and the BIOS region. + + Leave this empty if you're unsure. config LOCK_MANAGEMENT_ENGINE bool "Lock ME/TXE section"

1 0

Patch set updated for coreboot: Intel Firmware Descriptor: Add Lock ME Kconfig question
by Martin Roth 27 Jun '15

27 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10648 -gerrit commit ee122faf0b587b0d1f8d7e5374d48b53628b9ae2 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue Jun 23 21:47:19 2015 -0600 Intel Firmware Descriptor: Add Lock ME Kconfig question Add the Kconfig question to allow the user to lock the ME section using ifdtool. Change-Id: I46018c3bc9df3e309aa3083d693cbebf00e18062 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/southbridge/intel/common/firmware/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 8ad1fed..2767c0e 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -92,4 +92,18 @@ config IFD_PLATFORM_SECTION string default "" +config LOCK_MANAGEMENT_ENGINE + bool "Lock ME/TXE section" + depends on HAVE_ME_BIN + default n + help + The Intel Firmware Descriptor supports preventing write accesses + from the host to the ME or TXE section in the firmware + descriptor. If the section is locked, it can only be overwritten + with an external SPI flash programmer. You will want this if you + want to increase security of your ROM image once you are sure + that the ME/TXE firmware is no longer going to change. + + If unsure, say N. + endif #INTEL_FIRMWARE

1 0

New patch to review for coreboot: Intel Firmware Descriptor Kconfig: remove USES_INTEL_ME
by Martin Roth 27 Jun '15

27 Jun '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10678 -gerrit commit 352aa8d94854a92be20f8350f0e6fbb3472c58af Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Jun 27 08:59:10 2015 -0600 Intel Firmware Descriptor Kconfig: remove USES_INTEL_ME When I added the common IFD Kconfig and Makefile, My thinking was that I could use this symbol to differentiate between the ME and the TXE, and to exclude the ME questions from platforms that use the IFD, but don't use an ME, like Rangeley. In practice this made things a lot more complicated and isn't worth it. Change-Id: I4428744e53c6bb7fc00a4fa4f0aa782c25fc9013 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/southbridge/intel/common/firmware/Kconfig | 3 +-- src/southbridge/intel/fsp_bd82x6x/Kconfig | 1 - src/southbridge/intel/lynxpoint/Kconfig | 1 - 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 1f4d935..71434ac 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -39,7 +39,7 @@ config IFD_BIN_PATH config HAVE_ME_BIN bool "Add Intel Management Engine firmware" - depends on USES_INTEL_ME && HAVE_IFD_BIN + depends on HAVE_IFD_BIN help The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME @@ -90,5 +90,4 @@ config IFD_PLATFORM_SECTION string default "" - endif #INTEL_FIRMWARE diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index fc2b6b3..85c6ee7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -34,7 +34,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SPI_FLASH select COMMON_FADT select HAVE_INTEL_FIRMWARE - select USES_INTEL_ME config EHCI_BAR hex diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 2c71ab2..3c8ae11 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -33,7 +33,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select HAVE_INTEL_FIRMWARE - select USES_INTEL_ME config INTEL_LYNXPOINT_LP bool

1 0

Patch merged into coreboot/master: mainboard/asus/kfsn4-dre: Enable VGA support
by gerrit＠coreboot.org 27 Jun '15

27 Jun '15

the following patch was just integrated into master: commit 039edebc08fb8238a027a1f2277278cf1fde65b9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 26 14:56:51 2015 -0500 mainboard/asus/kfsn4-dre: Enable VGA support The ASUS KFSN4-DRE has full native VGA support, enable support for the VGA device by default in the Kconfig file. Change-Id: I09fc8845a30f26ca49f3547812f9784621ff4b5e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10673 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info(a)gluglug.org.uk> Reviewed-by: Martin Roth <gaumless(a)gmail.com> See http://review.coreboot.org/10673 for details. -gerrit

1 0

Patch merged into coreboot/master: lenovo/g505s: Add System Board ID to fix ACPI warning
by gerrit＠coreboot.org 27 Jun '15

27 Jun '15

the following patch was just integrated into master: commit b6c2f8919ee958d431da7d55194b09322c2f6ec8 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Jun 25 20:14:37 2015 -0600 lenovo/g505s: Add System Board ID to fix ACPI warning Add the System Board Hardware ID to fix the warning: dsdt.aml 88: Device (MB) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: Ie97b1e6792c8d4c8db2500cef6a79881b7ff94c8 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10669 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10669 for details. -gerrit

1 0

Patch merged into coreboot/master: google/parrot: Add System Board ID to fix ACPI warning
by gerrit＠coreboot.org 27 Jun '15

27 Jun '15

the following patch was just integrated into master: commit 9a4cbc9d15a8cf76705b7922489c85687f1a1a16 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Jun 25 20:13:12 2015 -0600 google/parrot: Add System Board ID to fix ACPI warning Add the System Board Hardware ID to fix the warning: dsdt.aml 88: Device (MB) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I063580142ae8053fdc05e165c01e86b8b7cd5ca6 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10668 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10668 for details. -gerrit

1 0

Patch merged into coreboot/master: Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols
by gerrit＠coreboot.org 27 Jun '15

27 Jun '15

the following patch was just integrated into master: commit 0458370bf7f579966d42c6eb7fa067715b44b393 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Jun 19 23:39:38 2015 -0600 Kconfig: Remove unnecessary and incorrect MRC_CACHE symbols Because of a misunderstanding of how Kconfig files are parsed, the OVERRIDE_MRC_CACHE_LOC symbol was added to make sure that the value was correctly set. This is not needed unless for some reason the Kconfig parser is suddenly rewritten to parse everything differently. At some point, the value in the FSP's Kconfig file was updated to OVERRIDE_CACHE_CACHE_LOC, while the entries in the mainboard Kconfig files were not updated. This resulted in the default values not getting set correctly by default on the FSP Bay Trail boards. This removes the whole bunch of incorrect and unnecessary symbols and just sets the default for the MRC cache location directly. Change-Id: I1cec758576866b7e0677272b8309bfde8d4a1ee4 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10611 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10611 for details. -gerrit

1 0

New patch to review for coreboot: vboot2: Enable VBOOT_DYNAMIC_WORK_BUFFER on x86
by Stefan Reinauer 27 Jun '15

27 Jun '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10677 -gerrit commit 70941941fdcea8f1c0828198deaf54e978a70c12 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jun 26 17:34:56 2015 -0700 vboot2: Enable VBOOT_DYNAMIC_WORK_BUFFER on x86 Change-Id: Iaadbd52d948000d1ed46865b83bdb0f4926ca429 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/google/chromeos/vboot2/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index 3106737..4401f86 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -118,6 +118,7 @@ config VBOOT_BL31_INDEX config VBOOT_DYNAMIC_WORK_BUFFER bool "Vboot's work buffer is dynamically allocated." + default y if ARCH_VERSTAGE_X86_32 default n depends on VBOOT_VERIFY_FIRMWARE help

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2015