coreboot-gerrit May 2015

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Patch set updated for coreboot: 945898f igd.asl rewrite
by Vladimir Serbinenko 19 May '15

19 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7472 -gerrit commit 945898f84c5d00b94c2b106c05b3b27a08722cde Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Oct 31 09:16:31 2014 +0100 igd.asl rewrite Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/Kconfig | 4 + src/drivers/intel/gma/Makefile.inc | 1 + src/drivers/intel/gma/acpi.c | 135 +++++++ src/drivers/intel/gma/i915.h | 7 + src/drivers/intel/gma/igd.asl | 113 ++++++ src/mainboard/apple/macbook21/acpi/video.asl | 51 --- src/mainboard/apple/macbook21/acpi_tables.c | 7 - src/mainboard/apple/macbook21/cmos.default | 1 - src/mainboard/apple/macbook21/cmos.layout | 1 - src/mainboard/apple/macbook21/devicetree.cb | 5 +- src/mainboard/emulation/qemu-q35/mainboard.c | 14 + src/mainboard/getac/p470/acpi/ec.asl | 2 +- src/mainboard/getac/p470/acpi/video.asl | 44 --- src/mainboard/getac/p470/acpi_tables.c | 8 - src/mainboard/getac/p470/devicetree.cb | 3 + src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 8 - src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 4 + .../gigabyte/ga-b75m-d3v/acpi/mainboard.asl | 48 --- src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c | 8 - src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb | 3 + src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl | 1 - src/mainboard/google/bolt/acpi_tables.c | 7 - src/mainboard/google/bolt/devicetree.cb | 3 + src/mainboard/google/butterfly/acpi_tables.c | 7 - src/mainboard/google/butterfly/devicetree.cb | 3 + src/mainboard/google/falco/acpi_tables.c | 7 - src/mainboard/google/falco/devicetree.cb | 3 + src/mainboard/google/link/acpi_tables.c | 8 - src/mainboard/google/link/devicetree.cb | 3 + src/mainboard/google/panther/acpi_tables.c | 7 - src/mainboard/google/panther/devicetree.cb | 3 + src/mainboard/google/parrot/acpi_tables.c | 7 - src/mainboard/google/parrot/devicetree.cb | 3 + src/mainboard/google/peppy/acpi_tables.c | 7 - src/mainboard/google/peppy/devicetree.cb | 3 + src/mainboard/google/slippy/acpi_tables.c | 7 - src/mainboard/google/slippy/devicetree.cb | 3 + src/mainboard/google/stout/acpi_tables.c | 7 - src/mainboard/google/stout/devicetree.cb | 3 + src/mainboard/ibase/mb899/acpi/video.asl | 42 -- src/mainboard/ibase/mb899/acpi_tables.c | 7 - src/mainboard/ibase/mb899/devicetree.cb | 4 + src/mainboard/intel/baskingridge/acpi_tables.c | 7 - src/mainboard/intel/baskingridge/devicetree.cb | 3 + src/mainboard/intel/cougar_canyon2/acpi_tables.c | 9 - src/mainboard/intel/cougar_canyon2/devicetree.cb | 3 + src/mainboard/intel/d945gclf/acpi/video.asl | 42 -- src/mainboard/intel/emeraldlake2/acpi_tables.c | 7 - src/mainboard/intel/emeraldlake2/devicetree.cb | 3 + src/mainboard/iwave/iWRainbowG6/acpi/video.asl | 44 --- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 8 - src/mainboard/iwave/iWRainbowG6/devicetree.cb | 3 + src/mainboard/kontron/986lcd-m/acpi/video.asl | 42 -- src/mainboard/kontron/986lcd-m/acpi_tables.c | 7 - src/mainboard/kontron/986lcd-m/devicetree.cb | 3 + src/mainboard/kontron/ktqm77/acpi_tables.c | 8 - src/mainboard/kontron/ktqm77/devicetree.cb | 3 + src/mainboard/lenovo/t420s/acpi_tables.c | 8 - src/mainboard/lenovo/t420s/devicetree.cb | 2 + src/mainboard/lenovo/t420s/dsdt.asl | 4 +- src/mainboard/lenovo/t430s/acpi_tables.c | 8 - src/mainboard/lenovo/t430s/devicetree.cb | 2 + src/mainboard/lenovo/t430s/dsdt.asl | 4 +- src/mainboard/lenovo/t520/acpi_tables.c | 7 - src/mainboard/lenovo/t520/devicetree.cb | 3 + src/mainboard/lenovo/t520/dsdt.asl | 5 +- src/mainboard/lenovo/t530/acpi_tables.c | 7 - src/mainboard/lenovo/t530/devicetree.cb | 3 + src/mainboard/lenovo/t530/dsdt.asl | 5 +- src/mainboard/lenovo/t60/acpi/video.asl | 24 +- src/mainboard/lenovo/t60/acpi_tables.c | 7 - src/mainboard/lenovo/t60/devicetree.cb | 3 + src/mainboard/lenovo/t60/dsdt.asl | 10 +- src/mainboard/lenovo/x200/acpi_tables.c | 7 - src/mainboard/lenovo/x200/devicetree.cb | 3 + src/mainboard/lenovo/x200/dsdt.asl | 4 +- src/mainboard/lenovo/x201/acpi_tables.c | 7 - src/mainboard/lenovo/x201/devicetree.cb | 3 + src/mainboard/lenovo/x201/dsdt.asl | 5 +- src/mainboard/lenovo/x220/acpi_tables.c | 6 - src/mainboard/lenovo/x220/devicetree.cb | 3 + src/mainboard/lenovo/x220/dsdt.asl | 5 +- src/mainboard/lenovo/x230/acpi_tables.c | 6 - src/mainboard/lenovo/x230/devicetree.cb | 3 + src/mainboard/lenovo/x230/dsdt.asl | 5 +- src/mainboard/lenovo/x60/acpi/video.asl | 55 --- src/mainboard/lenovo/x60/acpi_tables.c | 7 - src/mainboard/lenovo/x60/devicetree.cb | 3 + src/mainboard/lenovo/x60/dsdt.asl | 6 +- src/mainboard/packardbell/ms2290/acpi/ec.asl | 4 +- src/mainboard/packardbell/ms2290/acpi_tables.c | 7 - src/mainboard/packardbell/ms2290/devicetree.cb | 3 + src/mainboard/packardbell/ms2290/dsdt.asl | 2 - src/mainboard/roda/rk886ex/acpi/ec.asl | 2 +- src/mainboard/roda/rk886ex/acpi/video.asl | 44 --- src/mainboard/roda/rk886ex/acpi_tables.c | 7 - src/mainboard/roda/rk886ex/devicetree.cb | 3 + src/mainboard/roda/rk9/acpi_tables.c | 7 - src/mainboard/roda/rk9/devicetree.cb | 3 + src/mainboard/samsung/lumpy/acpi_tables.c | 7 - src/mainboard/samsung/lumpy/devicetree.cb | 3 + src/mainboard/samsung/stumpy/acpi_tables.c | 7 - src/mainboard/samsung/stumpy/devicetree.cb | 3 + src/northbridge/intel/fsp_sandybridge/Kconfig | 2 + src/northbridge/intel/fsp_sandybridge/acpi/igd.asl | 326 ++-------------- src/northbridge/intel/fsp_sandybridge/chip.h | 4 + src/northbridge/intel/fsp_sandybridge/gma.c | 22 ++ src/northbridge/intel/gm45/Kconfig | 1 + src/northbridge/intel/gm45/acpi/igd.asl | 423 ++------------------- src/northbridge/intel/gm45/gma.c | 22 ++ src/northbridge/intel/haswell/Kconfig | 1 + src/northbridge/intel/haswell/acpi/igd.asl | 326 ++-------------- src/northbridge/intel/haswell/chip.h | 4 + src/northbridge/intel/haswell/gma.c | 22 ++ src/northbridge/intel/i945/Kconfig | 1 + src/northbridge/intel/i945/acpi/i945.asl | 6 - src/northbridge/intel/i945/acpi/igd.asl | 329 ++-------------- src/northbridge/intel/i945/chip.h | 3 + src/northbridge/intel/i945/gma.c | 22 ++ src/northbridge/intel/nehalem/Kconfig | 1 + src/northbridge/intel/nehalem/acpi/igd.asl | 415 ++------------------ src/northbridge/intel/nehalem/gma.c | 22 ++ src/northbridge/intel/sandybridge/Kconfig | 4 + src/northbridge/intel/sandybridge/acpi/igd.asl | 411 ++------------------ src/northbridge/intel/sandybridge/gma.c | 22 ++ src/northbridge/intel/sch/Kconfig | 1 + src/northbridge/intel/sch/acpi/igd.asl | 325 ++-------------- src/northbridge/intel/sch/acpi/sch.asl | 6 - src/northbridge/intel/sch/chip.h | 30 ++ src/northbridge/intel/sch/gma.c | 24 ++ src/southbridge/intel/bd82x6x/lpc.c | 4 + src/southbridge/intel/fsp_bd82x6x/lpc.c | 6 + src/southbridge/intel/i82801gx/lpc.c | 7 + src/southbridge/intel/i82801ix/lpc.c | 6 + src/southbridge/intel/ibexpeak/lpc.c | 3 + src/southbridge/intel/lynxpoint/lpc.c | 6 + src/southbridge/intel/sch/lpc.c | 6 + 137 files changed, 917 insertions(+), 3032 deletions(-) diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 6657224..112f262 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -36,3 +36,7 @@ config INTEL_EDID config INTEL_INT15 bool default n + +config INTEL_GMA_ACPI + bool + default n diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index d963df9..039d1d4 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -23,3 +23,4 @@ ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c ifeq ($(CONFIG_VGA_ROM_RUN),y) ramstage-$(CONFIG_INTEL_INT15) += int15.c endif +ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c \ No newline at end of file diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c new file mode 100644 index 0000000..c3a9b8a --- /dev/null +++ b/src/drivers/intel/gma/acpi.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2014 Vladimir Serbinenko + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <string.h> +#include "i915.h" + +void +drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf) +{ + size_t i; + const char *names[] = { "UNK", "VGA", "TV", "DVI", "LCD" }; + int counters[ARRAY_SIZE(names)]; + + memset(counters, 0, sizeof(counters)); + + acpigen_write_scope("\\_SB.PCI0.GFX0"); + + /* + Method (_DOD, 0) + { + Return (Package() { + 0x5a5a5a5a, + 0x5a5a5a5a, + 0x5a5a5a5a + }) + } + */ + acpigen_write_method("_DOD", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_write_package(conf->ndid); + + for (i = 0; i < conf->ndid; i++) { + acpigen_write_dword (conf->did[i] | 0x80010000); + } + acpigen_pop_len(); /* End Package. */ + acpigen_pop_len(); /* End Method. */ + + for (i = 0; i < conf->ndid; i++) { + char name[10]; + char *ptr; + int kind; + kind = (conf->did[i] >> 8) & 0xf; + if (kind >= ARRAY_SIZE(names)) { + kind = 0; + } + strcpy(name, names[kind]); + for (ptr = name; *ptr; ptr++); + *ptr++ = counters[kind] + '0'; + *ptr++ = '\0'; + counters[kind]++; + acpigen_write_device(name); + /* Name (_ADR, 0x0410) */ + acpigen_write_name_dword("_ADR", conf->did[i] & 0xffff); + + /* ACPI brightness for LCD. */ + if (kind == 4) { + /* + Method (_BCL, 0, NotSerialized) + { + Return (^^XBCL()) + } + */ + acpigen_write_method("_BCL", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_namestring("^^XBCL"); + acpigen_pop_len(); + + /* + Method (_BCM, 1, NotSerialized) + { + ^^XBCM(Arg0) + } + */ + acpigen_write_method("_BCM", 1); + acpigen_emit_namestring("^^XBCM"); + acpigen_emit_byte(0x68); /* Arg0Op. */ + acpigen_pop_len(); + + /* + Method (_BQC, 0, NotSerialized) + { + Return (^^XBQC()) + } + */ + acpigen_write_method("_BQC", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_namestring("^^XBQC"); + acpigen_pop_len(); + } + + /* + Method(_DCS, 0) + { + Return (^^XDCS(<device number>)) + } + */ + acpigen_write_method("_DCS", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_namestring("^^XDCS"); + acpigen_write_byte(i); + acpigen_pop_len(); + + /* + Method(_DGS, 0) + { + Return (^^XDGS(<device number>)) + } + */ + acpigen_write_method("_DGS", 0); + acpigen_emit_byte(0xa4); /* ReturnOp. */ + acpigen_emit_namestring("^^XDGS"); + acpigen_write_byte(i); + acpigen_pop_len(); + + /* + Method(_DSS, 1) + { + ^^XDSS(0x5a, Arg0) + } + */ + acpigen_write_method("_DSS", 0); + acpigen_emit_namestring("^^XDSS"); + acpigen_write_byte(i); + acpigen_emit_byte(0x68); /* Arg0Op. */ + acpigen_pop_len(); + + acpigen_pop_len(); + } + + acpigen_pop_len(); +} diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 36ac5fc..542b321 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -292,8 +292,15 @@ struct i915_gpu_controller_info int link_frequency_270_mhz; int lvds_num_lanes; u32 backlight; + int ndid; + u32 did[5]; }; +void +drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void); + int i915lightup(unsigned int physbase, unsigned int mmio, unsigned int gfx, unsigned int init_fb); int panel_lightup(struct intel_dp *dp, unsigned int init_fb); diff --git a/src/drivers/intel/gma/igd.asl b/src/drivers/intel/gma/igd.asl new file mode 100644 index 0000000..31e8fec --- /dev/null +++ b/src/drivers/intel/gma/igd.asl @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + External(LCD0, DeviceObj) + + Name (BRCT, 0) + + Method(BRID, 1, NotSerialized) + { + Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) + If (LEqual (Local0, Ones)) + { + Return (Subtract(SizeOf(BRIG), One)) + } + Return (Local0) + } + + Method (XBCL, 0, NotSerialized) + { + Store (1, BRCT) + Return (BRIG) + } + + /* Display Output Switching */ + Method (_DOS, 1) + { + /* Windows 2000 and Windows XP call _DOS to enable/disable + * Display Output Switching during init and while a switch + * is already active + */ + Store (And(Arg0, 7), DSEN) + } + + /* Using Notify is the right way. But Windows doesn't handle + it well. So use both method in a way to avoid double action. + */ + Method (DECB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x87) + } Else { + Store (BRID (XBQC ()), Local0) + If (LNotEqual (Local0, 2)) + { + Decrement (Local0) + } + XBCM (DerefOf (Index (BRIG, Local0))) + } + } + + Method (INCB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x86) + } Else { + Store (BRID (XBQC ()), Local0) + If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One))) + { + Increment (Local0) + } + XBCM (DerefOf (Index (BRIG, Local0))) + } + } + + /* Device Current Status */ + Method(XDCS, 1) + { + TRAP(1) + If (And(CSTE, ShiftLeft (1, Arg0))) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(XDGS, 1) + { + If (And(NSTE, ShiftLeft (1, Arg0))) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(XDSS, 2) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } diff --git a/src/mainboard/apple/macbook21/acpi/video.asl b/src/mainboard/apple/macbook21/acpi/video.asl deleted file mode 100644 index c2f9dfb..0000000 --- a/src/mainboard/apple/macbook21/acpi/video.asl +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Device (DSPC) -{ - Name (_ADR, 0x00020001) - OperationRegion (DSPC, PCI_Config, 0x00, 0x100) - Field (DSPC, ByteAcc, NoLock, Preserve) - { - Offset (0xf4), - BRTC, 8 - } - - Method(BRTD, 0, NotSerialized) - { - Store(BRTC, Local0) - if (LGreater (Local0, 15)) - { - Subtract(Local0, 16, Local0) - Store(Local0, BRTC) - } - } - - Method(BRTU, 0, NotSerialized) - { - Store (BRTC, Local0) - if (LLess(Local0, 0xff)) - { - Add (Local0, 16, Local0) - Store(Local0, BRTC) - } - } -} diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c index c890677..f1b313f 100644 --- a/src/mainboard/apple/macbook21/acpi_tables.c +++ b/src/mainboard/apple/macbook21/acpi_tables.c @@ -37,13 +37,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index 0185e94..e0b992c 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -9,7 +9,6 @@ boot_default=0x40 cmos_defaults_loaded=Yes lpt=Enable volume=0x3 -tft_brightness=0xff first_battery=Primary bluetooth=Enable wlan=Enable diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 05e458a..2d73da4 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -86,7 +86,6 @@ entries 1052 4 r 0 C1DRT1 1064 8 h 0 volume -1072 8 h 0 tft_brightness 1080 1 e 9 first_battery 1081 1 e 1 bluetooth 1082 1 e 1 wwan diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 8ca84f8..71bdffc 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -21,11 +21,14 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" register "gpu_lvds_is_dual_channel" = "0" - register "gpu_backlight" = "0x1280128" + register "gpu_backlight" = "0x1290128" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index e991b53..a3ad312 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -25,6 +25,7 @@ #include <pc80/keyboard.h> #include <arch/io.h> #include <console/console.h> +#include <drivers/intel/gma/i915.h> #define Q35_PAM0 0x90 @@ -33,6 +34,19 @@ static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, }; +struct i915_gpu_controller_info gfx_controller_info = { + .ndid = 3, + .did = { + 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 + } +}; + +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + return &gfx_controller_info; +} + static void qemu_nb_init(device_t dev) { /* Map memory at 0xc0000 - 0xfffff */ diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 70e4224..c01a9fe 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -193,7 +193,7 @@ Device(EC0) { Store(0x3f, HOTK) If(IGDS) { - HKDS(10) + Notify (\_SB.PCI0.GFX0, 0x82) } Else { TRAP(0xE1) } diff --git a/src/mainboard/getac/p470/acpi/video.asl b/src/mainboard/getac/p470/acpi/video.asl deleted file mode 100644 index 3536913..0000000 --- a/src/mainboard/getac/p470/acpi/video.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index d421101..474d676 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -38,14 +38,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* Enable COM port(s) */ gnvs->cmap = 0x01; gnvs->cmbp = 0x00; - - /* IGD Displays */ - gnvs->ndid = 2; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000410; - gnvs->did[2] = 0x80000320; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } static long acpi_create_ecdt(acpi_ecdt_t * ecdt) diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index ddcd749..12f2768 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -20,6 +20,9 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "2" + register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c index 73b1c11..3830294 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -56,14 +56,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 3c7641a..fa949e9 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -1,4 +1,8 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + device cpu_cluster 0 on chip cpu/intel/socket_LGA1155 device lapic 0 on end diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl deleted file mode 100644 index 0db01bb..0000000 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Method (BRTN, 1, Serialized) -{ - If (LEqual (And (DID1, 0x0F00), 0x0400)) - { - Notify (\_SB.PCI0.GFX0.DD01, Arg0) - } - - If (LEqual (And (DID2, 0x0F00), 0x0400)) - { - Notify (\_SB.PCI0.GFX0.DD02, Arg0) - } - - If (LEqual (And (DID3, 0x0F00), 0x0400)) - { - Notify (\_SB.PCI0.GFX0.DD03, Arg0) - } - - If (LEqual (And (DID4, 0x0F00), 0x0400)) - { - Notify (\_SB.PCI0.GFX0.DD04, Arg0) - } - - If (LEqual (And (DID5, 0x0F00), 0x0400)) - { - Notify (\_SB.PCI0.GFX0.DD05, Arg0) - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c index 73b1c11..3830294 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c @@ -56,14 +56,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb index 1c08359..369bc6f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + device cpu_cluster 0 on chip cpu/intel/socket_LGA1155 device lapic 0 on end diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl index 1ce6dd4..84a889a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl @@ -9,7 +9,6 @@ DefinitionBlock( { // Some generic macros #include "acpi/platform.asl" - #include "acpi/mainboard.asl" #include <cpu/intel/model_206ax/acpi/cpu.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/google/bolt/acpi_tables.c b/src/mainboard/google/bolt/acpi_tables.c index 3b851c4..9b3a23d 100644 --- a/src/mainboard/google/bolt/acpi_tables.c +++ b/src/mainboard/google/bolt/acpi_tables.c @@ -66,13 +66,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb index 1d1eab5..1acd781 100644 --- a/src/mainboard/google/bolt/devicetree.cb +++ b/src/mainboard/google/bolt/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index cabc052..1c45c22 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -54,13 +54,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // TODO: MLR // The firmware read/write status is a "virtual" switch and diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 90925b9..47d6a10 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/falco/acpi_tables.c b/src/mainboard/google/falco/acpi_tables.c index 5849087..444d9e9 100644 --- a/src/mainboard/google/falco/acpi_tables.c +++ b/src/mainboard/google/falco/acpi_tables.c @@ -60,13 +60,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb index 7a8e757..8cdb032 100644 --- a/src/mainboard/google/falco/devicetree.cb +++ b/src/mainboard/google/falco/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index d1d4fcb..547717a 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -64,14 +64,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 1; - gnvs->did[0] = 0x80000000; - gnvs->did[1] = 0x80000000; - gnvs->did[2] = 0x00000000; - gnvs->did[3] = 0x00000000; - gnvs->did[4] = 0x00000000; - #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 5333dfc..382a8c4 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "1" + register "gfx.did" = "{ 0x80000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/panther/acpi_tables.c b/src/mainboard/google/panther/acpi_tables.c index 9340c5a..3954821 100644 --- a/src/mainboard/google/panther/acpi_tables.c +++ b/src/mainboard/google/panther/acpi_tables.c @@ -77,13 +77,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS // SuperIO is always RO diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb index 2032fd4..af6043f 100644 --- a/src/mainboard/google/panther/devicetree.cb +++ b/src/mainboard/google/panther/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Disable eDP Hotplug register "gpu_dp_d_hotplug" = "0x00" diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 0041c98..3f5b719 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -55,13 +55,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = parrot_ec_running_ro() ? diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index a4baafd..034309f 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort B Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" diff --git a/src/mainboard/google/peppy/acpi_tables.c b/src/mainboard/google/peppy/acpi_tables.c index 265fe65..369c7fb 100644 --- a/src/mainboard/google/peppy/acpi_tables.c +++ b/src/mainboard/google/peppy/acpi_tables.c @@ -69,13 +69,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb index 894d3ef..505b39e 100644 --- a/src/mainboard/google/peppy/devicetree.cb +++ b/src/mainboard/google/peppy/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 3b851c4..9b3a23d 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -66,13 +66,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index f50882c..3d4c8c5 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 23c47f9..9e5c6a1 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -58,13 +58,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS gnvs->chromeos.vbt2 = get_recovery_mode_switch() ? diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 4ac89f6..cd33cd7 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/ibase/mb899/acpi/video.asl b/src/mainboard/ibase/mb899/acpi/video.asl deleted file mode 100644 index cca1a3b..0000000 --- a/src/mainboard/ibase/mb899/acpi/video.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c index dba2953..93485a0 100644 --- a/src/mainboard/ibase/mb899/acpi_tables.c +++ b/src/mainboard/ibase/mb899/acpi_tables.c @@ -36,13 +36,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index a26d7c2..77ceadd 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -1,4 +1,8 @@ chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index d5a5f03..d3034a9 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -79,13 +79,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; #if CONFIG_CHROMEOS /* Emerald Lake has no EC (?) */ diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index cd341d1..a9cfb49 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/haswell + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/intel/cougar_canyon2/acpi_tables.c b/src/mainboard/intel/cougar_canyon2/acpi_tables.c index dca35b5..b89c865 100644 --- a/src/mainboard/intel/cougar_canyon2/acpi_tables.c +++ b/src/mainboard/intel/cougar_canyon2/acpi_tables.c @@ -62,16 +62,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 1; gnvs->s5u1 = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - acpi_update_thermal_table(gnvs); - } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index c386853..d7c6aab 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/fsp_sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/intel/d945gclf/acpi/video.asl b/src/mainboard/intel/d945gclf/acpi/video.asl deleted file mode 100644 index 7baf995..0000000 --- a/src/mainboard/intel/d945gclf/acpi/video.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index f17e1f4..2953e2b 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -78,13 +78,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 1; gnvs->s5u1 = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; acpi_update_thermal_table(gnvs); diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index e5a8ea0..0b3e788 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/video.asl b/src/mainboard/iwave/iWRainbowG6/acpi/video.asl deleted file mode 100644 index 3536913..0000000 --- a/src/mainboard/iwave/iWRainbowG6/acpi/video.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c index 4dcda79..eb4ab22 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c +++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c @@ -40,14 +40,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) /* Enable both COM ports. */ gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - - /* IGD Displays. */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb index 84cfc4b..29e9e5e 100644 --- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb +++ b/src/mainboard/iwave/iWRainbowG6/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sch + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_441 diff --git a/src/mainboard/kontron/986lcd-m/acpi/video.asl b/src/mainboard/kontron/986lcd-m/acpi/video.asl deleted file mode 100644 index cca1a3b..0000000 --- a/src/mainboard/kontron/986lcd-m/acpi/video.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c index 2e775ae..5f25c42 100644 --- a/src/mainboard/kontron/986lcd-m/acpi_tables.c +++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c @@ -36,13 +36,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 6a5b221..b9ddf75 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index d2d70e9..b434d5f 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -52,14 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 0; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - acpi_update_thermal_table(gnvs); } diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 855fd5c..24306ef 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c index 15b9d9a..35bbbef 100644 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ b/src/mainboard/lenovo/t420s/acpi_tables.c @@ -51,14 +51,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 7fd6a53..e43ac48 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -1,4 +1,6 @@ chip northbridge/intel/sandybridge + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index 85e2b4f..acd03d0 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -20,8 +20,8 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define HAVE_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c index 407c8f9..371856d 100644 --- a/src/mainboard/lenovo/t430s/acpi_tables.c +++ b/src/mainboard/lenovo/t430s/acpi_tables.c @@ -37,14 +37,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index af3de6c..23bce4e 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -1,4 +1,6 @@ chip northbridge/intel/sandybridge + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index 85e2b4f..acd03d0 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -20,8 +20,8 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 #define HAVE_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index 15b9d9a..862a5e5 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -51,13 +51,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index bf575d8..3688145 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 85e2b4f..e98afe0 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index 15b9d9a..862a5e5 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -51,13 +51,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index d59524b..d4c5837 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 85e2b4f..e98afe0 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl index 9a458e9..9dea2b0 100644 --- a/src/mainboard/lenovo/t60/acpi/video.asl +++ b/src/mainboard/lenovo/t60/acpi/video.asl @@ -21,35 +21,17 @@ #include "smi.h" -Device (DSPC) +Scope (\) { - Name (_ADR, 0x00020001) - OperationRegion (DSPC, PCI_Config, 0x00, 0x100) - Field (DSPC, ByteAcc, NoLock, Preserve) - { - Offset (0xf4), - BRTC, 8 - } - Method(BRTD, 0, NotSerialized) { Trap(SMI_BRIGHTNESS_DOWN) - Store(BRTC, Local0) - if (LGreater (Local0, 15)) - { - Subtract(Local0, 16, Local0) - Store(Local0, BRTC) - } + \_SB.PCI0.GFX0.DECB() } Method(BRTU, 0, NotSerialized) { Trap(SMI_BRIGHTNESS_UP) - Store (BRTC, Local0) - if (LLess(Local0, 0xff)) - { - Add (Local0, 16, Local0) - Store(Local0, BRTC) - } + \_SB.PCI0.GFX0.INCB() } } diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c index c890677..f1b313f 100644 --- a/src/mainboard/lenovo/t60/acpi_tables.c +++ b/src/mainboard/lenovo/t60/acpi_tables.c @@ -37,13 +37,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index bca0787..08364e8 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -21,6 +21,9 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 7807687..71ba71f 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -20,8 +20,8 @@ */ #define THINKPAD_EC_GPE 28 -#define BRIGHTNESS_UP \DSPC.BRTU -#define BRIGHTNESS_DOWN \DSPC.BRTD +#define BRIGHTNESS_UP \BRTU +#define BRIGHTNESS_DOWN \BRTD #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 DefinitionBlock( @@ -46,6 +46,12 @@ DefinitionBlock( // mainboard specific devices #include "acpi/mainboard.asl" + Scope (\) + { + // backlight control, display switching, lid + #include "acpi/video.asl" + } + #include <cpu/intel/model_6dx/acpi/cpu.asl> Scope (\_SB) { diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 77491dc..ebdfe8f 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -41,13 +41,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 0; /* Will use default of 0x00000400. */ - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 09bc08f..cb4a021 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/gm45 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gfx.use_spread_spectrum_clock" = "1" register "gfx.lvds_dual_channel" = "0" diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 0409e66..ac40bcc 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -20,8 +20,8 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1 diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index eef7bf7..89217d0 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -34,13 +34,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) { - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_slit(unsigned long current) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 402b9d4..63f2231 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -21,6 +21,9 @@ ## chip northbridge/intel/nehalem + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 5265a91..f7ec349c 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index 15b9d9a..eadc44b 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -52,12 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 6eb3b15..28e240a 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 85e2b4f..e98afe0 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index 15b9d9a..eadc44b 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -52,12 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u1 = 0; /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; // the lid is open by default. gnvs->lids = 1; diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 55677a3..88cf52d 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 85e2b4f..e98afe0 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -20,11 +20,10 @@ */ #define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define EC_LENOVO_H8_ME_WORKAROUND 1 -#define HAVE_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x60/acpi/video.asl b/src/mainboard/lenovo/x60/acpi/video.asl deleted file mode 100644 index b38d82b..0000000 --- a/src/mainboard/lenovo/x60/acpi/video.asl +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include "smi.h" - -Device (DSPC) -{ - Name (_ADR, 0x00020001) - OperationRegion (DSPC, PCI_Config, 0x00, 0x100) - Field (DSPC, ByteAcc, NoLock, Preserve) - { - Offset (0xf4), - BRTC, 8 - } - - Method(BRTD, 0, NotSerialized) - { - Store(BRTC, Local0) - if (LGreater (Local0, 15)) - { - Subtract(Local0, 16, Local0) - Store(Local0, BRTC) - Trap(SMI_SAVE_CMOS) - } - } - - Method(BRTU, 0, NotSerialized) - { - Store (BRTC, Local0) - if (LLess(Local0, 0xff)) - { - Add (Local0, 16, Local0) - Store(Local0, BRTC) - Trap(SMI_SAVE_CMOS) - } - } -} diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index c890677..f1b313f 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -37,13 +37,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 382ebaf..ab5ba63 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -21,6 +21,9 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 7807687..d8990ef 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -19,9 +19,11 @@ * MA 02110-1301 USA */ +#include "smi.h" + #define THINKPAD_EC_GPE 28 -#define BRIGHTNESS_UP \DSPC.BRTU -#define BRIGHTNESS_DOWN \DSPC.BRTD +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 DefinitionBlock( diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl index 3735f20..e53c367 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ec.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ec.asl @@ -122,12 +122,12 @@ Device(EC) /* Decrease brightness. */ Method(_Q1D, 0, NotSerialized) { - \_SB.PCI0.GFX0.LCD0.DECB() + \_SB.PCI0.GFX0.DECB() } /* Increase brightness. */ Method(_Q1C, 0, NotSerialized) { - \_SB.PCI0.GFX0.LCD0.INCB() + \_SB.PCI0.GFX0.INCB() } #include "battery.asl" diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c index eef7bf7..89217d0 100644 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ b/src/mainboard/packardbell/ms2290/acpi_tables.c @@ -34,13 +34,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs) { - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_slit(unsigned long current) diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 2f4bce1..ae2c5ed 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -21,6 +21,9 @@ ## chip northbridge/intel/nehalem + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gpu_dp_b_hotplug" = "0x04" register "gpu_dp_c_hotplug" = "0x04" diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index f0eb8ec..f9c0112 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -19,8 +19,6 @@ * MA 02110-1301 USA */ -#define HAVE_LCD_SCREEN 1 - DefinitionBlock( "dsdt.aml", "DSDT", diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index d174e98..f3b6021 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -98,8 +98,8 @@ Device(EC0) Method (_Q12, 0) { Store("_Q12: Fn-F9 (Display Switch) pressed", Debug) + Notify (\_SB.PCI0.GFX0, 0x82) // Store(1, TLST) - // HKDS(10) } Method (_Q30, 0) diff --git a/src/mainboard/roda/rk886ex/acpi/video.asl b/src/mainboard/roda/rk886ex/acpi/video.asl deleted file mode 100644 index 3536913..0000000 --- a/src/mainboard/roda/rk886ex/acpi/video.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// Brightness write -Method (BRTW, 1, Serialized) -{ - // TODO -} - -// Hot Key Display Switch -Method (HKDS, 1, Serialized) -{ - // TODO -} - -// Lid Switch Display Switch -Method (LSDS, 1, Serialized) -{ - // TODO -} - -// Brightness Notification -Method(BRTN,1,Serialized) -{ - // TODO (no displays defined yet) -} diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c index c890677..f1b313f 100644 --- a/src/mainboard/roda/rk886ex/acpi_tables.c +++ b/src/mainboard/roda/rk886ex/acpi_tables.c @@ -37,13 +37,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 3fe8b2a..c97d9f7 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -20,6 +20,9 @@ ## chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 77491dc..ebdfe8f 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -41,13 +41,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->cmap = 0x01; gnvs->cmbp = 0x01; - /* IGD Displays */ - gnvs->ndid = 0; /* Will use default of 0x00000400. */ - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index 2bd2358..003c08e 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/gm45 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 device lapic 0 on end diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 6d8517c..d115053 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -80,13 +80,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; acpi_update_thermal_table(gnvs); diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 0372614..a632b27 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index dc2197a..9dc24cc 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -79,13 +79,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 1; gnvs->s5u1 = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; acpi_update_thermal_table(gnvs); diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 60b112b..df91a72 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -1,4 +1,7 @@ chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 4eb5b8e..44ec95d 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -22,11 +22,13 @@ config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE bool select CPU_INTEL_FSP_MODEL_206AX select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE bool select CPU_INTEL_FSP_MODEL_306AX select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl index 9399554..15a7df2 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl @@ -23,301 +23,57 @@ Device (GFX0) { Name (_ADR, 0x00020000) - /* Display Output Switching */ - Method (_DOS, 1) + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) + Offset (0x10), + BAR0, 64 } - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0x48254), + BCLV, 16, + Offset (0xc8250), + CR1, 32, + CR2, 32 } - - Device(DD03) + Name (BRIG, Package (0x12) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x061a061a, CR2) } - - Device(DD05) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } - +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h index 9b5f605..656d0f3 100644 --- a/src/northbridge/intel/fsp_sandybridge/chip.h +++ b/src/northbridge/intel/fsp_sandybridge/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -38,4 +40,6 @@ struct northbridge_intel_fsp_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index d578d56..64b34b5 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -63,6 +63,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_fsp_sandybridge_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -71,6 +92,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = pci_dev_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 096c80f..508507e 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -31,6 +31,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl index 199765b..1b58383 100644 --- a/src/northbridge/intel/gm45/acpi/igd.asl +++ b/src/northbridge/intel/gm45/acpi/igd.asl @@ -27,10 +27,10 @@ Device (GFX0) Field (GFXC, DWordAcc, NoLock, Preserve) { Offset (0x10), - BAR0, 64 + BAR0, 64 } - OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) { Offset (0x61250), @@ -39,399 +39,40 @@ Device (GFX0) BCLM, 16, } - /* Display Output Switching */ - Method (_DOS, 1) + Name (BRIG, Package (0x12) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many GM45 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) - { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD3, 0)) - Store (Or(0x00010000, DID2), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD4, 0)) - Store (Or(0x00010000, DID2), Index(DOD4, 1)) - Store (Or(0x00010000, DID3), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD5, 0)) - Store (Or(0x00010000, DID2), Index(DOD5, 1)) - Store (Or(0x00010000, DID3), Index(DOD5, 2)) - Store (Or(0x00010000, DID4), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - -#ifdef DISPLAY_DEVICE_2_IS_LCD_SCREEN - Device (LCD0) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - Name (BRCT, 0) - - Name (BRIG, Package (0x12) - { - 0x61, - 0x61, - 0x2, - 0x4, - 0x5, - 0x7, - 0x9, - 0xb, - 0xd, - 0x11, - 0x14, - 0x17, - 0x1c, - 0x20, - 0x27, - 0x31, - 0x41, - 0x61, - }) - - Method (_BCL, 0, NotSerialized) - { - Store (1, BRCT) - Return (BRIG) - } - - Method (_BCM, 1, NotSerialized) - { - Store (ShiftLeft (Arg0, 4), ^^BCLV) - Store (0x80000000, ^^CR1) - Store (0x0610, ^^BCLM) - } - Method (_BQC, 0, NotSerialized) - { - Store (^^BCLV, Local0) - ShiftRight (Local0, 4, Local0) - Return (Local0) - } - - Method(BRID, 1, NotSerialized) - { - Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) - If (LEqual (Local0, Ones)) - { - Return (0x11) - } - Return (Local0) - } - - /* Using Notify is the right way. But Windows doesn't handle - it well. So use both method in a way to avoid double action. - */ - Method (DECB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x87) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 2)) - { - Decrement (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } - Method (INCB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x86) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 0x11)) - { - Increment (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } - } -#else - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } -#endif - - Device(DD03) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x0610, BCLM) } - - Device(DD05) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index c71b8b2..0bf3356 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -491,6 +491,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_gm45_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -499,6 +520,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 0845a3f..91ec62c 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -27,6 +27,7 @@ config NORTHBRIDGE_INTEL_HASWELL select INTEL_DDI select INTEL_DP select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/haswell/acpi/igd.asl b/src/northbridge/intel/haswell/acpi/igd.asl index 9399554..15a7df2 100644 --- a/src/northbridge/intel/haswell/acpi/igd.asl +++ b/src/northbridge/intel/haswell/acpi/igd.asl @@ -23,301 +23,57 @@ Device (GFX0) { Name (_ADR, 0x00020000) - /* Display Output Switching */ - Method (_DOS, 1) + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) + Offset (0x10), + BAR0, 64 } - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0x48254), + BCLV, 16, + Offset (0xc8250), + CR1, 32, + CR2, 32 } - - Device(DD03) + Name (BRIG, Package (0x12) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x061a061a, CR2) } - - Device(DD05) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } - +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index d60504c..97c4036 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <drivers/intel/gma/i915.h> + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -38,6 +40,8 @@ struct northbridge_intel_haswell_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + + struct i915_gpu_controller_info gfx; }; extern struct chip_operations northbridge_intel_haswell_ops; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 5d0e8e7..284f313 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -487,6 +487,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_haswell_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -496,6 +517,7 @@ static struct device_operations gma_func0_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, + .acpi_fill_ssdt_generator = gma_ssdt, .scan_bus = 0, .enable = 0, .ops_pci = &gma_pci_ops, diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 8a0cb5b..55dbda8 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -30,6 +30,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select LAPIC_MONOTONIC_TIMER select VGA select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 6a34b94..4eac006 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -100,9 +100,3 @@ Device (PDRC) // Integrated graphics 0:2.0 #include "igd.asl" - -Scope (\) -{ - // backlight control, display switching, lid - #include "acpi/video.asl" -} diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 9399554..1dc281f 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -23,301 +23,52 @@ Device (GFX0) { Name (_ADR, 0x00020000) - /* Display Output Switching */ - Method (_DOS, 1) + Name (BRIG, Package (0x12) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) - { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD03) + 0xf, + 0xf, + 0x0, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (Or(ShiftLeft (Arg0, 4), 0xf), ^^DSPC.BRTC) +#ifdef SMI_SAVE_CMOS + Trap(SMI_SAVE_CMOS) +#endif } - - Device(DD04) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (^^DSPC.BRTC, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } +#include <drivers/intel/gma/igd.asl> +} - - Device(DD05) +Device (DSPC) +{ + Name (_ADR, 0x00020001) + OperationRegion (DSPC, PCI_Config, 0x00, 0x100) + Field (DSPC, ByteAcc, NoLock, Preserve) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0xf4), + BRTC, 8 } - -} +} \ No newline at end of file diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 9e25ecc..5706086 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -1,6 +1,9 @@ +#include <drivers/intel/gma/i915.h> + struct northbridge_intel_i945_config { u32 gpu_hotplug; u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; int gpu_lvds_is_dual_channel; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e5974c9..af144f0 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -488,6 +488,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_i945_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -497,6 +518,7 @@ static struct device_operations gma_func0_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, + .acpi_fill_ssdt_generator = gma_ssdt, .scan_bus = 0, .enable = 0, .disable = gma_func0_disable, diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index ca5ffa5..dabd5a5 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select TSC_MONOTONIC_TIMER select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl index 8c6c174..15a7df2 100644 --- a/src/northbridge/intel/nehalem/acpi/igd.asl +++ b/src/northbridge/intel/nehalem/acpi/igd.asl @@ -27,10 +27,10 @@ Device (GFX0) Field (GFXC, DWordAcc, NoLock, Preserve) { Offset (0x10), - BAR0, 64 + BAR0, 64 } - OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) { Offset (0x48254), @@ -40,391 +40,40 @@ Device (GFX0) CR2, 32 } - /* Display Output Switching */ - Method (_DOS, 1) + Name (BRIG, Package (0x12) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x061a061a, CR2) } - Device(DD01) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD03) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD05) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - -#ifdef HAVE_LCD_SCREEN - Device (LCD0) - { - Name (_ADR, 0x0400) - Name (BRCT, 0) - - Name (BRIG, Package (0x12) - { - 0x61, - 0x61, - 0x2, - 0x4, - 0x5, - 0x7, - 0x9, - 0xb, - 0xd, - 0x11, - 0x14, - 0x17, - 0x1c, - 0x20, - 0x27, - 0x31, - 0x41, - 0x61, - }) - - Method (_BCL, 0, NotSerialized) - { - Store (1, BRCT) - Return (BRIG) - } - - Method (_BCM, 1, NotSerialized) - { - Store (ShiftLeft (Arg0, 4), ^^BCLV) - Store (0x80000000, ^^CR1) - Store (0x061a061a, ^^CR2) - } - Method (_BQC, 0, NotSerialized) - { - Store (^^BCLV, Local0) - ShiftRight (Local0, 4, Local0) - Return (Local0) - } - - Method(BRID, 1, NotSerialized) - { - Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) - If (LEqual (Local0, Ones)) - { - Return (0x11) - } - Return (Local0) - } - - /* Using Notify is the right way. But Windows doesn't handle - it well. So use both method in a way to avoid double action. - */ - Method (DECB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x87) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 2)) - { - Decrement (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } - Method (INCB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x86) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 0x11)) - { - Increment (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } -#endif +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 7d24bd5..6af9830 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -1071,6 +1071,27 @@ static void gma_read_resources(struct device *dev) res->size = (resource_t) 0x10000000; } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_nehalem_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -1079,6 +1100,7 @@ static struct device_operations gma_func0_ops = { .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index fc6d6a4..868ed18 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -24,6 +24,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_206AX select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE bool @@ -33,6 +34,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_IVYBRIDGE bool @@ -41,6 +43,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE bool @@ -50,6 +53,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl index 8c6c174..5c008f4 100644 --- a/src/northbridge/intel/sandybridge/acpi/igd.asl +++ b/src/northbridge/intel/sandybridge/acpi/igd.asl @@ -40,391 +40,40 @@ Device (GFX0) CR2, 32 } - /* Display Output Switching */ - Method (_DOS, 1) + Name (BRIG, Package (0x12) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x061a061a, CR2) } - Device(DD01) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD03) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD05) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - -#ifdef HAVE_LCD_SCREEN - Device (LCD0) - { - Name (_ADR, 0x0400) - Name (BRCT, 0) - - Name (BRIG, Package (0x12) - { - 0x61, - 0x61, - 0x2, - 0x4, - 0x5, - 0x7, - 0x9, - 0xb, - 0xd, - 0x11, - 0x14, - 0x17, - 0x1c, - 0x20, - 0x27, - 0x31, - 0x41, - 0x61, - }) - - Method (_BCL, 0, NotSerialized) - { - Store (1, BRCT) - Return (BRIG) - } - - Method (_BCM, 1, NotSerialized) - { - Store (ShiftLeft (Arg0, 4), ^^BCLV) - Store (0x80000000, ^^CR1) - Store (0x061a061a, ^^CR2) - } - Method (_BQC, 0, NotSerialized) - { - Store (^^BCLV, Local0) - ShiftRight (Local0, 4, Local0) - Return (Local0) - } - - Method(BRID, 1, NotSerialized) - { - Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) - If (LEqual (Local0, Ones)) - { - Return (0x11) - } - Return (Local0) - } - - /* Using Notify is the right way. But Windows doesn't handle - it well. So use both method in a way to avoid double action. - */ - Method (DECB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x87) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 2)) - { - Decrement (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } - Method (INCB, 0, NotSerialized) - { - If (BRCT) - { - Notify (LCD0, 0x86) - } Else { - Store (BRID (_BQC ()), Local0) - If (LNotEqual (Local0, 0x11)) - { - Increment (Local0) - } - _BCM (DerefOf (Index (BRIG, Local0))) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } -#endif +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 554c0a5..e9d0c05 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -613,6 +613,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_sandybridge_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -621,6 +642,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig index f495e6a..5cf52c9 100644 --- a/src/northbridge/intel/sch/Kconfig +++ b/src/northbridge/intel/sch/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_SCH select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES select LATE_CBMEM_INIT + select INTEL_GMA_ACPI if NORTHBRIDGE_INTEL_SCH diff --git a/src/northbridge/intel/sch/acpi/igd.asl b/src/northbridge/intel/sch/acpi/igd.asl index 9399554..1b58383 100644 --- a/src/northbridge/intel/sch/acpi/igd.asl +++ b/src/northbridge/intel/sch/acpi/igd.asl @@ -23,301 +23,56 @@ Device (GFX0) { Name (_ADR, 0x00020000) - /* Display Output Switching */ - Method (_DOS, 1) + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) + Offset (0x10), + BAR0, 64 } - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) + OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Offset (0x61250), + CR1, 32, + BCLV, 16, + BCLM, 16, } - - Device(DD03) + Name (BRIG, Package (0x12) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (XBCM, 1, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (ShiftLeft (Arg0, 4), BCLV) + Store (0x80000000, CR1) + Store (0x0610, BCLM) } - - Device(DD05) + Method (XBQC, 0, NotSerialized) { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } + Store (BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) } - +#include <drivers/intel/gma/igd.asl> } diff --git a/src/northbridge/intel/sch/acpi/sch.asl b/src/northbridge/intel/sch/acpi/sch.asl index 5e0b3f8..d1acc48 100644 --- a/src/northbridge/intel/sch/acpi/sch.asl +++ b/src/northbridge/intel/sch/acpi/sch.asl @@ -80,9 +80,3 @@ Device (PDRC) // Integrated graphics 0:2.0 #include "igd.asl" - -Scope (\) -{ - // backlight control, display switching, lid - #include "acpi/video.asl" -} diff --git a/src/northbridge/intel/sch/chip.h b/src/northbridge/intel/sch/chip.h new file mode 100644 index 0000000..d39931f --- /dev/null +++ b/src/northbridge/intel/sch/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_SCH_CHIP_H +#define NORTHBRIDGE_INTEL_SCH_CHIP_H + +#include <drivers/intel/gma/i915.h> + +struct northbridge_intel_sch_config { + struct i915_gpu_controller_info gfx; +}; + +#endif /* NORTHBRIDGE_INTEL_SCH_CHIP_H */ diff --git a/src/northbridge/intel/sch/gma.c b/src/northbridge/intel/sch/gma.c index 59ff024..3b2bf81 100644 --- a/src/northbridge/intel/sch/gma.c +++ b/src/northbridge/intel/sch/gma.c @@ -21,6 +21,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/i915.h> +#include "chip.h" static void gma_func0_init(struct device *dev) { @@ -44,6 +46,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_sch_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(void) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; @@ -52,6 +75,7 @@ static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .scan_bus = 0, .enable = 0, diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b207137..701cc0f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -678,6 +678,7 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); @@ -686,6 +687,9 @@ static void southbridge_inject_dsdt(void) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + #if CONFIG_CHROMEOS chromeos_init_vboot(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 6b95d08..5bb1776 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -640,11 +640,17 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); /* IGD OpRegion Base Address */ gnvs->aslb = (u32)opregion; + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 2e3182b..9dbb3ec 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -34,6 +34,7 @@ #include <arch/acpigen.h> #include <cbmem.h> #include <string.h> +#include <drivers/intel/gma/i915.h> #include "nvs.h" #define NMI_OFF 0 @@ -617,12 +618,18 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + memset(gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 4f576c4..a3e61a4 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -37,6 +37,7 @@ #include "i82801ix.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> +#include <drivers/intel/gma/i915.h> #define NMI_OFF 0 @@ -544,8 +545,13 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 6e41196..660d34d 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -671,6 +671,7 @@ static void southbridge_inject_dsdt(void) opregion = igd_make_opregion(); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof (*gnvs)); acpi_create_gnvs(gnvs); @@ -678,6 +679,8 @@ static void southbridge_inject_dsdt(void) gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); /* IGD OpRegion Base Address */ gnvs->aslb = (u32)opregion; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d83ec0a..74e7b0c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -38,6 +38,7 @@ #include "pch.h" #include <arch/acpigen.h> #include <cbmem.h> +#include <drivers/intel/gma/i915.h> #define NMI_OFF 0 @@ -755,6 +756,8 @@ static void southbridge_inject_dsdt(void) } if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + acpi_create_gnvs(gnvs); gnvs->apic = 1; @@ -768,6 +771,9 @@ static void southbridge_inject_dsdt(void) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index dcf9e33..176e562 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -29,6 +29,7 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <string.h> +#include <drivers/intel/gma/i915.h> #include "nvs.h" #include "chip.h" @@ -193,8 +194,13 @@ static void southbridge_inject_dsdt(void) global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); if (gnvs) { + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); + + gnvs->ndid = gfx->ndid; + memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); + /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL);

1 0

Patch set updated for coreboot: f0cc427 bd82x6x: Merge common platform ASL code.
by Vladimir Serbinenko 19 May '15

19 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10231 -gerrit commit f0cc4275e5e11a4a53a2da1c0dbf338868a9d5a6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun May 17 00:20:52 2015 +0200 bd82x6x: Merge common platform ASL code. This code in reality just describes the southbridge features, don't put a copy in every mainboard. Change-Id: I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 38 ------------------- src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 2 + .../gigabyte/ga-b75m-d3v/acpi/platform.asl | 38 ------------------- src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl | 2 + src/mainboard/google/butterfly/acpi/platform.asl | 38 ------------------- src/mainboard/google/butterfly/dsdt.asl | 2 + src/mainboard/google/link/acpi/platform.asl | 38 ------------------- src/mainboard/google/link/dsdt.asl | 2 + src/mainboard/google/parrot/acpi/platform.asl | 38 ------------------- src/mainboard/google/parrot/dsdt.asl | 2 + src/mainboard/google/stout/acpi/platform.asl | 38 ------------------- src/mainboard/google/stout/dsdt.asl | 2 + .../intel/cougar_canyon2/acpi/platform.asl | 38 ------------------- src/mainboard/intel/cougar_canyon2/dsdt.asl | 2 + src/mainboard/intel/emeraldlake2/acpi/platform.asl | 38 ------------------- src/mainboard/intel/emeraldlake2/dsdt.asl | 2 + src/mainboard/kontron/ktqm77/acpi/platform.asl | 38 ------------------- src/mainboard/kontron/ktqm77/dsdt.asl | 2 + src/mainboard/lenovo/t420s/acpi/platform.asl | 38 ------------------- src/mainboard/lenovo/t420s/dsdt.asl | 2 + src/mainboard/lenovo/t430s/acpi/platform.asl | 38 ------------------- src/mainboard/lenovo/t430s/dsdt.asl | 2 + src/mainboard/lenovo/t520/acpi/platform.asl | 38 ------------------- src/mainboard/lenovo/t520/dsdt.asl | 2 + src/mainboard/lenovo/t530/acpi/platform.asl | 38 ------------------- src/mainboard/lenovo/t530/dsdt.asl | 2 + src/mainboard/lenovo/x220/acpi/platform.asl | 38 ------------------- src/mainboard/lenovo/x220/dsdt.asl | 2 + src/mainboard/lenovo/x230/acpi/platform.asl | 38 ------------------- src/mainboard/lenovo/x230/dsdt.asl | 2 + src/mainboard/samsung/lumpy/acpi/platform.asl | 38 ------------------- src/mainboard/samsung/lumpy/dsdt.asl | 2 + src/mainboard/samsung/stumpy/acpi/platform.asl | 38 ------------------- src/mainboard/samsung/stumpy/dsdt.asl | 2 + src/southbridge/intel/bd82x6x/acpi/platform.asl | 44 ++++++++++++++++++++++ 35 files changed, 78 insertions(+), 646 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl index 1448aeb..ae676c5 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 84a889a..e79d611 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -7,6 +7,8 @@ DefinitionBlock( 0x20141018 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" #include <cpu/intel/model_206ax/acpi/cpu.asl> diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl index 3f63b8e..22f2c59 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl index 84a889a..e79d611 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl @@ -7,6 +7,8 @@ DefinitionBlock( 0x20141018 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" #include <cpu/intel/model_206ax/acpi/cpu.asl> diff --git a/src/mainboard/google/butterfly/acpi/platform.asl b/src/mainboard/google/butterfly/acpi/platform.asl index 7c75f30..0840be6 100644 --- a/src/mainboard/google/butterfly/acpi/platform.asl +++ b/src/mainboard/google/butterfly/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 7aa633c..265d494 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl index b59097b..5522ddd 100644 --- a/src/mainboard/google/link/acpi/platform.asl +++ b/src/mainboard/google/link/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index b4fbda7..eeb96dc 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/parrot/acpi/platform.asl b/src/mainboard/google/parrot/acpi/platform.asl index fb2b76d..82b23bf 100644 --- a/src/mainboard/google/parrot/acpi/platform.asl +++ b/src/mainboard/google/parrot/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 7aa633c..265d494 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/google/stout/acpi/platform.asl b/src/mainboard/google/stout/acpi/platform.asl index 83ed228..30e7fb8 100644 --- a/src/mainboard/google/stout/acpi/platform.asl +++ b/src/mainboard/google/stout/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 925dfd1..052bec1 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/cougar_canyon2/acpi/platform.asl b/src/mainboard/intel/cougar_canyon2/acpi/platform.asl index 136cc3c..5c5591f 100644 --- a/src/mainboard/intel/cougar_canyon2/acpi/platform.asl +++ b/src/mainboard/intel/cougar_canyon2/acpi/platform.asl @@ -18,44 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/intel/cougar_canyon2/dsdt.asl b/src/mainboard/intel/cougar_canyon2/dsdt.asl index cedb8a8..5e68247 100644 --- a/src/mainboard/intel/cougar_canyon2/dsdt.asl +++ b/src/mainboard/intel/cougar_canyon2/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/intel/emeraldlake2/acpi/platform.asl b/src/mainboard/intel/emeraldlake2/acpi/platform.asl index 5f605f0..009b682 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/platform.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/platform.asl @@ -18,44 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index cbac763..118c76f 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/kontron/ktqm77/acpi/platform.asl b/src/mainboard/kontron/ktqm77/acpi/platform.asl index ff6d94d..fe901c7 100644 --- a/src/mainboard/kontron/ktqm77/acpi/platform.asl +++ b/src/mainboard/kontron/ktqm77/acpi/platform.asl @@ -18,44 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index 3af7a0e..c39cbe0 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl index c59e26a..07a7d0c 100644 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ b/src/mainboard/lenovo/t420s/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index acd03d0..b6eaade 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -35,6 +35,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl index c59e26a..07a7d0c 100644 --- a/src/mainboard/lenovo/t430s/acpi/platform.asl +++ b/src/mainboard/lenovo/t430s/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index acd03d0..b6eaade 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -35,6 +35,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl index c59e26a..07a7d0c 100644 --- a/src/mainboard/lenovo/t520/acpi/platform.asl +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index e98afe0..6c0a98c 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -34,6 +34,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index 3ce4a5e..7bb8919 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index e98afe0..6c0a98c 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -34,6 +34,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index 3ce4a5e..7bb8919 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index e98afe0..6c0a98c 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -34,6 +34,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl index 3ce4a5e..7bb8919 100644 --- a/src/mainboard/lenovo/x230/acpi/platform.asl +++ b/src/mainboard/lenovo/x230/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index e98afe0..6c0a98c 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -34,6 +34,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/samsung/lumpy/acpi/platform.asl b/src/mainboard/samsung/lumpy/acpi/platform.asl index 1965843..390a8d7 100644 --- a/src/mainboard/samsung/lumpy/acpi/platform.asl +++ b/src/mainboard/samsung/lumpy/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index 06d2995..0b06800 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" diff --git a/src/mainboard/samsung/stumpy/acpi/platform.asl b/src/mainboard/samsung/stumpy/acpi/platform.asl index 1887509..535065f 100644 --- a/src/mainboard/samsung/stumpy/acpi/platform.asl +++ b/src/mainboard/samsung/stumpy/acpi/platform.asl @@ -17,44 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 7aa633c..265d494 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -27,6 +27,8 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + // Some generic macros #include "acpi/platform.asl" #include "acpi/mainboard.asl" diff --git a/src/southbridge/intel/bd82x6x/acpi/platform.asl b/src/southbridge/intel/bd82x6x/acpi/platform.asl new file mode 100644 index 0000000..0dc5b4d --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/platform.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +}

1 0

Patch set updated for coreboot: 31201d4 autoport: Experimental stuff
by Vladimir Serbinenko 19 May '15

19 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7131 -gerrit commit 31201d41374de037b2a87a51f47bd2994b657bb6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 15 21:51:47 2014 +0200 autoport: Experimental stuff Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/autoport/azalia.go | 62 ++++ util/autoport/bd82x6x.go | 365 +++++++++++++++++++++++ util/autoport/i82801gx.go | 531 ++++++++++++++++++++++++++++++++++ util/autoport/i945.go | 120 ++++++++ util/autoport/log_maker.go | 85 ++++++ util/autoport/log_reader.go | 314 ++++++++++++++++++++ util/autoport/main.go | 673 +++++++++++++++++++++++++++++++++++++++++++ util/autoport/rce823.go | 39 +++ util/autoport/root.go | 29 ++ util/autoport/sandybridge.go | 114 ++++++++ 10 files changed, 2332 insertions(+) diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go new file mode 100644 index 0000000..f9be1b1 --- /dev/null +++ b/util/autoport/azalia.go @@ -0,0 +1,62 @@ +package main + +import ( + "fmt" + "sort" +) + +type azalia struct { +} + +func (i azalia) Scan(ctx Context, addr PCIDevData) { + az := Create(ctx, "hda_verb.c") + defer az.Close() + + az.WriteString( + `#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +`) + + for _, codec := range ctx.InfoSource.GetAzaliaCodecs() { + fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n", + codec.VendorID, codec.Name) + fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n", + codec.SubsystemID) + fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n", + len(codec.PinConfig)+1) + fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n") + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + codec.CodecNo, codec.SubsystemID) + + keys := []int{} + for nid, _ := range codec.PinConfig { + keys = append(keys, nid) + } + + sort.Ints(keys) + + for _, nid := range keys { + fmt.Fprintf(az, "\n\t/* NID 0x%02x. */\n", nid) + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + codec.CodecNo, nid, codec.PinConfig[nid]) + } + } + + az.WriteString( + `}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; +`) + + PutPCIDev(addr, "Audio controller") +} + +func init() { + /* I82801GX/I945 */ + RegisterPCI(0x8086, 0x27d8, azalia{}) + /* C216/ivybridge */ + RegisterPCI(0x8086, 0x1e20, azalia{}) +} diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go new file mode 100644 index 0000000..7e38375 --- /dev/null +++ b/util/autoport/bd82x6x.go @@ -0,0 +1,365 @@ +package main + +import ( + "fmt" + "os" +) + +type bd82x6x struct { + variant string +} + +func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } +} + +func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + gpio.WriteString(`#include "southbridge/intel/bd82x6x/gpio.h" +`) + + adresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := adresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`static const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func ich9GetFlashSize(ctx Context) { + inteltool := ctx.InfoSource.GetInteltool() + switch (inteltool.RCBA[0x3410] >> 10) & 3 { + /* SPI. All boards I've seen with sandy/ivy use SPI. */ + case 3: + ROMProtocol = "SPI" + highflkb := uint32(0) + for reg := uint16(0); reg < 5; reg++ { + fl := (inteltool.RCBA[0x3854 + 4 * reg] >> 16) & 0x1fff + flkb := fl << 2 + if flkb > highflkb { + highflkb = flkb + } + } + ROMSizeKB = int(highflkb) + /* Shared with ME. Flashrom is unable to handle it. */ + FlashROMSupport = "n" + } +} + +func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + KconfigComment["SERIRQ_CONTINUOUS_MODE"] = "FIXME: check this" + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" + + /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. + But most systems don't have any of those. But the config needs to be set + nevertheless. So set it to southbridge subsys/subvendor. */ + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) + + ich9GetFlashSize(ctx) + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + pcieHotplugMap := "{ " + + for port := 0; port < 7; port++ { + if b.IsPCIeHotplug(ctx, port) { + pcieHotplugMap += "1, " + } else { + pcieHotplugMap += "0, " + } + } + + if b.IsPCIeHotplug(ctx, 7) { + pcieHotplugMap += "1 }" + } else { + pcieHotplugMap += "0 }" + } + + cur := DevTreeNode{ + Chip: "southbridge/intel/bd82x6x", + Comment: "Intel Series 6 Cougar Point PCH, FIXME: set gpiX_routing and alt_gp_smi_en for EC support", + + Registers: map[string]string{ + "sata_interface_speed_support": "0x3", + "gen1_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + "pcie_port_coalesce": "1", + "pcie_hotplug_map": pcieHotplugMap, + + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c2_latency": FormatHexLE16(FADT[96:98]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}] + + if ok { + cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8]) + cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0]) + cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4]) + } + + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMStageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ +`) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI32Simple(sb, addr, 0x84) + RestorePCI32Simple(sb, addr, 0x88) + RestorePCI32Simple(sb, addr, 0x8c) + RestorePCI32Simple(sb, addr, 0x90) + + RestorePCI16Simple(sb, addr, 0x80) + + RestorePCI32Simple(sb, addr, 0xac) + + sb.WriteString(`} + +void rcba_config(void) +{ + /* Disable devices. */ +`) + RestoreRCBA32(sb, inteltool, 0x3414) + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString("\n}\n") + + sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") + + currentMap := map[uint32]int{ + 0x20000153: 0, + 0x20000f57: 1, + 0x2000055b: 2, + 0x20000f51: 3, + 0x2000094a: 4, + } + + for port := uint(0); port < 14; port++ { + var pinmask uint32 + OCPin := -1 + if port < 8 { + pinmask = inteltool.RCBA[0x35a0] + } else { + pinmask = inteltool.RCBA[0x35a4] + } + for pin := uint(0); pin < 4; pin++ { + if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 { + OCPin = int(pin) + if port >= 8 { + OCPin += 4 + } + } + } + fmt.Fprintf(sb, "\t{ %d, %d, %d },\n", + ((inteltool.RCBA[0x359c]>>port)&1)^1, + currentMap[inteltool.RCBA[uint16(0x3500+4*port)]], + OCPin) + } + sb.WriteString("};\n") + + sb.WriteString(` +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} +`) + + gnvs := Create(ctx, "gnvs.c") + defer gnvs.Close() + + gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} +`) + + AddRAMStageFile("gnvs.c", "") +} + +func init() { + RegisterPCI(0x8086, 0x1e49, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e55, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e56, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e57, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e5c, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e5d, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e5e, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e5f, bd82x6x{variant: "C216"}) + RegisterPCI(0x8086, 0x1e31, GenericPCI{}) + RegisterPCI(0x8086, 0x1e26, GenericPCI{}) + RegisterPCI(0x8086, 0x1e2d, GenericPCI{}) + RegisterPCI(0x8086, 0x1e3a, GenericPCI{}) + RegisterPCI(0x8086, 0x1502, GenericPCI{}) + RegisterPCI(0x8086, 0x1e10, GenericPCI{}) + RegisterPCI(0x8086, 0x1e12, GenericPCI{}) + RegisterPCI(0x8086, 0x1e14, GenericPCI{}) + RegisterPCI(0x8086, 0x1e16, GenericPCI{}) + RegisterPCI(0x8086, 0x1e18, GenericPCI{}) + RegisterPCI(0x8086, 0x1e1a, GenericPCI{}) + RegisterPCI(0x8086, 0x1e1c, GenericPCI{}) + RegisterPCI(0x8086, 0x1e1e, GenericPCI{}) + RegisterPCI(0x8086, 0x1e03, GenericPCI{}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/i82801gx.go b/util/autoport/i82801gx.go new file mode 100644 index 0000000..4ffeb6a --- /dev/null +++ b/util/autoport/i82801gx.go @@ -0,0 +1,531 @@ +package main + +import ( + "fmt" + "os" +) + +type i82801gx struct { +} + +func (i i82801gx) writeGPIO(ctx Context, sb *os.File, inteltool InteltoolData, addr uint16, name string) { + fmt.Fprintf(sb, " outl(0x%08x, DEFAULT_GPIOBASE + %s);\n", + inteltool.GPIO[addr], name) +} + +func (i i82801gx) Scan(ctx Context, addr PCIDevData) { + + KconfigBool["HAVE_MP_TABLE"] = true + KconfigBool["SOUTHBRIDGE_INTEL_I82801GX"] = true + + sb := Create(ctx, "early_southbridge.c") + defer sb.Close() + AddROMStageFile("early_southbridge.c", "") + sb.WriteString(`#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} + +void setup_ich7_gpios(void) +{ + printk(BIOS_DEBUG, " GPIOS..."); + +`) + inteltool := ctx.InfoSource.GetInteltool() + i.writeGPIO(ctx, sb, inteltool, 0x0, "GPIO_USE_SEL") + i.writeGPIO(ctx, sb, inteltool, 0x4, "GP_IO_SEL") + i.writeGPIO(ctx, sb, inteltool, 0xc, "GP_LVL") + i.writeGPIO(ctx, sb, inteltool, 0x18, "GPO_BLINK") + i.writeGPIO(ctx, sb, inteltool, 0x2c, "GPI_INV") + i.writeGPIO(ctx, sb, inteltool, 0x30, "GPIO_USE_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x34, "GP_IO_SEL2") + i.writeGPIO(ctx, sb, inteltool, 0x38, "GP_LVL2") + + sb.WriteString(`} + +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + + // Enable address decodes +`) + + RestorePCI16Simple(sb, addr, 0x80) + RestorePCI16Simple(sb, addr, 0x82) + RestorePCI16Simple(sb, addr, 0x84) + RestorePCI16Simple(sb, addr, 0x86) + RestorePCI16Simple(sb, addr, 0x88) + RestorePCI16Simple(sb, addr, 0x8a) + RestorePCI16Simple(sb, addr, 0x8c) + RestorePCI16Simple(sb, addr, 0x8e) + RestorePCI16Simple(sb, addr, 0x90) + RestorePCI16Simple(sb, addr, 0x92) + + /* Just use the same interrupt map for all boards: just registers have to match ACPI. */ + sb.WriteString(`} + +void rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + /* V1CAP Virtual Channel 1 Resource Capability */ + RCBA32(0x001c) = 0x03128010; + + /* Disable devices. */ +`) + + RestoreRCBA32(sb, inteltool, 0x3418) + + sb.WriteString(` + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} +`) + + /* FIXME:XX does this one need adjustments? */ + sb.WriteString(`void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +`) + + ioapic := DevTreeNode{ + Chip: "drivers/generic/ioapic", + Registers: map[string]string{ + /* FIXME:XX hardcoded. */ + "have_isa_interrupts": "1", + "irq_on_fsb": "1", + "enable_virtual_wire": "0", + "base": "0xfec00000", + }, + Children: []DevTreeNode{ + { + Chip: "ioapic", + Dev: 2, + }, + }, + } + + PutPCIChip(addr, ioapic) + + ideConfig := uint8(0) + ide, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 1}] + if ok { + ideConfig = ide.ConfigDump[0x54] + } + + FADT := ctx.InfoSource.GetACPI()["FACP"] + + cur := DevTreeNode{ + Chip: "southbridge/intel/i82801gx", + Comment: "Southbridge, FIXME: set gpiX_routing, gpe0_en and alt_gp_smi_en for EC support", + MissingParent: "southbridge", + Registers: map[string]string{ + /* FIXME:XX should be a CMOS config */ + "sata_ahci": "0x1", + + "sata_ports_implemented": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0xf), + "ide_enable_primary": fmt.Sprintf("%d", (ideConfig>>1)&1), + "ide_enable_secondary": fmt.Sprintf("%d", (ideConfig>>3)&1), + "c4onc3_enable": fmt.Sprintf("%d", ((addr.ConfigDump[0xa0] >> 7) & 1)), + "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), + "c3_latency": FormatHexLE16(FADT[98:100]), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 1}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 2}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 3}, writeEmpty: true, additionalComment: "USB UHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 7}, writeEmpty: true, additionalComment: "USB EHCI"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 1}, writeEmpty: true, additionalComment: "IDE Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + }, + } + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x00}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x07}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1b}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1c}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x11, 0x10, 0x12, 0x13}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1d}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x17, 0x13, 0x12, 0x10}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1e}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0x14, 0, 0}} + IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1f}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x12, 0x13, 0, 0x10}} + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/i82801gx/acpi/ich7.asl", + }) + + ai := Create(ctx, "acpi/ich7_pci_irqs.asl") + defer ai.Close() + + /* FIXME:XX hardcoded. */ + ai.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} +`) + + ec := Create(ctx, "acpi/ec.asl") + defer ec.Close() + ec.WriteString("/* FIXME: Add EC support here. */") + + at := Create(ctx, "acpi_tables.c") + defer at.Close() + + at.WriteString( + `#include <stdint.h> +#include "southbridge/intel/i82801gx/nvs.h" + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; +} +`) + + si := Create(ctx, "acpi/superio.asl") + defer si.Close() + si.WriteString("/* FIXME: Add superio support here. */") + + ap := Create(ctx, "acpi/platform.asl") + defer ap.Close() + + /* FIXME:XX hardcoded. */ + ap.WriteString( + `Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Scope(\_SB) +{ + Method(_INI, 0) + { + \GOS() + } +} +`) + + + + sh := Create(ctx, "smihandler.c") + defer sh.Close() + + /* FIXME:XX hardcoded. */ + sh.WriteString( + ` +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include <pc80/mc146818rtc.h> +#include <delay.h> + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* FIXME: Add EC support here */ + break; + case APM_CNT_ACPI_DISABLE: + /* FIXME: Add EC support here */ + break; + default: + break; + } + return 0; +} +`) + mb := Create(ctx, "mainboard.c") + defer mb.Close() + + /* FIXME:XX hardcoded. */ + mb.WriteString( + `/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <northbridge/intel/i945/i945.h> +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <smbios.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_init(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, INT15_5F35_CL_DISPLAY_DEFAULT, 3); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; +`) + +} + +func init() { + RegisterPCI(0x8086, 0x27b9, i82801gx{}) + RegisterPCI(0x8086, 0x27c8, GenericPCI{}) + RegisterPCI(0x8086, 0x27c9, GenericPCI{}) + RegisterPCI(0x8086, 0x27ca, GenericPCI{}) + RegisterPCI(0x8086, 0x27cb, GenericPCI{}) + RegisterPCI(0x8086, 0x27cc, GenericPCI{}) + + RegisterPCI(0x8086, 0x27d0, GenericPCI{}) + RegisterPCI(0x8086, 0x27d2, GenericPCI{}) + RegisterPCI(0x8086, 0x27d4, GenericPCI{}) + RegisterPCI(0x8086, 0x27d6, GenericPCI{}) + + RegisterPCI(0x8086, 0x2448, GenericPCI{}) + + RegisterPCI(0x8086, 0x27c5, GenericPCI{}) + RegisterPCI(0x8086, 0x27c4, GenericPCI{}) + RegisterPCI(0x8086, 0x27df, GenericPCI{}) + RegisterPCI(0x8086, 0x27da, GenericPCI{MissingParent: "smbus"}) +} diff --git a/util/autoport/i945.go b/util/autoport/i945.go new file mode 100644 index 0000000..9a29002 --- /dev/null +++ b/util/autoport/i945.go @@ -0,0 +1,120 @@ +package main + +import ( + "log" + "strings" +) + +type i945mc struct { + variant string +} + +func (i i945mc) Scan(ctx Context, addr PCIDevData) { + + cpuModel := ctx.InfoSource.GetCPUModel()[0] + socket := "" + switch cpuModel >> 4 { + case 0x69, 0x6d, 0x6e, 0x6f: + socket = "mFCPGA478" + case 0x106c: + socket = "441" + default: + log.Fatalf("unsupported cpu: 0x%x", cpuModel) + } + DevTree = DevTreeNode{ + Chip: "northbridge/intel/i945", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME:XX hardcoded. */ + "gpu_hotplug": "0x00000220", + "gpu_lvds_use_spread_spectrum_clock": "1", + "gpu_lvds_is_dual_channel": "0", + "gpu_backlight": "0x1280128", + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_" + socket, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + }, + }, + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "VGA"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 1}, writeEmpty: true, additionalComment: "Display controller"}, + }, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME:XX Move part to northbridge? */ + /* FIXME:XX some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool["VGA"] = true + KconfigBool["MAINBOARD_DO_EDID"] = true + KconfigBool["EARLY_CBMEM_INIT"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_"+strings.ToUpper(socket)] = true + KconfigBool["NORTHBRIDGE_INTEL_I945"] = true + KconfigBool["CHANNEL_XOR_RANDOMIZATION"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigHex["DCACHE_RAM_BASE"] = 0xffdf8000 + KconfigHex["DCACHE_RAM_SIZE"] = 0x8000 + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 2 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_6dx/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/i945/acpi/i945.asl", + }) + + KconfigBool["NORTHBRIDGE_INTEL_SUBTYPE_" + i.variant] = true + + cs := Create(ctx, "cstates.c") + defer cs.Close() + AddRAMStageFile("cstates.c", "") + + cs.WriteString( + `#include <arch/acpigen.h> +#include <device/device.h> +#include <northbridge/intel/i945/i945.h> + +/* FIXME: fill this. */ +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} +`) +} + +func init() { + RegisterPCI(0x8086, 0x27a0, i945mc{variant:"I945GM"}) + RegisterPCI(0x8086, 0x27ac, i945mc{variant:"I945GM"}) + RegisterPCI(0x8086, 0x27a2, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, 0x27ae, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + RegisterPCI(0x8086, 0x27a6, GenericPCI{Comment: "display controller"}) +} diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go new file mode 100644 index 0000000..8db428d --- /dev/null +++ b/util/autoport/log_maker.go @@ -0,0 +1,85 @@ +package main + +import ( + "io" + "io/ioutil" + "log" + "os" + "os/exec" + "strings" +) + +func RunAndSave(output string, name string, arg ...string) { + cmd := exec.Command(name, arg...) + + f, err := os.Create(output) + if err != nil { + log.Fatal(err) + } + + cmd.Stdout = f + cmd.Stderr = f + + err = cmd.Start() + if err != nil { + log.Fatal(err) + } + cmd.Wait() +} + +func MakeLogs(outDir string) { + os.MkdirAll(outDir, 0700) + RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") + RunAndSave(outDir+"/dmidecode.log", "dmidecode") + RunAndSave(outDir+"/acpidump.log", "acpidump") + /* FIXME:XX */ + RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", "-a") + + SysDir := "/sys/class/sound/card0/" + files, _ := ioutil.ReadDir(SysDir) + for _, f := range files { + if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() { + in, err := os.Open(SysDir + f.Name() + "/init_pin_configs") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1)) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + ProcDir := "/proc/asound/card0/" + files, _ = ioutil.ReadDir(ProcDir) + for _, f := range files { + if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() { + in, err := os.Open(ProcDir + f.Name()) + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/" + f.Name()) + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) + } + } + + in, err := os.Open("/proc/cpuinfo") + defer in.Close() + if err != nil { + log.Fatal(err) + } + out, err := os.Create(outDir + "/cpuinfo.log") + if err != nil { + log.Fatal(err) + } + defer out.Close() + io.Copy(out, in) +} diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go new file mode 100644 index 0000000..a17a6e9 --- /dev/null +++ b/util/autoport/log_reader.go @@ -0,0 +1,314 @@ +package main + +import ( + "bufio" + "flag" + "fmt" + "log" + "os" + "strconv" + "strings" +) + +type LogDevReader struct { + InputDirectory string + ACPITables map[string][]byte +} + +func isXDigit(x uint8) bool { + if x >= '0' && x <= '9' { + return true + } + if x >= 'a' && x <= 'f' { + return true + } + if x >= 'A' && x <= 'F' { + return true + } + return false +} + +type HexLine struct { + length uint + values [16]byte + start uint +} + +func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) { + hex.start = 0 + line = strings.Trim(line, " ") + fmt.Sscanf(line, "%x:", &hex.start) + ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start, + &hex.values[0], &hex.values[1], &hex.values[2], + &hex.values[3], &hex.values[4], &hex.values[5], + &hex.values[6], &hex.values[7], &hex.values[8], + &hex.values[9], &hex.values[10], &hex.values[11], + &hex.values[12], &hex.values[13], &hex.values[14], + &hex.values[15]) + hex.length = uint(ll - 1) + return +} + +func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte { + hex := l.ReadHexLine(inp) + if hex.start+hex.length > uint(len(target)) { + target = target[0 : hex.start+hex.length] + } + copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length]) + return target +} + +func (l *LogDevReader) GetACPI() (Tables map[string][]byte) { + if l.ACPITables != nil { + return l.ACPITables + } + l.ACPITables = Tables + + file, err := os.Open(l.InputDirectory + "/acpidump.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + Tables = map[string][]byte{} + + curTable := "" + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) >= 6 && line[5] == '@': + curTable = line[0:4] + Tables[curTable] = make([]byte, 0, 100000) + case len(line) > 7 && line[0:2] == " " && isXDigit(line[2]) && isXDigit(line[3]) && isXDigit(line[4]) && isXDigit(line[5]) && line[6] == ':': + Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) { + file, err := os.Open(l.InputDirectory + "/lspci.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + + PCIList = []PCIDevData{} + + for scanner.Scan() { + line := scanner.Text() + switch { + case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])): + cur := PCIDevData{} + fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func) + lc := strings.LastIndex(line, ":") + li := strings.LastIndex(line[0:lc], "[") + if li < 0 { + continue + } + ven := 0 + dev := 0 + fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev) + cur.PCIDevID = uint16(dev) + cur.PCIVenID = uint16(ven) + cur.ConfigDump = make([]byte, 0x100, 0x1000) + PCIList = append(PCIList, cur) + case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':': + start := 0 + fmt.Sscanf(line, "%x:", &start) + cur := &PCIList[len(PCIList)-1] + cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + + return +} + +func (l *LogDevReader) GetInteltool() (ret InteltoolData) { + file, err := os.Open(l.InputDirectory + "/inteltool.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + ret.GPIO = map[uint16]uint32{} + ret.RCBA = map[uint16]uint32{} + for scanner.Scan() { + line := scanner.Text() + switch { + case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA": + addr, value := 0, 0 + fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value) + ret.RCBA[uint16(addr)] = uint32(value) + case strings.Contains(line, "DEFAULT"): + continue + case strings.Contains(line, "DIFF"): + continue + case strings.HasPrefix(line, "gpiobase"): + addr, value := 0, 0 + fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value) + ret.GPIO[uint16(addr)] = uint32(value) + case strings.HasPrefix(line, "============="): + paragraph = strings.Trim(line, "= ") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetDMI() (ret DMIData) { + file, err := os.Open(l.InputDirectory + "/dmidecode.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + paragraph := "" + for scanner.Scan() { + line := scanner.Text() + if !strings.HasPrefix(line, "\t") { + paragraph = strings.TrimSpace(line) + continue + } + idx := strings.Index(line, ":") + if idx < 0 { + continue + } + name := strings.TrimSpace(line[0:idx]) + value := strings.TrimSpace(line[idx+1:]) + switch paragraph + ":" + name { + case "System Information:Manufacturer": + ret.Vendor = value + case "System Information:Product Name": + ret.Model = value + case "System Information:Version": + ret.Version = value + case "Chassis Information:Type": + ret.IsLaptop = (value == "Notebook" || value == "Laptop") + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +func (l *LogDevReader) GetAzaliaCodecs() (ret []AzaliaCodec) { + for codecno := 0; codecno < 10; codecno++ { + cur := AzaliaCodec{CodecNo: codecno, PinConfig: map[int]uint32{}} + codec, err := os.Open(l.InputDirectory + "/codec#" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer codec.Close() + pin, err := os.Open(l.InputDirectory + "/pin_hwC0D" + strconv.Itoa(codecno)) + if err != nil { + continue + } + defer pin.Close() + + scanner := bufio.NewScanner(codec) + for scanner.Scan() { + line := scanner.Text() + if strings.HasPrefix(line, "Codec:") { + fmt.Sscanf(line, "Codec: %s", &cur.Name) + continue + } + if strings.HasPrefix(line, "Vendor Id:") { + fmt.Sscanf(line, "Vendor Id: 0x%x", &cur.VendorID) + continue + } + if strings.HasPrefix(line, "Subsystem Id:") { + fmt.Sscanf(line, "Subsystem Id: 0x%x", &cur.SubsystemID) + continue + } + } + + scanner = bufio.NewScanner(pin) + for scanner.Scan() { + line := scanner.Text() + addr := 0 + val := uint32(0) + fmt.Sscanf(line, "0x%x 0x%x", &addr, &val) + cur.PinConfig[addr] = val + } + ret = append(ret, cur) + } + return +} + +func (l *LogDevReader) GetCPUModel() (ret []uint32) { + file, err := os.Open(l.InputDirectory + "/cpuinfo.log") + if err != nil { + log.Fatal(err) + } + defer file.Close() + + scanner := bufio.NewScanner(file) + ret = make([]uint32, 0, 100) + proc := 0 + for scanner.Scan() { + line := scanner.Text() + sep := strings.Index(line, ":") + if sep < 0 { + continue + } + key := strings.TrimSpace(line[0:sep]) + val := strings.TrimSpace(line[sep+1:]) + + if key == "processor" { + proc, _ := strconv.Atoi(val) + if len(ret) <= proc { + ret = ret[0 : proc+1] + } + continue + } + if key == "cpu family" { + family, _ := strconv.Atoi(val) + ret[proc] |= uint32(((family & 0xf) << 8) | ((family & 0xff0) << 16)) + } + if key == "model" { + model, _ := strconv.Atoi(val) + ret[proc] |= uint32(((model & 0xf) << 4) | ((model & 0xf0) << 12)) + } + if key == "stepping" { + stepping, _ := strconv.Atoi(val) + ret[proc] |= uint32(stepping & 0xf) + } + } + + if err := scanner.Err(); err != nil { + log.Fatal(err) + } + return +} + +var FlagLogInput = flag.String("input_log", ".", "Input log directory") +var FlagLogMkLogs = flag.Bool("make_logs", false, "Dump logs") + +func MakeLogReader() *LogDevReader { + if *FlagLogMkLogs { + MakeLogs(*FlagLogInput) + } + return &LogDevReader{InputDirectory: *FlagLogInput} +} diff --git a/util/autoport/main.go b/util/autoport/main.go new file mode 100644 index 0000000..bad1982 --- /dev/null +++ b/util/autoport/main.go @@ -0,0 +1,673 @@ +/* This is just an experiment. Full automatic porting + is probably not possible but a lot can be automated. */ +package main + +import ( + "flag" + "fmt" + "log" + "os" + "sort" + "strings" +) + +type PCIAddr struct { + Bus int + Dev int + Func int +} + +type PCIDevData struct { + PCIAddr + PCIVenID uint16 + PCIDevID uint16 + ConfigDump []uint8 +} + +type PCIDevice interface { + Scan(ctx Context, addr PCIDevData) +} + +type InteltoolData struct { + GPIO map[uint16]uint32 + RCBA map[uint16]uint32 +} + +type DMIData struct { + Vendor string + Model string + Version string + IsLaptop bool +} + +type AzaliaCodec struct { + Name string + VendorID uint32 + SubsystemID uint32 + CodecNo int + PinConfig map[int]uint32 +} + +type DevReader interface { + GetPCIList() []PCIDevData + GetDMI() DMIData + GetInteltool() InteltoolData + GetAzaliaCodecs() []AzaliaCodec + GetACPI() map[string][]byte + GetCPUModel() []uint32 +} + +var ROMStageFiles map[string]string = map[string]string{} +var RAMStageFiles map[string]string = map[string]string{} + +type Context struct { + MoboID string + KconfigName string + Vendor string + Model string + BaseDirectory string + InfoSource DevReader +} + +type IOAPICIRQ struct { + APICID int + IRQNO [4]int +} + +var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{} +var KconfigBool map[string]bool = map[string]bool{} +var KconfigComment map[string]string = map[string]string{} +var KconfigString map[string]string = map[string]string{} +var KconfigStringUnquoted map[string]string = map[string]string{} +var KconfigHex map[string]uint32 = map[string]uint32{} +var KconfigInt map[string]int = map[string]int{} +var ROMSizeKB = 0 +var ROMProtocol = "" +var FlashROMSupport = "" + +func GetLE16(inp []byte) uint16 { + return uint16(inp[0])|(uint16(inp[1])<<8) +} + +func FormatHexLE16(inp []byte) string { + return fmt.Sprintf("0x%04x", GetLE16(inp)) +} + +func FormatHexLE32(d []uint8) string { + u := uint32(d[0]) | (uint32(d[1]) << 8) | (uint32(d[2]) << 16) | (uint32(d[3]) << 24) + return fmt.Sprintf("0x%08x", u) +} + +func FormatBool(inp bool) string { + if inp { + return "1" + } else { + return "0" + } +} + +func sanitize(inp string) string { + result := strings.ToLower(inp) + result = strings.Replace(result, " ", "_", -1) + result = strings.Replace(result, ",", "_", -1) + for strings.HasSuffix(result, ".") { + result = result[0 : len(result)-1] + } + return result +} + +func AddROMStageFile(Name string, Condition string) { + ROMStageFiles[Name] = Condition +} + +func AddRAMStageFile(Name string, Condition string) { + RAMStageFiles[Name] = Condition +} + +var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory") + +func writeMF(mf *os.File, files map[string]string, category string) { + for file, condition := range files { + if condition == "" { + fmt.Fprintf(mf, "%s-y += %s\n", category, file) + } else { + fmt.Fprintf(mf, "%s-$(%s) += %s\n", category, + condition, file) + } + } +} + +func Create(ctx Context, name string) *os.File { + li := strings.LastIndex(name, "/") + if li > 0 { + os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700) + } + mf, err := os.Create(ctx.BaseDirectory + "/" + name) + if err != nil { + log.Fatal(err) + } + return mf +} + +func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { + fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", + pcidev.Bus, pcidev.Dev, pcidev.Func, addr, + pcidev.ConfigDump[addr+3], + pcidev.ConfigDump[addr+2], + pcidev.ConfigDump[addr+1], + pcidev.ConfigDump[addr]) +} + +func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) { + fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr]) +} + +type PCISlot struct { + PCIAddr + additionalComment string + writeEmpty bool +} + +type DevTreeNode struct { + Bus int + Dev int + Func int + Disabled bool + Registers map[string]string + Children []DevTreeNode + PCISlots []PCISlot + PCIController bool + ChildPCIBus int + MissingParent string + SubVendor uint16 + SubSystem uint16 + Chip string + Comment string +} + +var DevTree DevTreeNode +var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{} +var unmatchedPCIChips map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} +var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{} + +func Offset(dt *os.File, offset int) { + for i := 0; i < offset; i++ { + fmt.Fprintf(dt, "\t") + } +} + +func MatchDev(dev *DevTreeNode) { + for idx := range dev.Children { + MatchDev(&dev.Children[idx]) + } + + for _, slot := range dev.PCISlots { + slotChip, ok := unmatchedPCIChips[slot.PCIAddr] + + if !ok { + continue + } + + if slot.additionalComment != "" && slotChip.Comment != "" { + slotChip.Comment = slot.additionalComment + " " + slotChip.Comment + } else { + slotChip.Comment = slot.additionalComment + slotChip.Comment + } + + delete(unmatchedPCIChips, slot.PCIAddr) + MatchDev(&slotChip) + dev.Children = append(dev.Children, slotChip) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIChips { + if slot.Bus == dev.ChildPCIBus { + delete(unmatchedPCIChips, slot) + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + } + } + } + + for _, slot := range dev.PCISlots { + slotDev, ok := unmatchedPCIDevices[slot.PCIAddr] + if !ok { + if slot.writeEmpty { + dev.Children = append(dev.Children, + DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: slot.Bus, + Dev: slot.Dev, + Func: slot.Func, + Comment: slot.additionalComment, + Disabled: true, + }, + ) + } + continue + } + + if slot.additionalComment != "" && slotDev.Comment != "" { + slotDev.Comment = slot.additionalComment + " " + slotDev.Comment + } else { + slotDev.Comment = slot.additionalComment + slotDev.Comment + } + + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot.PCIAddr) + } + + if dev.MissingParent != "" { + for _, child := range MissingChildren[dev.MissingParent] { + MatchDev(&child) + dev.Children = append(dev.Children, child) + } + delete(MissingChildren, dev.MissingParent) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIDevices { + if slot.Bus == dev.ChildPCIBus { + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + delete(unmatchedPCIDevices, slot) + } + } + } +} + +func writeOn(dt *os.File, dev DevTreeNode) { + if dev.Disabled { + fmt.Fprintf(dt, "off") + } else { + fmt.Fprintf(dt, "on") + } +} + +func WriteDev(dt *os.File, offset int, dev DevTreeNode) { + Offset(dt, offset) + switch dev.Chip { + case "cpu_cluster", "lapic", "domain", "ioapic": + fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev) + writeOn(dt, dev) + case "pci": + fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + writeOn(dt, dev) + default: + fmt.Fprintf(dt, "chip %s", dev.Chip) + } + if dev.Comment != "" { + fmt.Fprintf(dt, " # %s", dev.Comment) + } + fmt.Fprintf(dt, "\n") + if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem) + } + + ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}] + if dev.Chip == "pci" && ok { + for pin, irq := range ioapic.IRQNO { + if irq != 0 { + Offset(dt, offset+1) + fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq) + } + } + } + + keys := []string{} + for reg, _ := range dev.Registers { + keys = append(keys, reg) + } + + sort.Strings(keys) + + for _, reg := range keys { + val := dev.Registers[reg] + Offset(dt, offset+1) + fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val) + } + + for _, child := range dev.Children { + WriteDev(dt, offset+1, child) + } + + Offset(dt, offset) + fmt.Fprintf(dt, "end\n") +} + +func PutChip(domain string, cur DevTreeNode) { + MissingChildren[domain] = append(MissingChildren[domain], cur) +} + +func PutPCIChip(addr PCIDevData, cur DevTreeNode) { + unmatchedPCIChips[addr.PCIAddr] = cur +} + +func PutPCIDevParent(addr PCIDevData, comment string, parent string) { + cur := DevTreeNode{ + Registers: map[string]string{}, + Chip: "pci", + Bus: addr.Bus, + Dev: addr.Dev, + Func: addr.Func, + MissingParent: parent, + Comment: comment, + } + if addr.ConfigDump[0xa] == 0x04 && addr.ConfigDump[0xb] == 0x06 { + cur.PCIController = true + cur.ChildPCIBus = int(addr.ConfigDump[0x19]) + + loopCtr := 0 + for capPtr := addr.ConfigDump[0x34]; capPtr != 0; capPtr = addr.ConfigDump[capPtr + 1] { + /* Avoid hangs. There are only 0x100 different possible values for capPtr. + If we iterate longer than that, we're in endless loop. */ + loopCtr++ + if (loopCtr > 0x100) { + break + } + if addr.ConfigDump[capPtr] == 0x0d { + cur.SubVendor = GetLE16(addr.ConfigDump[capPtr+4:capPtr+6]) + cur.SubSystem = GetLE16(addr.ConfigDump[capPtr+6:capPtr+8]) + } + } + } else { + cur.SubVendor = GetLE16(addr.ConfigDump[0x2c:0x2e]) + cur.SubSystem = GetLE16(addr.ConfigDump[0x2e:0x30]) + } + unmatchedPCIDevices[addr.PCIAddr] = cur +} + +func PutPCIDev(addr PCIDevData, comment string) { + PutPCIDevParent(addr, comment, "") +} + +type GenericPCI struct { + Comment string + Bus0Subdiv string + MissingParent string +} + +type GenericVGA struct { + GenericPCI +} + +type DSDTInclude struct { + Comment string + File string +} + +var DSDTIncludes []DSDTInclude +var DSDTPCI0Includes []DSDTInclude + +func (g GenericPCI) Scan(ctx Context, addr PCIDevData) { + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { + KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x", + addr.PCIVenID, + addr.PCIDevID) + KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom", + addr.PCIVenID, + addr.PCIDevID) + PutPCIDevParent(addr, g.Comment, g.MissingParent) +} + +func makeKconfigName(ctx Context) { + kn := Create(ctx, "Kconfig.name") + defer kn.Close() + + fmt.Fprintf(kn, "config %s\n\tbool \"%s\"\n", ctx.KconfigName, ctx.Model) +} + +func makeComment(name string) string { + cmt, ok := KconfigComment[name] + if !ok { + return "" + } + return " # " + cmt +} + +func makeKconfig(ctx Context) { + kc := Create(ctx, "Kconfig") + defer kc.Close() + + fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName) + + fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS # dummy\n\tdef_bool y\n") + keys := []string{} + for name, val := range KconfigBool { + if val { + keys = append(keys, name) + } + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, "\tselect %s%s\n", name,makeComment(name)) + } + + keys = nil + for name, val := range KconfigBool { + if !val { + keys = append(keys, name) + } + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + bool + default n +`, name, makeComment(name)) + } + + keys = nil + for name, _ := range KconfigStringUnquoted { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + string + default %s +`, name, makeComment(name), KconfigStringUnquoted[name]) + } + + keys = nil + for name, _ := range KconfigString { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + string + default "%s" +`, name, makeComment(name), KconfigString[name]) + } + + keys = nil + for name, _ := range KconfigHex { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + hex + default 0x%x +`, name, makeComment(name), KconfigHex[name]) + } + + keys = nil + for name, _ := range KconfigInt { + keys = append(keys, name) + } + + sort.Strings(keys) + + for _, name := range keys { + fmt.Fprintf(kc, ` +config %s%s + int + default %d +`, name, makeComment(name), KconfigInt[name]) + } + + fmt.Fprintf(kc, "endif\n") +} + +func main() { + flag.Parse() + + ctx := Context{} + + ctx.InfoSource = MakeLogReader() + + dmi := ctx.InfoSource.GetDMI() + + ctx.Vendor = dmi.Vendor + + if dmi.Vendor == "LENOVO" { + ctx.Model = dmi.Version + } else { + ctx.Model = dmi.Model + } + + if dmi.IsLaptop { + KconfigBool["SYSTEM_TYPE_LAPTOP"] = true + } + ctx.MoboID = sanitize(ctx.Vendor) + "/" + sanitize(ctx.Model) + ctx.KconfigName = "BOARD_" + strings.ToUpper(sanitize(ctx.Vendor)+"_"+sanitize(ctx.Model)) + ctx.BaseDirectory = *FlagOutDir + "/src/mainboard/" + ctx.MoboID + KconfigStringUnquoted["MAINBOARD_DIR"] = ctx.MoboID + KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model + + os.MkdirAll(ctx.BaseDirectory, 0700) + + ScanRoot(ctx) + + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 { + mf := Create(ctx, "Makefile.inc") + defer mf.Close() + writeMF(mf, ROMStageFiles, "romstage") + writeMF(mf, RAMStageFiles, "ramstage") + } + + devtree := Create(ctx, "devicetree.cb") + defer devtree.Close() + + MatchDev(&DevTree) + WriteDev(devtree, 0, DevTree) + + bi := Create(ctx, "board_info.txt") + defer bi.Close() + + fixme := "" + + if dmi.IsLaptop { + bi.WriteString("Category: laptop\n") + } else { + bi.WriteString("Category: desktop\n") + fixme += "check category, " + } + + missing := "ROM package, ROM socketed" + + if ROMProtocol != "" { + fmt.Fprintf(bi, "ROM protocol: %s\n", ROMProtocol) + } else { + missing += ", ROM protocol" + } + + if FlashROMSupport != "" { + fmt.Fprintf(bi, "Flashrom support: %s\n", FlashROMSupport) + } else { + missing += ", Flashrom support" + } + + missing += ", Release year: 2012" + + if fixme != "" { + fmt.Fprintf(bi, "FIXME: %s, put %s\n", fixme, missing) + } else { + fmt.Fprintf(bi, "FIXME: put %s\n", missing) + } + + rs := Create(ctx, "romstage.c") + defer rs.Close() + rs.WriteString("/* dummy file */\n") + + if ROMSizeKB == 0 { + KconfigBool["BOARD_ROMSIZE_KB_2048"] = true + KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this" + } else { + KconfigBool[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = true + } + + makeKconfig(ctx) + makeKconfigName(ctx) + + dsdt := Create(ctx, "dsdt.asl") + defer dsdt.Close() + + dsdt.WriteString( + `DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" +`) + + for _, x := range DSDTIncludes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File) + } + + dsdt.WriteString(` + Scope (\_SB) { + Device (PCI0) + { +`) + for _, x := range DSDTPCI0Includes { + if x.Comment != "" { + fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment) + } + fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File) + } + dsdt.WriteString( + ` } + } +} +`) + +} diff --git a/util/autoport/rce823.go b/util/autoport/rce823.go new file mode 100644 index 0000000..7c92109 --- /dev/null +++ b/util/autoport/rce823.go @@ -0,0 +1,39 @@ +package main + +import "fmt" + +type rce823 struct { + variant string +} + +func (r rce823) Scan(ctx Context, addr PCIDevData) { + if addr.Dev == 0 && addr.Func == 0 { + cur := DevTreeNode{ + Chip: "drivers/ricoh/rce822", + Comment: "Ricoh cardreader", + Registers: map[string]string{ + + "sdwppol": fmt.Sprintf("%d", (addr.ConfigDump[0xfb]&2)>>1), + "disable_mask": fmt.Sprintf("0x%x", addr.ConfigDump[0xcb]), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 0}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 1}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 2}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 3}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 4}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 5}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 6}, writeEmpty: false}, + PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 7}, writeEmpty: false}, + }, + } + PutPCIChip(addr, cur) + } + PutPCIDev(addr, "Ricoh SD card reader") + KconfigBool["DRIVERS_RICOH_RCE822"] = true +} + +func init() { + RegisterPCI(0x1180, 0xe822, rce823{}) + RegisterPCI(0x1180, 0xe823, rce823{}) +} diff --git a/util/autoport/root.go b/util/autoport/root.go new file mode 100644 index 0000000..60b5ccd --- /dev/null +++ b/util/autoport/root.go @@ -0,0 +1,29 @@ +package main + +import "fmt" + +var supportedPCIDevices map[uint32]PCIDevice = map[uint32]PCIDevice{} +var PCIMap map[PCIAddr]PCIDevData = map[PCIAddr]PCIDevData{} + +func ScanRoot(ctx Context) { + for _, pciDev := range ctx.InfoSource.GetPCIList() { + PCIMap[pciDev.PCIAddr] = pciDev + } + for _, pciDev := range ctx.InfoSource.GetPCIList() { + vendevid := (uint32(pciDev.PCIDevID) << 16) | uint32(pciDev.PCIVenID) + + dev, ok := supportedPCIDevices[vendevid] + if !ok { + fmt.Printf("Unsupported PCI device %04x:%04x\n", + pciDev.PCIVenID, pciDev.PCIDevID) + dev = GenericPCI{Comment: fmt.Sprintf("Unsupported PCI device %04x:%04x", + pciDev.PCIVenID, pciDev.PCIDevID)} + } + dev.Scan(ctx, pciDev) + } +} + +func RegisterPCI(VenID uint16, DevID uint16, dev PCIDevice) { + vendevid := (uint32(DevID) << 16) | uint32(VenID) + supportedPCIDevices[vendevid] = dev +} diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go new file mode 100644 index 0000000..c19817a --- /dev/null +++ b/util/autoport/sandybridge.go @@ -0,0 +1,114 @@ +package main + +type sandybridgemc struct { + variant string +} + +func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { + DevTree = DevTreeNode{ + Chip: "northbridge/intel/sandybridge", + MissingParent: "northbridge", + Registers: map[string]string{ + /* FIXME:XX hardcoded. */ + "gpu_dp_d_hotplug": "0x06", + "gpu_panel_port_select": "0", + "gpu_panel_power_cycle_delay": "5", + "gpu_panel_power_up_delay": "300", + "gpu_panel_power_down_delay": "300", + "gpu_panel_power_backlight_on_delay": "2000", + "gpu_panel_power_backlight_off_delay": "2000", + "gfx.use_spread_spectrum_clock": "1", + "gfx.lvds_dual_channel": "0", + "gfx.link_frequency_270_mhz": "1", + "gfx.lvds_num_lanes": "4", + "gpu_cpu_backlight": "0x1155", + "gpu_pch_backlight": "0x06100610", + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/socket_rPGA989", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + }, + }, + + { + Chip: "cpu/intel/model_206ax", + Registers: map[string]string{ + /* FIXME:XX hardcoded. */ + "pstate_coord_type": "0xfe", + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + }, + }, + }, + } + PutPCIDev(addr, "Host bridge") + + /* FIXME:XX Move part to northbridge? */ + /* FIXME:XX some configs are unsupported. */ + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true + KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true + KconfigBool[i.variant+"BRIDGE_LVDS"] = true + + KconfigBool["VGA"] = true + KconfigBool["INTEL_EDID"] = true + KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true + KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE_NATIVE"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigBool["HAVE_IFD_BIN"] = false + KconfigBool["HAVE_ME_BIN"] = false + + KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/model_206ax/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"}) + RegisterPCI(0x8086, 0x0166, GenericVGA{GenericPCI{Comment: "VGA controller"}}) +}

1 0

Patch set updated for coreboot: 84e21a0 build system: use archives, not linker action to shorten command lines
by Patrick Georgi 19 May '15

19 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10139 -gerrit commit 84e21a0bd39f908342f727ff724139d567241653 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu May 7 22:24:41 2015 +0200 build system: use archives, not linker action to shorten command lines Intermediate linking may distort linker behavior (in particular related to weak symbols). The idea is that archives are closer to 'just a list of object files', and ideally makes the linker more predictable. Using --whole-archive, the linker doesn't optimize out object files just because their symbols were already provided by weak versions. However it shouldn't be used for libgcc, because that one has some unexpected side-effects. Change-Id: Ie226c198a93bcdca2d82c02431c72108a1c6ea60 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 4 ++-- src/arch/arm/Makefile.inc | 8 ++++---- src/arch/arm64/Makefile.inc | 8 ++++---- src/arch/mips/Makefile.inc | 6 +++--- src/arch/riscv/Makefile.inc | 6 +++--- src/arch/x86/Makefile.inc | 6 +++--- src/cpu/x86/smm/Makefile.inc | 2 +- src/lib/Makefile.inc | 2 +- 8 files changed, 21 insertions(+), 21 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index a8961cc..277408f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -115,8 +115,8 @@ files-in-dir=$(filter-out $(call dir-wildcards,$(call filter-out-dirs,$(1),$(sor # directory into an intermediate file ramstage-postprocess=$$(eval DEPENDENCIES+=$$(addsuffix .d,$$(basename $(1)))) \ $(foreach d,$(sort $(dir $(filter-out %.ld,$(1)))), \ - $(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(filter-out %.ld,$(1))); $$(LD_ramstage) -o $$@ -r $$^ ) \ - $(eval ramstage-objs:=$(d)ramstage.o $(filter-out $(filter-out %.ld, $(call files-in-dir,$(d),$(1))),$(ramstage-objs)))) + $(eval $(d)ramstage.a: $(call files-in-dir,$(d),$(filter-out %.ld,$(1))); rm -f $$@ && $(AR_ramstage) rcsT $$@ $$^ ) \ + $(eval ramstage-objs:=$(d)ramstage.a $(filter-out $(filter-out %.ld, $(call files-in-dir,$(d),$(1))),$(ramstage-objs)))) bootblock-generic-ccopts += -D__PRE_RAM__ -D__BOOTBLOCK__ romstage-generic-ccopts += -D__PRE_RAM__ -D__ROMSTAGE__ diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 0fd4fed..8d6abb4 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -63,7 +63,7 @@ bootblock-y += clock.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group verstage-y += boot.c verstage-y += div0.c @@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index b14e69e..ad00afd 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -74,7 +74,7 @@ bootblock-y += ../../lib/memmove.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -86,7 +86,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c verstage-y += boot.c @@ -129,7 +129,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld + $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -178,7 +178,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld + $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld # Build ARM Trusted Firmware (BL31) diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index 358e71d..b92127a 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -51,7 +51,7 @@ bootblock-S-ccopts += -undef $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_MIPS @@ -72,7 +72,7 @@ romstage-y += ../../lib/memset.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_MIPS @@ -96,6 +96,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_MIPS diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index a0feb3d..a34b18d 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -41,7 +41,7 @@ bootblock-y += \ $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \ - -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) \ + -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ $(LIBGCC_FILE_NAME_bootblock) --end-group endif @@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) @@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8b37d7a..659d006 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -202,7 +202,7 @@ romstage-libs ?= $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld + $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders && \ $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ @@ -211,7 +211,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null. $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld + $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld $(objgenerated)/romstage_null.ld: $(obj)/config.h $$(filter %.ld,$$(romstage-srcs)) @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -310,7 +310,7 @@ endif $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) $(COMPILER_RT_ramstage) --end-group + $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group endif # CONFIG_ARCH_RAMSTAGE_X86_32 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index a02be49..36f83c8 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -32,7 +32,7 @@ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --start-group $(smm-objs) $(COMPILER_RT_smm) --end-group + $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group ifeq ($(CONFIG_SMM_MODULES),y) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 88254b9..b583e6d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -191,7 +191,7 @@ RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --start-group $(filter-out %.ld,$(2)) --end-group + $$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map $(strip $(1)).rmod: $(strip $(1))

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Patch merged into coreboot/master: da3a146 arm64: Make SPSR exception masking on EL2 transition explicit
by gerrit＠coreboot.org 19 May '15

19 May '15

the following patch was just integrated into master: commit da3a146caea1e85c9651a7f5889ad2a547d6f5e7 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed May 13 11:19:33 2015 -0700 arm64: Make SPSR exception masking on EL2 transition explicit The configuration of SPSR bits that mask processor exceptions is kinda oddly hidden as an implict part of the transition() function right now. It would be odd but not impossible for programs to want to be entered with enabled exceptions, so let's move these bits to be explicitly set by the caller like the rest of SPSR instead. Also clear up some macro names. The SPSR[I] bit is currently defined as SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit actually *disables* (masks) interrupts. The fact that there is an additional SPSR_IRQ_MASK definition with the same value but a different purpose doesn't really help. There's rarely a point to have all three of xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so simplify this to a single definition per bit. (Other macros in lib_helpers.h should probably also be overhauled to conform, but I want to wait and see how many of them really stay relevant after upcoming changes first.) BRANCH=None BUG=None TEST=None Change-Id: Id126f70d365467e43b7f493c341542247e5026d2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297 Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270785 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10250 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10250 for details. -gerrit

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Patch merged into coreboot/master: 745a75f arm64: Add support for using ARM Trusted Firmware as secure monitor
by gerrit＠coreboot.org 19 May '15

19 May '15

the following patch was just integrated into master: commit 745a75faac970ec5dd35472412ddb94e888e4198 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon May 11 16:45:56 2015 -0700 arm64: Add support for using ARM Trusted Firmware as secure monitor This patch adds support for integrating the runtime-resident component of ARM Trusted Firmware (github.com/ARM-software/arm-trusted-firmware) called BL31. It expects the ARM TF source tree to be checked out under $(top)/3rdparty/arm-trusted-firmware, which will be set up in a later patch. Also include optional support for VBOOT2 verification (pretty hacky for now, since CBFSv1 is just around the corner and will make all this so much better). BRANCH=None BUG=None TEST=Booted Oak with ARM TF and working PSCI (with additional platform patches). Change-Id: I8c923226135bdf88a9a30a7f5ff163510c35608d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a1b3b2d56b25bfc1f3b2d19bf7876205075a987a Original-Change-Id: I0714cc10b5b10779af53ecbe711ceeb89fb30da2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270784 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10249 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10249 for details. -gerrit

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Patch merged into coreboot/master: bbca3a9 arm64: Reorganize payload entry code and related Kconfigs
by gerrit＠coreboot.org 19 May '15

19 May '15

the following patch was just integrated into master: commit bbca3a9cfa5248eb49bd2e42e8db25a6733835bb Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs This patch slightly reorganizes arm64/boot.c with the aim of being more readable: Make more obvious that there's no code execution here after payload_entry. [pg: taken from patch linked below] Change-Id: Ia341e5d290b10ad5ba3edb349b8a7f619022d99f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10247 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10247 for details. -gerrit

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Patch merged into coreboot/master: 883ec98 arm64: Reorganize payload entry code and related Kconfigs
by gerrit＠coreboot.org 19 May '15

19 May '15

the following patch was just integrated into master: commit 883ec987a65939ecccf4b602a02ba2aeaca696b2 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs This patch slightly reorganizes arm64/boot.c with the aim of being more readable: we need to sync the i-cache in both code paths, so do it in a single location. [pg: taken from patch linked below] Change-Id: Iab173acfc6d66e4dccb6f6ab916aea2007632bfd Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10246 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10246 for details. -gerrit

1 0

Patch merged into coreboot/master: b436ce1 arm64: Reorganize payload entry code and related Kconfigs
by gerrit＠coreboot.org 19 May '15

19 May '15

the following patch was just integrated into master: commit b436ce1ac6a9b10d9e1f499476e36dde8928e950 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs This patch slightly reorganizes arm64/boot.c with the aim of being more readable: Make spintable handling optional through a kconfig flag. [pg: taken from patch linked below] Change-Id: I64610640835473fcc3d9eff01feb5f861b753eb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10245 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10245 for details. -gerrit

1 0

Patch merged into coreboot/master: f52602a arm64: Reorganize payload entry code and related Kconfigs
by gerrit＠coreboot.org 19 May '15

19 May '15

the following patch was just integrated into master: commit f52602a74093a2e342454bc2930f8eee3bc4a670 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs This patch slightly reorganizes arm64/boot.c with the aim of being more readable. Improve locality of code. [pg: taken from patch linked below] Change-Id: Ie9ea6a10b9d5e5c33bf020369afcae4f10ef068e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10244 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10244 for details. -gerrit

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coreboot-gerrit May 2015