Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10258
-gerrit
commit ff696ee4926dbc0285ac312098e90c061811407e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue May 19 15:51:47 2015 -0500
riscv: enable function and data sections
Every other arch we support has these options enabled.
Enable it to make everything a lot easier in compiling common
code.
Change-Id: I86205468bbd793fbd377e471a1d32be617af5302
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
toolchain.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/toolchain.inc b/toolchain.inc
index 36402fe..e7edf71 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -69,6 +69,7 @@ CFLAGS_mips := -mips32r2 -G 0 -ffunction-sections -fdata-sections
CFLAGS_mips += -mno-abicalls -fno-pic
CFLAGS_x86_32 += -ffunction-sections -fdata-sections
+CFLAGS_riscv := -ffunction-sections -fdata-sections
toolchain_to_dir = \
$(foreach arch,$(ARCH_SUPPORTED),\
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10222
-gerrit
commit 99c47dc0b32e15134810f00b67d3abee4410428c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri May 15 16:56:27 2015 -0500
Revert "pistashio: bump up romstage size"
This reverts commit 701211a6e57a17ea861b4ad682dca7416fc9050e.
Change-Id: Ib3e573548bff5c17ab30cfab3d833a2065d689c9
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index ad1d1c5..bc67447 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,8 +38,8 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 40K)
- PRERAM_CBFS_CACHE(0x1a00f000, 68K)
+ ROMSTAGE(0x1a005000, 36K)
+ PRERAM_CBFS_CACHE(0x1a00e000, 72K)
SRAM_END(0x1a020000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.
the following patch was just integrated into master:
commit 18fed3dda68a29abf8bee987bc60a64258d2a83f
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Sat May 16 21:51:17 2015 -0500
superio/nuvoton: Add support for Nuvoton NCT6779D
Add support for Nuvoton NCT6779D, using NCT6776 as a baseline
Change-Id: I020a21267f7e30bdea4bb5f83d67bd94082fdf05
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: http://review.coreboot.org/10232
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
See http://review.coreboot.org/10232 for details.
-gerrit
the following patch was just integrated into master:
commit a6b4798ac00a72a5bab16605a1fdb9d2ffcffd71
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue May 19 21:30:20 2015 +0200
intel/haswell: Drop MONOTONIC_TIMER_MSR
The variable was set on all haswell boards, so we can do it like on
broadwell where the MSR based timer is assumed to be around, too.
Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/10256
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/10256 for details.
-gerrit
the following patch was just integrated into master:
commit e2b0affd6c36d332aaf31e9438a9be048943d611
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue May 19 21:24:15 2015 +0200
Remove Kconfig variable that has no effect
DYNAMIC_CBMEM is only selected a couple of times but never declared
or read. Remove it.
Change-Id: I5016dac2c935d3f261001e9f388a8989540e93ae
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/10255
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/10255 for details.
-gerrit