coreboot-gerrit May 2015

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New patch to review for coreboot: b2136bc Deactivate TPM
by Vladimir Serbinenko 20 May '15

20 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10270 -gerrit commit b2136bc95ab18e35adf9ef6264f84cac35d1be8d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:46:57 2015 +0200 Deactivate TPM Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/pc80/tpm/Kconfig | 7 +++++++ src/drivers/pc80/tpm/acpi/tpm.asl | 10 +++++----- src/drivers/pc80/tpm/romstage.c | 19 +++++++++++++++++++ 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 46f404e..8c64b0d 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -37,3 +37,10 @@ config SKIP_TPM_STARTUP_ON_NORMAL_BOOT depends on LPC_TPM help Skip TPM init on normal boot. Useful if payload does TPM init. + +config TPM_DEACTIVATE + bool "Deactivate TPM" + default n + depends on LPC_TPM + help + Deactivate TPM by issuing deactivate command. diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl index 7500211..e6c28db 100644 --- a/src/drivers/pc80/tpm/acpi/tpm.asl +++ b/src/drivers/pc80/tpm/acpi/tpm.asl @@ -27,11 +27,11 @@ Device (TPM) Method (_STA, 0) { - If (CONFIG_LPC_TPM) { - Return (0xf) - } Else { - Return (0x0) - } +#if CONFIG_LPC_TPM && !CONFIG_TPM_DEACTIVATE + Return (0xf) +#else + Return (0x0) +#endif } Name (IBUF, ResourceTemplate () diff --git a/src/drivers/pc80/tpm/romstage.c b/src/drivers/pc80/tpm/romstage.c index 8f4161b..a5e5442 100644 --- a/src/drivers/pc80/tpm/romstage.c +++ b/src/drivers/pc80/tpm/romstage.c @@ -51,6 +51,12 @@ static const struct { }; static const struct { + u8 buffer[12]; +} tpm_deactivate_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x3 } +}; + +static const struct { u8 buffer[10]; } tpm_continueselftest_cmd = { { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } @@ -181,6 +187,19 @@ void init_tpm(int s3resume) u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + if (CONFIG_TPM_DEACTIVATE) { + printk(BIOS_SPEW, "TPM: Deactivate\n"); + result = TlclSendReceive(tpm_deactivate_cmd.buffer, + response, sizeof(response)); + if (result == TPM_SUCCESS) { + printk(BIOS_SPEW, "TPM: OK.\n"); + return; + } + + printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); + return; + } + #if CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT /* Doing TPM startup when we're not coming in on the S3 resume path * saves us roughly 20ms in boot time only. This does not seem to

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New patch to review for coreboot: dce2f1a Move TPM code out of chromeos
by Vladimir Serbinenko 20 May '15

20 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10269 -gerrit commit dce2f1a3afd8f32ef027cb9783133165b3b8cbe9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:29:06 2015 +0200 Move TPM code out of chromeos This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 4 +- src/drivers/pc80/tpm/Kconfig | 24 ++- src/drivers/pc80/tpm/Makefile.inc | 1 + src/drivers/pc80/tpm/romstage.c | 242 +++++++++++++++++++++++++++ src/include/tpm.h | 2 + src/mainboard/google/bolt/Kconfig | 1 + src/mainboard/google/butterfly/Kconfig | 1 + src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/link/romstage.c | 9 +- src/mainboard/google/panther/Kconfig | 1 + src/mainboard/google/parrot/Kconfig | 1 + src/mainboard/google/parrot/romstage.c | 8 +- src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/rambi/Kconfig | 1 + src/mainboard/google/samus/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/google/stout/Kconfig | 1 + src/mainboard/google/stout/romstage.c | 8 +- src/mainboard/intel/baskingridge/Kconfig | 1 + src/mainboard/intel/emeraldlake2/romstage.c | 8 +- src/mainboard/intel/wtm2/Kconfig | 1 + src/mainboard/samsung/lumpy/Kconfig | 1 + src/mainboard/samsung/lumpy/romstage.c | 8 +- src/mainboard/samsung/stumpy/Kconfig | 1 + src/mainboard/samsung/stumpy/romstage.c | 8 +- src/soc/intel/baytrail/romstage/romstage.c | 13 +- src/soc/intel/broadwell/romstage/romstage.c | 13 +- src/vendorcode/google/chromeos/Kconfig | 2 + src/vendorcode/google/chromeos/chromeos.h | 4 - src/vendorcode/google/chromeos/vboot.c | 248 ---------------------------- 31 files changed, 314 insertions(+), 303 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8e4335f..f347a2c 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -276,8 +276,8 @@ void romstage_common(const struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 279da39..46f404e 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -1,5 +1,12 @@ +config MAINBOARD_HAS_LPC_TPM + bool + default n + help + Board has TPM support + config LPC_TPM - bool + bool "Enable TPM support" + depends on MAINBOARD_HAS_LPC_TPM default n help Enable this option to enable LPC TPM support in coreboot. @@ -15,3 +22,18 @@ config TPM_TIS_BASE_ADDRESS The default is specified by the TCG PC Client Specific TPM Interface Specification 1.2 and should not be changed unless the TPM being used does not conform to TPM TIS 1.2. + +config TPM_INIT_FAILURE_IS_FATAL + bool + default n + depends on LPC_TPM + help + What to do if TPM init failed. If true, force a hard reset, + otherwise just log error message to console. + +config SKIP_TPM_STARTUP_ON_NORMAL_BOOT + bool + default n + depends on LPC_TPM + help + Skip TPM init on normal boot. Useful if payload does TPM init. diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc index c900fe8..089d067 100644 --- a/src/drivers/pc80/tpm/Makefile.inc +++ b/src/drivers/pc80/tpm/Makefile.inc @@ -1,2 +1,3 @@ romstage-$(CONFIG_LPC_TPM) += tpm.c ramstage-$(CONFIG_LPC_TPM) += tpm.c +romstage-$(CONFIG_LPC_TPM) += romstage.c diff --git a/src/drivers/pc80/tpm/romstage.c b/src/drivers/pc80/tpm/romstage.c new file mode 100644 index 0000000..8f4161b --- /dev/null +++ b/src/drivers/pc80/tpm/romstage.c @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console/cbmem_console.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <tpm.h> +#include <reset.h> + +//#define EXTRA_LOGGING + +#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ + +#define TPM_SUCCESS ((u32)0x00000000) + +#define TPM_E_IOERROR ((u32)0x0000001f) +#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) +#define TPM_E_NON_FATAL ((u32)0x00000800) +#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) + +#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) +#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) + +static const struct { + u8 buffer[12]; +} tpm_resume_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } +}; + +static const struct { + u8 buffer[12]; +} tpm_startup_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1 } +}; + +static const struct { + u8 buffer[10]; +} tpm_continueselftest_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } +}; + +static inline void FromTpmUint32(const u8 * buffer, u32 * x) +{ + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); +} + +static inline int TpmCommandSize(const u8 * buffer) +{ + u32 size; + FromTpmUint32(buffer + sizeof(u16), &size); + return (int)size; +} + +/* Gets the code field of a TPM command. */ +static inline int TpmCommandCode(const u8 * buffer) +{ + u32 code; + FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); + return code; +} + +/* Gets the return code field of a TPM result. */ +static inline int TpmReturnCode(const u8 * buffer) +{ + return TpmCommandCode(buffer); +} + +/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or + * DOING_SELFTEST errors are returned. + */ +static u32 TlclSendReceiveNoRetry(const u8 * request, + u8 * response, int max_length) +{ + size_t response_length = max_length; + u32 result; + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", + request[0], request[1], + request[2], request[3], request[4], request[5], + request[6], request[7], request[8], request[9]); +#endif + + result = TPM_SUCCESS; + if (tis_sendrecv + (request, TpmCommandSize(request), response, &response_length)) + result = TPM_E_IOERROR; + + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + printk(BIOS_DEBUG, + "TPM: command 0x%x send/receive failed: 0x%x\n", + TpmCommandCode(request), result); + return TPM_E_COMMUNICATION_ERROR; + } + /* Otherwise, use the result code from the response */ + result = TpmReturnCode(response); + +/* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", + response[0], response[1], + response[2], response[3], response[4], response[5], + response[6], response[7], response[8], response[9]); +#endif + + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", + TpmCommandCode(request), result); + + return result; +} + +static inline u32 TlclContinueSelfTest(void) +{ + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + printk(BIOS_DEBUG, "TPM: Continue self test\n"); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); +} + +/* Sends a TPM command and gets a response. Returns 0 if success or the TPM + * error code if error. In the firmware, waits for the self test to complete + * if needed. In the host, reports the first error without retries. */ +static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) +{ + u32 result = TlclSendReceiveNoRetry(request, response, max_length); + /* When compiling for the firmware, hide command failures due to the self + * test not having run or completed. */ + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = TlclContinueSelfTest(); + if (result != TPM_SUCCESS) { + return result; + } +#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) + /* Retry only once */ + result = TlclSendReceiveNoRetry(request, response, max_length); +#else + /* This needs serious testing. The TPM specification says: + * "iii. The caller MUST wait for the actions of + * TPM_ContinueSelfTest to complete before reissuing the + * command C1." But, if ContinueSelfTest is non-blocking, how + * do we know that the actions have completed other than trying + * again? */ + do { + result = + TlclSendReceiveNoRetry(request, response, + max_length); + } while (result == TPM_E_DOING_SELFTEST); +#endif + } + + return result; +} + +void init_tpm(int s3resume) +{ + u32 result; + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + +#if CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT + /* Doing TPM startup when we're not coming in on the S3 resume path + * saves us roughly 20ms in boot time only. This does not seem to + * be worth an API change to vboot_reference-firmware right now, so + * let's keep the code around, but just bail out early: + */ + if (!s3resume) + return; +#endif + +#if CONFIG_NO_TPM_RESUME + if (s3resume) + return; +#endif + + printk(BIOS_DEBUG, "TPM initialization.\n"); + + printk(BIOS_SPEW, "TPM: Init\n"); + if (tis_init()) + return; + + printk(BIOS_SPEW, "TPM: Open\n"); + if (tis_open()) + return; + + + if (s3resume) { + /* S3 Resume */ + printk(BIOS_SPEW, "TPM: Resume\n"); + result = TlclSendReceive(tpm_resume_cmd.buffer, + response, sizeof(response)); + if (result == TPM_E_INVALID_POSTINIT) { + /* We're on a platform where the TPM maintains power + * in S3, so it's already initialized. + */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return; + } + } else { + printk(BIOS_SPEW, "TPM: Startup\n"); + result = TlclSendReceive(tpm_startup_cmd.buffer, + response, sizeof(response)); + } + + if (result == TPM_SUCCESS) { + printk(BIOS_SPEW, "TPM: OK.\n"); + return; + } + + printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); + +#if CONFIG_TPM_INIT_FAILURE_IS_FATAL + printk(BIOS_ERR, "Hard reset!\n"); + post_code(POST_TPM_FAILURE); + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); + hard_reset(); +#endif +} diff --git a/src/include/tpm.h b/src/include/tpm.h index e25ad6a..c33c9c1 100644 --- a/src/include/tpm.h +++ b/src/include/tpm.h @@ -66,4 +66,6 @@ int tis_close(void); int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf, size_t *recv_len); +void init_tpm(int s3resume); + #endif /* TPM_H_ */ diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 2239f70..74e1edd 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 7472c06..b1a64ee 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index a8faaab..5b97259 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 316434f..0f70925 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 5844aa6..5a1057e 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -41,9 +41,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <tpm.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> @@ -246,8 +244,9 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif + timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 31062ed..37a8548 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select PHYSICAL_REC_SWITCH diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 07405c6..9cf390a 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ab82bde..046a77f 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #include <cbfs.h> +#include <tpm.h> #include "ec/compal/ene932/ec.h" static void pch_enable_lpc(void) @@ -197,8 +195,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index d6a208b..2c1560a 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 4c9e891..1130d11 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select ALWAYS_LOAD_OPROM select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index f655b29..06317e9 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index fd4cb2f..cfbce5e 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_DP select INTEL_DDI diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index ec03d87..eca83da 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6a6aa48..e2a4243 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -40,9 +40,7 @@ #include <halt.h> #include "gpio.h" #include <bootmode.h> -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <tpm.h> #include <cbfs.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -251,8 +249,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index c3e3361..f916138 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 45d92d8..6e3af79 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> +#include <tpm.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #define SIO_PORT 0x164e @@ -255,8 +253,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 5a064d1..b8f616a 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 7c9dce4..fed4610 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select CPU_INTEL_SOCKET_RPGA989 select EC_SMSC_MEC1308 select HAVE_ACPI_RESUME diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 29a238a..4666584 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,6 +32,7 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> +#include <tpm.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -45,9 +46,6 @@ #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif static void pch_enable_lpc(void) { @@ -273,8 +271,8 @@ void main(unsigned long bist) } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 1eda8eb..f749c39 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select CPU_INTEL_SOCKET_RPGA989 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 346026f..2844908 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -41,13 +41,11 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> +#include <tpm.h> #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif /* Stumpy USB Reset Disable defined in cmos.layout */ #if CONFIG_USE_OPTION_TABLE @@ -283,8 +281,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 9c8bbc4..20107e8 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -33,6 +33,7 @@ #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> +#include <tpm.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -211,14 +212,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) return prev_sleep_state; } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ - init_chromeos(prev_sleep_state == 3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -250,7 +243,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(prev_sleep_state); +#if CONFIG_LPC_TPM + init_tpm(prev_sleep_state == 3); +#endif } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index c026004..11f4688 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -29,6 +29,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> +#include <tpm.h> #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> @@ -89,14 +90,6 @@ void * asmlinkage romstage_main(unsigned long bist, return setup_stack_and_mttrs(); } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */ - init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -132,7 +125,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(params->power_state->prev_sleep_state); +#if CONFIG_LPC_TPM + init_tpm(prev_sleep_state == SLEEP_STATE_S3); +#endif } void asmlinkage romstage_after_car(void) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 90e3505..34a19ba 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -26,6 +26,8 @@ config CHROMEOS bool "Build for ChromeOS" default n select TPM + select TPM_INIT_FAILURE_IS_FATAL + select SKIP_TPM_STARTUP_ON_NORMAL_BOOT select BOOTMODE_STRAPS select ELOG help diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a87fbdf..a999798 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -39,9 +39,6 @@ void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); #if CONFIG_CHROMEOS -/* functions implemented in vboot.c */ -void init_chromeos(int bootmode); - /* functions implemented in elog.c */ void elog_add_boot_reason(void); @@ -53,7 +50,6 @@ int vboot_enable_developer(void); int vboot_enable_recovery(void); int vboot_skip_display_init(void); #else -static inline void init_chromeos(int bootmode) { } static inline void elog_add_boot_reason(void) { return; } static inline void elog_add_watchdog_reset(void) { return; } static inline void reboot_from_watchdog(void) { return; } diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c deleted file mode 100644 index 7216373..0000000 --- a/src/vendorcode/google/chromeos/vboot.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <console/cbmem_console.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <tpm.h> -#include <reset.h> -#include "chromeos.h" - -//#define EXTRA_LOGGING -#define UBOOT_DOES_TPM_STARTUP - -#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ - -#define TPM_SUCCESS ((u32)0x00000000) - -#define TPM_E_IOERROR ((u32)0x0000001f) -#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) -#define TPM_E_NON_FATAL ((u32)0x00000800) -#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) - -#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) -#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) - -#if CONFIG_NO_TPM_RESUME -static void init_vboot(int bootmode) -{ -} -#else -static const struct { - u8 buffer[12]; -} tpm_resume_cmd = { - { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } -}; - -static const struct { - u8 buffer[12]; -} tpm_startup_cmd = { - {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1 } -}; - -static const struct { - u8 buffer[10]; -} tpm_continueselftest_cmd = { - { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } -}; - -static inline void FromTpmUint32(const u8 * buffer, u32 * x) -{ - *x = ((buffer[0] << 24) | - (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); -} - -static inline int TpmCommandSize(const u8 * buffer) -{ - u32 size; - FromTpmUint32(buffer + sizeof(u16), &size); - return (int)size; -} - -/* Gets the code field of a TPM command. */ -static inline int TpmCommandCode(const u8 * buffer) -{ - u32 code; - FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); - return code; -} - -/* Gets the return code field of a TPM result. */ -static inline int TpmReturnCode(const u8 * buffer) -{ - return TpmCommandCode(buffer); -} - -/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or - * DOING_SELFTEST errors are returned. - */ -static u32 TlclSendReceiveNoRetry(const u8 * request, - u8 * response, int max_length) -{ - size_t response_length = max_length; - u32 result; - -#ifdef EXTRA_LOGGING - printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", - request[0], request[1], - request[2], request[3], request[4], request[5], - request[6], request[7], request[8], request[9]); -#endif - - result = TPM_SUCCESS; - if (tis_sendrecv - (request, TpmCommandSize(request), response, &response_length)) - result = TPM_E_IOERROR; - - if (0 != result) { - /* Communication with TPM failed, so response is garbage */ - printk(BIOS_DEBUG, - "TPM: command 0x%x send/receive failed: 0x%x\n", - TpmCommandCode(request), result); - return TPM_E_COMMUNICATION_ERROR; - } - /* Otherwise, use the result code from the response */ - result = TpmReturnCode(response); - -/* TODO: add paranoia about returned response_length vs. max_length - * (and possibly expected length from the response header). See - * crosbug.com/17017 */ - -#ifdef EXTRA_LOGGING - printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", - response[0], response[1], - response[2], response[3], response[4], response[5], - response[6], response[7], response[8], response[9]); -#endif - - printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", - TpmCommandCode(request), result); - - return result; -} - -static inline u32 TlclContinueSelfTest(void) -{ - u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - printk(BIOS_DEBUG, "TPM: Continue self test\n"); - /* Call the No Retry version of SendReceive to avoid recursion. */ - return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, - response, sizeof(response)); -} - -/* Sends a TPM command and gets a response. Returns 0 if success or the TPM - * error code if error. In the firmware, waits for the self test to complete - * if needed. In the host, reports the first error without retries. */ -static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) -{ - u32 result = TlclSendReceiveNoRetry(request, response, max_length); - /* When compiling for the firmware, hide command failures due to the self - * test not having run or completed. */ - /* If the command fails because the self test has not completed, try it - * again after attempting to ensure that the self test has completed. */ - if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { - result = TlclContinueSelfTest(); - if (result != TPM_SUCCESS) { - return result; - } -#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) - /* Retry only once */ - result = TlclSendReceiveNoRetry(request, response, max_length); -#else - /* This needs serious testing. The TPM specification says: - * "iii. The caller MUST wait for the actions of - * TPM_ContinueSelfTest to complete before reissuing the - * command C1." But, if ContinueSelfTest is non-blocking, how - * do we know that the actions have completed other than trying - * again? */ - do { - result = - TlclSendReceiveNoRetry(request, response, - max_length); - } while (result == TPM_E_DOING_SELFTEST); -#endif - } - - return result; -} - -static void init_vboot(int bootmode) -{ - u32 result; - u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - -#ifdef UBOOT_DOES_TPM_STARTUP - /* Doing TPM startup when we're not coming in on the S3 resume path - * saves us roughly 20ms in boot time only. This does not seem to - * be worth an API change to vboot_reference-firmware right now, so - * let's keep the code around, but just bail out early: - */ - if (bootmode != 2) - return; -#endif - - printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); - - printk(BIOS_SPEW, "TPM: Init\n"); - if (tis_init()) - return; - - printk(BIOS_SPEW, "TPM: Open\n"); - if (tis_open()) - return; - - - if (bootmode == 2) { - /* S3 Resume */ - printk(BIOS_SPEW, "TPM: Resume\n"); - result = TlclSendReceive(tpm_resume_cmd.buffer, - response, sizeof(response)); - if (result == TPM_E_INVALID_POSTINIT) { - /* We're on a platform where the TPM maintains power - * in S3, so it's already initialized. - */ - printk(BIOS_DEBUG, "TPM: Already initialized.\n"); - return; - } - } else { - printk(BIOS_SPEW, "TPM: Startup\n"); - result = TlclSendReceive(tpm_startup_cmd.buffer, - response, sizeof(response)); - } - - if (result == TPM_SUCCESS) { - printk(BIOS_SPEW, "TPM: OK.\n"); - return; - } - -#if !MOCK_TPM - printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); - post_code(POST_TPM_FAILURE); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) - cbmem_dump_console(); - hard_reset(); -#endif -} -#endif - -void init_chromeos(int bootmode) -{ - init_vboot(bootmode); -}

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New patch to review for coreboot: 4c48d91 Kill ENABLE_TPM.
by Vladimir Serbinenko 20 May '15

20 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10268 -gerrit commit 4c48d91458966f84bdfab543ca7a0031d1e83c2b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 20 11:14:25 2015 +0200 Kill ENABLE_TPM. It's used only in P470 and lynxpoint machines. Remove it from other southbridges. New machines should use src/drivers/pc80/tpm. Change-Id: I4741e76df4c6204d65562f016abac9ed60558432 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/acpi/lpc.asl | 24 ------------------------ src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl | 24 ------------------------ src/southbridge/intel/fsp_rangeley/acpi/lpc.asl | 24 ------------------------ src/southbridge/intel/i82801ix/acpi/lpc.asl | 24 ------------------------ 4 files changed, 96 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index cc59850..6feb7f3 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -221,28 +221,4 @@ Device (LPCB) } #include "acpi/superio.asl" - -#ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - IRQ (Edge, Activehigh, Exclusive) { 6 } - }) - } -#endif } diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl index cc59850..6feb7f3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl @@ -221,28 +221,4 @@ Device (LPCB) } #include "acpi/superio.asl" - -#ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - IRQ (Edge, Activehigh, Exclusive) { 6 } - }) - } -#endif } diff --git a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl index 93c3bc1..437bc9f 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl @@ -228,28 +228,4 @@ Device (LPCB) // Include mainboard's superio.asl file. #include "acpi/superio.asl" - -#ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - IRQ (Edge, Activehigh, Exclusive) { 6 } - }) - } -#endif } diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index 0d1e68a..adf7480 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -204,30 +204,6 @@ Device (LPCB) #include "acpi/superio.asl" -#ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - IRQ (Edge, Activehigh, Exclusive) { 6 } - }) - } -#endif - Device (PS2K) // Keyboard { Name(_HID, EISAID("PNP0303"))

1 0

Patch set updated for coreboot: 1c774ef VBT parser.
by Vladimir Serbinenko 20 May '15

20 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5842 -gerrit commit 1c774ef1d44b8826e6bc625fecb4318e52364ed0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat May 24 16:34:29 2014 +0200 VBT parser. Change-Id: I32f6505dbf683478bf5a25b73db7ab0c60eff29c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/intelvbttool/intelvbttool.c | 544 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 544 insertions(+) diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c new file mode 100644 index 0000000..4151dc7 --- /dev/null +++ b/util/intelvbttool/intelvbttool.c @@ -0,0 +1,544 @@ +/* + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <stdio.h> +#include <sys/mman.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <errno.h> + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + + +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__ ((packed)) optionrom_header_t; + +struct vbt_header { + u8 signature[20]; + u16 version; + u16 header_size; + u16 vbt_size; + u8 vbt_checksum; + u8 reserved0; + u32 bdb_offset; + u32 aim_offset[4]; +} __attribute__ ((packed)); + +struct bdb_header { + u8 signature[16]; + u16 version; + u16 header_size; + u16 bdb_size; +}; + +struct vbios_data { + u8 type; /* 0 == desktop, 1 == mobile */ + u8 relstage; + u8 chipset; + u8 lvds_present:1; + u8 tv_present:1; + u8 rsvd2:6; /* finish byte */ + u8 rsvd3[4]; + u8 signon[155]; + u8 copyright[61]; + u16 code_segment; + u8 dos_boot_mode; + u8 bandwidth_percent; + u8 rsvd4; /* popup memory size */ + u8 resize_pci_bios; + u8 rsvd5; /* is crt already on ddc2 */ +} __attribute__ ((packed)); + +struct bdb_general_features { + /* bits 1 */ + u8 panel_fitting:2; + u8 flexaim:1; + u8 msg_enable:1; + u8 clear_screen:3; + u8 color_flip:1; + + /* bits 2 */ + u8 download_ext_vbt:1; + u8 enable_ssc:1; + u8 ssc_freq:1; + u8 enable_lfp_on_override:1; + u8 disable_ssc_ddt:1; + u8 rsvd7:1; + u8 display_clock_mode:1; + u8 rsvd8:1; /* finish byte */ + + /* bits 3 */ + u8 disable_smooth_vision:1; + u8 single_dvi:1; + u8 rsvd9:1; + u8 fdi_rx_polarity_inverted:1; + u8 rsvd10:4; /* finish byte */ + + /* bits 4 */ + u8 legacy_monitor_detect; + + /* bits 5 */ + u8 int_crt_support:1; + u8 int_tv_support:1; + u8 int_efp_support:1; + u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ + u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ + u8 rsvd11:3; /* finish byte */ +} __attribute__ ((packed)); + +struct common_child_dev_config { + u16 handle; + u16 device_type; + u8 not_common1[12]; + u8 dvo_port; + u8 i2c_pin; + u8 slave_addr; + u8 ddc_pin; + u16 edid_ptr; + u8 not_common3[6]; + u8 dvo_wiring; + u8 not_common4[4]; +} __attribute__ ((packed)); + +struct bdb_general_definitions { + /* DDC GPIO */ + u8 crt_ddc_gmbus_pin; + + /* DPMS bits */ + u8 dpms_acpi:1; + u8 skip_boot_crt_detect:1; + u8 dpms_aim:1; + u8 rsvd1:5; /* finish byte */ + + /* boot device bits */ + u8 boot_display[2]; + u8 child_dev_size; + + /* + * Device info: + * If TV is present, it'll be at devices[0]. + * LVDS will be next, either devices[0] or [1], if present. + * On some platforms the number of device is 6. But could be as few as + * 4 if both TV and LVDS are missing. + * And the device num is related with the size of general definition + * block. It is obtained by using the following formula: + * number = (block_size - sizeof(bdb_general_definitions))/ + * sizeof(child_device_config); + */ + struct common_child_dev_config devices[0]; +} __attribute__ ((packed)); + +struct bdb_driver_features { + u8 boot_dev_algorithm:1; + u8 block_display_switch:1; + u8 allow_display_switch:1; + u8 hotplug_dvo:1; + u8 dual_view_zoom:1; + u8 int15h_hook:1; + u8 sprite_in_clone:1; + u8 primary_lfp_id:1; + + u16 boot_mode_x; + u16 boot_mode_y; + u8 boot_mode_bpp; + u8 boot_mode_refresh; + + u16 enable_lfp_primary:1; + u16 selective_mode_pruning:1; + u16 dual_frequency:1; + u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ + u16 nt_clone_support:1; + u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ + u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ + u16 cui_aspect_scaling:1; + u16 preserve_aspect_ratio:1; + u16 sdvo_device_power_down:1; + u16 crt_hotplug:1; + u16 lvds_config:2; + u16 tv_hotplug:1; + u16 hdmi_config:2; + + u8 static_display:1; + u8 reserved2:7; + u16 legacy_crt_max_x; + u16 legacy_crt_max_y; + u8 legacy_crt_max_refresh; + + u8 hdmi_termination; + u8 custom_vbt_version; +} __attribute__ ((packed)); + +struct bdb_lvds_options { + u8 panel_type; + u8 rsvd1; + /* LVDS capabilities, stored in a dword */ + u8 pfit_mode:2; + u8 pfit_text_mode_enhanced:1; + u8 pfit_gfx_mode_enhanced:1; + u8 pfit_ratio_auto:1; + u8 pixel_dither:1; + u8 lvds_edid:1; + u8 rsvd2:1; + u8 rsvd4; +} __attribute__ ((packed)); + +struct bdb_sdvo_lvds_options { + u8 panel_backlight; + u8 h40_set_panel_type; + u8 panel_type; + u8 ssc_clk_freq; + u16 als_low_trip; + u16 als_high_trip; + u8 sclalarcoeff_tab_row_num; + u8 sclalarcoeff_tab_row_size; + u8 coefficient[8]; + u8 panel_misc_bits_1; + u8 panel_misc_bits_2; + u8 panel_misc_bits_3; + u8 panel_misc_bits_4; +} __attribute__ ((packed)); + + +#define BDB_GENERAL_FEATURES 1 +#define BDB_GENERAL_DEFINITIONS 2 + +#define BDB_DRIVER_FEATURES 12 +#define BDB_SDVO_LVDS_OPTIONS 22 +#define BDB_SDVO_PANEL_DTDS 23 +#define BDB_LVDS_OPTIONS 40 +#define BDB_LVDS_LFP_DATA_PTRS 41 +#define BDB_LVDS_LFP_DATA 42 + +#define BDB_SKIP 254 + +static void parse_vbt(const void *vbt) +{ + const struct vbt_header *head = vbt; + const struct bdb_header *bdb; + int i; + const u8 *ptr; + int is_first_skip = 1; + + if (memcmp(head->signature, "$VBT", 4) != 0) { + fprintf(stderr, "invalid VBT signature\n"); + exit(1); + } + printf("signature: <%20.20s>\n", head->signature); + printf("version: %d.%02d\n", head->version / 100, + head->version % 100); + if (head->header_size != sizeof(struct vbt_header)) + printf("header size: 0x%x\n", head->header_size); + printf("VBT size: 0x%x\n", head->vbt_size); + printf("VBT checksum: 0x%x\n", head->vbt_checksum); + if (head->reserved0) + printf("header reserved0: 0x%x\n", head->reserved0); + if (head->bdb_offset != sizeof(struct vbt_header)) + printf("BDB offset: 0x%x\n", head->bdb_offset); + + for (i = 0; i < 4; i++) + if (head->aim_offset[i]) + printf("AIM[%d] offset: 0x%x\n", i, + head->aim_offset[i]); + bdb = (const void *) ((const char *) vbt + head->bdb_offset); + + if (memcmp("BIOS_DATA_BLOCK ", bdb->signature, 16) != 0) { + fprintf(stderr, "invalid BDB signature:%s\n", + bdb->signature); + exit(1); + } + printf("BDB version: %d.%02d\n", bdb->version / 100, + bdb->version % 100); + if (bdb->header_size != sizeof(struct bdb_header)) + printf("BDB header size: 0x%x\n", bdb->header_size); + if (bdb->bdb_size != head->vbt_size - head->bdb_offset) + printf("BDB size: 0x%x\n", bdb->bdb_size); + for (ptr = (const u8 *) bdb + bdb->header_size; + ptr < (const u8 *) bdb + bdb->bdb_size;) { + u16 secsz = (ptr[1] | (ptr[2] << 8)); + u8 sectype = ptr[0]; + const u8 *section = ptr + 3; + + printf("section type %d, size 0x%x\n", sectype, secsz); + ptr += secsz + 3; + switch (sectype) { + case BDB_GENERAL_FEATURES:{ + const struct bdb_general_features *sec = + (const void *) section; + printf("General features:\n"); + + if (sec->panel_fitting) + printf("\tpanel_fitting = 0x%x\n", + sec->panel_fitting); + if (sec->flexaim) + printf("\tflexaim = 0x%x\n", + sec->flexaim); + if (sec->msg_enable) + printf("\tmsg_enable = 0x%x\n", + sec->msg_enable); + if (sec->clear_screen) + printf("\tclear_screen = 0x%x\n", + sec->clear_screen); + if (sec->color_flip) + printf("\tcolor_flip = 0x%x\n", + sec->color_flip); + if (sec->download_ext_vbt) + printf + ("\tdownload_ext_vbt = 0x%x\n", + sec->download_ext_vbt); + printf("\t*enable_ssc = 0x%x\n", + sec->enable_ssc); + printf("\t*ssc_freq = 0x%x\n", + sec->ssc_freq); + if (sec->enable_lfp_on_override) + printf + ("\tenable_lfp_on_override = 0x%x\n", + sec->enable_lfp_on_override); + if (sec->disable_ssc_ddt) + printf + ("\tdisable_ssc_ddt = 0x%x\n", + sec->disable_ssc_ddt); + if (sec->rsvd7) + printf("\trsvd7 = 0x%x\n", + sec->rsvd7); + printf("\t*display_clock_mode = 0x%x\n", + sec->display_clock_mode); + if (sec->rsvd8) + printf("\trsvd8 = 0x%x\n", + sec->rsvd8); + printf("\tdisable_smooth_vision = 0x%x\n", + sec->disable_smooth_vision); + if (sec->single_dvi) + printf("\tsingle_dvi = 0x%x\n", + sec->single_dvi); + if (sec->rsvd9) + printf("\trsvd9 = 0x%x\n", + sec->rsvd9); + printf + ("\t*fdi_rx_polarity_inverted = 0x%x\n", + sec->fdi_rx_polarity_inverted); + if (sec->rsvd10) + printf("\trsvd10 = 0x%x\n", + sec->rsvd10); + if (sec->legacy_monitor_detect) + printf + ("\tlegacy_monitor_detect = 0x%x\n", + sec->legacy_monitor_detect); + printf("\t*int_crt_support = 0x%x\n", + sec->int_crt_support); + printf("\t*int_tv_support = 0x%x\n", + sec->int_tv_support); + if (sec->int_efp_support) + printf + ("\tint_efp_support = 0x%x\n", + sec->int_efp_support); + if (sec->dp_ssc_enb) + printf("\tdp_ssc_enb = 0x%x\n", + sec->dp_ssc_enb); + if (sec->dp_ssc_freq) + printf("\tdp_ssc_freq = 0x%x\n", + sec->dp_ssc_freq); + if (sec->rsvd11) + printf("\trsvd11 = 0x%x\n", + sec->rsvd11); + break; + } + case BDB_DRIVER_FEATURES:{ + const struct bdb_driver_features *sec = + (const void *) section; + printf("\t*LVDS config: %d\n", + sec->lvds_config); + printf("\t*Dual frequency: %d\n", + sec->dual_frequency); + + break; + } + case BDB_SDVO_LVDS_OPTIONS:{ + const struct bdb_sdvo_lvds_options *sec = + (const void *) section; + printf("\t*Panel type: %d\n", + sec->panel_type); + + break; + } + case BDB_GENERAL_DEFINITIONS:{ + const struct bdb_general_definitions *sec = + (const void *) section; + printf("\t*CRT DDC GMBUS pin: %d\n", + sec->crt_ddc_gmbus_pin); + + printf("\tDPMS ACPI: %d\n", + sec->dpms_acpi); + printf("\tSkip boot CRT detect: %d\n", + sec->skip_boot_crt_detect); + printf("\tDPMS aim: %d\n", sec->dpms_aim); + if (sec->rsvd1) + printf("\trsvd1: 0x%x\n", + sec->rsvd1); + printf("\tboot_display: { %x, %x }\n", + sec->boot_display[0], + sec->boot_display[1]); + if (sec->child_dev_size != + sizeof(struct common_child_dev_config)) + printf("\tchild_dev_size: %d\n", + sec->child_dev_size); + printf("\t%d devices\n", + (secsz - + sizeof(*sec)) / + sizeof(struct + common_child_dev_config)); + for (i = 0; + i < + (secsz - + sizeof(*sec)) / + sizeof(struct + common_child_dev_config); + i++) { + printf("\t*device type: %x ", + sec->devices[i]. + device_type); +#define DEVICE_TYPE_INT_LFP 0x1022 +#define DEVICE_TYPE_INT_TV 0x1009 +#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 + switch (sec->devices[i]. + device_type) { + case DEVICE_TYPE_INT_LFP: + printf("(flat panel)\n"); + break; + case DEVICE_TYPE_INT_TV: + printf("(TV)\n"); + break; + case DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR: + printf + ("(DVI)\n"); + break; + case 0: + printf("(Empty)\n"); + break; + default: + printf("(Unknown)\n"); + break; + } + if (!sec->devices[i].device_type) + continue; + printf("\t *dvo_port: %x\n", + sec->devices[i].dvo_port); + printf("\t *i2c_pin: %x\n", + sec->devices[i].i2c_pin); + printf("\t *slave_addr: %x\n", + sec->devices[i].slave_addr); + printf("\t *ddc_pin: %x\n", + sec->devices[i].ddc_pin); + printf("\t *dvo_wiring: %x\n", + sec->devices[i].dvo_wiring); + printf("\t edid_ptr: %x\n", + sec->devices[i].edid_ptr); + } + + break; + } + case BDB_SKIP:{ + const struct vbios_data *sec = + (const void *) section; + if (!is_first_skip) + break; + is_first_skip = 0; + printf("\ttype: %x\n", sec->type); + printf("\trelstage: %x\n", sec->relstage); + printf("\tchipset: %x\n", sec->chipset); + printf(sec->lvds_present ? "\tLVDS\n" + : "\tNo LVDS\n"); + printf(sec->tv_present ? "\tTV\n" + : "\tNo TV\n"); + if (sec->rsvd2) + printf("\trsvd2: 0x%x\n", + sec->rsvd2); + for (i = 0; i < 4; i++) + if (sec->rsvd3[i]) + printf + ("\trsvd3[%d]: 0x%x\n", + i, sec->rsvd3[i]); + printf("\tSignon: %.155s\n", sec->signon); + printf("\tCopyright: %.155s\n", + sec->copyright); + printf("\tCode segment: %x\n", + sec->code_segment); + printf("\tDOS Boot mode: %x\n", + sec->dos_boot_mode); + printf("\tBandwidth percent: %x\n", + sec->bandwidth_percent); + if (sec->rsvd4) + printf("\trsvd4: 0x%x\n", + sec->rsvd4); + printf("\tBandwidth percent: %x\n", + sec->resize_pci_bios); + if (sec->rsvd5) + printf("\trsvd5: 0x%x\n", + sec->rsvd5); + break; + } + } + } + +} + +static void parse_vbios(const void *ptr) +{ + const optionrom_header_t *oh; + oh = ptr; + if (oh->signature != 0xaa55) { + fprintf(stderr, "bad oprom signature: %x\n", + oh->signature); + return; + } + if (!oh->vbt_offset) { + fprintf(stderr, "no VBT found\n"); + return; + } + parse_vbt((const char *) ptr + oh->vbt_offset); +} + +int main(int argc, char **argv) +{ + const void *ptr; + int fd; + if (argc == 2) { + fd = open(argv[1], O_RDONLY); + ptr = mmap(0, 65536, PROT_READ, MAP_SHARED, fd, 0); + } else { + fd = open("/dev/mem", O_RDONLY); + ptr = mmap(0, 65536, PROT_READ, MAP_SHARED, fd, 0xc0000); + } + if (ptr == MAP_FAILED) { + fprintf(stderr, "mmap failed: %s\n", strerror(errno)); + return 1; + } + parse_vbios(ptr); + close(fd); + return 0; +}

1 0

Patch set updated for coreboot: 2b74865 baytrail: Switch to per-device ACPI
by Vladimir Serbinenko 20 May '15

20 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7037 -gerrit commit 2b74865027abe7e90c34e938eaca6cadcaa00c4d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Oct 8 22:56:27 2014 +0200 baytrail: Switch to per-device ACPI Change-Id: I6a1b1daa291298c85e14f89aa47a0693837cec6f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/rambi/acpi_tables.c | 147 +--------------- src/mainboard/intel/bayleybay_fsp/acpi_tables.c | 175 +------------------ src/mainboard/intel/minnowmax/acpi_tables.c | 212 +----------------------- src/mainboard/siemens/mc_tcu3/acpi_tables.c | 175 +------------------ src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/acpi.c | 53 +++--- src/soc/intel/baytrail/acpi/globalnvs.asl | 3 +- src/soc/intel/baytrail/include/soc/nvs.h | 1 + src/soc/intel/baytrail/northcluster.c | 2 + src/soc/intel/baytrail/southcluster.c | 30 ++++ src/soc/intel/fsp_baytrail/Kconfig | 1 + src/soc/intel/fsp_baytrail/acpi.c | 93 ++++++++--- src/soc/intel/fsp_baytrail/acpi/globalnvs.asl | 3 +- src/soc/intel/fsp_baytrail/baytrail/acpi.h | 3 + src/soc/intel/fsp_baytrail/baytrail/nvs.h | 1 + src/soc/intel/fsp_baytrail/northcluster.c | 3 +- src/soc/intel/fsp_baytrail/southcluster.c | 6 + 17 files changed, 148 insertions(+), 761 deletions(-) diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index bf2f370..6b47a32 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -34,9 +34,7 @@ #include <soc/nvs.h> #include <soc/iomap.h> -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -68,146 +66,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - /* - * We explicitly add these tables later on: - */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - - /* If we want to use HPET Timers Linux wants an MADT */ - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ - smm_setup_structures(gnvs, NULL, NULL); - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - - printk(BIOS_DEBUG, "current = %lx\n", current); - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c b/src/mainboard/intel/bayleybay_fsp/acpi_tables.c index fd14700..cb63df6 100644 --- a/src/mainboard/intel/bayleybay_fsp/acpi_tables.c +++ b/src/mainboard/intel/bayleybay_fsp/acpi_tables.c @@ -35,10 +35,7 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> - -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -70,173 +67,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *ssdt2; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, - facs->length); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - ALIGN_CURRENT; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, - dsdt->length); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, - fadt->header.length); - - /* - * We explicitly add these tables later on: - */ - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, - hpet->header.length); - - /* If we want to use HPET Timers Linux wants an MADT */ - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, - madt->header.length); - - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, - mcfg->header.length); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ -#if CONFIG_HAVE_SMI_HANDLER - smm_setup_structures(gnvs, NULL, NULL); -#endif - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - ssdt = (acpi_header_t *)current; - memset(ssdt, 0, sizeof(acpi_header_t)); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length) { - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, - ssdt->length); - ALIGN_CURRENT; - } else { - ssdt = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); - } - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - ALIGN_CURRENT; - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c index aa07246..a107fe7 100644 --- a/src/mainboard/intel/minnowmax/acpi_tables.c +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -36,10 +36,7 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> - -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -61,210 +58,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *ssdt2; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, - facs->length); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - ALIGN_CURRENT; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, - dsdt->length); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, - fadt->header.length); - - /* - * We explicitly add these tables later on: - */ - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, - hpet->header.length); - - /* If we want to use HPET Timers Linux wants an MADT */ - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, - madt->header.length); - - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, - mcfg->header.length); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ -#if CONFIG_HAVE_SMI_HANDLER - smm_setup_structures(gnvs, NULL, NULL); -#endif - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - ssdt = (acpi_header_t *)current; - memset(ssdt, 0, sizeof(acpi_header_t)); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length) { - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, - ssdt->length); - ALIGN_CURRENT; - } else { - ssdt = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); - } - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - ALIGN_CURRENT; - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - -#if IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) - printk(BIOS_DEBUG, "rsdp\n"); - hexdump(BIOS_DEBUG, rsdp, sizeof(acpi_rsdp_t)); - - printk(BIOS_DEBUG, "rsdt\n"); - hexdump(BIOS_DEBUG, rsdt, sizeof(acpi_rsdt_t)); - - printk(BIOS_DEBUG, "hpet\n"); - hexdump(BIOS_DEBUG, hpet, hpet->header.length); - - printk(BIOS_DEBUG, "madt\n"); - hexdump(BIOS_DEBUG, madt, madt->header.length); - - printk(BIOS_DEBUG, "mcfg\n"); - hexdump(BIOS_DEBUG, mcfg, mcfg->header.length); - - printk(BIOS_DEBUG, "dsdt\n"); - hexdump(BIOS_DEBUG, dsdt, dsdt->length); - - if (ssdt != NULL) { - printk(BIOS_DEBUG, "ssdt\n"); - hexdump(BIOS_DEBUG, ssdt, ssdt->length); - } - - if (ssdt2 != NULL) { - printk(BIOS_DEBUG, "ssdt2\n"); - hexdump(BIOS_DEBUG, ssdt2, ssdt2->length); - } - - printk(BIOS_DEBUG, "fadt\n"); - hexdump(BIOS_DEBUG, fadt, fadt->header.length); - - printk(BIOS_DEBUG, "facs\n"); - hexdump(BIOS_DEBUG, facs, facs->length); - -#endif /* IS_ENABLED(CONFIG_DUMP_ACPI_TABLES) */ - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/mainboard/siemens/mc_tcu3/acpi_tables.c b/src/mainboard/siemens/mc_tcu3/acpi_tables.c index fd14700..cb63df6 100644 --- a/src/mainboard/siemens/mc_tcu3/acpi_tables.c +++ b/src/mainboard/siemens/mc_tcu3/acpi_tables.c @@ -35,10 +35,7 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> - -extern const unsigned char AmlCode[]; - -static void acpi_create_gnvs(global_nvs_t *gnvs) +void acpi_create_gnvs(global_nvs_t *gnvs) { acpi_init_gnvs(gnvs); @@ -70,173 +67,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - -unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) -{ - generate_cpu_entries(); - return (unsigned long) (acpigen_get_current()); -} - -#define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long write_acpi_tables(unsigned long start) -{ - unsigned long current; - int i; - acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; - acpi_mcfg_t *mcfg; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *ssdt; - acpi_header_t *ssdt2; - acpi_header_t *dsdt; - global_nvs_t *gnvs; - - current = start; - - /* Align ACPI tables to 16byte */ - ALIGN_CURRENT; - - printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); - - /* We need at least an RSDP and an RSDT Table */ - rsdp = (acpi_rsdp_t *) current; - current += sizeof(acpi_rsdp_t); - ALIGN_CURRENT; - rsdt = (acpi_rsdt_t *) current; - current += sizeof(acpi_rsdt_t); - ALIGN_CURRENT; - xsdt = (acpi_xsdt_t *) current; - current += sizeof(acpi_xsdt_t); - ALIGN_CURRENT; - - /* clear all table memory */ - memset((void *) start, 0, current - start); - - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); - - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - ALIGN_CURRENT; - acpi_create_facs(facs); - printk(BIOS_DEBUG, "ACPI: * FACS @ %p Length %x", facs, - facs->length); - - dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - ALIGN_CURRENT; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x", dsdt, - dsdt->length); - - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - ALIGN_CURRENT; - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - printk(BIOS_DEBUG, "ACPI: * FADT @ %p Length %x", fadt, - fadt->header.length); - - /* - * We explicitly add these tables later on: - */ - hpet = (acpi_hpet_t *) current; - current += sizeof(acpi_hpet_t); - ALIGN_CURRENT; - acpi_create_intel_hpet(hpet); - acpi_add_table(rsdp, hpet); - printk(BIOS_DEBUG, "ACPI: * HPET @ %p Length %x\n", hpet, - hpet->header.length); - - /* If we want to use HPET Timers Linux wants an MADT */ - madt = (acpi_madt_t *) current; - acpi_create_madt(madt); - current += madt->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, madt); - printk(BIOS_DEBUG, "ACPI: * MADT @ %p Length %x\n",madt, - madt->header.length); - - mcfg = (acpi_mcfg_t *) current; - acpi_create_mcfg(mcfg); - current += mcfg->header.length; - ALIGN_CURRENT; - acpi_add_table(rsdp, mcfg); - printk(BIOS_DEBUG, "ACPI: * MCFG @ %p Length %x\n",mcfg, - mcfg->header.length); - - /* Update GNVS pointer into CBMEM */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (!gnvs) { - printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); - gnvs = (global_nvs_t *)current; - } - - for (i=0; i < dsdt->length; i++) { - if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { - printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); - *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; - acpi_save_gnvs((unsigned long)gnvs); - break; - } - } - - /* And fill it */ - acpi_create_gnvs(gnvs); - - /* And tell SMI about it */ -#if CONFIG_HAVE_SMI_HANDLER - smm_setup_structures(gnvs, NULL, NULL); -#endif - - current += sizeof(global_nvs_t); - ALIGN_CURRENT; - - /* We patched up the DSDT, so we need to recalculate the checksum */ - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - - printk(BIOS_DEBUG, "ACPI Updated DSDT @ %p Length %x\n", dsdt, - dsdt->length); - - ssdt = (acpi_header_t *)current; - memset(ssdt, 0, sizeof(acpi_header_t)); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length) { - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT @ %p Length %x\n",ssdt, - ssdt->length); - ALIGN_CURRENT; - } else { - ssdt = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT not generated.\n"); - } - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - ALIGN_CURRENT; - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - - printk(BIOS_INFO, "ACPI: done.\n"); - return current; -} diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 85631fc..0240830 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC select SOC_INTEL_COMMON + select PER_DEVICE_ACPI_TABLES config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 74e7336..740b39d 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -295,24 +295,20 @@ static acpi_tstate_t baytrail_tss_table[] = { { 13, 125, 0, 0x12, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set NVS controlled T-state limit */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* Write TSS table for MSR access */ - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) @@ -336,9 +332,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -366,16 +361,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with NVS specified limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, 1, coord_type); + acpigen_write_PSD_package(core, 1, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = 1; @@ -388,14 +383,14 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; control_status = (ratio_turbo << 8) | vid_turbo; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ 10, /*lat1*/ @@ -404,14 +399,14 @@ static int generate_P_state_entries(int core, int cores_per_package) control_status); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); ratio_turbo = ratio_max; vid_turbo = vid_max; } /* First regular entry is max non-turbo ratio */ control_status = (ratio_max << 8) | vid_max; - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ 10, /*lat1*/ @@ -439,7 +434,7 @@ static int generate_P_state_entries(int core, int cores_per_package) clock = (ratio * pattrs->bclk_khz) / 1000; control_status = (ratio << 8) | (vid & 0xff); - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ 10, /*lat1*/ @@ -449,15 +444,12 @@ static int generate_P_state_entries(int core, int cores_per_package) } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } void generate_cpu_entries(void) { - int len_pr, core; + int core; int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); @@ -468,23 +460,22 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( core, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( core, pattrs->num_cpus); /* Generate C-state tables */ - len_pr += acpigen_write_CST_package( + acpigen_write_CST_package( cstate_map, ARRAY_SIZE(cstate_map)); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( core, pattrs->num_cpus); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index a201c03..946f123 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -30,7 +30,8 @@ Name(\PICM, 0) // IOAPIC/8259 */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 1ba30d5..04df736 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -70,6 +70,7 @@ typedef struct { device_nvs_t dev; } __attribute__((packed)) global_nvs_t; +void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 97b3bcc..24fb5fb 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <arch/acpi.h> #include <soc/iomap.h> #include <soc/iosf.h> @@ -133,6 +134,7 @@ static void nc_read_resources(device_t dev) static struct device_operations nc_ops = { .read_resources = nc_read_resources, + .acpi_fill_ssdt_generator = generate_cpu_entries, .set_resources = NULL, .enable_resources = NULL, .init = NULL, diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 8df1f1a..986695f 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -40,6 +40,9 @@ #include <soc/ramstage.h> #include <soc/spi.h> #include "chip.h" +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> static inline void add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) @@ -510,9 +513,36 @@ void southcluster_enable_dev(device_t dev) } } +static void southcluster_inject_dsdt(void) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); + } +} + + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .write_acpi_tables = acpi_write_hpet, .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 4881d8d..86d5b11 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select ROMSTAGE_RTC_INIT + select PER_DEVICE_ACPI_TABLES config SOC_INTEL_FSP_BAYTRAIL_MD bool diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 11c4493..5d561eb 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -47,6 +47,7 @@ #include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/pmc.h> +#include <cpu/cpu.h> #include <cbmem.h> #include "chip.h" @@ -402,9 +403,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static int generate_P_state_entries(int core, int cores_per_package) +static void generate_P_state_entries(int core, int cores_per_package) { - int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; int coord_type, power_max, power_unit, num_entries; int ratio, power, clock, clock_max; @@ -432,16 +432,16 @@ static int generate_P_state_entries(int core, int cores_per_package) power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; /* Write _PCT indicating use of FFixedHW */ - len = acpigen_write_empty_PCT(); + acpigen_write_empty_PCT(); /* Write _PPC with NVS specified limit on supported P-state */ - len += acpigen_write_PPC_NVS(); + acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ - len += acpigen_write_PSD_package(core, 1, coord_type); + acpigen_write_PSD_package(core, 1, coord_type); /* Add P-state entries in _PSS table */ - len += acpigen_write_name("_PSS"); + acpigen_write_name("_PSS"); /* Determine ratio points */ ratio_step = 1; @@ -454,14 +454,14 @@ static int generate_P_state_entries(int core, int cores_per_package) /* P[T] is Turbo state if enabled */ if (get_turbo_state() == TURBO_ENABLED) { /* _PSS package count including Turbo */ - len_pss = acpigen_write_package(num_entries + 2); + acpigen_write_package(num_entries + 2); ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; control_status = (ratio_turbo << 8) | vid_turbo; /* Add entry for Turbo ratio */ - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max + 1, /*MHz*/ power_max, /*mW*/ 10, /*lat1*/ @@ -470,14 +470,14 @@ static int generate_P_state_entries(int core, int cores_per_package) control_status); /*status*/ } else { /* _PSS package count without Turbo */ - len_pss = acpigen_write_package(num_entries + 1); + acpigen_write_package(num_entries + 1); ratio_turbo = ratio_max; vid_turbo = vid_max; } /* First regular entry is max non-turbo ratio */ control_status = (ratio_max << 8) | vid_max; - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock_max, /*MHz*/ power_max, /*mW*/ 10, /*lat1*/ @@ -505,7 +505,7 @@ static int generate_P_state_entries(int core, int cores_per_package) clock = (ratio * pattrs->bclk_khz) / 1000; control_status = (ratio << 8) | (vid & 0xff); - len_pss += acpigen_write_PSS_package( + acpigen_write_PSS_package( clock, /*MHz*/ power, /*mW*/ 10, /*lat1*/ @@ -515,15 +515,12 @@ static int generate_P_state_entries(int core, int cores_per_package) } /* Fix package length */ - len_pss--; - acpigen_patch_len(len_pss); - - return len + len_pss; + acpigen_pop_len(); } void generate_cpu_entries(void) { - int len_pr, core; + int core; int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); @@ -534,23 +531,22 @@ void generate_cpu_entries(void) } /* Generate processor \_PR.CPUx */ - len_pr = acpigen_write_processor( + acpigen_write_processor( core, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + generate_P_state_entries( core, pattrs->num_cpus); /* Generate C-state tables */ - len_pr += acpigen_write_CST_package( + acpigen_write_CST_package( cstate_map, ARRAY_SIZE(cstate_map)); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + generate_T_state_entries( core, pattrs->num_cpus); - len_pr--; - acpigen_patch_len(len_pr); + acpigen_pop_len(); } } @@ -575,3 +571,56 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) return current; } + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) + +unsigned long southcluster_write_acpi_tables(unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_header_t *ssdt2; + + current = acpi_write_hpet(current, rsdp); + ALIGN_CURRENT; + + ssdt2 = (acpi_header_t *)current; + memset(ssdt2, 0, sizeof(acpi_header_t)); + acpi_create_serialio_ssdt(ssdt2); + if (ssdt2->length) { + current += ssdt2->length; + acpi_add_table(rsdp, ssdt2); + printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, + ssdt2->length); + ALIGN_CURRENT; + } else { + ssdt2 = NULL; + printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); + } + + printk(BIOS_DEBUG, "current = %lx\n", current); + + return current; +} + +void southcluster_inject_dsdt(void) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl index 696390d..d2dc021 100644 --- a/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/fsp_baytrail/acpi/globalnvs.asl @@ -30,7 +30,8 @@ Name(\PICM, 0) // IOAPIC/8259 */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/acpi.h b/src/soc/intel/fsp_baytrail/baytrail/acpi.h index aaba61a..ea23974 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/acpi.h +++ b/src/soc/intel/fsp_baytrail/baytrail/acpi.h @@ -29,5 +29,8 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); +unsigned long southcluster_write_acpi_tables(unsigned long current, + struct acpi_rsdp *rsdp); +void southcluster_inject_dsdt(void); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/fsp_baytrail/baytrail/nvs.h b/src/soc/intel/fsp_baytrail/baytrail/nvs.h index 242f6d3..11ad72e 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/nvs.h +++ b/src/soc/intel/fsp_baytrail/baytrail/nvs.h @@ -68,6 +68,7 @@ typedef struct { device_nvs_t dev; } __attribute__((packed)) global_nvs_t; +void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ global_nvs_t *smm_get_gnvs(void); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 2238a8a..460d4be 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -32,7 +32,7 @@ #include <cbmem.h> #include <baytrail/baytrail.h> #include <drivers/intel/fsp1_0/fsp_util.h> - +#include <arch/acpi.h> static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; @@ -201,6 +201,7 @@ static void nc_enable(device_t dev) static struct device_operations nc_ops = { .read_resources = nc_read_resources, + .acpi_fill_ssdt_generator = generate_cpu_entries, .set_resources = NULL, .enable_resources = NULL, .init = NULL, diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index d515286..a64d00f 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -39,10 +39,14 @@ #include <baytrail/irq.h> #include <baytrail/lpc.h> #include <baytrail/nvs.h> +#include <baytrail/acpi.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> #include <baytrail/ramstage.h> #include "chip.h" +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> #define ENABLE_ACPI_MODE_IN_COREBOOT 0 #define TEST_SMM_FLASH_LOCKDOWN 0 @@ -598,6 +602,8 @@ void southcluster_enable_dev(device_t dev) static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, + .acpi_inject_dsdt_generator = southcluster_inject_dsdt, + .write_acpi_tables = southcluster_write_acpi_tables, .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev,

1 0

Patch set updated for coreboot: c6e3cb6 ACPI: slic support
by Vladimir Serbinenko 20 May '15

20 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7202 -gerrit commit c6e3cb6db5d6cbec338eb058af697476babc5da9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 26 20:42:08 2014 +0100 ACPI: slic support Export SLIC table from file in CBFS. Change-Id: Id0e7fe0a49b9cd50b5e43cd15030e1c2098728ec Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 4 --- src/arch/x86/boot/acpi.c | 61 +++++++++++++++++++++++------------ src/arch/x86/boot/tables.c | 6 ++-- src/arch/x86/include/arch/acpi.h | 8 ----- src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/getac/p470/Makefile.inc | 1 - src/mainboard/getac/p470/acpi_slic.c | 38 ---------------------- 7 files changed, 43 insertions(+), 76 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 480b8e9..0149931 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -406,10 +406,6 @@ config HAVE_ACPI_RESUME bool default n -config HAVE_ACPI_SLIC - bool - default n - config HAVE_HARD_RESET bool default n diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index b2e0df3..75d7d2e 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -33,6 +33,7 @@ #include <cbmem.h> #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> +#include <cbfs.h> #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif @@ -501,14 +502,14 @@ void acpi_create_facs(acpi_facs_t *facs) facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */ } -void acpi_write_rsdt(acpi_rsdt_t *rsdt) +static void acpi_write_rsdt(acpi_rsdt_t *rsdt, char *oem_id, char *oem_table_id) { acpi_header_t *header = &(rsdt->header); /* Fill out header fields. */ memcpy(header->signature, "RSDT", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->oem_id, oem_id, 6); + memcpy(header->oem_table_id, oem_table_id, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_rsdt_t); @@ -520,14 +521,14 @@ void acpi_write_rsdt(acpi_rsdt_t *rsdt) header->checksum = acpi_checksum((void *)rsdt, sizeof(acpi_rsdt_t)); } -void acpi_write_xsdt(acpi_xsdt_t *xsdt) +static void acpi_write_xsdt(acpi_xsdt_t *xsdt, char *oem_id, char *oem_table_id) { acpi_header_t *header = &(xsdt->header); /* Fill out header fields. */ memcpy(header->signature, "XSDT", 4); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->oem_id, oem_id, 6); + memcpy(header->oem_table_id, oem_table_id, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_xsdt_t); @@ -539,12 +540,13 @@ void acpi_write_xsdt(acpi_xsdt_t *xsdt) header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t)); } -void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) +static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, + acpi_xsdt_t *xsdt, char *oem_id) { memset(rsdp, 0, sizeof(acpi_rsdp_t)); memcpy(rsdp->signature, RSDP_SIG, 8); - memcpy(rsdp->oem_id, OEM_ID, 6); + memcpy(rsdp->oem_id, oem_id, 6); rsdp->length = sizeof(acpi_rsdp_t); rsdp->rsdt_address = (u32)rsdt; @@ -704,15 +706,15 @@ unsigned long write_acpi_tables(unsigned long start) acpi_xsdt_t *xsdt; acpi_fadt_t *fadt; acpi_facs_t *facs; -#if CONFIG_HAVE_ACPI_SLIC - acpi_header_t *slic; -#endif + acpi_header_t *slic_file, *slic; acpi_header_t *ssdt; acpi_header_t *dsdt; acpi_mcfg_t *mcfg; acpi_madt_t *madt; struct device *dev; unsigned long fw; + size_t slic_size; + char oem_id[6], oem_table_id[8]; current = start; @@ -723,6 +725,22 @@ unsigned long write_acpi_tables(unsigned long start) if (fw) return fw; + slic_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/slic", + CBFS_TYPE_RAW, &slic_size); + if (slic_file && (slic_file->length > slic_size + || slic_file->length < sizeof (acpi_header_t))) { + slic_file = 0; + } + + if (slic_file) { + memcpy(oem_id, slic_file->oem_id, 6); + memcpy(oem_table_id, slic_file->oem_table_id, 8); + } else { + memcpy(oem_id, OEM_ID, 6); + memcpy(oem_table_id, ACPI_TABLE_CREATOR, 8); + } + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); /* We need at least an RSDP and an RSDT Table */ @@ -739,9 +757,9 @@ unsigned long write_acpi_tables(unsigned long start) /* clear all table memory */ memset((void *) start, 0, current - start); - acpi_write_rsdp(rsdp, rsdt, xsdt); - acpi_write_rsdt(rsdt); - acpi_write_xsdt(xsdt); + acpi_write_rsdp(rsdp, rsdt, xsdt, oem_id); + acpi_write_rsdt(rsdt, oem_id, oem_table_id); + acpi_write_xsdt(xsdt, oem_id, oem_table_id); printk(BIOS_DEBUG, "ACPI: * FACS\n"); facs = (acpi_facs_t *) current; @@ -782,13 +800,14 @@ unsigned long write_acpi_tables(unsigned long start) acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(rsdp, fadt); -#if CONFIG_HAVE_ACPI_SLIC - printk(BIOS_DEBUG, "ACPI: * SLIC\n"); - slic = (acpi_header_t *)current; - current += acpi_create_slic(current); - ALIGN_CURRENT; - acpi_add_table(rsdp, slic); -#endif + if (slic_file) { + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + memcpy(slic, slic_file, slic_file->length); + current += slic_file->length; + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); + } printk(BIOS_DEBUG, "ACPI: * SSDT\n"); ssdt = (acpi_header_t *)current; diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 04efd6f..db761bd 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -147,9 +147,9 @@ void write_tables(void) acpi_rsdp_t *low_rsdp = (acpi_rsdp_t *)rom_table_end, *high_rsdp = (acpi_rsdp_t *)acpi_start; - acpi_write_rsdp(low_rsdp, - (acpi_rsdt_t *)(high_rsdp->rsdt_address), - (acpi_xsdt_t *)((unsigned long)high_rsdp->xsdt_address)); + /* Technically rsdp length varies but coreboot always + writes longest size available. */ + memcpy(low_rsdp, high_rsdp, sizeof(acpi_rsdp_t)); } else { printk(BIOS_ERR, "ERROR: Didn't find RSDP in high table.\n"); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 588de93..809c6fa 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -551,14 +551,6 @@ void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment, u8 dev, u8 fn); -#if CONFIG_HAVE_ACPI_SLIC -unsigned long acpi_create_slic(unsigned long current); -#endif - -void acpi_write_rsdt(acpi_rsdt_t *rsdt); -void acpi_write_xsdt(acpi_xsdt_t *xsdt); -void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt); - void acpi_write_hest(acpi_hest_t *hest); unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); unsigned long acpi_fill_hest(acpi_hest_t *hest); diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 919a8ef..3455872 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -35,7 +35,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select HAVE_ACPI_SLIC select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc index ebfdd49..1ba662e 100644 --- a/src/mainboard/getac/p470/Makefile.inc +++ b/src/mainboard/getac/p470/Makefile.inc @@ -17,4 +17,3 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-$(CONFIG_HAVE_ACPI_SLIC) += acpi_slic.c diff --git a/src/mainboard/getac/p470/acpi_slic.c b/src/mainboard/getac/p470/acpi_slic.c deleted file mode 100644 index b042f36..0000000 --- a/src/mainboard/getac/p470/acpi_slic.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> - -static const char slic[0x4] = { - 0x53, 0x4c, 0x49, 0x43 /* incomplete. */ - /* If you wish to compile coreboot images with a windows license key - * built in, you need to extract the ACPI SLIC from your machine and - * add it here. - */ -}; - -unsigned long acpi_create_slic(unsigned long current) -{ - memcpy((void *) current, slic, sizeof(slic)); - return sizeof(slic); -}

1 0

Patch set updated for coreboot: e2f6392 acpigen: Remove all explicit length tracking
by Vladimir Serbinenko 20 May '15

20 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7367 -gerrit commit e2f6392e43e393057b36defeb23dd51ebf66c39c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 03:51:32 2014 +0100 acpigen: Remove all explicit length tracking Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 381 +++++++++++++-------------------- src/arch/x86/include/arch/acpigen.h | 72 +++---- src/cpu/intel/model_2065x/acpi.c | 16 +- src/cpu/intel/model_206ax/acpi.c | 16 +- src/soc/intel/broadwell/acpi.c | 20 +- src/soc/intel/fsp_baytrail/acpi.c | 14 +- src/southbridge/intel/lynxpoint/acpi.c | 8 +- 7 files changed, 212 insertions(+), 315 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 662bc96..bbd5ae1 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -37,13 +37,12 @@ static char *gencurrent; char *len_stack[ACPIGEN_LENSTACK_SIZE]; int ltop = 0; -int acpigen_write_len_f(void) +void acpigen_write_len_f(void) { ASSERT(ltop < (ACPIGEN_LENSTACK_SIZE - 1)) len_stack[ltop++] = gencurrent; acpigen_emit_byte(0); acpigen_emit_byte(0); - return 2; } void acpigen_pop_len(void) @@ -69,31 +68,27 @@ char *acpigen_get_current(void) return gencurrent; } -int acpigen_emit_byte(unsigned char b) +void acpigen_emit_byte(unsigned char b) { (*gencurrent++) = b; - return 1; } -int acpigen_write_package(int nr_el) +void acpigen_write_package(int nr_el) { - int len; /* package op */ acpigen_emit_byte(0x12); - len = acpigen_write_len_f(); + acpigen_write_len_f(); acpigen_emit_byte(nr_el); - return len + 2; } -int acpigen_write_byte(unsigned int data) +void acpigen_write_byte(unsigned int data) { /* byte op */ acpigen_emit_byte(0xa); acpigen_emit_byte(data & 0xff); - return 2; } -int acpigen_write_dword(unsigned int data) +void acpigen_write_dword(unsigned int data) { /* dword op */ acpigen_emit_byte(0xc); @@ -101,10 +96,9 @@ int acpigen_write_dword(unsigned int data) acpigen_emit_byte((data >> 8) & 0xff); acpigen_emit_byte((data >> 16) & 0xff); acpigen_emit_byte((data >> 24) & 0xff); - return 5; } -int acpigen_write_qword(uint64_t data) +void acpigen_write_qword(uint64_t data) { /* qword op */ acpigen_emit_byte(0xe); @@ -116,40 +110,32 @@ int acpigen_write_qword(uint64_t data) acpigen_emit_byte((data >> 40) & 0xff); acpigen_emit_byte((data >> 48) & 0xff); acpigen_emit_byte((data >> 56) & 0xff); - return 9; } -int acpigen_write_name_byte(const char *name, uint8_t val) +void acpigen_write_name_byte(const char *name, uint8_t val) { - int len; - len = acpigen_write_name(name); - len += acpigen_write_byte(val); - return len; + acpigen_write_name(name); + acpigen_write_byte(val); } -int acpigen_write_name_dword(const char *name, uint32_t val) +void acpigen_write_name_dword(const char *name, uint32_t val) { - int len; - len = acpigen_write_name(name); - len += acpigen_write_dword(val); - return len; + acpigen_write_name(name); + acpigen_write_dword(val); } -int acpigen_write_name_qword(const char *name, uint64_t val) +void acpigen_write_name_qword(const char *name, uint64_t val) { - int len; - len = acpigen_write_name(name); - len += acpigen_write_qword(val); - return len; + acpigen_write_name(name); + acpigen_write_qword(val); } -int acpigen_emit_stream(const char *data, int size) +void acpigen_emit_stream(const char *data, int size) { int i; for (i = 0; i < size; i++) { acpigen_emit_byte(data[i]); } - return size; } /* @@ -161,39 +147,36 @@ int acpigen_emit_stream(const char *data, int size) * Check sections 5.3, 18.2.2 and 18.4 of ACPI spec 3.0 for details. */ -static int acpigen_emit_simple_namestring(const char *name) { - int i, len = 0; +static void acpigen_emit_simple_namestring(const char *name) { + int i; char ud[] = "____"; for (i = 0; i < 4; i++) { if ((name[i] == '\0') || (name[i] == '.')) { - len += acpigen_emit_stream(ud, 4 - i); + acpigen_emit_stream(ud, 4 - i); break; } else { - len += acpigen_emit_byte(name[i]); + acpigen_emit_byte(name[i]); } } - return len; } -static int acpigen_emit_double_namestring(const char *name, int dotpos) { - int len = 0; +static void acpigen_emit_double_namestring(const char *name, int dotpos) { /* mark dual name prefix */ - len += acpigen_emit_byte(0x2e); - len += acpigen_emit_simple_namestring(name); - len += acpigen_emit_simple_namestring(&name[dotpos + 1]); - return len; + acpigen_emit_byte(0x2e); + acpigen_emit_simple_namestring(name); + acpigen_emit_simple_namestring(&name[dotpos + 1]); } -static int acpigen_emit_multi_namestring(const char *name) { - int len = 0, count = 0; +static void acpigen_emit_multi_namestring(const char *name) { + int count = 0; unsigned char *pathlen; /* mark multi name prefix */ - len += acpigen_emit_byte(0x2f); - len += acpigen_emit_byte(0x0); + acpigen_emit_byte(0x2f); + acpigen_emit_byte(0x0); pathlen = ((unsigned char *) acpigen_get_current()) - 1; while (name[0] != '\0') { - len += acpigen_emit_simple_namestring(name); + acpigen_emit_simple_namestring(name); /* find end or next entity */ while ((name[0] != '.') && (name[0] != '\0')) name++; @@ -204,32 +187,30 @@ static int acpigen_emit_multi_namestring(const char *name) { } pathlen[0] = count; - return len; } -int acpigen_emit_namestring(const char *namepath) { +void acpigen_emit_namestring(const char *namepath) { int dotcount = 0, i; int dotpos = 0; - int len = 0; /* We can start with a '\'. */ if (namepath[0] == '\\') { - len += acpigen_emit_byte('\\'); + acpigen_emit_byte('\\'); namepath++; } /* And there can be any number of '^' */ while (namepath[0] == '^') { - len += acpigen_emit_byte('^'); + acpigen_emit_byte('^'); namepath++; } /* If we have only \\ or only ^...^. Then we need to put a null name (0x00). */ if(namepath[0] == '\0') { - len += acpigen_emit_byte(0x00); - return len; + acpigen_emit_byte(0x00); + return; } i = 0; @@ -242,58 +223,53 @@ int acpigen_emit_namestring(const char *namepath) { } if (dotcount == 0) { - len += acpigen_emit_simple_namestring(namepath); + acpigen_emit_simple_namestring(namepath); } else if (dotcount == 1) { - len += acpigen_emit_double_namestring(namepath, dotpos); + acpigen_emit_double_namestring(namepath, dotpos); } else { - len += acpigen_emit_multi_namestring(namepath); + acpigen_emit_multi_namestring(namepath); } - return len; } -int acpigen_write_name(const char *name) +void acpigen_write_name(const char *name) { - int len; /* name op */ - len = acpigen_emit_byte(0x8); - return len + acpigen_emit_namestring(name); + acpigen_emit_byte(0x8); + acpigen_emit_namestring(name); } -int acpigen_write_scope(const char *name) +void acpigen_write_scope(const char *name) { - int len; /* scope op */ - len = acpigen_emit_byte(0x10); - len += acpigen_write_len_f(); - return len + acpigen_emit_namestring(name); + acpigen_emit_byte(0x10); + acpigen_write_len_f(); + acpigen_emit_namestring(name); } -int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) +void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) { */ char pscope[16]; - int len; /* processor op */ acpigen_emit_byte(0x5b); acpigen_emit_byte(0x83); - len = acpigen_write_len_f(); + acpigen_write_len_f(); snprintf(pscope, sizeof (pscope), "\\_PR.CP%02d", (unsigned int) cpuindex); - len += acpigen_emit_namestring(pscope); + acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); acpigen_emit_byte((pblock_addr >> 8) & 0xff); acpigen_emit_byte((pblock_addr >> 16) & 0xff); acpigen_emit_byte((pblock_addr >> 24) & 0xff); acpigen_emit_byte(pblock_len); - return 6 + 2 + len; } -int acpigen_write_empty_PCT(void) +void acpigen_write_empty_PCT(void) { /* Name (_PCT, Package (0x02) @@ -326,10 +302,10 @@ int acpigen_write_empty_PCT(void) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */ 0x00, 0x79, 0x00 }; - return acpigen_emit_stream(stream, ARRAY_SIZE(stream)); + acpigen_emit_stream(stream, ARRAY_SIZE(stream)); } -int acpigen_write_empty_PTC(void) +void acpigen_write_empty_PTC(void) { /* Name (_PTC, Package (0x02) @@ -353,7 +329,6 @@ int acpigen_write_empty_PTC(void) } }) */ - int len, nlen, rlen; acpi_addr_t addr = { .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = 0, @@ -365,55 +340,44 @@ int acpigen_write_empty_PTC(void) .addrh = 0, }; - nlen = acpigen_write_name("_PTC"); - len = acpigen_write_package(2); + acpigen_write_name("_PTC"); + acpigen_write_package(2); /* ControlRegister */ - rlen = acpigen_write_resourcetemplate_header(); - rlen += acpigen_write_register(&addr); - len += acpigen_write_resourcetemplate_footer(); - len += rlen; + acpigen_write_resourcetemplate_header(); + acpigen_write_register(&addr); + acpigen_write_resourcetemplate_footer(); /* StatusRegister */ - rlen = acpigen_write_resourcetemplate_header(); - rlen += acpigen_write_register(&addr); - len += acpigen_write_resourcetemplate_footer(); - len += rlen; + acpigen_write_resourcetemplate_header(); + acpigen_write_register(&addr); + acpigen_write_resourcetemplate_footer(); acpigen_pop_len(); - return len + nlen; } -int acpigen_write_method(const char *name, int nargs) +void acpigen_write_method(const char *name, int nargs) { - int len; - /* method op */ - len = acpigen_emit_byte(0x14); - len += acpigen_write_len_f(); - len += acpigen_emit_namestring(name); - len += acpigen_emit_byte(nargs & 7); - - return len; + acpigen_emit_byte(0x14); + acpigen_write_len_f(); + acpigen_emit_namestring(name); + acpigen_emit_byte(nargs & 7); } -int acpigen_write_device(const char *name) +void acpigen_write_device(const char *name) { - int len; - /* method op */ - len = acpigen_emit_byte(0x5b); - len += acpigen_emit_byte(0x82); - len += acpigen_write_len_f(); - len += acpigen_emit_namestring(name); - - return len; + acpigen_emit_byte(0x5b); + acpigen_emit_byte(0x82); + acpigen_write_len_f(); + acpigen_emit_namestring(name); } /* * Generates a func with max supported P-states. */ -int acpigen_write_PPC(u8 nr) +void acpigen_write_PPC(u8 nr) { /* Method (_PPC, 0, NotSerialized) @@ -421,23 +385,19 @@ int acpigen_write_PPC(u8 nr) Return (nr) } */ - int len; - len = acpigen_write_method("_PPC", 0); + acpigen_write_method("_PPC", 0); /* return */ acpigen_emit_byte(0xa4); /* arg */ - len += acpigen_write_byte(nr); - /* add all single bytes */ - len += 1; + acpigen_write_byte(nr); acpigen_pop_len(); - return len; } /* * Generates a func with max supported P-states saved * in the variable PPCM. */ -int acpigen_write_PPC_NVS(void) +void acpigen_write_PPC_NVS(void) { /* Method (_PPC, 0, NotSerialized) @@ -445,20 +405,15 @@ int acpigen_write_PPC_NVS(void) Return (PPCM) } */ - int len; - - len = acpigen_write_method("_PPC", 0); + acpigen_write_method("_PPC", 0); /* return */ acpigen_emit_byte(0xa4); /* arg */ - len += acpigen_emit_namestring("PPCM"); - /* add all single bytes */ - len += 1; + acpigen_emit_namestring("PPCM"); acpigen_pop_len(); - return len; } -int acpigen_write_TPC(const char *gnvs_tpc_limit) +void acpigen_write_TPC(const char *gnvs_tpc_limit) { /* // Sample _TPC method @@ -467,88 +422,68 @@ int acpigen_write_TPC(const char *gnvs_tpc_limit) Return (\TLVL) } */ - int len; - - len = acpigen_write_method("_TPC", 0); - len += acpigen_emit_byte(0xa4); /* ReturnOp */ - len += acpigen_emit_namestring(gnvs_tpc_limit); + acpigen_write_method("_TPC", 0); + acpigen_emit_byte(0xa4); /* ReturnOp */ + acpigen_emit_namestring(gnvs_tpc_limit); acpigen_pop_len(); - return len; } -int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, +void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status) { - int len; - len = acpigen_write_package(6); - len += acpigen_write_dword(coreFreq); - len += acpigen_write_dword(power); - len += acpigen_write_dword(transLat); - len += acpigen_write_dword(busmLat); - len += acpigen_write_dword(control); - len += acpigen_write_dword(status); - // pkglen without the len opcode + acpigen_write_package(6); + acpigen_write_dword(coreFreq); + acpigen_write_dword(power); + acpigen_write_dword(transLat); + acpigen_write_dword(busmLat); + acpigen_write_dword(control); + acpigen_write_dword(status); acpigen_pop_len(); printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n", coreFreq, power, control, status); - - return len; } -int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) +void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) { - int len, lenh, lenp; - lenh = acpigen_write_name("_PSD"); - lenp = acpigen_write_package(1); - len = acpigen_write_package(5); - len += acpigen_write_byte(5); // 5 values - len += acpigen_write_byte(0); // revision 0 - len += acpigen_write_dword(domain); - len += acpigen_write_dword(coordtype); - len += acpigen_write_dword(numprocs); + acpigen_write_name("_PSD"); + acpigen_write_package(1); + acpigen_write_package(5); + acpigen_write_byte(5); // 5 values + acpigen_write_byte(0); // revision 0 + acpigen_write_dword(domain); + acpigen_write_dword(coordtype); + acpigen_write_dword(numprocs); acpigen_pop_len(); - len += lenp; acpigen_pop_len(); - return len + lenh; } -int acpigen_write_CST_package_entry(acpi_cstate_t *cstate) +void acpigen_write_CST_package_entry(acpi_cstate_t *cstate) { - int len, len0; - char *start, *end; - - len0 = acpigen_write_package(4); - len = acpigen_write_resourcetemplate_header(); - start = acpigen_get_current(); + acpigen_write_package(4); + acpigen_write_resourcetemplate_header(); acpigen_write_register(&cstate->resource); - end = acpigen_get_current(); - len += end - start; - len += acpigen_write_resourcetemplate_footer(); - len += len0; - len += acpigen_write_dword(cstate->ctype); - len += acpigen_write_dword(cstate->latency); - len += acpigen_write_dword(cstate->power); + acpigen_write_resourcetemplate_footer(); + acpigen_write_dword(cstate->ctype); + acpigen_write_dword(cstate->latency); + acpigen_write_dword(cstate->power); acpigen_pop_len(); - return len; } -int acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) +void acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) { - int len, lenh, lenp, i; - lenh = acpigen_write_name("_CST"); - lenp = acpigen_write_package(nentries+1); - len = acpigen_write_dword(nentries); + int i; + acpigen_write_name("_CST"); + acpigen_write_package(nentries+1); + acpigen_write_dword(nentries); for (i = 0; i < nentries; i++) - len += acpigen_write_CST_package_entry(cstate + i); + acpigen_write_CST_package_entry(cstate + i); - len += lenp; acpigen_pop_len(); - return len + lenh; } -int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) +void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) { /* Sample _TSS package with 100% and 50% duty cycles @@ -558,48 +493,43 @@ int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) Package(){50, 520, 0, 0x18, 0) }) */ - int i, len, plen, nlen; + int i; acpi_tstate_t *tstate = tstate_list; - nlen = acpigen_write_name("_TSS"); - plen = acpigen_write_package(entries); + acpigen_write_name("_TSS"); + acpigen_write_package(entries); for (i = 0; i < entries; i++) { - len = acpigen_write_package(5); - len += acpigen_write_dword(tstate->percent); - len += acpigen_write_dword(tstate->power); - len += acpigen_write_dword(tstate->latency); - len += acpigen_write_dword(tstate->control); - len += acpigen_write_dword(tstate->status); + acpigen_write_package(5); + acpigen_write_dword(tstate->percent); + acpigen_write_dword(tstate->power); + acpigen_write_dword(tstate->latency); + acpigen_write_dword(tstate->control); + acpigen_write_dword(tstate->status); acpigen_pop_len(); tstate++; - plen += len; } acpigen_pop_len(); - return plen + nlen; } -int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) +void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) { - int len, lenh, lenp; - lenh = acpigen_write_name("_TSD"); - lenp = acpigen_write_package(1); - len = acpigen_write_package(5); - len += acpigen_write_byte(5); // 5 values - len += acpigen_write_byte(0); // revision 0 - len += acpigen_write_dword(domain); - len += acpigen_write_dword(coordtype); - len += acpigen_write_dword(numprocs); + acpigen_write_name("_TSD"); + acpigen_write_package(1); + acpigen_write_package(5); + acpigen_write_byte(5); // 5 values + acpigen_write_byte(0); // revision 0 + acpigen_write_dword(domain); + acpigen_write_dword(coordtype); + acpigen_write_dword(numprocs); acpigen_pop_len(); - len += lenp; acpigen_pop_len(); - return len + lenh; } -int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) +void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) { /* * acpi 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor @@ -621,10 +551,9 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) acpigen_emit_byte((size >> 8) & 0xff); acpigen_emit_byte((size >> 16) & 0xff); acpigen_emit_byte((size >> 24) & 0xff); - return 12; } -int acpigen_write_register(acpi_addr_t *addr) +void acpigen_write_register(acpi_addr_t *addr) { acpigen_emit_byte(0x82); /* Register Descriptor */ acpigen_emit_byte(0x0c); /* Register Length 7:0 */ @@ -641,10 +570,9 @@ int acpigen_write_register(acpi_addr_t *addr) acpigen_emit_byte((addr->addrh >> 8) & 0xff); acpigen_emit_byte((addr->addrh >> 16) & 0xff); acpigen_emit_byte((addr->addrh >> 24) & 0xff); - return 15; } -int acpigen_write_irq(u16 mask) +void acpigen_write_irq(u16 mask) { /* * acpi 3.0b section 6.4.2.1: IRQ Descriptor @@ -656,10 +584,9 @@ int acpigen_write_irq(u16 mask) acpigen_emit_byte(0x22); acpigen_emit_byte(mask & 0xff); acpigen_emit_byte((mask >> 8) & 0xff); - return 3; } -int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) +void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) { /* * acpi 4.0 section 6.4.2.6: I/O Port Descriptor @@ -681,28 +608,25 @@ int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) /* alignment for min base */ acpigen_emit_byte(align & 0xff); acpigen_emit_byte(len & 0xff); - return 8; } -int acpigen_write_resourcetemplate_header(void) +void acpigen_write_resourcetemplate_header(void) { - int len; /* * A ResourceTemplate() is a Buffer() with a * (Byte|Word|DWord) containing the length, followed by one or more * resource items, terminated by the end tag. * (small item 0xf, len 1) */ - len = acpigen_emit_byte(0x11); /* Buffer opcode */ - len += acpigen_write_len_f(); - len += acpigen_emit_byte(0x0b); /* Word opcode */ + acpigen_emit_byte(0x11); /* Buffer opcode */ + acpigen_write_len_f(); + acpigen_emit_byte(0x0b); /* Word opcode */ len_stack[ltop++] = acpigen_get_current(); - len += acpigen_emit_byte(0x00); - len += acpigen_emit_byte(0x00); - return len; + acpigen_emit_byte(0x00); + acpigen_emit_byte(0x00); } -int acpigen_write_resourcetemplate_footer(void) +void acpigen_write_resourcetemplate_footer(void) { char *p = len_stack[--ltop]; int len; @@ -722,7 +646,6 @@ int acpigen_write_resourcetemplate_footer(void) p[1] = (len >> 8) & 0xff; /* patch len field */ acpigen_pop_len(); - return 2; } static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, @@ -744,13 +667,9 @@ static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, } } -int acpigen_write_mainboard_resource_template(void) +void acpigen_write_mainboard_resource_template(void) { - int len; - char *start; - char *end; - len = acpigen_write_resourcetemplate_header(); - start = acpigen_get_current(); + acpigen_write_resourcetemplate_header(); /* Add reserved memory ranges. */ search_global_resources( @@ -764,20 +683,15 @@ int acpigen_write_mainboard_resource_template(void) IORESOURCE_IO | IORESOURCE_RESERVE, acpigen_add_mainboard_rsvd_io, 0); - end = acpigen_get_current(); - len += end-start; - len += acpigen_write_resourcetemplate_footer(); - return len; + acpigen_write_resourcetemplate_footer(); } -int acpigen_write_mainboard_resources(const char *scope, const char *name) +void acpigen_write_mainboard_resources(const char *scope, const char *name) { - int len; - len = acpigen_write_scope(scope); - len += acpigen_write_name(name); - len += acpigen_write_mainboard_resource_template(); + acpigen_write_scope(scope); + acpigen_write_name(name); + acpigen_write_mainboard_resource_template(); acpigen_pop_len(); - return len; } static int hex2bin(const char c) @@ -789,7 +703,7 @@ static int hex2bin(const char c) return c - '0'; } -int acpigen_emit_eisaid(const char *eisaid) +void acpigen_emit_eisaid(const char *eisaid) { u32 compact = 0; @@ -811,5 +725,4 @@ int acpigen_emit_eisaid(const char *eisaid) acpigen_emit_byte((compact >> 16) & 0xff); acpigen_emit_byte((compact >> 8) & 0xff); acpigen_emit_byte(compact & 0xff); - return 5; } diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index e4d6f1e..1ec512f 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -25,47 +25,47 @@ #include <stdint.h> #include <arch/acpi.h> -int acpigen_write_len_f(void); +void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); char *acpigen_get_current(void); -int acpigen_write_package(int nr_el); -int acpigen_write_byte(unsigned int data); -int acpigen_emit_byte(unsigned char data); -int acpigen_emit_stream(const char *data, int size); -int acpigen_emit_namestring(const char *namepath); -int acpigen_emit_eisaid(const char *eisaid); -int acpigen_write_dword(unsigned int data); -int acpigen_write_qword(uint64_t data); -int acpigen_write_name(const char *name); -int acpigen_write_name_dword(const char *name, uint32_t val); -int acpigen_write_name_qword(const char *name, uint64_t val); -int acpigen_write_name_byte(const char *name, uint8_t val); -int acpigen_write_scope(const char *name); -int acpigen_write_method(const char *name, int nargs); -int acpigen_write_device(const char *name); -int acpigen_write_PPC(u8 nr); -int acpigen_write_PPC_NVS(void); -int acpigen_write_empty_PCT(void); -int acpigen_write_empty_PTC(void); -int acpigen_write_TPC(const char *gnvs_tpc_limit); -int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, +void acpigen_write_package(int nr_el); +void acpigen_write_byte(unsigned int data); +void acpigen_emit_byte(unsigned char data); +void acpigen_emit_stream(const char *data, int size); +void acpigen_emit_namestring(const char *namepath); +void acpigen_emit_eisaid(const char *eisaid); +void acpigen_write_dword(unsigned int data); +void acpigen_write_qword(uint64_t data); +void acpigen_write_name(const char *name); +void acpigen_write_name_dword(const char *name, uint32_t val); +void acpigen_write_name_qword(const char *name, uint64_t val); +void acpigen_write_name_byte(const char *name, uint8_t val); +void acpigen_write_scope(const char *name); +void acpigen_write_method(const char *name, int nargs); +void acpigen_write_device(const char *name); +void acpigen_write_PPC(u8 nr); +void acpigen_write_PPC_NVS(void); +void acpigen_write_empty_PCT(void); +void acpigen_write_empty_PTC(void); +void acpigen_write_TPC(const char *gnvs_tpc_limit); +void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; -int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -int acpigen_write_CST_package_entry(acpi_cstate_t *cstate); -int acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); -int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); -int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); -int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); -int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); -int acpigen_write_register(acpi_addr_t *addr); -int acpigen_write_resourcetemplate_header(void); -int acpigen_write_resourcetemplate_footer(void); -int acpigen_write_mainboard_resource_template(void); -int acpigen_write_mainboard_resources(const char *scope, const char *name); -int acpigen_write_irq(u16 mask); +void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); +void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); +void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); +void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); +void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); +void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); +void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); +void acpigen_write_register(acpi_addr_t *addr); +void acpigen_write_resourcetemplate_header(void); +void acpigen_write_resourcetemplate_footer(void); +void acpigen_write_mainboard_resource_template(void); +void acpigen_write_mainboard_resources(const char *scope, const char *name); +void acpigen_write_irq(u16 mask); int get_cst_entries(acpi_cstate_t **); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 8d8757a..b4258c8 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -153,31 +153,27 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 465525b..28bb7dc 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -153,31 +153,27 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index f038e87..a4f80c5 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -365,34 +365,30 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; } -static int generate_C_state_entries(void) +static void generate_C_state_entries(void) { device_t dev = SA_DEV_ROOT; config_t *config = dev->chip_info; @@ -411,7 +407,7 @@ static int generate_C_state_entries(void) } /* Generate C-state tables */ - return acpigen_write_CST_package(map, ARRAY_SIZE(map)); + acpigen_write_CST_package(map, ARRAY_SIZE(map)); } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 5d561eb..b1d3132 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -362,24 +362,20 @@ static acpi_tstate_t baytrail_tss_table[] = { { 13, 125, 0, 0x12, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set NVS controlled T-state limit */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* Write TSS table for MSR access */ - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index d1c8934..731aa2a 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -57,18 +57,18 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } -static int acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) +static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) { char sio_name[5] = {}; snprintf(sio_name, sizeof (sio_name), "S%1uEN", id); - return acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); + acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); } void acpi_create_serialio_ssdt(acpi_header_t *ssdt) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - int id, len = 0; + int id; if (!gnvs) return; @@ -87,7 +87,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) /* Fill the SSDT with an entry for each SerialIO device */ for (id = 0; id < 8; id++) - len += acpi_create_serialio_ssdt_entry(id, gnvs); + acpi_create_serialio_ssdt_entry(id, gnvs); /* (Re)calculate length and checksum. */ current = (unsigned long)acpigen_get_current();

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Patch set updated for coreboot: cdfdd93 acpigen: Remove acpigen_patch_len
by Vladimir Serbinenko 20 May '15

20 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7365 -gerrit commit cdfdd9380f54ed77f76c010eb6ba823b23699899 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 03:33:51 2014 +0100 acpigen: Remove acpigen_patch_len Change-Id: I77276342b3f44c7c845a10682ff1f15599c4c721 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 13 +------------ src/arch/x86/include/arch/acpigen.h | 1 - 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 76fe2d6..662bc96 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -22,7 +22,7 @@ /* * If you need to change this, change acpigen_write_f and - * acpigen_patch_len + * acpigen_pop_len */ #define ACPIGEN_MAXLEN 0xfff @@ -46,17 +46,6 @@ int acpigen_write_len_f(void) return 2; } -void acpigen_patch_len(int len) -{ - ASSERT(len <= ACPIGEN_MAXLEN) - ASSERT(ltop > 0) - char *p = len_stack[--ltop]; - /* generate store length for 0xfff max */ - p[0] = (0x40 | (len & 0xf)); - p[1] = (len >> 4 & 0xff); - -} - void acpigen_pop_len(void) { int len; diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 64f4969..e4d6f1e 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -26,7 +26,6 @@ #include <arch/acpi.h> int acpigen_write_len_f(void); -void acpigen_patch_len(int len); void acpigen_pop_len(void); void acpigen_set_current(char *curr); char *acpigen_get_current(void);

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Patch merged into coreboot/master: 54e6aa7 util/board_status: Fetch and rebase after failed push
by gerrit＠coreboot.org 20 May '15

20 May '15

the following patch was just integrated into master: commit 54e6aa7216a6776daa67c94c97d8568e1d395861 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 20 07:35:56 2015 +0200 util/board_status: Fetch and rebase after failed push Currently, when the remote master branch of the board-status repository changes between cloning and pushing, `git push origin` fails. This race condition happens quite often with REACTS testing commits at the same time on different systems. If that happens, just download the objects and refs from the board-status repository and rebase the local changes on it. Try that three times before exiting with an error message. Change-Id: I628ebce54895f44be6232b622d56acbcc421b847 Helped-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Helped-by: Patrick Georgi <pgeorgi(a)google.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10262 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/10262 for details. -gerrit

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Patch merged into coreboot/master: 16c12c0 Remove unused functions
by gerrit＠coreboot.org 20 May '15

20 May '15

the following patch was just integrated into master: commit 16c12c0a302a64c523e85d90a6f6e0269618093a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu May 21 07:34:53 2015 +0200 Remove unused functions acpi_fill_slit and acpi_fill_srat were removed in commit 5e597572e. Take care of the boards that were added in the mean time. Change-Id: I907e51de5d4ce9acfcce82e6bb30eefff312d35d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10266 for details. -gerrit

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coreboot-gerrit May 2015