coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: b890a12 Remove address from GPLv2 headers
by gerrit＠coreboot.org 21 May '15

21 May '15

the following patch was just integrated into master: commit b890a1228d22b2d48792575986d4750e88751c8b Author: Patrick Georgi <pgeorgi(a)google.com> Date: Thu Mar 26 15:17:45 2015 +0100 Remove address from GPLv2 headers As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/9233 for details. -gerrit

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New patch to review for coreboot: 7c1053f x201: Add TPM declaration.
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10278 -gerrit commit 7c1053fbf245f002cef42c01fe02b3f5e1474a29 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 21 09:28:14 2015 +0200 x201: Add TPM declaration. This allows to deactivate TPM on X201. Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 1 + src/mainboard/lenovo/x201/devicetree.cb | 3 +++ src/mainboard/lenovo/x201/dsdt.asl | 8 ++++++++ src/mainboard/lenovo/x201/romstage.c | 5 +++++ 4 files changed, 17 insertions(+) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 93bfb02..7f96cbe 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 402b9d4..448b2a7 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -154,6 +154,9 @@ chip northbridge/intel/nehalem # DLPC, not connected device pnp 164e.19 off end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 5265a91..b6a563e 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -88,6 +88,14 @@ DefinitionBlock( } } +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + /* Chipset specific sleep states */ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 624440a..09bc189 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -38,6 +38,7 @@ #include <timestamp.h> #include <arch/acpi.h> #include <cbmem.h> +#include <tpm.h> #include "gpio.h" #include "dock.h" @@ -307,5 +308,9 @@ void main(unsigned long bist) } #endif +#if CONFIG_LPC_TPM + init_tpm(s3resume); +#endif + timestamp_add_now(TS_END_ROMSTAGE); }

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Patch set updated for coreboot: 4b2b2da Move TPM code out of chromeos
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10269 -gerrit commit 4b2b2da8953a2e0705a7156cbf69beb20e929aa8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:29:06 2015 +0200 Move TPM code out of chromeos This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 4 +- src/drivers/pc80/tpm/Kconfig | 24 ++- src/drivers/pc80/tpm/Makefile.inc | 1 + src/drivers/pc80/tpm/romstage.c | 236 ++++++++++++++++++++++++++ src/include/tpm.h | 2 + src/mainboard/google/bolt/Kconfig | 1 + src/mainboard/google/butterfly/Kconfig | 1 + src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/link/romstage.c | 9 +- src/mainboard/google/panther/Kconfig | 1 + src/mainboard/google/parrot/Kconfig | 1 + src/mainboard/google/parrot/romstage.c | 8 +- src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/rambi/Kconfig | 1 + src/mainboard/google/samus/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/google/stout/Kconfig | 1 + src/mainboard/google/stout/romstage.c | 8 +- src/mainboard/intel/baskingridge/Kconfig | 1 + src/mainboard/intel/emeraldlake2/romstage.c | 8 +- src/mainboard/intel/wtm2/Kconfig | 1 + src/mainboard/samsung/lumpy/Kconfig | 1 + src/mainboard/samsung/lumpy/romstage.c | 8 +- src/mainboard/samsung/stumpy/Kconfig | 1 + src/mainboard/samsung/stumpy/romstage.c | 8 +- src/soc/intel/baytrail/romstage/romstage.c | 13 +- src/soc/intel/broadwell/romstage/romstage.c | 13 +- src/vendorcode/google/chromeos/Kconfig | 2 + src/vendorcode/google/chromeos/Makefile.inc | 1 - src/vendorcode/google/chromeos/chromeos.h | 4 - src/vendorcode/google/chromeos/vboot.c | 248 ---------------------------- 32 files changed, 308 insertions(+), 304 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8e4335f..c8a9472 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -276,8 +276,8 @@ void romstage_common(const struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(wake_from_s3); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 279da39..46f404e 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -1,5 +1,12 @@ +config MAINBOARD_HAS_LPC_TPM + bool + default n + help + Board has TPM support + config LPC_TPM - bool + bool "Enable TPM support" + depends on MAINBOARD_HAS_LPC_TPM default n help Enable this option to enable LPC TPM support in coreboot. @@ -15,3 +22,18 @@ config TPM_TIS_BASE_ADDRESS The default is specified by the TCG PC Client Specific TPM Interface Specification 1.2 and should not be changed unless the TPM being used does not conform to TPM TIS 1.2. + +config TPM_INIT_FAILURE_IS_FATAL + bool + default n + depends on LPC_TPM + help + What to do if TPM init failed. If true, force a hard reset, + otherwise just log error message to console. + +config SKIP_TPM_STARTUP_ON_NORMAL_BOOT + bool + default n + depends on LPC_TPM + help + Skip TPM init on normal boot. Useful if payload does TPM init. diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc index c900fe8..089d067 100644 --- a/src/drivers/pc80/tpm/Makefile.inc +++ b/src/drivers/pc80/tpm/Makefile.inc @@ -1,2 +1,3 @@ romstage-$(CONFIG_LPC_TPM) += tpm.c ramstage-$(CONFIG_LPC_TPM) += tpm.c +romstage-$(CONFIG_LPC_TPM) += romstage.c diff --git a/src/drivers/pc80/tpm/romstage.c b/src/drivers/pc80/tpm/romstage.c new file mode 100644 index 0000000..b227f6c --- /dev/null +++ b/src/drivers/pc80/tpm/romstage.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console/cbmem_console.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <tpm.h> +#include <reset.h> + +//#define EXTRA_LOGGING + +#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ + +#define TPM_SUCCESS ((u32)0x00000000) + +#define TPM_E_IOERROR ((u32)0x0000001f) +#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) +#define TPM_E_NON_FATAL ((u32)0x00000800) +#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) + +#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) +#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) + +static const struct { + u8 buffer[12]; +} tpm_resume_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } +}; + +static const struct { + u8 buffer[12]; +} tpm_startup_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1 } +}; + +static const struct { + u8 buffer[10]; +} tpm_continueselftest_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } +}; + +static inline void FromTpmUint32(const u8 * buffer, u32 * x) +{ + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); +} + +static inline int TpmCommandSize(const u8 * buffer) +{ + u32 size; + FromTpmUint32(buffer + sizeof(u16), &size); + return (int)size; +} + +/* Gets the code field of a TPM command. */ +static inline int TpmCommandCode(const u8 * buffer) +{ + u32 code; + FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); + return code; +} + +/* Gets the return code field of a TPM result. */ +static inline int TpmReturnCode(const u8 * buffer) +{ + return TpmCommandCode(buffer); +} + +/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or + * DOING_SELFTEST errors are returned. + */ +static u32 TlclSendReceiveNoRetry(const u8 * request, + u8 * response, int max_length) +{ + size_t response_length = max_length; + u32 result; + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", + request[0], request[1], + request[2], request[3], request[4], request[5], + request[6], request[7], request[8], request[9]); +#endif + + result = TPM_SUCCESS; + if (tis_sendrecv + (request, TpmCommandSize(request), response, &response_length)) + result = TPM_E_IOERROR; + + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + printk(BIOS_DEBUG, + "TPM: command 0x%x send/receive failed: 0x%x\n", + TpmCommandCode(request), result); + return TPM_E_COMMUNICATION_ERROR; + } + /* Otherwise, use the result code from the response */ + result = TpmReturnCode(response); + +/* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", + response[0], response[1], + response[2], response[3], response[4], response[5], + response[6], response[7], response[8], response[9]); +#endif + + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", + TpmCommandCode(request), result); + + return result; +} + +static inline u32 TlclContinueSelfTest(void) +{ + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + printk(BIOS_DEBUG, "TPM: Continue self test\n"); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); +} + +/* Sends a TPM command and gets a response. Returns 0 if success or the TPM + * error code if error. In the firmware, waits for the self test to complete + * if needed. In the host, reports the first error without retries. */ +static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) +{ + u32 result = TlclSendReceiveNoRetry(request, response, max_length); + /* When compiling for the firmware, hide command failures due to the self + * test not having run or completed. */ + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = TlclContinueSelfTest(); + if (result != TPM_SUCCESS) { + return result; + } +#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) + /* Retry only once */ + result = TlclSendReceiveNoRetry(request, response, max_length); +#else + /* This needs serious testing. The TPM specification says: + * "iii. The caller MUST wait for the actions of + * TPM_ContinueSelfTest to complete before reissuing the + * command C1." But, if ContinueSelfTest is non-blocking, how + * do we know that the actions have completed other than trying + * again? */ + do { + result = + TlclSendReceiveNoRetry(request, response, + max_length); + } while (result == TPM_E_DOING_SELFTEST); +#endif + } + + return result; +} + +void init_tpm(int s3resume) +{ + u32 result; + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + + /* Doing TPM startup when we're not coming in on the S3 resume path + * saves us roughly 20ms in boot time only. This does not seem to + * be worth an API change to vboot_reference-firmware right now, so + * let's keep the code around, but just bail out early: + */ + if (s3resume ? CONFIG_NO_TPM_RESUME + : CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT) + return; + + printk(BIOS_DEBUG, "TPM initialization.\n"); + + printk(BIOS_SPEW, "TPM: Init\n"); + if (tis_init()) + return; + + printk(BIOS_SPEW, "TPM: Open\n"); + if (tis_open()) + return; + + + if (s3resume) { + /* S3 Resume */ + printk(BIOS_SPEW, "TPM: Resume\n"); + result = TlclSendReceive(tpm_resume_cmd.buffer, + response, sizeof(response)); + if (result == TPM_E_INVALID_POSTINIT) { + /* We're on a platform where the TPM maintains power + * in S3, so it's already initialized. + */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return; + } + } else { + printk(BIOS_SPEW, "TPM: Startup\n"); + result = TlclSendReceive(tpm_startup_cmd.buffer, + response, sizeof(response)); + } + + if (result == TPM_SUCCESS) { + printk(BIOS_SPEW, "TPM: OK.\n"); + return; + } + + printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); + + if (CONFIG_TPM_INIT_FAILURE_IS_FATAL) { + printk(BIOS_ERR, "Hard reset!\n"); + post_code(POST_TPM_FAILURE); + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); + hard_reset(); + } +} diff --git a/src/include/tpm.h b/src/include/tpm.h index e25ad6a..c33c9c1 100644 --- a/src/include/tpm.h +++ b/src/include/tpm.h @@ -66,4 +66,6 @@ int tis_close(void); int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf, size_t *recv_len); +void init_tpm(int s3resume); + #endif /* TPM_H_ */ diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 2239f70..74e1edd 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 7472c06..b1a64ee 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index a8faaab..5b97259 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 316434f..0f70925 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 5844aa6..5a1057e 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -41,9 +41,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <tpm.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> @@ -246,8 +244,9 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif + timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 31062ed..37a8548 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select PHYSICAL_REC_SWITCH diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 07405c6..9cf390a 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ab82bde..046a77f 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #include <cbfs.h> +#include <tpm.h> #include "ec/compal/ene932/ec.h" static void pch_enable_lpc(void) @@ -197,8 +195,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index d6a208b..2c1560a 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 4c9e891..1130d11 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select ALWAYS_LOAD_OPROM select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index f655b29..06317e9 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index fd4cb2f..cfbce5e 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_DP select INTEL_DDI diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index ec03d87..eca83da 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 6a6aa48..e2a4243 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -40,9 +40,7 @@ #include <halt.h> #include "gpio.h" #include <bootmode.h> -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <tpm.h> #include <cbfs.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -251,8 +249,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index c3e3361..f916138 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 45d92d8..6e3af79 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> +#include <tpm.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #define SIO_PORT 0x164e @@ -255,8 +253,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 5a064d1..b8f616a 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 7c9dce4..fed4610 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select CPU_INTEL_SOCKET_RPGA989 select EC_SMSC_MEC1308 select HAVE_ACPI_RESUME diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 29a238a..4666584 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,6 +32,7 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> +#include <tpm.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -45,9 +46,6 @@ #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif static void pch_enable_lpc(void) { @@ -273,8 +271,8 @@ void main(unsigned long bist) } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 1eda8eb..f749c39 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select CPU_INTEL_SOCKET_RPGA989 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 346026f..2844908 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -41,13 +41,11 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> +#include <tpm.h> #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif /* Stumpy USB Reset Disable defined in cmos.layout */ #if CONFIG_USE_OPTION_TABLE @@ -283,8 +281,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 9c8bbc4..20107e8 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -33,6 +33,7 @@ #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> +#include <tpm.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -211,14 +212,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) return prev_sleep_state; } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ - init_chromeos(prev_sleep_state == 3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -250,7 +243,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(prev_sleep_state); +#if CONFIG_LPC_TPM + init_tpm(prev_sleep_state == 3); +#endif } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index c026004..11f4688 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -29,6 +29,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> +#include <tpm.h> #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> @@ -89,14 +90,6 @@ void * asmlinkage romstage_main(unsigned long bist, return setup_stack_and_mttrs(); } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */ - init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -132,7 +125,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(params->power_state->prev_sleep_state); +#if CONFIG_LPC_TPM + init_tpm(prev_sleep_state == SLEEP_STATE_S3); +#endif } void asmlinkage romstage_after_car(void) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 90e3505..34a19ba 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -26,6 +26,8 @@ config CHROMEOS bool "Build for ChromeOS" default n select TPM + select TPM_INIT_FAILURE_IS_FATAL + select SKIP_TPM_STARTUP_ON_NORMAL_BOOT select BOOTMODE_STRAPS select ELOG help diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 7c41ec8..0384feb 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -32,7 +32,6 @@ verstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c romstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c -romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c verstage-y += fmap.c diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a87fbdf..a999798 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -39,9 +39,6 @@ void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); #if CONFIG_CHROMEOS -/* functions implemented in vboot.c */ -void init_chromeos(int bootmode); - /* functions implemented in elog.c */ void elog_add_boot_reason(void); @@ -53,7 +50,6 @@ int vboot_enable_developer(void); int vboot_enable_recovery(void); int vboot_skip_display_init(void); #else -static inline void init_chromeos(int bootmode) { } static inline void elog_add_boot_reason(void) { return; } static inline void elog_add_watchdog_reset(void) { return; } static inline void reboot_from_watchdog(void) { return; } diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c deleted file mode 100644 index 7216373..0000000 --- a/src/vendorcode/google/chromeos/vboot.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <console/cbmem_console.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <tpm.h> -#include <reset.h> -#include "chromeos.h" - -//#define EXTRA_LOGGING -#define UBOOT_DOES_TPM_STARTUP - -#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ - -#define TPM_SUCCESS ((u32)0x00000000) - -#define TPM_E_IOERROR ((u32)0x0000001f) -#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) -#define TPM_E_NON_FATAL ((u32)0x00000800) -#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) - -#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) -#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) - -#if CONFIG_NO_TPM_RESUME -static void init_vboot(int bootmode) -{ -} -#else -static const struct { - u8 buffer[12]; -} tpm_resume_cmd = { - { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } -}; - -static const struct { - u8 buffer[12]; -} tpm_startup_cmd = { - {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1 } -}; - -static const struct { - u8 buffer[10]; -} tpm_continueselftest_cmd = { - { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } -}; - -static inline void FromTpmUint32(const u8 * buffer, u32 * x) -{ - *x = ((buffer[0] << 24) | - (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); -} - -static inline int TpmCommandSize(const u8 * buffer) -{ - u32 size; - FromTpmUint32(buffer + sizeof(u16), &size); - return (int)size; -} - -/* Gets the code field of a TPM command. */ -static inline int TpmCommandCode(const u8 * buffer) -{ - u32 code; - FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); - return code; -} - -/* Gets the return code field of a TPM result. */ -static inline int TpmReturnCode(const u8 * buffer) -{ - return TpmCommandCode(buffer); -} - -/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or - * DOING_SELFTEST errors are returned. - */ -static u32 TlclSendReceiveNoRetry(const u8 * request, - u8 * response, int max_length) -{ - size_t response_length = max_length; - u32 result; - -#ifdef EXTRA_LOGGING - printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", - request[0], request[1], - request[2], request[3], request[4], request[5], - request[6], request[7], request[8], request[9]); -#endif - - result = TPM_SUCCESS; - if (tis_sendrecv - (request, TpmCommandSize(request), response, &response_length)) - result = TPM_E_IOERROR; - - if (0 != result) { - /* Communication with TPM failed, so response is garbage */ - printk(BIOS_DEBUG, - "TPM: command 0x%x send/receive failed: 0x%x\n", - TpmCommandCode(request), result); - return TPM_E_COMMUNICATION_ERROR; - } - /* Otherwise, use the result code from the response */ - result = TpmReturnCode(response); - -/* TODO: add paranoia about returned response_length vs. max_length - * (and possibly expected length from the response header). See - * crosbug.com/17017 */ - -#ifdef EXTRA_LOGGING - printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", - response[0], response[1], - response[2], response[3], response[4], response[5], - response[6], response[7], response[8], response[9]); -#endif - - printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", - TpmCommandCode(request), result); - - return result; -} - -static inline u32 TlclContinueSelfTest(void) -{ - u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - printk(BIOS_DEBUG, "TPM: Continue self test\n"); - /* Call the No Retry version of SendReceive to avoid recursion. */ - return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, - response, sizeof(response)); -} - -/* Sends a TPM command and gets a response. Returns 0 if success or the TPM - * error code if error. In the firmware, waits for the self test to complete - * if needed. In the host, reports the first error without retries. */ -static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) -{ - u32 result = TlclSendReceiveNoRetry(request, response, max_length); - /* When compiling for the firmware, hide command failures due to the self - * test not having run or completed. */ - /* If the command fails because the self test has not completed, try it - * again after attempting to ensure that the self test has completed. */ - if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { - result = TlclContinueSelfTest(); - if (result != TPM_SUCCESS) { - return result; - } -#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) - /* Retry only once */ - result = TlclSendReceiveNoRetry(request, response, max_length); -#else - /* This needs serious testing. The TPM specification says: - * "iii. The caller MUST wait for the actions of - * TPM_ContinueSelfTest to complete before reissuing the - * command C1." But, if ContinueSelfTest is non-blocking, how - * do we know that the actions have completed other than trying - * again? */ - do { - result = - TlclSendReceiveNoRetry(request, response, - max_length); - } while (result == TPM_E_DOING_SELFTEST); -#endif - } - - return result; -} - -static void init_vboot(int bootmode) -{ - u32 result; - u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - -#ifdef UBOOT_DOES_TPM_STARTUP - /* Doing TPM startup when we're not coming in on the S3 resume path - * saves us roughly 20ms in boot time only. This does not seem to - * be worth an API change to vboot_reference-firmware right now, so - * let's keep the code around, but just bail out early: - */ - if (bootmode != 2) - return; -#endif - - printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); - - printk(BIOS_SPEW, "TPM: Init\n"); - if (tis_init()) - return; - - printk(BIOS_SPEW, "TPM: Open\n"); - if (tis_open()) - return; - - - if (bootmode == 2) { - /* S3 Resume */ - printk(BIOS_SPEW, "TPM: Resume\n"); - result = TlclSendReceive(tpm_resume_cmd.buffer, - response, sizeof(response)); - if (result == TPM_E_INVALID_POSTINIT) { - /* We're on a platform where the TPM maintains power - * in S3, so it's already initialized. - */ - printk(BIOS_DEBUG, "TPM: Already initialized.\n"); - return; - } - } else { - printk(BIOS_SPEW, "TPM: Startup\n"); - result = TlclSendReceive(tpm_startup_cmd.buffer, - response, sizeof(response)); - } - - if (result == TPM_SUCCESS) { - printk(BIOS_SPEW, "TPM: OK.\n"); - return; - } - -#if !MOCK_TPM - printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); - post_code(POST_TPM_FAILURE); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) - cbmem_dump_console(); - hard_reset(); -#endif -} -#endif - -void init_chromeos(int bootmode) -{ - init_vboot(bootmode); -}

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Patch set updated for coreboot: 0effa74 Deactivate TPM
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10270 -gerrit commit 0effa741f38d8dd2a575bb0b21d479cb2d0d5c69 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:46:57 2015 +0200 Deactivate TPM Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/pc80/tpm/Kconfig | 7 +++++++ src/drivers/pc80/tpm/acpi/tpm.asl | 10 +++++----- src/drivers/pc80/tpm/romstage.c | 19 +++++++++++++++++++ 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 46f404e..8c64b0d 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -37,3 +37,10 @@ config SKIP_TPM_STARTUP_ON_NORMAL_BOOT depends on LPC_TPM help Skip TPM init on normal boot. Useful if payload does TPM init. + +config TPM_DEACTIVATE + bool "Deactivate TPM" + default n + depends on LPC_TPM + help + Deactivate TPM by issuing deactivate command. diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl index 7500211..e6c28db 100644 --- a/src/drivers/pc80/tpm/acpi/tpm.asl +++ b/src/drivers/pc80/tpm/acpi/tpm.asl @@ -27,11 +27,11 @@ Device (TPM) Method (_STA, 0) { - If (CONFIG_LPC_TPM) { - Return (0xf) - } Else { - Return (0x0) - } +#if CONFIG_LPC_TPM && !CONFIG_TPM_DEACTIVATE + Return (0xf) +#else + Return (0x0) +#endif } Name (IBUF, ResourceTemplate () diff --git a/src/drivers/pc80/tpm/romstage.c b/src/drivers/pc80/tpm/romstage.c index b227f6c..0e4fe6f 100644 --- a/src/drivers/pc80/tpm/romstage.c +++ b/src/drivers/pc80/tpm/romstage.c @@ -51,6 +51,12 @@ static const struct { }; static const struct { + u8 buffer[12]; +} tpm_deactivate_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x3 } +}; + +static const struct { u8 buffer[10]; } tpm_continueselftest_cmd = { { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } @@ -181,6 +187,19 @@ void init_tpm(int s3resume) u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + if (CONFIG_TPM_DEACTIVATE) { + printk(BIOS_SPEW, "TPM: Deactivate\n"); + result = TlclSendReceive(tpm_deactivate_cmd.buffer, + response, sizeof(response)); + if (result == TPM_SUCCESS) { + printk(BIOS_SPEW, "TPM: OK.\n"); + return; + } + + printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); + return; + } + /* Doing TPM startup when we're not coming in on the S3 resume path * saves us roughly 20ms in boot time only. This does not seem to * be worth an API change to vboot_reference-firmware right now, so

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Patch set updated for coreboot: c599e01 Hide TPM_TIS_BASE_ADDRESS
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10271 -gerrit commit c599e01f18c92bef33ff45b03223ea5f24982540 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 20 12:05:39 2015 +0200 Hide TPM_TIS_BASE_ADDRESS TPM_TIS_BASE_ADDRESS is technical setting, shouldn't be user-visible. Change-Id: Ibf74f52be16fb7d2cfa78419087a4c3e7607368a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/pc80/tpm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 8c64b0d..1483871 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -14,7 +14,7 @@ config LPC_TPM If unsure, say N. config TPM_TIS_BASE_ADDRESS - hex "TPM Base Address" + hex default 0xfed40000 depends on LPC_TPM help

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Patch set updated for coreboot: 9394d31 Add TCPA table.
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10274 -gerrit commit 9394d314f03356f164a83f0838905975f4116a59 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 20 19:52:01 2015 +0200 Add TCPA table. This allows SeaBIOS to fill it as necessarry. This is the last step to make BitLocker work. Change-Id: I35858cd31a90c799ee1a240547c4b4a80fa13dd8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 69 ++++++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 7 ++++ src/include/cbmem.h | 1 + 3 files changed, 77 insertions(+) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index b2e0df3..4d7fb27 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -249,6 +249,65 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) header->checksum = acpi_checksum((void *)mcfg, header->length); } +#if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static void *get_tcpa_log(u32 *size) +{ + const struct cbmem_entry *ce; + const u32 tcpa_default_log_len = 0x10000; + void *lasa; + ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); + if (ce) { + lasa = cbmem_entry_start(ce); + *size = cbmem_entry_size(ce); + printk(BIOS_DEBUG, "TCPA log found at %p\n", lasa); + return lasa; + } + lasa = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_default_log_len); + if (!lasa) { + printk(BIOS_ERR, "TCPA log creation failed\n"); + return NULL; + } + + printk(BIOS_DEBUG, "TCPA log created at %p\n", lasa); + memset (lasa, 0, tcpa_default_log_len); + + *size = tcpa_default_log_len; + return lasa; +} + +static void acpi_create_tcpa(acpi_tcpa_t *tcpa) +{ + acpi_header_t *header = &(tcpa->header); + u32 tcpa_log_len; + void *lasa; + + memset((void *)tcpa, 0, sizeof(acpi_tcpa_t)); + + lasa = get_tcpa_log(&tcpa_log_len); + if (!lasa) { + return; + } + + /* Fill out header fields. */ + memcpy(header->signature, "TCPA", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_tcpa_t); + header->revision = 2; + + tcpa->platform_class = 0; + tcpa->laml = tcpa_log_len; + tcpa->lasa = (u32) lasa; + + /* Calculate checksum. */ + header->checksum = acpi_checksum((void *)tcpa, header->length); +} + +#endif + #if !IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) /* * This can be overridden by platform ACPI setup code, if it calls @@ -710,6 +769,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *dsdt; acpi_mcfg_t *mcfg; + acpi_tcpa_t *tcpa; acpi_madt_t *madt; struct device *dev; unsigned long fw; @@ -808,6 +868,15 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, mcfg); } + printk(BIOS_DEBUG, "ACPI: * TCPA\n"); + tcpa = (acpi_tcpa_t *) current; + acpi_create_tcpa(tcpa); + if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { + current += tcpa->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, tcpa); + } + printk(BIOS_DEBUG, "ACPI: * MADT\n"); madt = (acpi_madt_t *) current; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 588de93..938b663 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -129,6 +129,13 @@ typedef struct acpi_mcfg { u8 reserved[8]; } __attribute__ ((packed)) acpi_mcfg_t; +typedef struct acpi_tcpa { + struct acpi_table_header header; + u16 platform_class; + u32 laml; + u64 lasa; +} __attribute__ ((packed)) acpi_tcpa_t; + typedef struct acpi_mcfg_mmconfig { u32 base_address; u32 base_reserved; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 08c1d64..cacbc9d 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -86,6 +86,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 +#define CBMEM_ID_TCPA_LOG 0x54435041 #ifndef __ASSEMBLER__ #include <stddef.h>

1 0

Patch set updated for coreboot: d287fad x230: Add TPM declaration.
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10273 -gerrit commit d287fad62a4872dd1f79ecb371276e28860e6617 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 13 17:47:58 2015 +0200 x230: Add TPM declaration. This allows to deactivate TPM on X230. Change-Id: I73d4272da62335ec3766ce4814d5b46538b190fe Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/Kconfig | 1 + src/mainboard/lenovo/x230/devicetree.cb | 4 ++++ src/mainboard/lenovo/x230/dsdt.asl | 8 ++++++++ 3 files changed, 13 insertions(+) diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 05b7506..1551e27 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 + select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 55677a3..c8274e2 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -128,6 +128,10 @@ chip northbridge/intel/sandybridge register "dock_event_enable" = "0x01" end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 85e2b4f..7db79af 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -50,6 +50,14 @@ DefinitionBlock( #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>

1 0

Patch set updated for coreboot: c0de705 sandybridge native: Add call to TPM code.
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10272 -gerrit commit c0de705cbbf8052f17a7a71323432f44d92cdddb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:31:35 2015 +0200 sandybridge native: Add call to TPM code. This allows to deactivate TPM on boards using native sandy/ivy init. Change-Id: I9455179c7b51097a3a9554c16a407365fbc65e6f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/romstage_native.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 332d9ba..84c2f58 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -32,6 +32,7 @@ #include <device/pci_def.h> #include <device/device.h> #include <halt.h> +#include <tpm.h> #include "raminit_native.h" #include <northbridge/intel/sandybridge/chip.h> #include "southbridge/intel/bd82x6x/pch.h" @@ -129,6 +130,10 @@ void main(unsigned long bist) northbridge_romstage_finalize(s3resume); +#if CONFIG_LPC_TPM + init_tpm(s3resume); +#endif + post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); }

1 0

New patch to review for coreboot: fdfa80a MAINTAINERS: grab build system responsibility
by Patrick Georgi 21 May '15

21 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10277 -gerrit commit fdfa80a751ab70f50672ba616391659c61266b54 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu May 21 18:54:10 2015 +0200 MAINTAINERS: grab build system responsibility Since nobody else stepped up, I hereby claim responsibility for the build system. Change-Id: I580b906d15fc2f049f0072e7b4608b1f19db83ab Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b054f4d..bd49c41 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -139,6 +139,14 @@ M: Patrick Georgi <patrick(a)georgi-clan.de> S: Supported F: util/lint/ +BUILD SYSTEM +M: Patrick Georgi <patrick(a)georgi-clan.de> +S: Supported +F: Makefile +F: *.inc +F: util/kconfig +F: util/sconfig + THE REST M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> L: coreboot(a)coreboot.org

1 0

Patch merged into coreboot/master: 537283d lenovo: Remerge smbios_mainboard_bios_version.
by gerrit＠coreboot.org 21 May '15

21 May '15

the following patch was just integrated into master: commit 537283ddc55549b5fa0f1ba05f2b447a0cd9478f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 21 09:51:00 2015 +0200 lenovo: Remerge smbios_mainboard_bios_version. Change-Id: I8df5b7f6707957b925f7bb4dc06a717252c70868 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10275 Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10275 for details. -gerrit

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