coreboot-gerrit May 2015

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Patch set updated for coreboot: b9fbfcc assets: abstract away the firmware assets used for booting
by Aaron Durbin 21 May '15

21 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10264 -gerrit commit b9fbfcc903849da8d13787fb1f69b915f90a8056 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 20 12:08:55 2015 -0500 assets: abstract away the firmware assets used for booting As there can be more than one source of firmware assets this patch generalizes the notion of locating a particular asset. struct asset is added along with some helper functions for working on assets as a first class citizen. Change-Id: I2ce575d1e5259aed4c34c3dcfd438abe9db1d7b9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/boot.c | 2 +- src/arch/x86/boot/boot.c | 2 +- src/include/assets.h | 90 +++++++++++++++++++++ src/include/program_loading.h | 54 ++++++++----- src/lib/Makefile.inc | 4 + src/lib/assets.c | 93 ++++++++++++++++++++++ src/lib/cbfs.c | 8 +- src/lib/prog_loaders.c | 90 ++------------------- src/lib/rmodule.c | 6 +- src/lib/selfboot.c | 9 ++- src/soc/intel/baytrail/refcode.c | 6 +- src/soc/intel/broadwell/refcode.c | 6 +- .../google/chromeos/vboot2/vboot_loader.c | 48 +++++------ 13 files changed, 269 insertions(+), 149 deletions(-) diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 226d8d7..03ad053 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -73,7 +73,7 @@ void arch_prog_run(struct prog *prog) void (*doit)(void *); void *arg; - if (ENV_RAMSTAGE && prog->type == PROG_PAYLOAD) { + if (ENV_RAMSTAGE && prog_type(prog) == ASSET_PAYLOAD) { run_payload(prog); return; } diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 0ff8a6c..d86a6c3 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -125,7 +125,7 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) static void try_payload(struct prog *prog) { - if (prog->type == PROG_PAYLOAD) { + if (prog_type(prog) == ASSET_PAYLOAD) { if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) jmp_payload_no_bounce_buffer(prog_entry(prog)); else diff --git a/src/include/assets.h b/src/include/assets.h new file mode 100644 index 0000000..7b08054 --- /dev/null +++ b/src/include/assets.h @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#ifndef ASSETS_H +#define ASSETS_H + +#include <region.h> + +/* An asset represents data used to boot the system. It can be found within + * CBFS or some other mechanism. While CBFS can be a source of an asset, note + * that using the asset API implies querying of other sources. */ + +enum asset_type { + ASSET_UNKNOWN, + ASSET_VERSTAGE, + ASSET_ROMSTAGE, + ASSET_RAMSTAGE, + ASSET_REFCODE, + ASSET_PAYLOAD, +}; + +struct asset { + enum asset_type type; + const char *name; + struct region_device rdev; +}; + +static inline const char *asset_name(const struct asset *asset) +{ + return asset->name; +} + +static inline enum asset_type asset_type(const struct asset *asset) +{ + return asset->type; +} + +static struct region_device *asset_rdev(struct asset *asset) +{ + return &asset->rdev; +} + +static inline size_t asset_size(const struct asset *asset) +{ + return region_device_sz(&asset->rdev); +} + +/* Returns NULL on error. */ +static inline void *asset_mmap(const struct asset *asset) +{ + return rdev_mmap_full(&asset->rdev); +} + +#define ASSET_INIT(type_, name_) \ + { \ + .type = (type_), \ + .name = (name_), \ + } + +/* Locate the asset as described by the parameter. It will query all known + * asset providers. Returns 0 on success. < 0 on error. */ +int asset_locate(struct asset *asset); + +struct asset_provider { + const char *name; + /* Determines if the provider is the active one. If so returns 1 else 0 + * or < 0 on error. */ + int (*is_active)(struct asset *asset); + /* Returns < 0 on error or 0 on success. This function locates + * the rdev representing the file data associated with the passed in + * prog. */ + int (*locate)(struct asset *asset); +}; + +#endif /* ASSETS_H */ diff --git a/src/include/program_loading.h b/src/include/program_loading.h index d8e7de3..49a36fa 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -22,7 +22,7 @@ #include <stdint.h> #include <stddef.h> -#include <region.h> +#include <assets.h> enum { /* Last segment of program. Can be used to take different actions for @@ -34,39 +34,49 @@ enum { * set on the last segment loaded. */ void arch_segment_loaded(uintptr_t start, size_t size, int flags); -enum prog_type { - PROG_VERSTAGE, - PROG_ROMSTAGE, - PROG_RAMSTAGE, - PROG_REFCODE, - PROG_PAYLOAD, -}; - /* Representation of a program. */ struct prog { - enum prog_type type; - const char *name; - /* Source of program content to load. After loading program it - * represents the memory region of the stages and payload. For - * achitectures that use a bounce buffer then it would represent - * the bounce buffer. */ - struct region_device rdev; + /* The region_device within the asset is the source of program content + * to load. After loading program it represents the memory region of + * the stages and payload. For achitectures that use a bounce buffer + * then it would represent the bounce buffer. */ + struct asset asset; /* Entry to program with optional argument. It's up to the architecture * to decide if argument is passed. */ void (*entry)(void *); void *arg; }; +#define PROG_INIT(type_, name_) \ + { \ + .asset = ASSET_INIT(type_, name_), \ + } + +static inline const char *prog_name(const struct prog *prog) +{ + return asset_name(&prog->asset); +} + +static inline enum asset_type prog_type(const struct prog *prog) +{ + return asset_type(&prog->asset); +} + +static inline struct region_device *prog_rdev(struct prog *prog) +{ + return asset_rdev(&prog->asset); +} + /* Only valid for loaded programs. */ static inline size_t prog_size(const struct prog *prog) { - return region_device_sz(&prog->rdev); + return asset_size(&prog->asset); } /* Only valid for loaded programs. */ static inline void *prog_start(const struct prog *prog) { - return rdev_mmap_full(&prog->rdev); + return asset_mmap(&prog->asset); } static inline void *prog_entry(const struct prog *prog) @@ -85,7 +95,7 @@ extern const struct mem_region_device addrspace_32bit; static inline void prog_memory_init(struct prog *prog, uintptr_t ptr, size_t size) { - rdev_chain(&prog->rdev, &addrspace_32bit.rdev, ptr, size); + rdev_chain(&prog->asset.rdev, &addrspace_32bit.rdev, ptr, size); } static inline void prog_set_area(struct prog *prog, void *start, size_t size) @@ -100,7 +110,11 @@ static inline void prog_set_entry(struct prog *prog, void *e, void *arg) } /* Locate the identified program to run. Return 0 on success. < 0 on error. */ -int prog_locate(struct prog *prog); +static inline int prog_locate(struct prog *prog) +{ + return asset_locate(&prog->asset); +} + /* Run the program described by prog. */ void prog_run(struct prog *prog); /* Per architecture implementation running a program. */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4a0301e..a5d227b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -18,6 +18,7 @@ # subdirs-y += loaders +bootblock-y += assets.c bootblock-y += prog_loaders.c bootblock-y += prog_ops.c bootblock-y += cbfs.c @@ -36,6 +37,7 @@ bootblock-y += region.c bootblock-y += boot_device.c bootblock-y += fmap.c +verstage-y += assets.c verstage-y += prog_loaders.c verstage-y += prog_ops.c verstage-y += delay.c @@ -60,6 +62,7 @@ verstage-$(CONFIG_GENERIC_UDELAY) += timer.c verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c verstage-y += mem_pool.c +romstage-y += assets.c romstage-y += prog_loaders.c romstage-y += prog_ops.c romstage-y += memchr.c @@ -92,6 +95,7 @@ endif romstage-$(CONFIG_GENERIC_UDELAY) += timer.c +ramstage-y += assets.c ramstage-y += prog_loaders.c ramstage-y += prog_ops.c ramstage-y += hardwaremain.c diff --git a/src/lib/assets.c b/src/lib/assets.c new file mode 100644 index 0000000..656f0b1 --- /dev/null +++ b/src/lib/assets.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + +#include <assets.h> +#include <boot_device.h> +#include <cbfs.h> +#include <console/console.h> +#include <rules.h> +#include <stdlib.h> + +#define DEFAULT_CBFS_PROVIDER_PRESENT \ + (!ENV_VERSTAGE || (ENV_VERSTAGE && !CONFIG_RETURN_FROM_VERSTAGE)) + +#if DEFAULT_CBFS_PROVIDER_PRESENT +static int cbfs_boot_asset_locate(struct asset *asset) +{ + return cbfs_boot_locate(&asset->rdev, asset->name, NULL); +} + +static const struct asset_provider cbfs_default_provider = { + .name = "CBFS", + .locate = cbfs_boot_asset_locate, +}; +#endif + +extern const struct asset_provider vboot_provider; + +static const struct asset_provider *providers[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_provider, +#endif +#if DEFAULT_CBFS_PROVIDER_PRESENT + &cbfs_default_provider, +#endif +}; + +int asset_locate(struct asset *asset) +{ + int i; + + boot_device_init(); + + for (i = 0; i < ARRAY_SIZE(providers); i++) { + /* Default provider state is active. */ + int ret = 1; + const struct asset_provider *ops; + + ops = providers[i]; + + if (ops->is_active != NULL) + ret = ops->is_active(asset); + + if (ret == 0) { + printk(BIOS_DEBUG, "%s provider inactive.\n", + ops->name); + continue; + } else if (ret < 0) { + printk(BIOS_DEBUG, "%s provider failure.\n", + ops->name); + continue; + } + + printk(BIOS_DEBUG, "%s provider active.\n", ops->name); + + if (ops->locate(asset)) + continue; + + printk(BIOS_DEBUG, "'%s' located at offset: %zx size: %zx\n", + asset->name, region_device_offset(&asset->rdev), + region_device_sz(&asset->rdev)); + + return 0; + } + + return -1; +} diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 23dfee7..3e83765 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -188,12 +188,10 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) void *cbfs_boot_load_stage_by_name(const char *name) { - struct prog stage = { - .name = name, - }; + struct prog stage = PROG_INIT(ASSET_UNKNOWN, name); uint32_t type = CBFS_TYPE_STAGE; - if (cbfs_boot_locate(&stage.rdev, name, &type)) + if (cbfs_boot_locate(&stage.asset.rdev, name, &type)) return NULL; if (cbfs_prog_stage_load(&stage)) @@ -209,7 +207,7 @@ int cbfs_prog_stage_load(struct prog *pstage) void *entry; size_t fsize; size_t foffset; - const struct region_device *fh = &pstage->rdev; + const struct region_device *fh = &pstage->asset.rdev; if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) return 0; diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 7799994..ec5eeb8 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -20,7 +20,6 @@ #include <stdlib.h> #include <arch/stages.h> -#include <boot_device.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -38,83 +37,10 @@ /* Only can represent up to 1 byte less than size_t. */ const struct mem_region_device addrspace_32bit = MEM_REGION_DEV_INIT(0, ~0UL); -#define DEFAULT_CBFS_LOADER_PRESENT \ - (!ENV_VERSTAGE || (ENV_VERSTAGE && !CONFIG_RETURN_FROM_VERSTAGE)) - -#if DEFAULT_CBFS_LOADER_PRESENT -static int cbfs_boot_prog_locate(struct prog *prog) -{ - return cbfs_boot_locate(&prog->rdev, prog->name, NULL); -} - -static const struct prog_loader_ops cbfs_default_loader = { - .locate = cbfs_boot_prog_locate, -}; -#endif - -extern const struct prog_loader_ops vboot_loader; - -static const struct prog_loader_ops *loaders[] = { -#if CONFIG_VBOOT_VERIFY_FIRMWARE - &vboot_loader, -#endif -#if DEFAULT_CBFS_LOADER_PRESENT - &cbfs_default_loader, -#endif -}; - -int prog_locate(struct prog *prog) -{ - int i; - - boot_device_init(); - - for (i = 0; i < ARRAY_SIZE(loaders); i++) { - /* Default loader state is active. */ - int ret = 1; - const struct prog_loader_ops *ops; - - ops = loaders[i]; - - if (ops->is_loader_active != NULL) - ret = ops->is_loader_active(prog); - - if (ret == 0) { - printk(BIOS_DEBUG, "%s loader inactive.\n", - ops->name); - continue; - } else if (ret < 0) { - printk(BIOS_DEBUG, "%s loader failure.\n", - ops->name); - continue; - } - - printk(BIOS_DEBUG, "%s loader active.\n", ops->name); - - if (ops->locate(prog)) - continue; - - printk(BIOS_DEBUG, "'%s' located at offset: %zx size: %zx\n", - prog->name, region_device_offset(&prog->rdev), - region_device_sz(&prog->rdev)); - - return 0; - } - - return -1; -} - void run_romstage(void) { - struct prog romstage = { - .name = CONFIG_CBFS_PREFIX "/romstage", - .type = PROG_ROMSTAGE, - }; - - /* The only time the default CBFS loader isn't present is during - * VERSTAGE in which it returns back to the calling stage. */ - if (!DEFAULT_CBFS_LOADER_PRESENT) - return; + struct prog romstage = + PROG_INIT(ASSET_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); if (prog_locate(&romstage)) goto fail; @@ -166,10 +92,8 @@ static int load_relocatable_ramstage(struct prog *ramstage) void run_ramstage(void) { - struct prog ramstage = { - .name = CONFIG_CBFS_PREFIX "/ramstage", - .type = PROG_RAMSTAGE, - }; + struct prog ramstage = + PROG_INIT(ASSET_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage"); /* Only x86 systems currently take the same firmware path on resume. */ if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) @@ -197,10 +121,8 @@ fail: die("Ramstage was not loaded!\n"); } -static struct prog global_payload = { - .name = CONFIG_CBFS_PREFIX "/payload", - .type = PROG_PAYLOAD, -}; +static struct prog global_payload = + PROG_INIT(ASSET_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); void __attribute__((weak)) mirror_payload(struct prog *payload) { diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index e986590..ed7978a 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -264,10 +264,10 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) void *rmod_loc; struct region_device *fh; - if (rsl->prog == NULL || rsl->prog->name == NULL) + if (rsl->prog == NULL || prog_name(rsl->prog) == NULL) return -1; - fh = &rsl->prog->rdev; + fh = prog_rdev(rsl->prog); if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) return -1; @@ -284,7 +284,7 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) rmod_loc = &stage_region[rmodule_offset]; printk(BIOS_INFO, "Decompressing stage %s @ 0x%p (%d bytes)\n", - rsl->prog->name, rmod_loc, stage.memlen); + prog_name(rsl->prog), rmod_loc, stage.memlen); if (stage.compression == CBFS_COMPRESS_NONE) { if (rdev_readat(fh, rmod_loc, sizeof(stage), stage.len) != diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index abe1df5..f8a3918 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -454,7 +454,7 @@ void *selfload(struct prog *payload) struct segment head; void *data; - data = rdev_mmap_full(&payload->rdev); + data = rdev_mmap_full(prog_rdev(payload)); if (data == NULL) return NULL; @@ -469,7 +469,10 @@ void *selfload(struct prog *payload) printk(BIOS_SPEW, "Loaded segments\n"); - rdev_munmap(&payload->rdev, data); + rdev_munmap(prog_rdev(payload), data); + + /* Update the payload's area with the bounce buffer information. */ + prog_set_area(payload, (void *)(uintptr_t)bounce_buffer, bounce_size); /* Update the payload's area with the bounce buffer information. */ prog_set_area(payload, (void *)(uintptr_t)bounce_buffer, bounce_size); @@ -477,6 +480,6 @@ void *selfload(struct prog *payload) return (void *)entry; out: - rdev_munmap(&payload->rdev, data); + rdev_munmap(prog_rdev(payload), data); return NULL; } diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 618fefd..278351e 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -48,10 +48,8 @@ static efi_wrapper_entry_t load_refcode_from_cache(void) static efi_wrapper_entry_t load_reference_code(void) { - struct prog prog = { - .type = PROG_REFCODE, - .name = CONFIG_CBFS_PREFIX "/refcode", - }; + struct prog prog = + PROG_INIT(ASSET_REFCODE, CONFIG_CBFS_PREFIX "/refcode"); struct rmod_stage_load refcode = { .cbmem_id = CBMEM_ID_REFCODE, .prog = &prog, diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index f39fa92..8e2c468 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -44,10 +44,8 @@ static pei_wrapper_entry_t load_refcode_from_cache(void) static efi_wrapper_entry_t load_reference_code(void) { - struct prog prog = { - .type = PROG_REFCODE, - .name = CONFIG_CBFS_PREFIX "/refcode", - }; + struct prog prog = + PROG_INIT(ASSET_REFCODE, CONFIG_CBFS_PREFIX "/refcode"); struct rmod_stage_load refcode = { .cbmem_id = CBMEM_ID_REFCODE, .prog = &prog, diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c index c6a75bd..00e4110 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c @@ -17,10 +17,10 @@ * Foundation, Inc. */ +#include <assets.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <program_loading.h> #include <rmodule.h> #include <rules.h> #include <string.h> @@ -79,7 +79,7 @@ static void init_vb2_working_data(void) wd->buffer_size = work_size - wd->buffer_offset; } -static int vboot_loader_active(struct prog *prog) +static int vboot_active(struct asset *asset) { struct vb2_working_data *wd; int run_verification; @@ -90,15 +90,15 @@ static int vboot_loader_active(struct prog *prog) init_vb2_working_data(); verstage_main(); } else if (verstage_should_load()) { - struct prog verstage = { - .type = PROG_VERSTAGE, - .name = CONFIG_CBFS_PREFIX "/verstage", - }; + struct prog verstage = + PROG_INIT(ASSET_VERSTAGE, + CONFIG_CBFS_PREFIX "/verstage"); printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n"); /* load verstage from RO */ - if (cbfs_boot_locate(&verstage.rdev, verstage.name, NULL) || + if (cbfs_boot_locate(prog_rdev(&verstage), + prog_name(&verstage), NULL) || cbfs_prog_stage_load(&verstage)) die("failed to load verstage"); @@ -126,22 +126,22 @@ static int vboot_loader_active(struct prog *prog) } static int vboot_locate_by_components(const struct region_device *fw_main, - struct prog *prog) + struct asset *asset) { struct vboot_components *fw_info; size_t metadata_sz; size_t offset; size_t size; - struct region_device *fw = &prog->rdev; + struct region_device *fw = asset_rdev(asset); int fw_index = 0; - if (prog->type == PROG_ROMSTAGE) + if (asset_type(asset) == ASSET_ROMSTAGE) fw_index = CONFIG_VBOOT_ROMSTAGE_INDEX; - else if (prog->type == PROG_RAMSTAGE) + else if (asset_type(asset) == ASSET_RAMSTAGE) fw_index = CONFIG_VBOOT_RAMSTAGE_INDEX; - else if (prog->type == PROG_PAYLOAD) + else if (asset_type(asset) == ASSET_PAYLOAD) fw_index = CONFIG_VBOOT_BOOT_LOADER_INDEX; - else if (prog->type == PROG_REFCODE) + else if (asset_type(asset) == ASSET_REFCODE) fw_index = CONFIG_VBOOT_REFCODE_INDEX; else die("Invalid program type for vboot."); @@ -175,7 +175,7 @@ static int vboot_locate_by_components(const struct region_device *fw_main, } static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main, - struct prog *prog) + struct asset *asset) { struct cbfsd cbfs; struct region_device rdev; @@ -190,21 +190,21 @@ static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main, cbfs.rdev = &rdev; cbfs.align = props.align; - return cbfs_locate(&prog->rdev, &cbfs, prog->name, NULL); + return cbfs_locate(asset_rdev(asset), &cbfs, asset_name(asset), NULL); } -static int vboot_prog_locate(const struct region_device *fw_main, - struct prog *prog) +static int vboot_asset_locate(const struct region_device *fw_main, + struct asset *asset) { if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) - return vboot_locate_by_multi_cbfs(fw_main, prog); + return vboot_locate_by_multi_cbfs(fw_main, asset); else - return vboot_locate_by_components(fw_main, prog); + return vboot_locate_by_components(fw_main, asset); } -/* This function is only called when vboot_loader_active() returns 1. That +/* This function is only called when vboot_active() returns 1. That * means we are taking vboot paths. */ -static int vboot_locate(struct prog *prog) +static int vboot_locate(struct asset *asset) { struct vb2_working_data *wd; struct region_device fw_main; @@ -219,11 +219,11 @@ static int vboot_locate(struct prog *prog) if (vb2_get_selected_region(wd, &fw_main)) die("failed to reference selected region\n"); - return vboot_prog_locate(&fw_main, prog); + return vboot_asset_locate(&fw_main, asset); } -const struct prog_loader_ops vboot_loader = { +const struct asset_provider vboot_provider = { .name = "VBOOT", - .is_loader_active = vboot_loader_active, + .is_active = vboot_active, .locate = vboot_locate, };

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Patch set updated for coreboot: 6d1a8f8 assets: abstract away the firmware assets used for booting
by Aaron Durbin 21 May '15

21 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10264 -gerrit commit 6d1a8f8c8a0e306d3e413b28dfb7ecd2e8a0dce3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed May 20 12:08:55 2015 -0500 assets: abstract away the firmware assets used for booting As there can be more than one source of firmware assets this patch generalizes the notion of locating a particular asset. struct asset is added along with some helper functions for working on assets as a first class citizen. Change-Id: I2ce575d1e5259aed4c34c3dcfd438abe9db1d7b9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/boot.c | 2 +- src/arch/x86/boot/boot.c | 2 +- src/include/assets.h | 90 +++++++++++++++++++++ src/include/program_loading.h | 54 ++++++++----- src/lib/Makefile.inc | 4 + src/lib/assets.c | 93 ++++++++++++++++++++++ src/lib/cbfs.c | 8 +- src/lib/prog_loaders.c | 90 ++------------------- src/lib/rmodule.c | 6 +- src/lib/selfboot.c | 9 ++- src/soc/intel/baytrail/refcode.c | 6 +- src/soc/intel/broadwell/refcode.c | 6 +- .../google/chromeos/vboot2/vboot_loader.c | 48 +++++------ 13 files changed, 269 insertions(+), 149 deletions(-) diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 226d8d7..03ad053 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -73,7 +73,7 @@ void arch_prog_run(struct prog *prog) void (*doit)(void *); void *arg; - if (ENV_RAMSTAGE && prog->type == PROG_PAYLOAD) { + if (ENV_RAMSTAGE && prog_type(prog) == ASSET_PAYLOAD) { run_payload(prog); return; } diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 0ff8a6c..d86a6c3 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -125,7 +125,7 @@ static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) static void try_payload(struct prog *prog) { - if (prog->type == PROG_PAYLOAD) { + if (prog_type(prog) == ASSET_PAYLOAD) { if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) jmp_payload_no_bounce_buffer(prog_entry(prog)); else diff --git a/src/include/assets.h b/src/include/assets.h new file mode 100644 index 0000000..7b08054 --- /dev/null +++ b/src/include/assets.h @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#ifndef ASSETS_H +#define ASSETS_H + +#include <region.h> + +/* An asset represents data used to boot the system. It can be found within + * CBFS or some other mechanism. While CBFS can be a source of an asset, note + * that using the asset API implies querying of other sources. */ + +enum asset_type { + ASSET_UNKNOWN, + ASSET_VERSTAGE, + ASSET_ROMSTAGE, + ASSET_RAMSTAGE, + ASSET_REFCODE, + ASSET_PAYLOAD, +}; + +struct asset { + enum asset_type type; + const char *name; + struct region_device rdev; +}; + +static inline const char *asset_name(const struct asset *asset) +{ + return asset->name; +} + +static inline enum asset_type asset_type(const struct asset *asset) +{ + return asset->type; +} + +static struct region_device *asset_rdev(struct asset *asset) +{ + return &asset->rdev; +} + +static inline size_t asset_size(const struct asset *asset) +{ + return region_device_sz(&asset->rdev); +} + +/* Returns NULL on error. */ +static inline void *asset_mmap(const struct asset *asset) +{ + return rdev_mmap_full(&asset->rdev); +} + +#define ASSET_INIT(type_, name_) \ + { \ + .type = (type_), \ + .name = (name_), \ + } + +/* Locate the asset as described by the parameter. It will query all known + * asset providers. Returns 0 on success. < 0 on error. */ +int asset_locate(struct asset *asset); + +struct asset_provider { + const char *name; + /* Determines if the provider is the active one. If so returns 1 else 0 + * or < 0 on error. */ + int (*is_active)(struct asset *asset); + /* Returns < 0 on error or 0 on success. This function locates + * the rdev representing the file data associated with the passed in + * prog. */ + int (*locate)(struct asset *asset); +}; + +#endif /* ASSETS_H */ diff --git a/src/include/program_loading.h b/src/include/program_loading.h index d8e7de3..49a36fa 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -22,7 +22,7 @@ #include <stdint.h> #include <stddef.h> -#include <region.h> +#include <assets.h> enum { /* Last segment of program. Can be used to take different actions for @@ -34,39 +34,49 @@ enum { * set on the last segment loaded. */ void arch_segment_loaded(uintptr_t start, size_t size, int flags); -enum prog_type { - PROG_VERSTAGE, - PROG_ROMSTAGE, - PROG_RAMSTAGE, - PROG_REFCODE, - PROG_PAYLOAD, -}; - /* Representation of a program. */ struct prog { - enum prog_type type; - const char *name; - /* Source of program content to load. After loading program it - * represents the memory region of the stages and payload. For - * achitectures that use a bounce buffer then it would represent - * the bounce buffer. */ - struct region_device rdev; + /* The region_device within the asset is the source of program content + * to load. After loading program it represents the memory region of + * the stages and payload. For achitectures that use a bounce buffer + * then it would represent the bounce buffer. */ + struct asset asset; /* Entry to program with optional argument. It's up to the architecture * to decide if argument is passed. */ void (*entry)(void *); void *arg; }; +#define PROG_INIT(type_, name_) \ + { \ + .asset = ASSET_INIT(type_, name_), \ + } + +static inline const char *prog_name(const struct prog *prog) +{ + return asset_name(&prog->asset); +} + +static inline enum asset_type prog_type(const struct prog *prog) +{ + return asset_type(&prog->asset); +} + +static inline struct region_device *prog_rdev(struct prog *prog) +{ + return asset_rdev(&prog->asset); +} + /* Only valid for loaded programs. */ static inline size_t prog_size(const struct prog *prog) { - return region_device_sz(&prog->rdev); + return asset_size(&prog->asset); } /* Only valid for loaded programs. */ static inline void *prog_start(const struct prog *prog) { - return rdev_mmap_full(&prog->rdev); + return asset_mmap(&prog->asset); } static inline void *prog_entry(const struct prog *prog) @@ -85,7 +95,7 @@ extern const struct mem_region_device addrspace_32bit; static inline void prog_memory_init(struct prog *prog, uintptr_t ptr, size_t size) { - rdev_chain(&prog->rdev, &addrspace_32bit.rdev, ptr, size); + rdev_chain(&prog->asset.rdev, &addrspace_32bit.rdev, ptr, size); } static inline void prog_set_area(struct prog *prog, void *start, size_t size) @@ -100,7 +110,11 @@ static inline void prog_set_entry(struct prog *prog, void *e, void *arg) } /* Locate the identified program to run. Return 0 on success. < 0 on error. */ -int prog_locate(struct prog *prog); +static inline int prog_locate(struct prog *prog) +{ + return asset_locate(&prog->asset); +} + /* Run the program described by prog. */ void prog_run(struct prog *prog); /* Per architecture implementation running a program. */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4a0301e..a5d227b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -18,6 +18,7 @@ # subdirs-y += loaders +bootblock-y += assets.c bootblock-y += prog_loaders.c bootblock-y += prog_ops.c bootblock-y += cbfs.c @@ -36,6 +37,7 @@ bootblock-y += region.c bootblock-y += boot_device.c bootblock-y += fmap.c +verstage-y += assets.c verstage-y += prog_loaders.c verstage-y += prog_ops.c verstage-y += delay.c @@ -60,6 +62,7 @@ verstage-$(CONFIG_GENERIC_UDELAY) += timer.c verstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c verstage-y += mem_pool.c +romstage-y += assets.c romstage-y += prog_loaders.c romstage-y += prog_ops.c romstage-y += memchr.c @@ -92,6 +95,7 @@ endif romstage-$(CONFIG_GENERIC_UDELAY) += timer.c +ramstage-y += assets.c ramstage-y += prog_loaders.c ramstage-y += prog_ops.c ramstage-y += hardwaremain.c diff --git a/src/lib/assets.c b/src/lib/assets.c new file mode 100644 index 0000000..7434c41 --- /dev/null +++ b/src/lib/assets.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + +#include <assets.h> +#include <boot_device.h> +#include <cbfs.h> +#include <console/console.h> +#include <rules.h> +#include <stdlib.h> + +#define DEFAULT_CBFS_PROVIDER_PRESENT \ + (!ENV_VERSTAGE || (ENV_VERSTAGE && !CONFIG_RETURN_FROM_VERSTAGE)) + +#if DEFAULT_CBFS_PROVIDER_PRESENT +static int cbfs_boot_asset_locate(struct asset *asset) +{ + return cbfs_boot_locate(&asset->rdev, asset->name, NULL); +} + +static const struct asset_provider cbfs_default_provider = { + .name = "CBFS" + .locate = cbfs_boot_asset_locate, +}; +#endif + +extern const struct asset_provider vboot_provider; + +static const struct asset_provider *providers[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_provider, +#endif +#if DEFAULT_CBFS_PROVIDER_PRESENT + &cbfs_default_provider, +#endif +}; + +int asset_locate(struct asset *asset) +{ + int i; + + boot_device_init(); + + for (i = 0; i < ARRAY_SIZE(providers); i++) { + /* Default provider state is active. */ + int ret = 1; + const struct asset_provider *ops; + + ops = providers[i]; + + if (ops->is_active != NULL) + ret = ops->is_active(asset); + + if (ret == 0) { + printk(BIOS_DEBUG, "%s provider inactive.\n", + ops->name); + continue; + } else if (ret < 0) { + printk(BIOS_DEBUG, "%s provider failure.\n", + ops->name); + continue; + } + + printk(BIOS_DEBUG, "%s provider active.\n", ops->name); + + if (ops->locate(asset)) + continue; + + printk(BIOS_DEBUG, "'%s' located at offset: %zx size: %zx\n", + asset->name, region_device_offset(&asset->rdev), + region_device_sz(&asset->rdev)); + + return 0; + } + + return -1; +} diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 23dfee7..3e83765 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -188,12 +188,10 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) void *cbfs_boot_load_stage_by_name(const char *name) { - struct prog stage = { - .name = name, - }; + struct prog stage = PROG_INIT(ASSET_UNKNOWN, name); uint32_t type = CBFS_TYPE_STAGE; - if (cbfs_boot_locate(&stage.rdev, name, &type)) + if (cbfs_boot_locate(&stage.asset.rdev, name, &type)) return NULL; if (cbfs_prog_stage_load(&stage)) @@ -209,7 +207,7 @@ int cbfs_prog_stage_load(struct prog *pstage) void *entry; size_t fsize; size_t foffset; - const struct region_device *fh = &pstage->rdev; + const struct region_device *fh = &pstage->asset.rdev; if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) return 0; diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 7799994..ec5eeb8 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -20,7 +20,6 @@ #include <stdlib.h> #include <arch/stages.h> -#include <boot_device.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -38,83 +37,10 @@ /* Only can represent up to 1 byte less than size_t. */ const struct mem_region_device addrspace_32bit = MEM_REGION_DEV_INIT(0, ~0UL); -#define DEFAULT_CBFS_LOADER_PRESENT \ - (!ENV_VERSTAGE || (ENV_VERSTAGE && !CONFIG_RETURN_FROM_VERSTAGE)) - -#if DEFAULT_CBFS_LOADER_PRESENT -static int cbfs_boot_prog_locate(struct prog *prog) -{ - return cbfs_boot_locate(&prog->rdev, prog->name, NULL); -} - -static const struct prog_loader_ops cbfs_default_loader = { - .locate = cbfs_boot_prog_locate, -}; -#endif - -extern const struct prog_loader_ops vboot_loader; - -static const struct prog_loader_ops *loaders[] = { -#if CONFIG_VBOOT_VERIFY_FIRMWARE - &vboot_loader, -#endif -#if DEFAULT_CBFS_LOADER_PRESENT - &cbfs_default_loader, -#endif -}; - -int prog_locate(struct prog *prog) -{ - int i; - - boot_device_init(); - - for (i = 0; i < ARRAY_SIZE(loaders); i++) { - /* Default loader state is active. */ - int ret = 1; - const struct prog_loader_ops *ops; - - ops = loaders[i]; - - if (ops->is_loader_active != NULL) - ret = ops->is_loader_active(prog); - - if (ret == 0) { - printk(BIOS_DEBUG, "%s loader inactive.\n", - ops->name); - continue; - } else if (ret < 0) { - printk(BIOS_DEBUG, "%s loader failure.\n", - ops->name); - continue; - } - - printk(BIOS_DEBUG, "%s loader active.\n", ops->name); - - if (ops->locate(prog)) - continue; - - printk(BIOS_DEBUG, "'%s' located at offset: %zx size: %zx\n", - prog->name, region_device_offset(&prog->rdev), - region_device_sz(&prog->rdev)); - - return 0; - } - - return -1; -} - void run_romstage(void) { - struct prog romstage = { - .name = CONFIG_CBFS_PREFIX "/romstage", - .type = PROG_ROMSTAGE, - }; - - /* The only time the default CBFS loader isn't present is during - * VERSTAGE in which it returns back to the calling stage. */ - if (!DEFAULT_CBFS_LOADER_PRESENT) - return; + struct prog romstage = + PROG_INIT(ASSET_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); if (prog_locate(&romstage)) goto fail; @@ -166,10 +92,8 @@ static int load_relocatable_ramstage(struct prog *ramstage) void run_ramstage(void) { - struct prog ramstage = { - .name = CONFIG_CBFS_PREFIX "/ramstage", - .type = PROG_RAMSTAGE, - }; + struct prog ramstage = + PROG_INIT(ASSET_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage"); /* Only x86 systems currently take the same firmware path on resume. */ if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) @@ -197,10 +121,8 @@ fail: die("Ramstage was not loaded!\n"); } -static struct prog global_payload = { - .name = CONFIG_CBFS_PREFIX "/payload", - .type = PROG_PAYLOAD, -}; +static struct prog global_payload = + PROG_INIT(ASSET_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); void __attribute__((weak)) mirror_payload(struct prog *payload) { diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index e986590..ed7978a 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -264,10 +264,10 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) void *rmod_loc; struct region_device *fh; - if (rsl->prog == NULL || rsl->prog->name == NULL) + if (rsl->prog == NULL || prog_name(rsl->prog) == NULL) return -1; - fh = &rsl->prog->rdev; + fh = prog_rdev(rsl->prog); if (rdev_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) return -1; @@ -284,7 +284,7 @@ int rmodule_stage_load(struct rmod_stage_load *rsl) rmod_loc = &stage_region[rmodule_offset]; printk(BIOS_INFO, "Decompressing stage %s @ 0x%p (%d bytes)\n", - rsl->prog->name, rmod_loc, stage.memlen); + prog_name(rsl->prog), rmod_loc, stage.memlen); if (stage.compression == CBFS_COMPRESS_NONE) { if (rdev_readat(fh, rmod_loc, sizeof(stage), stage.len) != diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index abe1df5..f8a3918 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -454,7 +454,7 @@ void *selfload(struct prog *payload) struct segment head; void *data; - data = rdev_mmap_full(&payload->rdev); + data = rdev_mmap_full(prog_rdev(payload)); if (data == NULL) return NULL; @@ -469,7 +469,10 @@ void *selfload(struct prog *payload) printk(BIOS_SPEW, "Loaded segments\n"); - rdev_munmap(&payload->rdev, data); + rdev_munmap(prog_rdev(payload), data); + + /* Update the payload's area with the bounce buffer information. */ + prog_set_area(payload, (void *)(uintptr_t)bounce_buffer, bounce_size); /* Update the payload's area with the bounce buffer information. */ prog_set_area(payload, (void *)(uintptr_t)bounce_buffer, bounce_size); @@ -477,6 +480,6 @@ void *selfload(struct prog *payload) return (void *)entry; out: - rdev_munmap(&payload->rdev, data); + rdev_munmap(prog_rdev(payload), data); return NULL; } diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 618fefd..278351e 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -48,10 +48,8 @@ static efi_wrapper_entry_t load_refcode_from_cache(void) static efi_wrapper_entry_t load_reference_code(void) { - struct prog prog = { - .type = PROG_REFCODE, - .name = CONFIG_CBFS_PREFIX "/refcode", - }; + struct prog prog = + PROG_INIT(ASSET_REFCODE, CONFIG_CBFS_PREFIX "/refcode"); struct rmod_stage_load refcode = { .cbmem_id = CBMEM_ID_REFCODE, .prog = &prog, diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index f39fa92..8e2c468 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -44,10 +44,8 @@ static pei_wrapper_entry_t load_refcode_from_cache(void) static efi_wrapper_entry_t load_reference_code(void) { - struct prog prog = { - .type = PROG_REFCODE, - .name = CONFIG_CBFS_PREFIX "/refcode", - }; + struct prog prog = + PROG_INIT(ASSET_REFCODE, CONFIG_CBFS_PREFIX "/refcode"); struct rmod_stage_load refcode = { .cbmem_id = CBMEM_ID_REFCODE, .prog = &prog, diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c index c6a75bd..00e4110 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c @@ -17,10 +17,10 @@ * Foundation, Inc. */ +#include <assets.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <program_loading.h> #include <rmodule.h> #include <rules.h> #include <string.h> @@ -79,7 +79,7 @@ static void init_vb2_working_data(void) wd->buffer_size = work_size - wd->buffer_offset; } -static int vboot_loader_active(struct prog *prog) +static int vboot_active(struct asset *asset) { struct vb2_working_data *wd; int run_verification; @@ -90,15 +90,15 @@ static int vboot_loader_active(struct prog *prog) init_vb2_working_data(); verstage_main(); } else if (verstage_should_load()) { - struct prog verstage = { - .type = PROG_VERSTAGE, - .name = CONFIG_CBFS_PREFIX "/verstage", - }; + struct prog verstage = + PROG_INIT(ASSET_VERSTAGE, + CONFIG_CBFS_PREFIX "/verstage"); printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n"); /* load verstage from RO */ - if (cbfs_boot_locate(&verstage.rdev, verstage.name, NULL) || + if (cbfs_boot_locate(prog_rdev(&verstage), + prog_name(&verstage), NULL) || cbfs_prog_stage_load(&verstage)) die("failed to load verstage"); @@ -126,22 +126,22 @@ static int vboot_loader_active(struct prog *prog) } static int vboot_locate_by_components(const struct region_device *fw_main, - struct prog *prog) + struct asset *asset) { struct vboot_components *fw_info; size_t metadata_sz; size_t offset; size_t size; - struct region_device *fw = &prog->rdev; + struct region_device *fw = asset_rdev(asset); int fw_index = 0; - if (prog->type == PROG_ROMSTAGE) + if (asset_type(asset) == ASSET_ROMSTAGE) fw_index = CONFIG_VBOOT_ROMSTAGE_INDEX; - else if (prog->type == PROG_RAMSTAGE) + else if (asset_type(asset) == ASSET_RAMSTAGE) fw_index = CONFIG_VBOOT_RAMSTAGE_INDEX; - else if (prog->type == PROG_PAYLOAD) + else if (asset_type(asset) == ASSET_PAYLOAD) fw_index = CONFIG_VBOOT_BOOT_LOADER_INDEX; - else if (prog->type == PROG_REFCODE) + else if (asset_type(asset) == ASSET_REFCODE) fw_index = CONFIG_VBOOT_REFCODE_INDEX; else die("Invalid program type for vboot."); @@ -175,7 +175,7 @@ static int vboot_locate_by_components(const struct region_device *fw_main, } static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main, - struct prog *prog) + struct asset *asset) { struct cbfsd cbfs; struct region_device rdev; @@ -190,21 +190,21 @@ static int vboot_locate_by_multi_cbfs(const struct region_device *fw_main, cbfs.rdev = &rdev; cbfs.align = props.align; - return cbfs_locate(&prog->rdev, &cbfs, prog->name, NULL); + return cbfs_locate(asset_rdev(asset), &cbfs, asset_name(asset), NULL); } -static int vboot_prog_locate(const struct region_device *fw_main, - struct prog *prog) +static int vboot_asset_locate(const struct region_device *fw_main, + struct asset *asset) { if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) - return vboot_locate_by_multi_cbfs(fw_main, prog); + return vboot_locate_by_multi_cbfs(fw_main, asset); else - return vboot_locate_by_components(fw_main, prog); + return vboot_locate_by_components(fw_main, asset); } -/* This function is only called when vboot_loader_active() returns 1. That +/* This function is only called when vboot_active() returns 1. That * means we are taking vboot paths. */ -static int vboot_locate(struct prog *prog) +static int vboot_locate(struct asset *asset) { struct vb2_working_data *wd; struct region_device fw_main; @@ -219,11 +219,11 @@ static int vboot_locate(struct prog *prog) if (vb2_get_selected_region(wd, &fw_main)) die("failed to reference selected region\n"); - return vboot_prog_locate(&fw_main, prog); + return vboot_asset_locate(&fw_main, asset); } -const struct prog_loader_ops vboot_loader = { +const struct asset_provider vboot_provider = { .name = "VBOOT", - .is_loader_active = vboot_loader_active, + .is_active = vboot_active, .locate = vboot_locate, };

1 0

Patch set updated for coreboot: e3dd169 Move TPM code out of chromeos
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10269 -gerrit commit e3dd169b71e21320c07b76aa2fcbd1e74234b60b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:29:06 2015 +0200 Move TPM code out of chromeos This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 4 +- src/drivers/pc80/tpm/Kconfig | 24 ++- src/drivers/pc80/tpm/Makefile.inc | 1 + src/drivers/pc80/tpm/romstage.c | 236 ++++++++++++++++++++++++++ src/include/tpm.h | 2 + src/mainboard/google/bolt/Kconfig | 1 + src/mainboard/google/butterfly/Kconfig | 1 + src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/link/romstage.c | 9 +- src/mainboard/google/panther/Kconfig | 1 + src/mainboard/google/parrot/Kconfig | 1 + src/mainboard/google/parrot/romstage.c | 8 +- src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/rambi/Kconfig | 1 + src/mainboard/google/samus/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/google/stout/Kconfig | 1 + src/mainboard/google/stout/romstage.c | 8 +- src/mainboard/intel/baskingridge/Kconfig | 1 + src/mainboard/intel/emeraldlake2/romstage.c | 8 +- src/mainboard/intel/wtm2/Kconfig | 1 + src/mainboard/samsung/lumpy/Kconfig | 1 + src/mainboard/samsung/lumpy/romstage.c | 8 +- src/mainboard/samsung/stumpy/Kconfig | 1 + src/mainboard/samsung/stumpy/romstage.c | 8 +- src/soc/intel/baytrail/romstage/romstage.c | 13 +- src/soc/intel/broadwell/romstage/romstage.c | 13 +- src/vendorcode/google/chromeos/Kconfig | 2 + src/vendorcode/google/chromeos/Makefile.inc | 1 - src/vendorcode/google/chromeos/chromeos.h | 4 - src/vendorcode/google/chromeos/vboot.c | 248 ---------------------------- 32 files changed, 308 insertions(+), 304 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 998f887..61fde00 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -276,8 +276,8 @@ void romstage_common(const struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(wake_from_s3); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 279da39..46f404e 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -1,5 +1,12 @@ +config MAINBOARD_HAS_LPC_TPM + bool + default n + help + Board has TPM support + config LPC_TPM - bool + bool "Enable TPM support" + depends on MAINBOARD_HAS_LPC_TPM default n help Enable this option to enable LPC TPM support in coreboot. @@ -15,3 +22,18 @@ config TPM_TIS_BASE_ADDRESS The default is specified by the TCG PC Client Specific TPM Interface Specification 1.2 and should not be changed unless the TPM being used does not conform to TPM TIS 1.2. + +config TPM_INIT_FAILURE_IS_FATAL + bool + default n + depends on LPC_TPM + help + What to do if TPM init failed. If true, force a hard reset, + otherwise just log error message to console. + +config SKIP_TPM_STARTUP_ON_NORMAL_BOOT + bool + default n + depends on LPC_TPM + help + Skip TPM init on normal boot. Useful if payload does TPM init. diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc index c900fe8..089d067 100644 --- a/src/drivers/pc80/tpm/Makefile.inc +++ b/src/drivers/pc80/tpm/Makefile.inc @@ -1,2 +1,3 @@ romstage-$(CONFIG_LPC_TPM) += tpm.c ramstage-$(CONFIG_LPC_TPM) += tpm.c +romstage-$(CONFIG_LPC_TPM) += romstage.c diff --git a/src/drivers/pc80/tpm/romstage.c b/src/drivers/pc80/tpm/romstage.c new file mode 100644 index 0000000..5e29e3a --- /dev/null +++ b/src/drivers/pc80/tpm/romstage.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <types.h> +#include <console/cbmem_console.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <tpm.h> +#include <reset.h> + +//#define EXTRA_LOGGING + +#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ + +#define TPM_SUCCESS ((u32)0x00000000) + +#define TPM_E_IOERROR ((u32)0x0000001f) +#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) +#define TPM_E_NON_FATAL ((u32)0x00000800) +#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) + +#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) +#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) + +static const struct { + u8 buffer[12]; +} tpm_resume_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } +}; + +static const struct { + u8 buffer[12]; +} tpm_startup_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1 } +}; + +static const struct { + u8 buffer[10]; +} tpm_continueselftest_cmd = { + { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } +}; + +static inline void FromTpmUint32(const u8 * buffer, u32 * x) +{ + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); +} + +static inline int TpmCommandSize(const u8 * buffer) +{ + u32 size; + FromTpmUint32(buffer + sizeof(u16), &size); + return (int)size; +} + +/* Gets the code field of a TPM command. */ +static inline int TpmCommandCode(const u8 * buffer) +{ + u32 code; + FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); + return code; +} + +/* Gets the return code field of a TPM result. */ +static inline int TpmReturnCode(const u8 * buffer) +{ + return TpmCommandCode(buffer); +} + +/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or + * DOING_SELFTEST errors are returned. + */ +static u32 TlclSendReceiveNoRetry(const u8 * request, + u8 * response, int max_length) +{ + size_t response_length = max_length; + u32 result; + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", + request[0], request[1], + request[2], request[3], request[4], request[5], + request[6], request[7], request[8], request[9]); +#endif + + result = TPM_SUCCESS; + if (tis_sendrecv + (request, TpmCommandSize(request), response, &response_length)) + result = TPM_E_IOERROR; + + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + printk(BIOS_DEBUG, + "TPM: command 0x%x send/receive failed: 0x%x\n", + TpmCommandCode(request), result); + return TPM_E_COMMUNICATION_ERROR; + } + /* Otherwise, use the result code from the response */ + result = TpmReturnCode(response); + +/* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + +#ifdef EXTRA_LOGGING + printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", + response[0], response[1], + response[2], response[3], response[4], response[5], + response[6], response[7], response[8], response[9]); +#endif + + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", + TpmCommandCode(request), result); + + return result; +} + +static inline u32 TlclContinueSelfTest(void) +{ + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + printk(BIOS_DEBUG, "TPM: Continue self test\n"); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); +} + +/* Sends a TPM command and gets a response. Returns 0 if success or the TPM + * error code if error. In the firmware, waits for the self test to complete + * if needed. In the host, reports the first error without retries. */ +static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) +{ + u32 result = TlclSendReceiveNoRetry(request, response, max_length); + /* When compiling for the firmware, hide command failures due to the self + * test not having run or completed. */ + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = TlclContinueSelfTest(); + if (result != TPM_SUCCESS) { + return result; + } +#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) + /* Retry only once */ + result = TlclSendReceiveNoRetry(request, response, max_length); +#else + /* This needs serious testing. The TPM specification says: + * "iii. The caller MUST wait for the actions of + * TPM_ContinueSelfTest to complete before reissuing the + * command C1." But, if ContinueSelfTest is non-blocking, how + * do we know that the actions have completed other than trying + * again? */ + do { + result = + TlclSendReceiveNoRetry(request, response, + max_length); + } while (result == TPM_E_DOING_SELFTEST); +#endif + } + + return result; +} + +void init_tpm(int s3resume) +{ + u32 result; + u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + + /* Doing TPM startup when we're not coming in on the S3 resume path + * saves us roughly 20ms in boot time only. This does not seem to + * be worth an API change to vboot_reference-firmware right now, so + * let's keep the code around, but just bail out early: + */ + if (s3resume ? CONFIG_NO_TPM_RESUME + : CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT) + return; + + printk(BIOS_DEBUG, "TPM initialization.\n"); + + printk(BIOS_SPEW, "TPM: Init\n"); + if (tis_init()) + return; + + printk(BIOS_SPEW, "TPM: Open\n"); + if (tis_open()) + return; + + + if (s3resume) { + /* S3 Resume */ + printk(BIOS_SPEW, "TPM: Resume\n"); + result = TlclSendReceive(tpm_resume_cmd.buffer, + response, sizeof(response)); + if (result == TPM_E_INVALID_POSTINIT) { + /* We're on a platform where the TPM maintains power + * in S3, so it's already initialized. + */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return; + } + } else { + printk(BIOS_SPEW, "TPM: Startup\n"); + result = TlclSendReceive(tpm_startup_cmd.buffer, + response, sizeof(response)); + } + + if (result == TPM_SUCCESS) { + printk(BIOS_SPEW, "TPM: OK.\n"); + return; + } + + printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); + + if (CONFIG_TPM_INIT_FAILURE_IS_FATAL) { + printk(BIOS_ERR, "Hard reset!\n"); + post_code(POST_TPM_FAILURE); + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) + cbmem_dump_console(); + hard_reset(); + } +} diff --git a/src/include/tpm.h b/src/include/tpm.h index 464f32e..9b4db4a 100644 --- a/src/include/tpm.h +++ b/src/include/tpm.h @@ -66,4 +66,6 @@ int tis_close(void); int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf, size_t *recv_len); +void init_tpm(int s3resume); + #endif /* TPM_H_ */ diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 2239f70..74e1edd 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 7472c06..b1a64ee 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index a8faaab..5b97259 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 316434f..0f70925 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index ca8c2bd..6a5a866 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -41,9 +41,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <tpm.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> @@ -246,8 +244,9 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif + timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 31062ed..37a8548 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select PHYSICAL_REC_SWITCH diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 07405c6..9cf390a 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index d0fab67..c2e16b1 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #include <cbfs.h> +#include <tpm.h> #include "ec/compal/ene932/ec.h" static void pch_enable_lpc(void) @@ -197,8 +195,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index d6a208b..2c1560a 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 4c9e891..1130d11 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select ALWAYS_LOAD_OPROM select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index f655b29..06317e9 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index fd4cb2f..cfbce5e 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_DP select INTEL_DDI diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index ec03d87..eca83da 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index ee6ca4f..65d6a5d 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -40,9 +40,7 @@ #include <halt.h> #include "gpio.h" #include <bootmode.h> -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif +#include <tpm.h> #include <cbfs.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" @@ -251,8 +249,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index c3e3361..f916138 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index c9d5cf1..13aaae4 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -39,10 +39,8 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> +#include <tpm.h> #include "gpio.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif #define SIO_PORT 0x164e @@ -255,8 +253,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 5a064d1..b8f616a 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 7c9dce4..fed4610 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select CPU_INTEL_SOCKET_RPGA989 select EC_SMSC_MEC1308 select HAVE_ACPI_RESUME diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 9b1a023..72d7aa1 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,6 +32,7 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> +#include <tpm.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -45,9 +46,6 @@ #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif static void pch_enable_lpc(void) { @@ -273,8 +271,8 @@ void main(unsigned long bist) } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 1eda8eb..f749c39 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select CPU_INTEL_SOCKET_RPGA989 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 6506c80..9e0ed3c 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -41,13 +41,11 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <halt.h> +#include <tpm.h> #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> #endif -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#endif /* Stumpy USB Reset Disable defined in cmos.layout */ #if CONFIG_USE_OPTION_TABLE @@ -283,8 +281,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); +#if CONFIG_LPC_TPM + init_tpm(bootmode == 2); #endif timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index bfc8678..669ec89 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -33,6 +33,7 @@ #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> +#include <tpm.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -211,14 +212,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) return prev_sleep_state; } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ - init_chromeos(prev_sleep_state == 3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -250,7 +243,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(prev_sleep_state); +#if CONFIG_LPC_TPM + init_tpm(prev_sleep_state == 3); +#endif } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 50d5b24..e950b1e 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -29,6 +29,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> +#include <tpm.h> #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> @@ -89,14 +90,6 @@ void * asmlinkage romstage_main(unsigned long bist, return setup_stack_and_mttrs(); } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */ - init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -132,7 +125,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(params->power_state->prev_sleep_state); +#if CONFIG_LPC_TPM + init_tpm(prev_sleep_state == SLEEP_STATE_S3); +#endif } void asmlinkage romstage_after_car(void) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 17bbc31..0fc0d54 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -26,6 +26,8 @@ config CHROMEOS bool "Build for ChromeOS" default n select TPM + select TPM_INIT_FAILURE_IS_FATAL + select SKIP_TPM_STARTUP_ON_NORMAL_BOOT select BOOTMODE_STRAPS select ELOG help diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 5c7140f..6e416ee 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -32,7 +32,6 @@ verstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c romstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c -romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c verstage-y += fmap.c diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index e495a11..c7048dd 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -39,9 +39,6 @@ void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); #if CONFIG_CHROMEOS -/* functions implemented in vboot.c */ -void init_chromeos(int bootmode); - /* functions implemented in elog.c */ void elog_add_boot_reason(void); @@ -53,7 +50,6 @@ int vboot_enable_developer(void); int vboot_enable_recovery(void); int vboot_skip_display_init(void); #else -static inline void init_chromeos(int bootmode) { } static inline void elog_add_boot_reason(void) { return; } static inline void elog_add_watchdog_reset(void) { return; } static inline void reboot_from_watchdog(void) { return; } diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c deleted file mode 100644 index 6678aaa..0000000 --- a/src/vendorcode/google/chromeos/vboot.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <types.h> -#include <console/cbmem_console.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <tpm.h> -#include <reset.h> -#include "chromeos.h" - -//#define EXTRA_LOGGING -#define UBOOT_DOES_TPM_STARTUP - -#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ - -#define TPM_SUCCESS ((u32)0x00000000) - -#define TPM_E_IOERROR ((u32)0x0000001f) -#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) -#define TPM_E_NON_FATAL ((u32)0x00000800) -#define TPM_E_INVALID_POSTINIT ((u32)0x00000026) - -#define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) -#define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) - -#if CONFIG_NO_TPM_RESUME -static void init_vboot(int bootmode) -{ -} -#else -static const struct { - u8 buffer[12]; -} tpm_resume_cmd = { - { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 } -}; - -static const struct { - u8 buffer[12]; -} tpm_startup_cmd = { - {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1 } -}; - -static const struct { - u8 buffer[10]; -} tpm_continueselftest_cmd = { - { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } -}; - -static inline void FromTpmUint32(const u8 * buffer, u32 * x) -{ - *x = ((buffer[0] << 24) | - (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]); -} - -static inline int TpmCommandSize(const u8 * buffer) -{ - u32 size; - FromTpmUint32(buffer + sizeof(u16), &size); - return (int)size; -} - -/* Gets the code field of a TPM command. */ -static inline int TpmCommandCode(const u8 * buffer) -{ - u32 code; - FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code); - return code; -} - -/* Gets the return code field of a TPM result. */ -static inline int TpmReturnCode(const u8 * buffer) -{ - return TpmCommandCode(buffer); -} - -/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or - * DOING_SELFTEST errors are returned. - */ -static u32 TlclSendReceiveNoRetry(const u8 * request, - u8 * response, int max_length) -{ - size_t response_length = max_length; - u32 result; - -#ifdef EXTRA_LOGGING - printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n", - request[0], request[1], - request[2], request[3], request[4], request[5], - request[6], request[7], request[8], request[9]); -#endif - - result = TPM_SUCCESS; - if (tis_sendrecv - (request, TpmCommandSize(request), response, &response_length)) - result = TPM_E_IOERROR; - - if (0 != result) { - /* Communication with TPM failed, so response is garbage */ - printk(BIOS_DEBUG, - "TPM: command 0x%x send/receive failed: 0x%x\n", - TpmCommandCode(request), result); - return TPM_E_COMMUNICATION_ERROR; - } - /* Otherwise, use the result code from the response */ - result = TpmReturnCode(response); - -/* TODO: add paranoia about returned response_length vs. max_length - * (and possibly expected length from the response header). See - * crosbug.com/17017 */ - -#ifdef EXTRA_LOGGING - printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n", - response[0], response[1], - response[2], response[3], response[4], response[5], - response[6], response[7], response[8], response[9]); -#endif - - printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", - TpmCommandCode(request), result); - - return result; -} - -static inline u32 TlclContinueSelfTest(void) -{ - u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - printk(BIOS_DEBUG, "TPM: Continue self test\n"); - /* Call the No Retry version of SendReceive to avoid recursion. */ - return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, - response, sizeof(response)); -} - -/* Sends a TPM command and gets a response. Returns 0 if success or the TPM - * error code if error. In the firmware, waits for the self test to complete - * if needed. In the host, reports the first error without retries. */ -static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length) -{ - u32 result = TlclSendReceiveNoRetry(request, response, max_length); - /* When compiling for the firmware, hide command failures due to the self - * test not having run or completed. */ - /* If the command fails because the self test has not completed, try it - * again after attempting to ensure that the self test has completed. */ - if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { - result = TlclContinueSelfTest(); - if (result != TPM_SUCCESS) { - return result; - } -#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) - /* Retry only once */ - result = TlclSendReceiveNoRetry(request, response, max_length); -#else - /* This needs serious testing. The TPM specification says: - * "iii. The caller MUST wait for the actions of - * TPM_ContinueSelfTest to complete before reissuing the - * command C1." But, if ContinueSelfTest is non-blocking, how - * do we know that the actions have completed other than trying - * again? */ - do { - result = - TlclSendReceiveNoRetry(request, response, - max_length); - } while (result == TPM_E_DOING_SELFTEST); -#endif - } - - return result; -} - -static void init_vboot(int bootmode) -{ - u32 result; - u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - -#ifdef UBOOT_DOES_TPM_STARTUP - /* Doing TPM startup when we're not coming in on the S3 resume path - * saves us roughly 20ms in boot time only. This does not seem to - * be worth an API change to vboot_reference-firmware right now, so - * let's keep the code around, but just bail out early: - */ - if (bootmode != 2) - return; -#endif - - printk(BIOS_DEBUG, "Verified boot TPM initialization.\n"); - - printk(BIOS_SPEW, "TPM: Init\n"); - if (tis_init()) - return; - - printk(BIOS_SPEW, "TPM: Open\n"); - if (tis_open()) - return; - - - if (bootmode == 2) { - /* S3 Resume */ - printk(BIOS_SPEW, "TPM: Resume\n"); - result = TlclSendReceive(tpm_resume_cmd.buffer, - response, sizeof(response)); - if (result == TPM_E_INVALID_POSTINIT) { - /* We're on a platform where the TPM maintains power - * in S3, so it's already initialized. - */ - printk(BIOS_DEBUG, "TPM: Already initialized.\n"); - return; - } - } else { - printk(BIOS_SPEW, "TPM: Startup\n"); - result = TlclSendReceive(tpm_startup_cmd.buffer, - response, sizeof(response)); - } - - if (result == TPM_SUCCESS) { - printk(BIOS_SPEW, "TPM: OK.\n"); - return; - } - -#if !MOCK_TPM - printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result); - post_code(POST_TPM_FAILURE); - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) - cbmem_dump_console(); - hard_reset(); -#endif -} -#endif - -void init_chromeos(int bootmode) -{ - init_vboot(bootmode); -}

1 0

Patch set updated for coreboot: aec1628 Deactivate TPM
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10270 -gerrit commit aec1628c7b8f5c4459677c18758b066c66c5f6e3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:46:57 2015 +0200 Deactivate TPM Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/pc80/tpm/Kconfig | 7 +++++++ src/drivers/pc80/tpm/acpi/tpm.asl | 10 +++++----- src/drivers/pc80/tpm/romstage.c | 19 +++++++++++++++++++ 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 46f404e..8c64b0d 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -37,3 +37,10 @@ config SKIP_TPM_STARTUP_ON_NORMAL_BOOT depends on LPC_TPM help Skip TPM init on normal boot. Useful if payload does TPM init. + +config TPM_DEACTIVATE + bool "Deactivate TPM" + default n + depends on LPC_TPM + help + Deactivate TPM by issuing deactivate command. diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl index 30b14ce..0562f2a 100644 --- a/src/drivers/pc80/tpm/acpi/tpm.asl +++ b/src/drivers/pc80/tpm/acpi/tpm.asl @@ -27,11 +27,11 @@ Device (TPM) Method (_STA, 0) { - If (CONFIG_LPC_TPM) { - Return (0xf) - } Else { - Return (0x0) - } +#if CONFIG_LPC_TPM && !CONFIG_TPM_DEACTIVATE + Return (0xf) +#else + Return (0x0) +#endif } Name (IBUF, ResourceTemplate () diff --git a/src/drivers/pc80/tpm/romstage.c b/src/drivers/pc80/tpm/romstage.c index 5e29e3a..96760e2 100644 --- a/src/drivers/pc80/tpm/romstage.c +++ b/src/drivers/pc80/tpm/romstage.c @@ -51,6 +51,12 @@ static const struct { }; static const struct { + u8 buffer[12]; +} tpm_deactivate_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x3 } +}; + +static const struct { u8 buffer[10]; } tpm_continueselftest_cmd = { { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } @@ -181,6 +187,19 @@ void init_tpm(int s3resume) u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + if (CONFIG_TPM_DEACTIVATE) { + printk(BIOS_SPEW, "TPM: Deactivate\n"); + result = TlclSendReceive(tpm_deactivate_cmd.buffer, + response, sizeof(response)); + if (result == TPM_SUCCESS) { + printk(BIOS_SPEW, "TPM: OK.\n"); + return; + } + + printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); + return; + } + /* Doing TPM startup when we're not coming in on the S3 resume path * saves us roughly 20ms in boot time only. This does not seem to * be worth an API change to vboot_reference-firmware right now, so

1 0

Patch set updated for coreboot: 9f8fe89 Hide TPM_TIS_BASE_ADDRESS
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10271 -gerrit commit 9f8fe8918c1098cb4291af434a3c32712af09fb7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 20 12:05:39 2015 +0200 Hide TPM_TIS_BASE_ADDRESS TPM_TIS_BASE_ADDRESS is technical setting, shouldn't be user-visible. Change-Id: Ibf74f52be16fb7d2cfa78419087a4c3e7607368a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/pc80/tpm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 8c64b0d..1483871 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -14,7 +14,7 @@ config LPC_TPM If unsure, say N. config TPM_TIS_BASE_ADDRESS - hex "TPM Base Address" + hex default 0xfed40000 depends on LPC_TPM help

1 0

Patch set updated for coreboot: 95f9998 x201: Add TPM declaration.
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10278 -gerrit commit 95f999880f6b8993a69bd8328fa66d29308d3556 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 21 09:28:14 2015 +0200 x201: Add TPM declaration. This allows to deactivate TPM on X201. Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 1 + src/mainboard/lenovo/x201/devicetree.cb | 3 +++ src/mainboard/lenovo/x201/dsdt.asl | 8 ++++++++ src/mainboard/lenovo/x201/romstage.c | 5 +++++ 4 files changed, 17 insertions(+) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 93bfb02..7f96cbe 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index d892926..f87ab10 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -153,6 +153,9 @@ chip northbridge/intel/nehalem # DLPC, not connected device pnp 164e.19 off end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 20d647e..dab66e4 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -87,6 +87,14 @@ DefinitionBlock( } } +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + /* Chipset specific sleep states */ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8d12890..1e335d3 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -37,6 +37,7 @@ #include <timestamp.h> #include <arch/acpi.h> #include <cbmem.h> +#include <tpm.h> #include "gpio.h" #include "dock.h" @@ -306,5 +307,9 @@ void main(unsigned long bist) } #endif +#if CONFIG_LPC_TPM + init_tpm(s3resume); +#endif + timestamp_add_now(TS_END_ROMSTAGE); }

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Patch set updated for coreboot: 520f258 Add TCPA table.
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10274 -gerrit commit 520f258c60c0d6e03dc5afb9f894231977ed1e7c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 20 19:52:01 2015 +0200 Add TCPA table. This allows SeaBIOS to fill it as necessarry. This is the last step to make BitLocker work. Change-Id: I35858cd31a90c799ee1a240547c4b4a80fa13dd8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 69 ++++++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 7 ++++ src/include/cbmem.h | 1 + 3 files changed, 77 insertions(+) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index b2e0df3..4d7fb27 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -249,6 +249,65 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) header->checksum = acpi_checksum((void *)mcfg, header->length); } +#if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static void *get_tcpa_log(u32 *size) +{ + const struct cbmem_entry *ce; + const u32 tcpa_default_log_len = 0x10000; + void *lasa; + ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); + if (ce) { + lasa = cbmem_entry_start(ce); + *size = cbmem_entry_size(ce); + printk(BIOS_DEBUG, "TCPA log found at %p\n", lasa); + return lasa; + } + lasa = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_default_log_len); + if (!lasa) { + printk(BIOS_ERR, "TCPA log creation failed\n"); + return NULL; + } + + printk(BIOS_DEBUG, "TCPA log created at %p\n", lasa); + memset (lasa, 0, tcpa_default_log_len); + + *size = tcpa_default_log_len; + return lasa; +} + +static void acpi_create_tcpa(acpi_tcpa_t *tcpa) +{ + acpi_header_t *header = &(tcpa->header); + u32 tcpa_log_len; + void *lasa; + + memset((void *)tcpa, 0, sizeof(acpi_tcpa_t)); + + lasa = get_tcpa_log(&tcpa_log_len); + if (!lasa) { + return; + } + + /* Fill out header fields. */ + memcpy(header->signature, "TCPA", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_tcpa_t); + header->revision = 2; + + tcpa->platform_class = 0; + tcpa->laml = tcpa_log_len; + tcpa->lasa = (u32) lasa; + + /* Calculate checksum. */ + header->checksum = acpi_checksum((void *)tcpa, header->length); +} + +#endif + #if !IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) /* * This can be overridden by platform ACPI setup code, if it calls @@ -710,6 +769,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *dsdt; acpi_mcfg_t *mcfg; + acpi_tcpa_t *tcpa; acpi_madt_t *madt; struct device *dev; unsigned long fw; @@ -808,6 +868,15 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, mcfg); } + printk(BIOS_DEBUG, "ACPI: * TCPA\n"); + tcpa = (acpi_tcpa_t *) current; + acpi_create_tcpa(tcpa); + if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { + current += tcpa->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, tcpa); + } + printk(BIOS_DEBUG, "ACPI: * MADT\n"); madt = (acpi_madt_t *) current; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 067a26a..891b711 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -129,6 +129,13 @@ typedef struct acpi_mcfg { u8 reserved[8]; } __attribute__ ((packed)) acpi_mcfg_t; +typedef struct acpi_tcpa { + struct acpi_table_header header; + u16 platform_class; + u32 laml; + u64 lasa; +} __attribute__ ((packed)) acpi_tcpa_t; + typedef struct acpi_mcfg_mmconfig { u32 base_address; u32 base_reserved; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 20cc174..b56a51b 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -86,6 +86,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 +#define CBMEM_ID_TCPA_LOG 0x54435041 #ifndef __ASSEMBLER__ #include <stddef.h>

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Patch set updated for coreboot: 016293a x230: Add TPM declaration.
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10273 -gerrit commit 016293ae52e080b2971844d47f6b9c350066302f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 13 17:47:58 2015 +0200 x230: Add TPM declaration. This allows to deactivate TPM on X230. Change-Id: I73d4272da62335ec3766ce4814d5b46538b190fe Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/Kconfig | 1 + src/mainboard/lenovo/x230/devicetree.cb | 4 ++++ src/mainboard/lenovo/x230/dsdt.asl | 8 ++++++++ 3 files changed, 13 insertions(+) diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 05b7506..1551e27 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 + select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 55677a3..c8274e2 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -128,6 +128,10 @@ chip northbridge/intel/sandybridge register "dock_event_enable" = "0x01" end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 94da7ba..a63606e 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -50,6 +50,14 @@ DefinitionBlock( #include <southbridge/intel/bd82x6x/acpi/pch.asl> } } +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>

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Patch set updated for coreboot: 8515e0b sandybridge native: Add call to TPM code.
by Vladimir Serbinenko 21 May '15

21 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10272 -gerrit commit 8515e0b8ebc36f88d58209d221a7e922f7e69194 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:31:35 2015 +0200 sandybridge native: Add call to TPM code. This allows to deactivate TPM on boards using native sandy/ivy init. Change-Id: I9455179c7b51097a3a9554c16a407365fbc65e6f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/romstage_native.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 657ceb8..45f671c 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -32,6 +32,7 @@ #include <device/pci_def.h> #include <device/device.h> #include <halt.h> +#include <tpm.h> #include "raminit_native.h" #include <northbridge/intel/sandybridge/chip.h> #include "southbridge/intel/bd82x6x/pch.h" @@ -129,6 +130,10 @@ void main(unsigned long bist) northbridge_romstage_finalize(s3resume); +#if CONFIG_LPC_TPM + init_tpm(s3resume); +#endif + post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); }

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Patch merged into coreboot/master: 11b01a9 Kill ENABLE_TPM.
by gerrit＠coreboot.org 21 May '15

21 May '15

the following patch was just integrated into master: commit 11b01a957439d0406b607ee8c8160e319672bf45 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 20 11:14:25 2015 +0200 Kill ENABLE_TPM. It's used only in P470 and lynxpoint machines. Remove it from other southbridges. New machines should use src/drivers/pc80/tpm. Change-Id: I4741e76df4c6204d65562f016abac9ed60558432 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10268 for details. -gerrit

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