coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

1 participants
1299 discussions

New patch to review for coreboot: 0d5ecaa tpm: Add Infineon TPM 1.2 support
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10302 -gerrit commit 0d5ecaab5d2fc7e5b10bd9ef1749960919653070 Author: Subrata <subrata.banik(a)intel.com> Date: Thu May 14 14:38:07 2015 +0530 tpm: Add Infineon TPM 1.2 support This patch provides support for TPM Infineon TT1.2 devices by enumerating the TT1.2 ID in the Infineon device list. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I9daecc09311477fd9947e829d80abc040b2c9e3d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3ff86f96cb3e2f203dbc86e7004f1a037b98b90a Original-Change-Id: I8b59eba348fc44632e22600646eb0b10eb2f4901 Original-Signed-off-by: Subrata <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271256 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> --- src/drivers/pc80/tpm/tpm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c index 12eba28..1013c05 100644 --- a/src/drivers/pc80/tpm/tpm.c +++ b/src/drivers/pc80/tpm/tpm.c @@ -127,6 +127,7 @@ static const struct device_name atmel_devices[] = { static const struct device_name infineon_devices[] = { {0x000b, "SLB9635 TT 1.2"}, + {0x001a, "SLB9660 TT 1.2"}, {0xffff} };

1 0

Patch merged into coreboot/master: e288758 bd82x6x: Merge common platform ASL code.
by gerrit＠coreboot.org 25 May '15

25 May '15

the following patch was just integrated into master: commit e288758b0388f11650ca080dfda674bf31ba2268 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun May 17 00:20:52 2015 +0200 bd82x6x: Merge common platform ASL code. This code in reality just describes the southbridge features, don't put a copy in every mainboard. Change-Id: I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10231 Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10231 for details. -gerrit

1 0

Patch merged into coreboot/master: 1f8e4cb cbfstool: update fmd_scanner.c_shipped
by gerrit＠coreboot.org 25 May '15

25 May '15

the following patch was just integrated into master: commit 1f8e4cbd5392acdde28e0125aa111ec01a2f6bd2 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon May 25 22:53:19 2015 +0200 cbfstool: update fmd_scanner.c_shipped We updated the source files, but not the precompiled results. Change-Id: I49634409d01c8d7cf841944e01d36571ae66c0ac Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10296 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/10296 for details. -gerrit

1 0

Patch merged into coreboot/master: d07ff9e build system: only query the compiler runtime's location once
by gerrit＠coreboot.org 25 May '15

25 May '15

the following patch was just integrated into master: commit d07ff9eb27a6b96e19e108eb25f1ac9dd79f8efd Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon May 25 20:12:59 2015 +0200 build system: only query the compiler runtime's location once No need to execute the compiler to figure this out once for each source file (or so). Change-Id: I56bf084f1217b96748296931617e9233f21183d5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10294 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10294 for details. -gerrit

1 0

Patch set updated for coreboot: db4e59d x230: Fix headset microphone support.
by Vladimir Serbinenko 25 May '15

25 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10286 -gerrit commit db4e59df73890cdcabfdf3f9ede61fec4bd199c4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 25 01:47:20 2015 +0200 x230: Fix headset microphone support. Previously only internal mic really worked but since it's of good quality it's not really noticeable. Change-Id: Ie14c377b0370302d97e1f89eae5787e05e73b7d2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/hda_verb.c | 42 +++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/src/mainboard/lenovo/x230/hda_verb.c b/src/mainboard/lenovo/x230/hda_verb.c index 317bd61..210f493 100644 --- a/src/mainboard/lenovo/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/hda_verb.c @@ -31,7 +31,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC 0x17aa21fa, // Subsystem ID - 0x00000012, // Number of 4 dword sets + 0x00000013, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -76,27 +76,35 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0), - 0x01970804, - 0x01870803, - 0x01470740, - 0x00970600, - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), /* Misc entries */ - 0x00370600, - 0x00270600, - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for - combo Jack - Master Port - Port B used for Jack Presence Detect - Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ - 0x00170500, /* Set power state to D0 */ + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970640, + + 0x00370680, + 0x00270680, + 0x01470C02, + 0x01570C02, + + /* ALC coefficients. */ + + /* 08 */ + 0x02050008, + 0x02040700, + /* 18 */ + 0x02050018, + 0x02045184, + /* 1c */ + 0x0205001c, + 0x02042800, + + 0x01870724, /* Enable Vrefout for mic */ + 0x00170500, /* Set power state to D0 */ /* --- Next Codec --- */

1 0

New patch to review for coreboot: ab9081c CBMEM console: Fix buffer without EARLY_CBMEM_INIT
by Kyösti Mälkki 25 May '15

25 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10301 -gerrit commit ab9081c5a8f488b9e60bce3c5fc371e9a7bb64cd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 06:46:41 2015 +0300 CBMEM console: Fix buffer without EARLY_CBMEM_INIT On S3 resume, CBMEM_ID_CONSOLE from previous boot is found in ramstage, even when romstage did not create it. So buffer did not get cleared on S3 resume path. Also do not allocate for preram_cbmem_console in CAR when there are no means to back it up to ram. Change-Id: I175cebbb938adf2a7414703fefffb8da796e9fa9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/romstage.ld | 2 +- src/lib/cbmem_console.c | 7 ++----- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 27e8de1..ae7049b 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -65,7 +65,7 @@ SECTIONS * statically checked because the cache-as-ram region usage is * cpu/chipset dependent. */ _preram_cbmem_console = .; - _epreram_cbmem_console = . + 0xc00; + _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); } /* Global variables are not allowed in romstage diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 30bf439..e9607f3 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -225,11 +225,8 @@ void cbmemc_reinit(void) /* Need to reset the newly added cbmem console in ramstage * when there was no console in preram environment. */ - if (ENV_RAMSTAGE) { - cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); - if (cbm_cons_p == NULL) - flags |= CBMEMC_RESET; - } + if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) + flags |= CBMEMC_RESET; /* If CBMEM entry already existed, old contents is not altered. */ cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, size);

1 0

New patch to review for coreboot: ed15047 timestamp: Fix collection without EARLY_CBMEM_INIT
by Kyösti Mälkki 25 May '15

25 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10300 -gerrit commit ed15047544ecdf3cef5eb6fc58da3f7a6fdca0e9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 06:23:02 2015 +0300 timestamp: Fix collection without EARLY_CBMEM_INIT With LATE_CBMEM_INIT, do not search for the initial collection from CBMEM in ramstage. On S3 resume this would find the non-empty collection from previous run of ramstage. Start with an empty table instead. Remove a spurious error message as the stamps get stashed and will be copied to CBMEM later. Change-Id: Ib94049531c0ac23af25407bd2ca7644ee0163d69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/timestamp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 98ab243..8c82649 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -42,10 +42,8 @@ static void timestamp_real_init(uint64_t base) sizeof(struct timestamp_table) + MAX_TIMESTAMPS * sizeof(struct timestamp_entry)); - if (!tst) { - printk(BIOS_ERR, "ERROR: failed to allocate timestamp table\n"); + if (!tst) return; - } tst->base_time = base; tst->max_entries = MAX_TIMESTAMPS; @@ -142,10 +140,12 @@ void timestamp_init(uint64_t base) /* Copy of basetime, it is too early for CBMEM. */ car_set_var(ts_basetime, base); #else - struct timestamp_table* tst; + struct timestamp_table *tst = NULL; /* Locate and use an already existing table. */ - tst = cbmem_find(CBMEM_ID_TIMESTAMP); + if (!IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) + tst = cbmem_find(CBMEM_ID_TIMESTAMP); + if (tst) { car_set_var(ts_table_p, tst); return;

1 0

Patch merged into coreboot/master: 32532ac cbfstool: Make update-fit action work on new-style images
by gerrit＠coreboot.org 25 May '15

25 May '15

the following patch was just integrated into master: commit 32532ac92dd83d08e5d10de2d3a41fe3c9092e2c Author: Sol Boucher <solb(a)chromium.org> Date: Wed May 6 14:44:40 2015 -0700 cbfstool: Make update-fit action work on new-style images Because new images place the bootblock in a separate region from the primary CBFS, performing an update-fit operation requires reading an additional section and choosing a different destination for the write based on the image type. Since other actions are not affected by these requirements, the logic for the optional read and all writing is implemented in the cbfs_update_fit() function itself, rather than relying on the main() function for writing as the other actions do. Change-Id: I2024c59715120ecc3b9b158e007ebce75acff023 Signed-off-by: Sol Boucher <solb(a)chromium.org> Reviewed-on: http://review.coreboot.org/10137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10137 for details. -gerrit

1 0

New patch to review for coreboot: 9f0f0a6 CBMEM: Fix S3 resume path without EARLY_CBMEM_INIT
by Kyösti Mälkki 25 May '15

25 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10299 -gerrit commit 9f0f0a6ab0662764c1ae88f0a550e8192e4779cd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 00:30:10 2015 +0300 CBMEM: Fix S3 resume path without EARLY_CBMEM_INIT Implementation for cbmem_find() did not work for boards without EARLY_CBMEM_INIT in romstage. This is required for S3 resume to work on AGESA plaforms. First broken with commit 0dff57d cbmem: switch over to imd-based cbmem Change-Id: I9c1a4f6839f5d90f825787baad2a3824a04b5bdc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 1 - src/lib/imd_cbmem.c | 7 ++++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 9ee5db4..30206b7 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -43,7 +43,6 @@ void set_top_of_ram(uint64_t ramtop) unsigned long __attribute__((weak)) get_top_of_ram(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index fc12c25..8e6a99a 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -97,8 +97,9 @@ static struct imd *imd_init_backing_with_recover(struct imd *backing) imd = imd_init_backing(backing); if (!ENV_RAMSTAGE) { /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) + if (cbmem_top() != NULL) imd_handle_init(imd, cbmem_top()); + /* Need to partially recover all the time outside of ramstage * because there's object storage outside of the stack. */ imd_handle_init_partial_recovery(imd); @@ -120,7 +121,7 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) imd = imd_init_backing(&imd_backing); /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) + if (cbmem_top() != NULL) imd_handle_init(imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); @@ -159,7 +160,7 @@ int cbmem_initialize_id_size(u32 id, u64 size) imd = imd_init_backing(&imd_backing); /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) + if (cbmem_top() != NULL) imd_handle_init(imd, cbmem_top()); if (imd_recover(imd))

1 0

Patch set updated for coreboot: 1de9f40 acpi/sata: add generic sata ssdt port generator
by Alexander Couzens 25 May '15

25 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9708 -gerrit commit 1de9f40e92b91a452cd58ad42ae4a0236f334255 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:03:26 2015 +0200 acpi/sata: add generic sata ssdt port generator generate_sata_ssdt_ports() generates ports based on sata enable map Change-Id: Ie68e19c93f093d6c61634c4adfde484b88f28a77 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- Makefile.inc | 2 +- src/Kconfig | 2 ++ src/acpi/Kconfig | 6 +++++ src/acpi/Makefile.inc | 1 + src/acpi/sata.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/acpi/sata.h | 4 ++++ 6 files changed, 75 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 0c688f7..03b4489 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,7 +52,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/console src/device +subdirs-y := src/lib src/console src/device src/acpi subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode diff --git a/src/Kconfig b/src/Kconfig index 8751d5b..0c4d377 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -320,6 +320,8 @@ config RAM_CODE_SUPPORT endmenu +source "src/acpi/Kconfig" + source "src/mainboard/Kconfig" source "src/arch/*/Kconfig" diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig new file mode 100644 index 0000000..e025f99 --- /dev/null +++ b/src/acpi/Kconfig @@ -0,0 +1,6 @@ + +config ACPI_SATA_GENERATOR + bool + default n + help + Use acpi sata port generator. diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc new file mode 100644 index 0000000..53ac679 --- /dev/null +++ b/src/acpi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_ACPI_SATA_GENERATOR) += sata.c diff --git a/src/acpi/sata.c b/src/acpi/sata.c new file mode 100644 index 0000000..b488574 --- /dev/null +++ b/src/acpi/sata.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "sata.h" + +#include <arch/acpi.h> +#include <arch/acpigen.h> + +/* e.g. + * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); + * generates: + * Scope (\_SB.PCI0.SATA) + * { + * Device (PRT0) + * { + * Name (_ADR, 0x0000FFFF) // _ADR: Address + * } + * + * Device (PRT1) + * { + * Name (_ADR, 0x0001FFFF) // _ADR: Address + * } + * } + */ +void generate_sata_ssdt_ports(const char *scope, uint8_t enable_map) +{ + int i; + int bit; + char port_name[4] = "PRT0"; + + acpigen_write_scope(scope); + + /* generate a device for every enabled port */ + for (i = 0; i < 8; i++) { + bit = 1 << i; + if (!(bit & enable_map)) + continue; + + port_name[3] = '0' + i; + acpigen_write_device(port_name); + + acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000); + acpigen_pop_len(); /* close PRT%d */ + } + + acpigen_pop_len(); /* close scope */ +} diff --git a/src/acpi/sata.h b/src/acpi/sata.h new file mode 100644 index 0000000..affaa34 --- /dev/null +++ b/src/acpi/sata.h @@ -0,0 +1,4 @@ + +#include <stdint.h> + +void generate_sata_ssdt_ports(const char *scope, uint8_t enable_map);

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2015