coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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1299 discussions

Patch set updated for coreboot: f5f5e18 acpigen: Remove acpigen_patch_len
by Vladimir Serbinenko 26 May '15

26 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7365 -gerrit commit f5f5e18064d91c8f905ae4241e446f914d05c6e2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 03:33:51 2014 +0100 acpigen: Remove acpigen_patch_len Change-Id: I77276342b3f44c7c845a10682ff1f15599c4c721 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 13 +------------ src/arch/x86/include/arch/acpigen.h | 1 - 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 0fb400e..108d6c8 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -22,7 +22,7 @@ /* * If you need to change this, change acpigen_write_f and - * acpigen_patch_len + * acpigen_pop_len */ #define ACPIGEN_MAXLEN 0xfff @@ -46,17 +46,6 @@ int acpigen_write_len_f(void) return 2; } -void acpigen_patch_len(int len) -{ - ASSERT(len <= ACPIGEN_MAXLEN) - ASSERT(ltop > 0) - char *p = len_stack[--ltop]; - /* generate store length for 0xfff max */ - p[0] = (0x40 | (len & 0xf)); - p[1] = (len >> 4 & 0xff); - -} - void acpigen_pop_len(void) { int len; diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index b84a979..55bc87f 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -26,7 +26,6 @@ #include <arch/acpi.h> int acpigen_write_len_f(void); -void acpigen_patch_len(int len); void acpigen_pop_len(void); void acpigen_set_current(char *curr); char *acpigen_get_current(void);

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New patch to review for coreboot: 5d238b1 arm64: Guard prints in mmu.c
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10311 -gerrit commit 5d238b1fce3e90fa7d47758e8a7243217ae219bb Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 20 17:10:55 2015 -0700 arm64: Guard prints in mmu.c We have observed issues with enabling CONFIG_SMP and adding prints before MMU is enabled on Tegra-based SoCs. This seems to be related to the hardware assisted locks and the restrictions laid down by ARMv8 spec. BUG=None BRANCH=None TEST=Boots to kernel prompt on smaug. Change-Id: I29a52f5a972baf396c01faba3ae3e5ecd27563e9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f52ee4b5b2e9b7f54eee0d105cb7e17f9a7e1613 Original-Change-Id: I432895560f468903c7beef00e78b6d38275a619c Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272449 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/mmu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 0bd678a..e16ee71 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -220,9 +220,12 @@ void mmu_config_range(void *start, size_t size, uint64_t tag) uint64_t base_addr = (uintptr_t)start; uint64_t temp_size = size; - printk(BIOS_INFO, "Mapping address range [%p:%p) as ", - start, start + size); - print_tag(BIOS_INFO, tag); + if (!IS_ENABLED(CONFIG_SMP)) { + printk(BIOS_INFO, "Mapping address range [%p:%p) as ", + start, start + size); + print_tag(BIOS_INFO, tag); + } + sanity_check(base_addr, temp_size); while (temp_size)

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New patch to review for coreboot: 64d3675 ipq806x: clear the RPM initialization Acknowledge bit
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10310 -gerrit commit 64d367592fb123b9d95ba801de3b23a3976933f1 Author: Sourabh Banerjee <sbanerje(a)codeaurora.org> Date: Fri Apr 24 22:54:18 2015 +0530 ipq806x: clear the RPM initialization Acknowledge bit The RPM initialization Acknowledge is cleared by writing 1 into bit-10 of the RPM_INT_ACK register. The existing code got it wrong and is writing zero to that bit. BRANCH=storm BUG=chrome-os-partner:39231 TEST=with this patch and an RPM firmware update, an SP4 device survived more than 1000 reboots in a row. Change-Id: Ibba296ed0571ad9403a0c51c7f82f07f185b4e83 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 13b4a0f093ba652ad6bccdfc4b3686c0741c6fe7 Original-Change-Id: I39e6ea50e0f66b4af68bdb868dd4437c34bb4524 Original-Signed-off-by: Viswanath Kraleti <vkraleti(a)codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/266969 Original-Reviewed-by: Manoj Juneja <mjuneja(a)qti.qualcomm.com> --- src/soc/qualcomm/ipq806x/blobs_init.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index dc52200..ae7e4d4 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -131,7 +131,11 @@ void start_rpm(void) printk(BIOS_INFO, "Starting RPM\n"); /* Clear 'ready' indication. */ - write32(RPM_INT_ACK, read32(RPM_INT_ACK) & ~ready_mask); + /* + * RPM_INT_ACK is clear-on-write type register, + * read-modify-write is not recommended. + */ + write32(RPM_INT_ACK, ready_mask); /* Set RPM entry address */ write32(RPM_SIGNAL_ENTRY, load_addr);

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New patch to review for coreboot: 80d2500 arm64: Remove PLAT= variable initialization based on Kconfig variable
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10309 -gerrit commit 80d2500e2fa914d3b0c435f2030389d7c49cc798 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 20 11:31:08 2015 -0700 arm64: Remove PLAT= variable initialization based on Kconfig variable Each SoC should have a BL31_MAKEARGS += ... defining all the make arguments required for bl31 component compilation. BUG=chrome-os-partner:40414 BRANCH=None TEST=Compiles successfully and boots into bl31. Change-Id: I20383ab61d012f7294d969f196044a5f1c07dfc1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 72bd297994248a9d96acc6f21d06bb6ff0d5292c Original-Change-Id: I1ddd5c38e9214021d857d9d586310e23fa4114e0 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272430 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 66155a4..13e8415 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -186,8 +186,6 @@ ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) BL31_SOURCE := $(top)/3rdparty/arm-trusted-firmware -BL31_MAKEARGS := PLAT=$(call strip_quotes,$(CONFIG_ARM_TF_PLATFORM_NAME)) - ifeq ($(V),1) BL31_MAKEARGS += V=1 endif

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New patch to review for coreboot: e05f000 arm64: Add weak implementation of soc_get_bl31_plat_params
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10308 -gerrit commit e05f000c87b735cd2bba3459f184ea3f3b7cf6fd Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 20 11:03:50 2015 -0700 arm64: Add weak implementation of soc_get_bl31_plat_params This function is required to be implemented by SoC only if some platform specific parameters are to be passed in from the early bootloader to bl31 component. BUG=chrome-os-partner:40414 BRANCH=None TEST=Compiles successfully. Change-Id: I6e76a0b6735267971e12aa72a987e8d83f5ad102 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6ab8bc12ffc2ee5bf69cef68bae852dcbf7ccb98 Original-Change-Id: If55aaee8d18a8045a5d842145c0e2c97a37a8bca Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272377 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/arm_tf.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index c5d46e3..1bdf522 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -65,6 +65,12 @@ static void *vboot_get_bl31(void) return bl31_entry; } +void __attribute__((weak)) *soc_get_bl31_plat_params(bl31_params_t *params) +{ + /* Default weak implementation. */ + return NULL; +} + void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) { const char *bl31_filename = CONFIG_CBFS_PREFIX"/bl31";

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New patch to review for coreboot: 4d16e03 arm64: Pass in CROSS_COMPILE_arm64 for ARM TF compilation
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10307 -gerrit commit 4d16e031a280fc2eb259f19cf6e0edb222e8122a Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 20 10:12:19 2015 -0700 arm64: Pass in CROSS_COMPILE_arm64 for ARM TF compilation BUG=chrome-os-partner:40414 BRANCH=None TEST=ATF compilation successful Change-Id: Ib4eeced911181f756bd47c19eeb2d196ab5a0a2f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3061a219c24294a9fec4f26fc60b02f67bb55d66 Original-Change-Id: I39849d4048d7333eeab9bd698b4fd496181081a2 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272374 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c2980d8..66155a4 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -207,7 +207,7 @@ BL31 := $(obj)/3rdparty/arm-trusted-firmware/bl31/bl31.elf $(BL31): @printf " MAKE $(subst $(obj)/,,$(@))\n" - CROSS_COMPILE="$(CROSS_COMPILE)" \ + CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ CFLAGS="$(BL31_CFLAGS)" \ LDFLAGS="$(BL31_LDFLAGS)" \ $(MAKE) -C $(BL31_SOURCE) $(BL31_MAKEARGS) bl31

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New patch to review for coreboot: 90ea2e8 xcompile: Add CROSS_COMPILE_* variable
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10306 -gerrit commit 90ea2e8a4006cbe5e48ff00763a5d0afc931288e Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 20 10:09:45 2015 -0700 xcompile: Add CROSS_COMPILE_* variable Add CROSS_COMPILE_* variable that can be passed to third-party component compilations. BUG=chrome-os-partner:40414 BRANCH=None TEST=CROSS_COMPILE_* variable is passed in correctly. Change-Id: I053325524601adf76ea35f7e74811fbc1c31781e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c07bd66e25900d064d6c69bddada67112ba5f183 Original-Change-Id: I3e4a5262acd84830205f64ba9a935974dd36ebbd Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272372 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> --- util/xcompile/xcompile | 1 + 1 file changed, 1 insertion(+) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 37fe406..28b3d26 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -173,6 +173,7 @@ OBJDUMP_${TARCH}:=${GCCPREFIX}objdump READELF_${TARCH}:=${GCCPREFIX}readelf STRIP_${TARCH}:=${GCCPREFIX}strip AR_${TARCH}:=${GCCPREFIX}ar +CROSS_COMPILE_${TARCH}:=${GCCPREFIX} EOF }

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New patch to review for coreboot: eb43738 veyron_brain: Remove unused USB GPIOs
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10305 -gerrit commit eb43738b8e0bae6469e00305348b6b0b7d71fddf Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 14 20:02:23 2015 -0700 veyron_brain: Remove unused USB GPIOs Brain doesn't have HOST1_PWR_EN (GPIO0_B3) and 5V_DRV (GPIO7_C5). The only USB power enable pin connected to the AP is USB2_PWR_EN (GPIO0_B4) which controls power for both the physical type-A ports. BUG=none BRANCH=none TEST=built and booted on Brain, both USB host mode ports work Change-Id: Iea371926c7dcd111aa2e671a15fe97a3519bfc04 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4db71095a5116666cd27aedb09b4f02557362346 Original-Change-Id: Ibbb4b9b424156eb3db1ccfdd948050c1c067ad3c Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271309 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_brain/mainboard.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mainboard/google/veyron_brain/mainboard.c b/src/mainboard/google/veyron_brain/mainboard.c index 4aa4770..a5c40c23 100644 --- a/src/mainboard/google/veyron_brain/mainboard.c +++ b/src/mainboard/google/veyron_brain/mainboard.c @@ -43,9 +43,7 @@ static void configure_usb(void) { - gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */ - gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */ - gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */ + gpio_output(GPIO(0, B, 4), 1); /* USB2_PWR_EN */ } static void configure_emmc(void)

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New patch to review for coreboot: f9001c6 arm64: Decouple MMU functions from memranges
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10304 -gerrit commit f9001c647eb692c0c179efa8e469e977d2b55fe0 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon May 18 13:11:12 2015 -0700 arm64: Decouple MMU functions from memranges The current arm64 MMU interface is difficult to use in pre-RAM environments. It is based on the memranges API which makes use of malloc(), and early stages usually don't have a heap. It is also built as a one-shot interface that requires all memory ranges to be laid out beforehand, which is a problem when existing areas need to change (e.g. after initializing DRAM). The long-term goal of this patch is to completely switch to a configure-as-you-go interface based on the mmu_config_range() function, similar to what ARM32 does. As a first step this feature is added side-by-side to the existing interface so that existing SoC implementations continue to work and can be slowly ported over one by one. Like the ARM32 version it does not garbage collect page tables that become unused, so repeated mapping at different granularities will exhaust the available table space (this is presumed to be a reasonable limitation for a firmware environment and keeps the code much simpler). Also do some cleanup, align comments between coreboot and libpayload for easier diffing, and change all error cases to assert()s. Right now the code just propagates error codes up the stack until it eventually reaches a function that doesn't check them anymore. MMU configuration errors (essentially just misaligned requests and running out of table space) should always be compile-time programming errors, so failing hard and fast seems like the best way to deal with them. BRANCH=None BUG=None TEST=Compile-tested rush_ryu. Booted on Oak and hacked MMU init to use mmu_config_range() insted of memranges. Confirmed that CRCs over all page tables before and after the change are equal. Change-Id: I93585b44a277c1d96d31ee9c3dd2522b5e10085b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f10fcba107aba1f3ea239471cb5a4f9239809539 Original-Change-Id: I6a2a11e3b94e6ae9e1553871f0cccd3b556b3e65 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271991 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/arch/arm64/mmu.c | 193 ++++++++++--------------- payloads/libpayload/include/arm64/arch/cache.h | 16 -- payloads/libpayload/include/arm64/arch/mmu.h | 3 + src/arch/arm64/armv8/mmu.c | 169 ++++++++++------------ src/arch/arm64/include/armv8/arch/mmu.h | 2 + 5 files changed, 153 insertions(+), 230 deletions(-) diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index f0781f5..e2a0cb1 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -44,6 +44,12 @@ static uint64_t *xlat_addr; static int free_idx; static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE))); +static const char * const tag_to_string[] = { + [TYPE_NORMAL_MEM] = "normal", + [TYPE_DEV_MEM] = "device", + [TYPE_DMA_MEM] = "uncached", +}; + /* * The usedmem_ranges is used to describe all the memory ranges that are * actually used by payload i.e. _start -> _end in linker script and the @@ -56,25 +62,12 @@ static uint8_t ttb_buffer[TTB_DEFAULT_SIZE] __attribute__((aligned(GRANULE_SIZE) */ static struct mmu_ranges usedmem_ranges; -static const uint64_t level_to_addr_mask[] = { - L1_ADDR_MASK, - L2_ADDR_MASK, - L3_ADDR_MASK, -}; - -static const uint64_t level_to_addr_shift[] = { - L1_ADDR_SHIFT, - L2_ADDR_SHIFT, - L3_ADDR_SHIFT, -}; - static void __attribute__((noreturn)) mmu_error(void) { halt(); } -/* - * Func : get_block_attr +/* Func : get_block_attr * Desc : Get block descriptor attributes based on the value of tag in memrange * region */ @@ -107,21 +100,7 @@ static uint64_t get_block_attr(unsigned long tag) return attr; } -/* - * Func : get_index_from_addr - * Desc : Get index into table at a given level using appropriate bits from the - * base address - */ -static uint64_t get_index_from_addr(uint64_t addr, uint8_t level) -{ - uint64_t mask = level_to_addr_mask[level-1]; - uint8_t shift = level_to_addr_shift[level-1]; - - return ((addr & mask) >> shift); -} - -/* - * Func : table_desc_valid +/* Func : table_desc_valid * Desc : Check if a table entry contains valid desc */ static uint64_t table_desc_valid(uint64_t desc) @@ -129,29 +108,34 @@ static uint64_t table_desc_valid(uint64_t desc) return((desc & TABLE_DESC) == TABLE_DESC); } -/* - * Func : get_new_table - * Desc : Return the next free XLAT table from ttb buffer +/* Func : setup_new_table + * Desc : Get next free table from TTB and set it up to match old parent entry. */ -static uint64_t *get_new_table(void) +static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size) { - uint64_t *new; + uint64_t *new, *entry; - if (free_idx >= max_tables) { - printf("ARM64 MMU: No free table\n"); - return NULL; - } + assert(free_idx < max_tables); new = (uint64_t*)((unsigned char *)xlat_addr + free_idx * GRANULE_SIZE); free_idx++; - memset(new, 0, GRANULE_SIZE); + if (!desc) { + memset(new, 0, GRANULE_SIZE); + } else { + /* Can reuse old parent entry, but may need to adjust type. */ + if (xlat_size == L3_XLAT_SIZE) + desc |= PAGE_DESC; + + for (entry = new; (u8 *)entry < (u8 *)new + GRANULE_SIZE; + entry++, desc += xlat_size) + *entry = desc; + } return new; } -/* - * Func : get_table_from_desc +/* Func : get_table_from_desc * Desc : Get next level table address from table descriptor */ static uint64_t *get_table_from_desc(uint64_t desc) @@ -160,27 +144,23 @@ static uint64_t *get_table_from_desc(uint64_t desc) return ptr; } -/* - * Func: get_next_level_table - * Desc: Check if the table entry is a valid descriptor. If not, allocate new +/* Func: get_next_level_table + * Desc: Check if the table entry is a valid descriptor. If not, initialize new * table, update the entry and return the table addr. If valid, return the addr. */ -static uint64_t *get_next_level_table(uint64_t *ptr) +static uint64_t *get_next_level_table(uint64_t *ptr, size_t xlat_size) { uint64_t desc = *ptr; if (!table_desc_valid(desc)) { - uint64_t *new_table = get_new_table(); - if (new_table == NULL) - return NULL; + uint64_t *new_table = setup_new_table(desc, xlat_size); desc = ((uint64_t)new_table) | TABLE_DESC; *ptr = desc; } return get_table_from_desc(desc); } -/* - * Func : init_xlat_table +/* Func : init_xlat_table * Desc : Given a base address and size, it identifies the indices within * different level XLAT tables which map the given base addr. Similar to table * walk, except that all invalid entries during the walk are updated @@ -191,18 +171,16 @@ static uint64_t init_xlat_table(uint64_t base_addr, uint64_t size, uint64_t tag) { - uint64_t l1_index = get_index_from_addr(base_addr,1); - uint64_t l2_index = get_index_from_addr(base_addr,2); - uint64_t l3_index = get_index_from_addr(base_addr,3); + uint64_t l1_index = (base_addr & L1_ADDR_MASK) >> L1_ADDR_SHIFT; + uint64_t l2_index = (base_addr & L2_ADDR_MASK) >> L2_ADDR_SHIFT; + uint64_t l3_index = (base_addr & L3_ADDR_MASK) >> L3_ADDR_SHIFT; uint64_t *table = xlat_addr; uint64_t desc; uint64_t attr = get_block_attr(tag); - /* - * L1 table lookup + /* L1 table lookup * If VA has bits more than L2 can resolve, lookup starts at L1 - * Assumption: we don't need L0 table in coreboot - */ + * Assumption: we don't need L0 table in coreboot */ if (BITS_PER_VA > L1_ADDR_SHIFT) { if ((size >= L1_XLAT_SIZE) && IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) { @@ -213,94 +191,71 @@ static uint64_t init_xlat_table(uint64_t base_addr, table[l1_index] = desc; /* L2 lookup is not required */ return L1_XLAT_SIZE; - } else { - table = get_next_level_table(&table[l1_index]); - if (!table) - return 0; } + table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE); } - /* - * L2 table lookup + /* L2 table lookup * If lookup was performed at L1, L2 table addr is obtained from L1 desc - * else, lookup starts at ttbr address - */ + * else, lookup starts at ttbr address */ if ((size >= L2_XLAT_SIZE) && IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) { - /* - * If block address is aligned and size is greater than or equal - * to size addressed by each L2 entry, we can - * directly store a block desc - */ + /* If block address is aligned and size is greater than + * or equal to size addressed by each L2 entry, we can + * directly store a block desc */ desc = base_addr | BLOCK_DESC | attr; table[l2_index] = desc; /* L3 lookup is not required */ return L2_XLAT_SIZE; - } else { - /* L2 entry stores a table descriptor */ - table = get_next_level_table(&table[l2_index]); - if (!table) - return 0; } + /* L2 entry stores a table descriptor */ + table = get_next_level_table(&table[l2_index], L3_XLAT_SIZE); + /* L3 table lookup */ desc = base_addr | PAGE_DESC | attr; table[l3_index] = desc; return L3_XLAT_SIZE; } -/* - * Func : sanity_check - * Desc : Check if the address is aligned and size is atleast the granule size +/* Func : sanity_check + * Desc : Check address/size alignment of a table or page. */ -static uint64_t sanity_check(uint64_t addr, - uint64_t size) +static void sanity_check(uint64_t addr, uint64_t size) { - /* Address should be atleast 64 KiB aligned */ - if (addr & GRANULE_SIZE_MASK) - return 1; - - /* Size should be atleast granule size */ - if (size < GRANULE_SIZE) - return 1; - - return 0; + assert(!(addr & GRANULE_SIZE_MASK) && + !(size & GRANULE_SIZE_MASK) && + size >= GRANULE_SIZE); } -/* - * Func : init_mmap_entry - * Desc : For each mmap entry, this function calls init_xlat_table with the base +/* Func : mmu_config_range + * Desc : This function repeatedly calls init_xlat_table with the base * address. Based on size returned from init_xlat_table, base_addr is updated * and subsequent calls are made for initializing the xlat table until the whole * region is initialized. */ -static void init_mmap_entry(struct mmu_memrange *r) +void mmu_config_range(void *start, size_t size, uint64_t tag) { - uint64_t base_addr = r->base; - uint64_t size = r->size; - uint64_t tag = r->type; + uint64_t base_addr = (uintptr_t)start; uint64_t temp_size = size; - while (temp_size) { - uint64_t ret; - - if (sanity_check(base_addr,temp_size)) { - printf("Libpayload: ARM64 MMU: sanity check failed\n"); - return; - } - - ret = init_xlat_table(base_addr + (size - temp_size), - temp_size, tag); + assert(tag < ARRAY_SIZE(tag_to_string)); + printf("Libpayload: ARM64 MMU: Mapping address range [%p:%p) as %s\n", + start, start + size, tag_to_string[tag]); + sanity_check(base_addr, temp_size); - if (ret == 0) - return; + while (temp_size) + temp_size -= init_xlat_table(base_addr + (size - temp_size), + temp_size, tag); - temp_size -= ret; - } + /* ARMv8 MMUs snoop L1 data cache, no need to flush it. */ + dsb(); + tlbiall_current(); + dsb(); + isb(); } -/* - * Func : mmu_init +/* Func : mmu_init * Desc : Initialize mmu based on the mmu_memrange passed. ttb_buffer is used as * the base address for xlat tables. TTB_DEFAULT_SIZE defines the max number of * tables that can be used @@ -308,8 +263,6 @@ static void init_mmap_entry(struct mmu_memrange *r) */ uint64_t mmu_init(struct mmu_ranges *mmu_ranges) { - struct mmu_memrange devrange = { 0, 0x80000000, TYPE_DEV_MEM }; - int i = 0; xlat_addr = (uint64_t *)&ttb_buffer; @@ -321,11 +274,12 @@ uint64_t mmu_init(struct mmu_ranges *mmu_ranges) printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n", (void*)xlat_addr, max_tables); - init_mmap_entry(&devrange); + mmu_config_range(NULL, 0x80000000, TYPE_DEV_MEM); - for (; i < mmu_ranges->used; i++) { - init_mmap_entry(&mmu_ranges->entries[i]); - } + for (; i < mmu_ranges->used; i++) + mmu_config_range((void *)mmu_ranges->entries[i].base, + mmu_ranges->entries[i].size, + mmu_ranges->entries[i].type); printf("Libpayload ARM64: MMU init done\n"); return 0; @@ -388,8 +342,7 @@ void mmu_enable(void) /* Initialize TTBR */ raw_write_ttbr0_current((uintptr_t)xlat_addr); - /* Ensure all translation table writes are committed before enabling MMU */ - dsb(); + /* Ensure system register writes are committed before enabling MMU */ isb(); /* Enable MMU */ diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h index 7248869..de68cee 100644 --- a/payloads/libpayload/include/arm64/arch/cache.h +++ b/payloads/libpayload/include/arm64/arch/cache.h @@ -117,20 +117,4 @@ static inline void icache_invalidate_all(void) : : : "memory"); } -/* - * Generalized setup/init functions - */ - -enum dcache_policy { - DCACHE_OFF, - DCACHE_WRITEBACK, - DCACHE_WRITETHROUGH, -}; - -/* disable the mmu for a range. Primarily useful to lock out address 0. */ -void mmu_disable_range(unsigned long start_mb, unsigned long size_mb); -/* mmu range configuration (set dcache policy) */ -void mmu_config_range(unsigned long start_mb, unsigned long size_mb, - enum dcache_policy policy); - #endif /* ARM64_CACHE_H */ diff --git a/payloads/libpayload/include/arm64/arch/mmu.h b/payloads/libpayload/include/arm64/arch/mmu.h index 79bc783..30a1973 100644 --- a/payloads/libpayload/include/arm64/arch/mmu.h +++ b/payloads/libpayload/include/arm64/arch/mmu.h @@ -175,6 +175,9 @@ void mmu_enable(void); /* Disable mmu */ void mmu_disable(void); +/* Change a memory type for a range of bytes at runtime. */ +void mmu_config_range(void *start, size_t size, uint64_t tag); + /* * Based on the memory ranges provided in coreboot tables, * initialize the mmu_memranges used for mmu initialization diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 99c97fb..0bd678a 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -27,10 +27,12 @@ * SUCH DAMAGE. */ +#include <assert.h> #include <stdlib.h> #include <stdint.h> #include <string.h> +#include <console/console.h> #include <memrange.h> #include <arch/mmu.h> #include <arch/lib_helpers.h> @@ -42,17 +44,17 @@ static unsigned int max_tables; static uint64_t *xlat_addr; static int free_idx; -static const uint64_t level_to_addr_mask[] = { - L1_ADDR_MASK, - L2_ADDR_MASK, - L3_ADDR_MASK, -}; - -static const uint64_t level_to_addr_shift[] = { - L1_ADDR_SHIFT, - L2_ADDR_SHIFT, - L3_ADDR_SHIFT, -}; +static void print_tag(int level, uint64_t tag) +{ + printk(level, tag & MA_MEM_NC ? " cacheable | " : + "non-cacheable | "); + printk(level, tag & MA_RO ? "read-only | " : + "read-write | "); + printk(level, tag & MA_NS ? "non-secure | " : + " secure | "); + printk(level, tag & MA_MEM ? "normal\n" : + "device\n"); +} /* Func : get_block_attr * Desc : Get block descriptor attributes based on the value of tag in memrange @@ -79,18 +81,6 @@ static uint64_t get_block_attr(unsigned long tag) return attr; } -/* Func : get_index_from_addr - * Desc : Get index into table at a given level using appropriate bits from the - * base address - */ -static uint64_t get_index_from_addr(uint64_t addr, uint8_t level) -{ - uint64_t mask = level_to_addr_mask[level-1]; - uint8_t shift = level_to_addr_shift[level-1]; - - return ((addr & mask) >> shift); -} - /* Func : table_desc_valid * Desc : Check if a table entry contains valid desc */ @@ -99,21 +89,29 @@ static uint64_t table_desc_valid(uint64_t desc) return((desc & TABLE_DESC) == TABLE_DESC); } -/* Func : get_new_table - * Desc : Return the next free XLAT table from ttb buffer +/* Func : setup_new_table + * Desc : Get next free table from TTB and set it up to match old parent entry. */ -static uint64_t *get_new_table(void) +static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size) { - uint64_t *new; + uint64_t *new, *entry; - if (free_idx >= max_tables) { - return NULL; - } + assert(free_idx < max_tables); new = (uint64_t*)((unsigned char *)xlat_addr + free_idx * GRANULE_SIZE); free_idx++; - memset(new, 0, GRANULE_SIZE); + if (!desc) { + memset(new, 0, GRANULE_SIZE); + } else { + /* Can reuse old parent entry, but may need to adjust type. */ + if (xlat_size == L3_XLAT_SIZE) + desc |= PAGE_DESC; + + for (entry = new; (u8 *)entry < (u8 *)new + GRANULE_SIZE; + entry++, desc += xlat_size) + *entry = desc; + } return new; } @@ -128,17 +126,15 @@ static uint64_t *get_table_from_desc(uint64_t desc) } /* Func: get_next_level_table - * Desc: Check if the table entry is a valid descriptor. If not, allocate new + * Desc: Check if the table entry is a valid descriptor. If not, initialize new * table, update the entry and return the table addr. If valid, return the addr */ -static uint64_t *get_next_level_table(uint64_t *ptr) +static uint64_t *get_next_level_table(uint64_t *ptr, size_t xlat_size) { uint64_t desc = *ptr; if (!table_desc_valid(desc)) { - uint64_t *new_table = get_new_table(); - if (new_table == NULL) - return NULL; + uint64_t *new_table = setup_new_table(desc, xlat_size); desc = ((uint64_t)new_table) | TABLE_DESC; *ptr = desc; } @@ -150,22 +146,22 @@ static uint64_t *get_next_level_table(uint64_t *ptr) * different level XLAT tables which map the given base addr. Similar to table * walk, except that all invalid entries during the walk are updated * accordingly. On success, it returns the size of the block/page addressed by - * the final table + * the final table. */ static uint64_t init_xlat_table(uint64_t base_addr, uint64_t size, uint64_t tag) { - uint64_t l1_index = get_index_from_addr(base_addr,1); - uint64_t l2_index = get_index_from_addr(base_addr,2); - uint64_t l3_index = get_index_from_addr(base_addr,3); + uint64_t l1_index = (base_addr & L1_ADDR_MASK) >> L1_ADDR_SHIFT; + uint64_t l2_index = (base_addr & L2_ADDR_MASK) >> L2_ADDR_SHIFT; + uint64_t l3_index = (base_addr & L3_ADDR_MASK) >> L3_ADDR_SHIFT; uint64_t *table = xlat_addr; uint64_t desc; uint64_t attr = get_block_attr(tag); - /* L1 table lookup */ - /* If VA has bits more than L2 can resolve, lookup starts at L1 - Assumption: we don't need L0 table in coreboot */ + /* L1 table lookup + * If VA has bits more than L2 can resolve, lookup starts at L1 + * Assumption: we don't need L0 table in coreboot */ if (BITS_PER_VA > L1_ADDR_SHIFT) { if ((size >= L1_XLAT_SIZE) && IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) { @@ -176,16 +172,13 @@ static uint64_t init_xlat_table(uint64_t base_addr, table[l1_index] = desc; /* L2 lookup is not required */ return L1_XLAT_SIZE; - } else { - table = get_next_level_table(&table[l1_index]); - if (!table) - return 0; } + table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE); } - /* L2 table lookup */ - /* If lookup was performed at L1, L2 table addr is obtained from L1 desc - else, lookup starts at ttbr address */ + /* L2 table lookup + * If lookup was performed at L1, L2 table addr is obtained from L1 desc + * else, lookup starts at ttbr address */ if ((size >= L2_XLAT_SIZE) && IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) { /* If block address is aligned and size is greater than @@ -195,13 +188,11 @@ static uint64_t init_xlat_table(uint64_t base_addr, table[l2_index] = desc; /* L3 lookup is not required */ return L2_XLAT_SIZE; - } else { - /* L2 entry stores a table descriptor */ - table = get_next_level_table(&table[l2_index]); - if (!table) - return 0; } + /* L2 entry stores a table descriptor */ + table = get_next_level_table(&table[l2_index], L3_XLAT_SIZE); + /* L3 table lookup */ desc = base_addr | PAGE_DESC | attr; table[l3_index] = desc; @@ -209,50 +200,40 @@ static uint64_t init_xlat_table(uint64_t base_addr, } /* Func : sanity_check - * Desc : Check if the address is aligned and size is atleast the granule size + * Desc : Check address/size alignment of a table or page. */ -static uint64_t sanity_check(uint64_t addr, - uint64_t size) +static void sanity_check(uint64_t addr, uint64_t size) { - /* Address should be atleast 64 KiB aligned */ - if (addr & GRANULE_SIZE_MASK) - return 1; - - /* Size should be atleast granule size */ - if (size < GRANULE_SIZE) - return 1; - - return 0; + assert(!(addr & GRANULE_SIZE_MASK) && + !(size & GRANULE_SIZE_MASK) && + size >= GRANULE_SIZE); } -/* Func : init_mmap_entry - * Desc : For each mmap entry, this function calls init_xlat_table with the base +/* Func : mmu_config_range + * Desc : This function repeatedly calls init_xlat_table with the base * address. Based on size returned from init_xlat_table, base_addr is updated * and subsequent calls are made for initializing the xlat table until the whole * region is initialized. */ -static void init_mmap_entry(struct range_entry *r) +void mmu_config_range(void *start, size_t size, uint64_t tag) { - uint64_t base_addr = range_entry_base(r); - uint64_t size = range_entry_size(r); - uint64_t tag = range_entry_tag(r); + uint64_t base_addr = (uintptr_t)start; uint64_t temp_size = size; - while (temp_size) { - uint64_t ret; - - if (sanity_check(base_addr,temp_size)) { - return; - } + printk(BIOS_INFO, "Mapping address range [%p:%p) as ", + start, start + size); + print_tag(BIOS_INFO, tag); + sanity_check(base_addr, temp_size); - ret = init_xlat_table(base_addr + (size - temp_size), - temp_size,tag); + while (temp_size) + temp_size -= init_xlat_table(base_addr + (size - temp_size), + temp_size, tag); - if (ret == 0) - return; - - temp_size -= ret; - } + /* ARMv8 MMUs snoop L1 data cache, no need to flush it. */ + dsb(); + tlbiall_current(); + dsb(); + isb(); } /* Func : mmu_init @@ -266,18 +247,19 @@ void mmu_init(struct memranges *mmap_ranges, { struct range_entry *mmap_entry; - if (sanity_check((uint64_t)ttb_buffer, ttb_size)) { - return; - } + sanity_check((uint64_t)ttb_buffer, ttb_size); memset((void*)ttb_buffer, 0, GRANULE_SIZE); max_tables = (ttb_size >> GRANULE_SIZE_SHIFT); xlat_addr = ttb_buffer; free_idx = 1; - memranges_each_entry(mmap_entry, mmap_ranges) { - init_mmap_entry(mmap_entry); - } + if (mmap_ranges) + memranges_each_entry(mmap_entry, mmap_ranges) { + mmu_config_range((void *)range_entry_base(mmap_entry), + range_entry_size(mmap_entry), + range_entry_tag(mmap_entry)); + } } void mmu_enable(void) @@ -298,8 +280,7 @@ void mmu_enable(void) /* Initialize TTBR */ raw_write_ttbr0_el3((uintptr_t)xlat_addr); - /* Ensure all translation table writes are committed before enabling MMU */ - dsb(); + /* Ensure system register writes are committed before enabling MMU */ isb(); /* Enable MMU */ diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index c487c1f..f5111ae 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -148,5 +148,7 @@ void mmu_init(struct memranges *ranges, uint64_t *ttb, uint64_t ttb_size); /* Enable the mmu based on previous mmu_init(). */ void mmu_enable(void); +/* Change a memory type for a range of bytes at runtime. */ +void mmu_config_range(void *start, size_t size, uint64_t tag); #endif // __ARCH_ARM64_MMU_H__

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New patch to review for coreboot: ea91cde tpm: Fix multiple device support
by Patrick Georgi 26 May '15

26 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10303 -gerrit commit ea91cdec81b50f657ff660619593957c67db5828 Author: Subrata <subrata.banik(a)intel.com> Date: Thu May 14 14:38:07 2015 +0530 tpm: Fix multiple device support Current TPM driver does not support multiple devices for a given vendor. As the device object never takes the 2nd ID in the list. This patch fixes the same. BRANCH=None BUG=None TEST=Built for sklrvp and tested on RVP3. Change-Id: I82c3267c6c74b22650fc53dc6abdc2eb3daa138e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ff42613f11b4f1a79e907601f1ecb7b83a3aeaab Original-Change-Id: Ieb44735c37208bfe90a8e22e0348dd41c8c642d2 Original-Signed-off-by: Subrata <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271727 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Original-Commit-Queue: Pravin K Angolkar <pravin.k.angolkar(a)intel.com> Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar(a)intel.com> --- src/drivers/pc80/tpm/tpm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c index 1013c05..0ee3a90 100644 --- a/src/drivers/pc80/tpm/tpm.c +++ b/src/drivers/pc80/tpm/tpm.c @@ -404,6 +404,7 @@ static u32 tis_probe(void) break; } j++; + dev = &vendor_names[i].dev_names[j]; } break; }

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coreboot-gerrit May 2015