New patch to review for coreboot: 0e41148 AGESA: Move S3 related SPI writes again
by Kyösti Mälkki 25 May '15
by Kyösti Mälkki 25 May '15
25 May '15
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10295
-gerrit
commit 0e411483ebd93cf868eac2c4c9bc1ea6e94d84dc
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun May 24 09:06:03 2015 +0300
AGESA: Move S3 related SPI writes again
This is more agesawrapper-related code than CPU.
Change-Id: I3058ef965a83aed1972e02f0f566f81d5dbd7adf
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/agesa/Makefile.inc | 1 -
src/cpu/amd/agesa/s3_resume.c | 35 +-------------
src/cpu/amd/agesa/s3_resume.h | 3 +-
src/cpu/amd/agesa/spi.c | 49 --------------------
src/northbridge/amd/agesa/Makefile.inc | 3 ++
src/northbridge/amd/agesa/oem_s3.c | 83 ++++++++++++++++++++++++++++++++++
6 files changed, 89 insertions(+), 85 deletions(-)
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index df93f3d..de4aafa 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -26,7 +26,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += s3_resume.c
ramstage-y += s3_resume.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 15a9ee4..2ba6846 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -34,40 +34,6 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "s3_resume.h"
-/* The size needs to be 4k aligned, which is the sector size of most flashes. */
-#define S3_DATA_VOLATILE_SIZE 0x6000
-#define S3_DATA_MTRR_SIZE 0x1000
-#define S3_DATA_NONVOLATILE_SIZE 0x1000
-
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
- (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
-#error "Please increase the value of S3_DATA_SIZE"
-#endif
-
-static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
-{
- /* FIXME: Find file from CBFS. */
- u32 s3_data = CONFIG_S3_DATA_POS;
-
- switch (S3DataType) {
- case S3DataTypeVolatile:
- *pos = s3_data;
- *len = S3_DATA_VOLATILE_SIZE;
- break;
- case S3DataTypeMTRR:
- *pos = s3_data + S3_DATA_VOLATILE_SIZE;
- *len = S3_DATA_MTRR_SIZE;
- break;
- case S3DataTypeNonVolatile:
- *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE;
- *len = S3_DATA_NONVOLATILE_SIZE;
- break;
- default:
- *pos = 0;
- *len = 0;
- break;
- }
-}
void restore_mtrr(void)
{
@@ -173,6 +139,7 @@ static void move_stack_high_mem(void)
#ifndef __PRE_RAM__
/* FIXME: Why store MTRR in SPI, just use CBMEM ? */
+#define S3_DATA_MTRR_SIZE 0x1000
static u8 mtrr_store[S3_DATA_MTRR_SIZE];
static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index d7b3b89..79f6f1b 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -33,6 +33,7 @@ u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
void OemAgesaSaveMtrr (void);
-void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
+void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len);
+int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
#endif
diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c
deleted file mode 100644
index 05a29d7..0000000
--- a/src/cpu/amd/agesa/spi.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <console/console.h>
-#include <spi-generic.h>
-#include <spi_flash.h>
-
-#include "s3_resume.h"
-
-void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
-{
- struct spi_flash *flash;
-
- spi_init();
- flash = spi_flash_probe(0, 0);
- if (!flash) {
- printk(BIOS_DEBUG, "Could not find SPI device\n");
- /* Dont make flow stop. */
- return;
- }
-
- flash->spi->rw = SPI_WRITE_FLAG;
- spi_claim_bus(flash->spi);
-
- flash->erase(flash, pos, size);
- flash->write(flash, pos, sizeof(len), &len);
- flash->write(flash, pos + sizeof(len), len, buf);
-
- flash->spi->rw = SPI_WRITE_FLAG;
- spi_release_bus(flash->spi);
-
- return;
-}
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index 05c3c1a..284b6e2 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -30,4 +30,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += def_callouts.c agesawrapper.c eventlog.c
ramstage-y += def_callouts.c agesawrapper.c eventlog.c
+romstage-y += oem_s3.c
+ramstage-y += oem_s3.c
+
endif
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
new file mode 100644
index 0000000..c196be2
--- /dev/null
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <spi-generic.h>
+#include <spi_flash.h>
+#include <string.h>
+#include <cpu/amd/agesa/s3_resume.h>
+
+/* The size needs to be 4k aligned, which is the sector size of most flashes. */
+#define S3_DATA_VOLATILE_SIZE 0x6000
+#define S3_DATA_MTRR_SIZE 0x1000
+#define S3_DATA_NONVOLATILE_SIZE 0x1000
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
+ (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
+#error "Please increase the value of S3_DATA_SIZE"
+#endif
+
+void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
+{
+ /* FIXME: Find file from CBFS. */
+ u32 s3_data = CONFIG_S3_DATA_POS;
+
+ switch (S3DataType) {
+ case S3DataTypeVolatile:
+ *pos = s3_data;
+ *len = S3_DATA_VOLATILE_SIZE;
+ break;
+ case S3DataTypeMTRR:
+ *pos = s3_data + S3_DATA_VOLATILE_SIZE;
+ *len = S3_DATA_MTRR_SIZE;
+ break;
+ case S3DataTypeNonVolatile:
+ *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE;
+ *len = S3_DATA_NONVOLATILE_SIZE;
+ break;
+ default:
+ *pos = 0;
+ *len = 0;
+ break;
+ }
+}
+
+int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
+{
+#if IS_ENABLED(CONFIG_SPI_FLASH)
+ struct spi_flash *flash;
+
+ spi_init();
+ flash = spi_flash_probe(0, 0);
+ if (!flash)
+ return -1;
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ spi_claim_bus(flash->spi);
+
+ flash->erase(flash, pos, size);
+ flash->write(flash, pos, sizeof(len), &len);
+ flash->write(flash, pos + sizeof(len), len, buf);
+
+ flash->spi->rw = SPI_WRITE_FLAG;
+ spi_release_bus(flash->spi);
+ return 0;
+#else
+ return -1;
+#endif
+}
1
0
25 May '15
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8607
-gerrit
commit dbe7f2369d659b4fffa5205f621b9f47ac8471c3
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Jan 1 17:51:51 2015 +0200
AGESA: Split S3 support file
Separate it to low-memory backup in romstage and MTRR recovery
in ramstage. How much of the MTRR part we really need will be
resolved later.
Change-Id: Ic64b3f74cf6ef0954eda6e84754745de81c465b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/agesa/Makefile.inc | 2 +-
src/cpu/amd/agesa/s3_mtrr.c | 138 +++++++++++++++++++++++++++++++++++++++++
src/cpu/amd/agesa/s3_resume.c | 128 --------------------------------------
3 files changed, 139 insertions(+), 129 deletions(-)
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index de4aafa..153b2db 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -25,7 +25,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += family15rl
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += s3_resume.c
-ramstage-y += s3_resume.c
+ramstage-y += s3_mtrr.c
cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
diff --git a/src/cpu/amd/agesa/s3_mtrr.c b/src/cpu/amd/agesa/s3_mtrr.c
new file mode 100644
index 0000000..af23125
--- /dev/null
+++ b/src/cpu/amd/agesa/s3_mtrr.c
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <string.h>
+#include "s3_resume.h"
+
+static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
+{
+ msr_t msr_data;
+ msr_data = rdmsr(idx);
+
+ memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data));
+ *p_nvram_pos += sizeof(msr_data);
+}
+
+void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
+{
+ u8 *nvram_pos = mtrr_store;
+ msr_t msr_data;
+ u32 i;
+
+ /* Enable access to AMD RdDram and WrDram extension bits */
+ msr_data = rdmsr(SYSCFG_MSR);
+ msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+ wrmsr(SYSCFG_MSR, msr_data);
+
+ /* Fixed MTRRs */
+ write_mtrr(&nvram_pos, 0x250);
+ write_mtrr(&nvram_pos, 0x258);
+ write_mtrr(&nvram_pos, 0x259);
+
+ for (i = 0x268; i < 0x270; i++)
+ write_mtrr(&nvram_pos, i);
+
+ /* Disable access to AMD RdDram and WrDram extension bits */
+ msr_data = rdmsr(SYSCFG_MSR);
+ msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+ wrmsr(SYSCFG_MSR, msr_data);
+
+ /* Variable MTRRs */
+ for (i = 0x200; i < 0x210; i++)
+ write_mtrr(&nvram_pos, i);
+
+ /* SYSCFG_MSR */
+ write_mtrr(&nvram_pos, SYSCFG_MSR);
+ /* TOM */
+ write_mtrr(&nvram_pos, 0xC001001A);
+ /* TOM2 */
+ write_mtrr(&nvram_pos, 0xC001001D);
+
+ *mtrr_store_size = nvram_pos - (u8*) mtrr_store;
+}
+
+void restore_mtrr(void)
+{
+ volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage();
+ u32 msr;
+ msr_t msr_data;
+
+ if (!msrPtr)
+ return;
+
+ disable_cache();
+
+ /* Enable access to AMD RdDram and WrDram extension bits */
+ msr_data = rdmsr(SYSCFG_MSR);
+ msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+ wrmsr(SYSCFG_MSR, msr_data);
+
+ /* Now restore the Fixed MTRRs */
+ msr_data.lo = *msrPtr;
+ msrPtr ++;
+ msr_data.hi = *msrPtr;
+ msrPtr ++;
+ wrmsr(0x250, msr_data);
+
+ msr_data.lo = *msrPtr;
+ msrPtr ++;
+ msr_data.hi = *msrPtr;
+ msrPtr ++;
+ wrmsr(0x258, msr_data);
+
+ msr_data.lo = *msrPtr;
+ msrPtr ++;
+ msr_data.hi = *msrPtr;
+ msrPtr ++;
+ wrmsr(0x259, msr_data);
+
+ for (msr = 0x268; msr <= 0x26F; msr++) {
+ msr_data.lo = *msrPtr;
+ msrPtr ++;
+ msr_data.hi = *msrPtr;
+ msrPtr ++;
+ wrmsr(msr, msr_data);
+ }
+
+ /* Disable access to AMD RdDram and WrDram extension bits */
+ msr_data = rdmsr(SYSCFG_MSR);
+ msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+ wrmsr(SYSCFG_MSR, msr_data);
+
+ /* Restore the Variable MTRRs */
+ for (msr = 0x200; msr <= 0x20F; msr++) {
+ msr_data.lo = *msrPtr;
+ msrPtr ++;
+ msr_data.hi = *msrPtr;
+ msrPtr ++;
+ wrmsr(msr, msr_data);
+ }
+
+ /* Restore SYSCFG MTRR */
+ msr_data.lo = *msrPtr;
+ msrPtr ++;
+ msr_data.hi = *msrPtr;
+ msrPtr ++;
+ wrmsr(SYSCFG_MSR, msr_data);
+}
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 9789cc4..7de2d66 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -17,8 +17,6 @@
* Foundation, Inc.
*/
-#include <AGESA.h>
-#include <Lib/amdlib.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
@@ -26,84 +24,10 @@
#include <cpu/amd/mtrr.h>
#include <cpu/x86/cache.h>
#include <cbmem.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <arch/acpi.h>
#include <string.h>
-#include "Porting.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "s3_resume.h"
-#ifndef __PRE_RAM__
-
-void restore_mtrr(void)
-{
- volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage();
- u32 msr;
- msr_t msr_data;
-
- if (!msrPtr)
- return;
-
- disable_cache();
-
- /* Enable access to AMD RdDram and WrDram extension bits */
- msr_data = rdmsr(SYS_CFG);
- msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
- wrmsr(SYS_CFG, msr_data);
-
- /* Now restore the Fixed MTRRs */
- msr_data.lo = *msrPtr;
- msrPtr ++;
- msr_data.hi = *msrPtr;
- msrPtr ++;
- wrmsr(0x250, msr_data);
-
- msr_data.lo = *msrPtr;
- msrPtr ++;
- msr_data.hi = *msrPtr;
- msrPtr ++;
- wrmsr(0x258, msr_data);
-
- msr_data.lo = *msrPtr;
- msrPtr ++;
- msr_data.hi = *msrPtr;
- msrPtr ++;
- wrmsr(0x259, msr_data);
-
- for (msr = 0x268; msr <= 0x26F; msr++) {
- msr_data.lo = *msrPtr;
- msrPtr ++;
- msr_data.hi = *msrPtr;
- msrPtr ++;
- wrmsr(msr, msr_data);
- }
-
- /* Disable access to AMD RdDram and WrDram extension bits */
- msr_data = rdmsr(SYS_CFG);
- msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
- wrmsr(SYS_CFG, msr_data);
-
- /* Restore the Variable MTRRs */
- for (msr = 0x200; msr <= 0x20F; msr++) {
- msr_data.lo = *msrPtr;
- msrPtr ++;
- msr_data.hi = *msrPtr;
- msrPtr ++;
- wrmsr(msr, msr_data);
- }
-
- /* Restore SYSCFG MTRR */
- msr_data.lo = *msrPtr;
- msrPtr ++;
- msr_data.hi = *msrPtr;
- msrPtr ++;
- wrmsr(SYS_CFG, msr_data);
-}
-
-#endif
-
-#ifdef __PRE_RAM__
static void *backup_resume(void)
{
void *resume_backup_memory;
@@ -135,58 +59,7 @@ static void move_stack_high_mem(void)
(high_stack - BSP_STACK_BASE_ADDR)
:);
}
-#endif
-
-#ifndef __PRE_RAM__
-static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
-{
- msr_t msr_data;
- msr_data = rdmsr(idx);
-
- memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data));
- *p_nvram_pos += sizeof(msr_data);
-}
-
-void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
-{
- u8 *nvram_pos = mtrr_store;
- msr_t msr_data;
- u32 i;
-
- /* Enable access to AMD RdDram and WrDram extension bits */
- msr_data = rdmsr(SYS_CFG);
- msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
- wrmsr(SYS_CFG, msr_data);
-
- /* Fixed MTRRs */
- write_mtrr(&nvram_pos, 0x250);
- write_mtrr(&nvram_pos, 0x258);
- write_mtrr(&nvram_pos, 0x259);
-
- for (i = 0x268; i < 0x270; i++)
- write_mtrr(&nvram_pos, i);
-
- /* Disable access to AMD RdDram and WrDram extension bits */
- msr_data = rdmsr(SYS_CFG);
- msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
- wrmsr(SYS_CFG, msr_data);
-
- /* Variable MTRRs */
- for (i = 0x200; i < 0x210; i++)
- write_mtrr(&nvram_pos, i);
-
- /* SYS_CFG */
- write_mtrr(&nvram_pos, 0xC0010010);
- /* TOM */
- write_mtrr(&nvram_pos, 0xC001001A);
- /* TOM2 */
- write_mtrr(&nvram_pos, 0xC001001D);
-
- *mtrr_store_size = nvram_pos - (u8*) mtrr_store;
-}
-#endif
-#ifdef __PRE_RAM__
static void set_resume_cache(void)
{
msr_t msr;
@@ -236,4 +109,3 @@ void prepare_for_resume(void)
printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
}
-#endif
1
0
25 May '15
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8606
-gerrit
commit a566797077233323d54268575918b6e0cbe203a8
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Dec 16 19:50:47 2014 +0200
AGESA: Refactor OEM S3 storage
Use function prototypes that match more closely with the structure
of other OEM hooks in agesawrappers.
Change-Id: Id241fdce78a21a5138ef60ac2f841b694da92241
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/agesa/s3_resume.c | 57 ++++----------------
src/cpu/amd/agesa/s3_resume.h | 14 +----
src/northbridge/amd/agesa/agesawrapper.c | 37 +++----------
src/northbridge/amd/agesa/agesawrapper.h | 5 ++
src/northbridge/amd/agesa/oem_s3.c | 90 +++++++++++++++++++++++++++++++-
5 files changed, 112 insertions(+), 91 deletions(-)
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 2ba6846..9789cc4 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -34,18 +34,16 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "s3_resume.h"
+#ifndef __PRE_RAM__
void restore_mtrr(void)
{
+ volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage();
u32 msr;
- volatile UINT32 *msrPtr;
msr_t msr_data;
- printk(BIOS_SPEW, "%s\n", __func__);
-
- u32 pos, size;
- get_s3nv_data(S3DataTypeMTRR, &pos, &size);
- msrPtr = (UINT32 *)(pos + sizeof(UINT32));
+ if (!msrPtr)
+ return;
disable_cache();
@@ -103,6 +101,8 @@ void restore_mtrr(void)
wrmsr(SYS_CFG, msr_data);
}
+#endif
+
#ifdef __PRE_RAM__
static void *backup_resume(void)
{
@@ -138,10 +138,6 @@ static void move_stack_high_mem(void)
#endif
#ifndef __PRE_RAM__
-/* FIXME: Why store MTRR in SPI, just use CBMEM ? */
-#define S3_DATA_MTRR_SIZE 0x1000
-static u8 mtrr_store[S3_DATA_MTRR_SIZE];
-
static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
{
msr_t msr_data;
@@ -151,13 +147,12 @@ static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
*p_nvram_pos += sizeof(msr_data);
}
-void OemAgesaSaveMtrr(void)
+void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
{
+ u8 *nvram_pos = mtrr_store;
msr_t msr_data;
u32 i;
- u8 *nvram_pos = (u8 *) mtrr_store;
-
/* Enable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYS_CFG);
msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
@@ -187,44 +182,10 @@ void OemAgesaSaveMtrr(void)
/* TOM2 */
write_mtrr(&nvram_pos, 0xC001001D);
-#if IS_ENABLED(CONFIG_SPI_FLASH)
- u32 pos, size;
- get_s3nv_data(S3DataTypeMTRR, &pos, &size);
- spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store);
-#endif
-}
-
-u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
-{
-#if IS_ENABLED(CONFIG_SPI_FLASH)
- u32 pos, size;
- get_s3nv_data(S3DataType, &pos, &size);
- spi_SaveS3info(pos, size, Data, DataSize);
-#endif
- return AGESA_SUCCESS;
+ *mtrr_store_size = nvram_pos - (u8*) mtrr_store;
}
#endif
-void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data)
-{
- AMD_CONFIG_PARAMS StdHeader;
-
- u32 pos, size;
- get_s3nv_data(S3DataType, &pos, &size);
-
- if (S3DataType == S3DataTypeNonVolatile) {
- *DataSize = *(UINT32 *) pos;
- *Data = (void *) (pos + sizeof(UINT32));
- } else if (S3DataType == S3DataTypeVolatile) {
- u32 len = *(UINT32 *) pos;
- void *src = (void *) (pos + sizeof(UINT32));
- void *dst = (void *) GetHeapBase(&StdHeader);
- memcpy(dst, src, len);
- *DataSize = len;
- *Data = dst;
- }
-}
-
#ifdef __PRE_RAM__
static void set_resume_cache(void)
{
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index 79f6f1b..ce16f7d 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -20,20 +20,10 @@
#ifndef S3_RESUME_H
#define S3_RESUME_H
-typedef enum {
- S3DataTypeNonVolatile=0, ///< NonVolatile Data Type
- S3DataTypeVolatile, ///< Volatile Data Type
- S3DataTypeMTRR ///< MTRR storage
-} S3_DATA_TYPE;
-
void restore_mtrr(void);
void prepare_for_resume(void);
-u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
-void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
-void OemAgesaSaveMtrr (void);
-
-void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len);
-int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
+void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
+const void *OemS3Saved_MTRR_Storage(void);
#endif
diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c
index 82088ac..8ad36c7 100644
--- a/src/northbridge/amd/agesa/agesawrapper.c
+++ b/src/northbridge/amd/agesa/agesawrapper.c
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <string.h>
-#include <cpu/amd/agesa/s3_resume.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "amdlib.h"
@@ -125,7 +124,6 @@ AGESA_STATUS agesawrapper_amdinitresume(void)
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
- S3_DATA_TYPE S3DataType;
memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
@@ -141,13 +139,9 @@ AGESA_STATUS agesawrapper_amdinitresume(void)
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
- S3DataType = S3DataTypeNonVolatile;
+ OemInitResume(AmdResumeParamsPtr);
- OemAgesaGetS3Info(S3DataType,
- (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
- (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage);
-
- status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr);
+ status = AmdInitResume(AmdResumeParamsPtr);
AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
AmdReleaseStruct(&AmdParamStruct);
@@ -185,7 +179,6 @@ AGESA_STATUS agesawrapper_amds3laterestore(void)
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
- S3_DATA_TYPE S3DataType;
memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
@@ -199,12 +192,12 @@ AGESA_STATUS agesawrapper_amds3laterestore(void)
AmdCreateStruct(&AmdInterfaceParams);
+#if 0
+ /* TODO: What to do with NvStorage here? */
+ AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0;
+#endif
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
- S3DataType = S3DataTypeVolatile;
-
- OemAgesaGetS3Info(S3DataType,
- (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
- (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
+ OemS3LateRestore(AmdS3LateParamsPtr);
status = AmdS3LateRestore(AmdS3LateParamsPtr);
AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
@@ -249,7 +242,6 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
AGESA_STATUS status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
- S3_DATA_TYPE S3DataType;
memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
@@ -269,21 +261,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
ASSERT(status == AGESA_SUCCESS);
- S3DataType = S3DataTypeNonVolatile;
-
- status = OemAgesaSaveS3Info(S3DataType,
- AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
- AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
-
- if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
- S3DataType = S3DataTypeVolatile;
-
- status = OemAgesaSaveS3Info(S3DataType,
- AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
- AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
- }
+ OemS3Save(AmdS3SaveParamsPtr);
- OemAgesaSaveMtrr();
AmdReleaseStruct(&AmdInterfaceParams);
return status;
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h
index 9ec6b75..eb1a59c 100644
--- a/src/northbridge/amd/agesa/agesawrapper.h
+++ b/src/northbridge/amd/agesa/agesawrapper.h
@@ -71,4 +71,9 @@ struct OEM_HOOK
extern const struct OEM_HOOK OemCustomize;
+/* For suspend-to-ram support. */
+AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams);
+AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams);
+AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams);
+
#endif /* _AGESAWRAPPER_H_ */
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index c196be2..08f68e5 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -21,6 +21,15 @@
#include <spi_flash.h>
#include <string.h>
#include <cpu/amd/agesa/s3_resume.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <AGESA.h>
+
+typedef enum {
+ S3DataTypeNonVolatile=0, ///< NonVolatile Data Type
+ S3DataTypeVolatile, ///< Volatile Data Type
+ S3DataTypeMTRR ///< MTRR storage
+} S3_DATA_TYPE;
/* The size needs to be 4k aligned, which is the sector size of most flashes. */
#define S3_DATA_VOLATILE_SIZE 0x6000
@@ -32,7 +41,7 @@
#error "Please increase the value of S3_DATA_SIZE"
#endif
-void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
+static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
{
/* FIXME: Find file from CBFS. */
u32 s3_data = CONFIG_S3_DATA_POS;
@@ -57,7 +66,42 @@ void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
}
}
-int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
+#if defined(__PRE_RAM__)
+
+AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams)
+{
+ AMD_S3_PARAMS *dataBlock = &ResumeParams->S3DataBlock;
+ u32 pos, size;
+
+ get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
+
+ /* TODO: Our NvStorage is really const. */
+ dataBlock->NvStorageSize = *(UINT32 *) pos;
+ dataBlock->NvStorage = (void *) (pos + sizeof(UINT32));
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams)
+{
+ AMD_S3_PARAMS *dataBlock = &S3LateParams->S3DataBlock;
+ AMD_CONFIG_PARAMS StdHeader;
+ u32 pos, size;
+
+ get_s3nv_data(S3DataTypeVolatile, &pos, &size);
+
+ u32 len = *(UINT32 *) pos;
+ void *src = (void *) (pos + sizeof(UINT32));
+ void *dst = (void *) GetHeapBase(&StdHeader);
+
+ memcpy(dst, src, len);
+ dataBlock->VolatileStorageSize = len;
+ dataBlock->VolatileStorage = dst;
+ return AGESA_SUCCESS;
+}
+
+#else
+
+static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
{
#if IS_ENABLED(CONFIG_SPI_FLASH)
struct spi_flash *flash;
@@ -81,3 +125,45 @@ int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
return -1;
#endif
}
+
+AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams)
+{
+ AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock;
+ u8 MTRRStorage[S3_DATA_MTRR_SIZE];
+ u32 MTRRStorageSize = 0;
+ u32 pos, size;
+
+ /* To be consumed in AmdInitResume. */
+ get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
+ if (size && dataBlock->NvStorageSize)
+ spi_SaveS3info(pos, size, dataBlock->NvStorage,
+ dataBlock->NvStorageSize);
+
+ /* To be consumed in AmdS3LateRestore. */
+ get_s3nv_data(S3DataTypeVolatile, &pos, &size);
+ if (size && dataBlock->VolatileStorageSize)
+ spi_SaveS3info(pos, size, dataBlock->VolatileStorage,
+ dataBlock->VolatileStorageSize);
+
+ /* Collect MTRR setup. */
+ backup_mtrr(MTRRStorage, &MTRRStorageSize);
+
+ /* To be consumed in restore_mtrr, CPU enumeration in ramstage. */
+ get_s3nv_data(S3DataTypeMTRR, &pos, &size);
+ if (size && MTRRStorageSize)
+ spi_SaveS3info(pos, size, MTRRStorage, MTRRStorageSize);
+
+ return AGESA_SUCCESS;
+}
+
+const void *OemS3Saved_MTRR_Storage(void)
+{
+ u32 pos, size;
+ get_s3nv_data(S3DataTypeMTRR, &pos, &size);
+ if (!size)
+ return NULL;
+
+ return (void*)(pos + sizeof(UINT32));
+}
+
+#endif
1
0
Patch merged into coreboot/master: 8307050 gitignore: Have multiple crossgcc versions
by gerrit＠coreboot.org 25 May '15
by gerrit＠coreboot.org 25 May '15
25 May '15
the following patch was just integrated into master:
commit 83070504125a8023a24cb87c3f3184d3ad9b1d20
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Mon May 25 19:18:37 2015 +0300
gitignore: Have multiple crossgcc versions
Make it so that git does not remove old copies or the symlink.
Change-Id: I27be60c897d2f86cdf274480c83cbbfe38fcdf94
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/10292
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/10292 for details.
-gerrit
1
0
New patch to review for coreboot: e58f68f build system: only query the compiler runtime's location once
by Patrick Georgi 25 May '15
by Patrick Georgi 25 May '15
25 May '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10294
-gerrit
commit e58f68f6c7d20f2c84769c884724f4764f60157a
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Mon May 25 20:12:59 2015 +0200
build system: only query the compiler runtime's location once
No need to execute the compiler to figure this out once for each
source file (or so).
Change-Id: I56bf084f1217b96748296931617e9233f21183d5
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
toolchain.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/toolchain.inc b/toolchain.inc
index de50471..e089f2e 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -106,9 +106,9 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2))
CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2))
COMPILER_RT_FLAGS_$(1) :=
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-COMPILER_RT_$(1) = $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-librt-file-name 2>/dev/null)
+COMPILER_RT_$(1) := $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-librt-file-name 2>/dev/null)
else
-COMPILER_RT_$(1) = $(wildcard $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-libgcc-file-name))
+COMPILER_RT_$(1) := $(wildcard $(shell $(CC_$(2)) $(CFLAGS_$(2)) -print-libgcc-file-name))
ifeq ($(2),x86_32)
COMPILER_RT_FLAGS_$(1) := --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3
endif
1
0
Patch set updated for coreboot: 1cf7e21 AGESA f16kb: Fix PCI device notation
by Fabian Kunkel 25 May '15
by Fabian Kunkel 25 May '15
25 May '15
Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10289
-gerrit
commit 1cf7e214c95386f51cf606004691c30561b8a050
Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com>
Date: Mon May 25 17:16:02 2015 +0200
AGESA f16kb: Fix PCI device notation
Old file defines wrong PCI devices (1.2 2.2 3.2 4.2 5.2).
Wrong defines cause PCI devices not to be found in the pirq_data table.
Example error output:
PCI IRQ: Found device 0:02.01 using PIN A
PCI Devfn (0x11) not found in pirq_data table
PCI IRQ: Found device 0:02.02 using PIN B
Found this device in pirq_data table entry 3
Orig INT_PIN : 2 (PIN B)
PCI_INTR idx : 0x02 (INTC# )
INT_LINE : 0xA (IRQ 10)
PCI IRQ: Found device 0:02.03 using PIN C
PCI Devfn (0x13) not found in pirq_data table
PCI IRQ: Found device 0:02.04 using PIN D
PCI Devfn (0x14) not found in pirq_data table
PCI IRQ: Found device 0:02.05 using PIN A
PCI Devfn (0x15) not found in pirq_data table
Patch fixes, that pirq_data entries for pci devices 2.1 - 2.5 get found.
Change-Id: I4503433427f4ec90d022b65084c52077ba4f3511
Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com>
---
src/northbridge/amd/agesa/family16kb/pci_devs.h | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/northbridge/amd/agesa/family16kb/pci_devs.h b/src/northbridge/amd/agesa/family16kb/pci_devs.h
index 28e3c68..9642a2a 100644
--- a/src/northbridge/amd/agesa/family16kb/pci_devs.h
+++ b/src/northbridge/amd/agesa/family16kb/pci_devs.h
@@ -32,17 +32,17 @@
#define ACTL_DEVFN PCI_DEVFN(GFX_DEV,ACTL_FUNC)
/* PCIe Ports */
-#define NB_PCIE_PORT1_DEV 0x1
-#define NB_PCIE_PORT2_DEV 0x2
-#define NB_PCIE_PORT3_DEV 0x3
-#define NB_PCIE_PORT4_DEV 0x4
-#define NB_PCIE_PORT5_DEV 0x5
-#define NB_PCIE_FUNC 2
+#define NB_PCIE_PORT1_FUNC 0x1
+#define NB_PCIE_PORT2_FUNC 0x2
+#define NB_PCIE_PORT3_FUNC 0x3
+#define NB_PCIE_PORT4_FUNC 0x4
+#define NB_PCIE_PORT5_FUNC 0x5
+#define NB_PCIE_DEV 2
#define NB_PCIE_PORT_DEVID 0x1439
-#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT1_DEV,NB_PCIE_FUNC)
-#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC)
-#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT3_DEV,NB_PCIE_FUNC)
-#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT4_DEV,NB_PCIE_FUNC)
-#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT5_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_DEV,NB_PCIE_PORT1_FUNC)
+#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_DEV,NB_PCIE_PORT2_FUNC)
+#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_DEV,NB_PCIE_PORT3_FUNC)
+#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_DEV,NB_PCIE_PORT4_FUNC)
+#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_DEV,NB_PCIE_PORT5_FUNC)
#endif /* _AMD_FAM16KB_PCI_DEVS_H_ */
1
0
Patch merged into coreboot/master: 188aec0 inteltool: dump gfx registers.
by gerrit＠coreboot.org 25 May '15
by gerrit＠coreboot.org 25 May '15
25 May '15
the following patch was just integrated into master:
commit 188aec06401e802cddf209b564a5ad06e3945e9e
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed May 20 14:04:41 2015 +0200
inteltool: dump gfx registers.
Useful for autoport and other gfx-related developpement.
Change-Id: I1fc0952bc30ab15cd39a4f0c00649714dcf318f3
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/10276
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
See http://review.coreboot.org/10276 for details.
-gerrit
1
0
Patch set updated for coreboot: debe785 autoport: Experimental stuff
by Vladimir Serbinenko 25 May '15
by Vladimir Serbinenko 25 May '15
25 May '15
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7131
-gerrit
commit debe7854f48b9e8558e163709755432c15d3e24a
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Oct 15 21:51:47 2014 +0200
autoport: Experimental stuff
Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
util/autoport/azalia.go | 62 ++++
util/autoport/bd82x6x.go | 368 +++++++++++++++++++++++
util/autoport/i82801gx.go | 531 +++++++++++++++++++++++++++++++++
util/autoport/i945.go | 120 ++++++++
util/autoport/log_maker.go | 85 ++++++
util/autoport/log_reader.go | 319 ++++++++++++++++++++
util/autoport/main.go | 682 +++++++++++++++++++++++++++++++++++++++++++
util/autoport/rce823.go | 39 +++
util/autoport/root.go | 29 ++
util/autoport/sandybridge.go | 142 +++++++++
10 files changed, 2377 insertions(+)
diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
new file mode 100644
index 0000000..f9be1b1
--- /dev/null
+++ b/util/autoport/azalia.go
@@ -0,0 +1,62 @@
+package main
+
+import (
+ "fmt"
+ "sort"
+)
+
+type azalia struct {
+}
+
+func (i azalia) Scan(ctx Context, addr PCIDevData) {
+ az := Create(ctx, "hda_verb.c")
+ defer az.Close()
+
+ az.WriteString(
+ `#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+`)
+
+ for _, codec := range ctx.InfoSource.GetAzaliaCodecs() {
+ fmt.Fprintf(az, "\t0x%08x, /* Codec Vendor / Device ID: %s */\n",
+ codec.VendorID, codec.Name)
+ fmt.Fprintf(az, "\t0x%08x, /* Subsystem ID */\n",
+ codec.SubsystemID)
+ fmt.Fprintf(az, "\n\t0x%08x, /* Number of 4 dword sets */\n",
+ len(codec.PinConfig)+1)
+ fmt.Fprintf(az, "\t/* NID 0x01: Subsystem ID. */\n")
+ fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n",
+ codec.CodecNo, codec.SubsystemID)
+
+ keys := []int{}
+ for nid, _ := range codec.PinConfig {
+ keys = append(keys, nid)
+ }
+
+ sort.Ints(keys)
+
+ for _, nid := range keys {
+ fmt.Fprintf(az, "\n\t/* NID 0x%02x. */\n", nid)
+ fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n",
+ codec.CodecNo, nid, codec.PinConfig[nid])
+ }
+ }
+
+ az.WriteString(
+ `};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+`)
+
+ PutPCIDev(addr, "Audio controller")
+}
+
+func init() {
+ /* I82801GX/I945 */
+ RegisterPCI(0x8086, 0x27d8, azalia{})
+ /* C216/ivybridge */
+ RegisterPCI(0x8086, 0x1e20, azalia{})
+}
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
new file mode 100644
index 0000000..8354ce0
--- /dev/null
+++ b/util/autoport/bd82x6x.go
@@ -0,0 +1,368 @@
+package main
+
+import (
+ "fmt"
+ "os"
+)
+
+type bd82x6x struct {
+ variant string
+}
+
+func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File,
+ val uint32, set uint, partno int) {
+
+ max := uint(32)
+ if set == 3 {
+ max = 12
+ }
+
+ bits := [6][2]string{
+ {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
+ {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
+ {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
+ {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
+ {"GPIO_NO_INVERT", "GPIO_INVERT"},
+ {"GPIO_NO_BLINK", "GPIO_BLINK"},
+ }
+
+ for i := uint(0); i < max; i++ {
+ fmt.Fprintf(sb, " .gpio%d = %s,\n",
+ (set-1)*32+i,
+ bits[partno][(val>>i)&1])
+ }
+}
+
+func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) {
+ gpio := Create(ctx, "gpio.c")
+ defer gpio.Close()
+
+ AddROMStageFile("gpio.c", "")
+
+ gpio.WriteString(`#include "southbridge/intel/bd82x6x/gpio.h"
+`)
+
+ adresses := [3][6]int{
+ {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
+ {0x30, 0x34, 0x38, 0x64, -1, -1},
+ {0x40, 0x44, 0x48, 0x68, -1, -1},
+ }
+
+ for set := 1; set <= 3; set++ {
+ for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
+ addr := adresses[set-1][partno]
+ if addr < 0 {
+ continue
+ }
+ fmt.Fprintf(gpio, "const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
+ set, set, part)
+
+ b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno)
+ gpio.WriteString("};\n\n")
+ }
+ }
+
+ gpio.WriteString(`static const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
+`)
+}
+
+func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool {
+ portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
+ if !ok {
+ return false
+ }
+ return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
+}
+
+func ich9GetFlashSize(ctx Context) {
+ inteltool := ctx.InfoSource.GetInteltool()
+ switch (inteltool.RCBA[0x3410] >> 10) & 3 {
+ /* SPI. All boards I've seen with sandy/ivy use SPI. */
+ case 3:
+ ROMProtocol = "SPI"
+ highflkb := uint32(0)
+ for reg := uint16(0); reg < 5; reg++ {
+ fl := (inteltool.RCBA[0x3854 + 4 * reg] >> 16) & 0x1fff
+ flkb := fl << 2
+ if flkb > highflkb {
+ highflkb = flkb
+ }
+ }
+ ROMSizeKB = int(highflkb)
+ /* Shared with ME. Flashrom is unable to handle it. */
+ FlashROMSupport = "n"
+ }
+}
+
+func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
+ inteltool := ctx.InfoSource.GetInteltool()
+ b.GPIO(ctx, inteltool)
+
+ KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true
+ KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+ KconfigComment["SERIRQ_CONTINUOUS_MODE"] = "FIXME: check this"
+ KconfigInt["USBDEBUG_HCD_INDEX"] = 2
+ KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
+ KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
+
+ /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices.
+ But most systems don't have any of those. But the config needs to be set
+ nevertheless. So set it to southbridge subsys/subvendor. */
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e]))
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30]))
+
+ ich9GetFlashSize(ctx)
+
+ FADT := ctx.InfoSource.GetACPI()["FACP"]
+
+ pcieHotplugMap := "{ "
+
+ for port := 0; port < 7; port++ {
+ if b.IsPCIeHotplug(ctx, port) {
+ pcieHotplugMap += "1, "
+ } else {
+ pcieHotplugMap += "0, "
+ }
+ }
+
+ if b.IsPCIeHotplug(ctx, 7) {
+ pcieHotplugMap += "1 }"
+ } else {
+ pcieHotplugMap += "0 }"
+ }
+
+ cur := DevTreeNode{
+ Chip: "southbridge/intel/bd82x6x",
+ Comment: "Intel Series 6 Cougar Point PCH, FIXME: set gpiX_routing and alt_gp_smi_en for EC support",
+
+ Registers: map[string]string{
+ "sata_interface_speed_support": "0x3",
+ "gen1_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
+ "gen2_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
+ "gen3_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
+ "gen4_dec": FormatHexLE32 (PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
+ "pcie_port_coalesce": "1",
+ "pcie_hotplug_map": pcieHotplugMap,
+
+ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
+
+ "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
+ "c2_latency": FormatHexLE16(FADT[96:98]),
+ "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
+ },
+ }
+
+ xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}]
+
+ if ok {
+ cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8])
+ cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0])
+ cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4])
+ }
+
+
+ PutPCIChip(addr, cur)
+ PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/bd82x6x/acpi/platform.asl",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl",
+ Comment: "global NVS and variables",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl",
+ })
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "southbridge/intel/bd82x6x/acpi/pch.asl",
+ })
+
+ sb := Create(ctx, "early_southbridge.c")
+ defer sb.Close()
+ AddROMStageFile("early_southbridge.c", "")
+ sb.WriteString(`#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+void pch_enable_lpc(void)
+{
+`)
+ RestorePCI16Simple(sb, addr, 0x82)
+ RestorePCI32Simple(sb, addr, 0x84)
+ RestorePCI32Simple(sb, addr, 0x88)
+ RestorePCI32Simple(sb, addr, 0x8c)
+ RestorePCI32Simple(sb, addr, 0x90)
+
+ RestorePCI16Simple(sb, addr, 0x80)
+
+ RestorePCI32Simple(sb, addr, 0xac)
+
+ sb.WriteString(`}
+
+void rcba_config(void)
+{
+ /* Disable devices. */
+`)
+ RestoreRCBA32(sb, inteltool, 0x3414)
+ RestoreRCBA32(sb, inteltool, 0x3418)
+
+ sb.WriteString("\n}\n")
+
+ sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n")
+
+ currentMap := map[uint32]int{
+ 0x20000153: 0,
+ 0x20000f57: 1,
+ 0x2000055b: 2,
+ 0x20000f51: 3,
+ 0x2000094a: 4,
+ }
+
+ for port := uint(0); port < 14; port++ {
+ var pinmask uint32
+ OCPin := -1
+ if port < 8 {
+ pinmask = inteltool.RCBA[0x35a0]
+ } else {
+ pinmask = inteltool.RCBA[0x35a4]
+ }
+ for pin := uint(0); pin < 4; pin++ {
+ if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 {
+ OCPin = int(pin)
+ if port >= 8 {
+ OCPin += 4
+ }
+ }
+ }
+ fmt.Fprintf(sb, "\t{ %d, %d, %d },\n",
+ ((inteltool.RCBA[0x359c]>>port)&1)^1,
+ currentMap[inteltool.RCBA[uint16(0x3500+4*port)]],
+ OCPin)
+ }
+ sb.WriteString("};\n")
+
+ sb.WriteString(`
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd)
+{
+ read_spd(&spd[0], 0x50);
+ read_spd(&spd[1], 0x51);
+ read_spd(&spd[2], 0x52);
+ read_spd(&spd[3], 0x53);
+}
+`)
+
+ gnvs := Create(ctx, "gnvs.c")
+ defer gnvs.Close()
+
+ gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
+`)
+
+ AddRAMStageFile("gnvs.c", "")
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x1e49, bd82x6x{variant: "C216"})
+ RegisterPCI(0x8086, 0x1e55, bd82x6x{variant: "C216"})
+ RegisterPCI(0x8086, 0x1e56, bd82x6x{variant: "C216"})
+ RegisterPCI(0x8086, 0x1e57, bd82x6x{variant: "C216"})
+ RegisterPCI(0x8086, 0x1e5c, bd82x6x{variant: "C216"})
+ RegisterPCI(0x8086, 0x1e5d, bd82x6x{variant: "C216"})
+ RegisterPCI(0x8086, 0x1e5e, bd82x6x{variant: "C216"})
+ RegisterPCI(0x8086, 0x1e5f, bd82x6x{variant: "C216"})
+ RegisterPCI(0x8086, 0x1e31, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e26, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e2d, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e3a, GenericPCI{})
+ RegisterPCI(0x8086, 0x1502, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e10, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e12, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e14, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e16, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e18, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e1a, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e1c, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e1e, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e03, GenericPCI{})
+ RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
+}
diff --git a/util/autoport/i82801gx.go b/util/autoport/i82801gx.go
new file mode 100644
index 0000000..4ffeb6a
--- /dev/null
+++ b/util/autoport/i82801gx.go
@@ -0,0 +1,531 @@
+package main
+
+import (
+ "fmt"
+ "os"
+)
+
+type i82801gx struct {
+}
+
+func (i i82801gx) writeGPIO(ctx Context, sb *os.File, inteltool InteltoolData, addr uint16, name string) {
+ fmt.Fprintf(sb, " outl(0x%08x, DEFAULT_GPIOBASE + %s);\n",
+ inteltool.GPIO[addr], name)
+}
+
+func (i i82801gx) Scan(ctx Context, addr PCIDevData) {
+
+ KconfigBool["HAVE_MP_TABLE"] = true
+ KconfigBool["SOUTHBRIDGE_INTEL_I82801GX"] = true
+
+ sb := Create(ctx, "early_southbridge.c")
+ defer sb.Close()
+ AddROMStageFile("early_southbridge.c", "")
+ sb.WriteString(`#include <stdint.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd)
+{
+ read_spd(&spd[0], 0x50);
+ read_spd(&spd[1], 0x51);
+ read_spd(&spd[2], 0x52);
+ read_spd(&spd[3], 0x53);
+}
+
+void setup_ich7_gpios(void)
+{
+ printk(BIOS_DEBUG, " GPIOS...");
+
+`)
+ inteltool := ctx.InfoSource.GetInteltool()
+ i.writeGPIO(ctx, sb, inteltool, 0x0, "GPIO_USE_SEL")
+ i.writeGPIO(ctx, sb, inteltool, 0x4, "GP_IO_SEL")
+ i.writeGPIO(ctx, sb, inteltool, 0xc, "GP_LVL")
+ i.writeGPIO(ctx, sb, inteltool, 0x18, "GPO_BLINK")
+ i.writeGPIO(ctx, sb, inteltool, 0x2c, "GPI_INV")
+ i.writeGPIO(ctx, sb, inteltool, 0x30, "GPIO_USE_SEL2")
+ i.writeGPIO(ctx, sb, inteltool, 0x34, "GP_IO_SEL2")
+ i.writeGPIO(ctx, sb, inteltool, 0x38, "GP_LVL2")
+
+ sb.WriteString(`}
+
+void ich7_enable_lpc(void)
+{
+ // Enable Serial IRQ
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+
+ // Enable address decodes
+`)
+
+ RestorePCI16Simple(sb, addr, 0x80)
+ RestorePCI16Simple(sb, addr, 0x82)
+ RestorePCI16Simple(sb, addr, 0x84)
+ RestorePCI16Simple(sb, addr, 0x86)
+ RestorePCI16Simple(sb, addr, 0x88)
+ RestorePCI16Simple(sb, addr, 0x8a)
+ RestorePCI16Simple(sb, addr, 0x8c)
+ RestorePCI16Simple(sb, addr, 0x8e)
+ RestorePCI16Simple(sb, addr, 0x90)
+ RestorePCI16Simple(sb, addr, 0x92)
+
+ /* Just use the same interrupt map for all boards: just registers have to match ACPI. */
+ sb.WriteString(`}
+
+void rcba_config(void)
+{
+ /* V0CTL Virtual Channel 0 Resource Control */
+ RCBA32(0x0014) = 0x80000001;
+ /* V1CAP Virtual Channel 1 Resource Capability */
+ RCBA32(0x001c) = 0x03128010;
+
+ /* Disable devices. */
+`)
+
+ RestoreRCBA32(sb, inteltool, 0x3418)
+
+ sb.WriteString(`
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(0x1e9c) = 0x000200f0;
+ RCBA32(0x1e98) = 0x000c0801;
+}
+`)
+
+ /* FIXME:XX does this one need adjustments? */
+ sb.WriteString(`void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+
+ // program secondary mlt XXX byte?
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+ // reset rtc power status
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+ // usb transient disconnect
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030549;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(0x3418) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
+`)
+
+ ioapic := DevTreeNode{
+ Chip: "drivers/generic/ioapic",
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "have_isa_interrupts": "1",
+ "irq_on_fsb": "1",
+ "enable_virtual_wire": "0",
+ "base": "0xfec00000",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "ioapic",
+ Dev: 2,
+ },
+ },
+ }
+
+ PutPCIChip(addr, ioapic)
+
+ ideConfig := uint8(0)
+ ide, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 1}]
+ if ok {
+ ideConfig = ide.ConfigDump[0x54]
+ }
+
+ FADT := ctx.InfoSource.GetACPI()["FACP"]
+
+ cur := DevTreeNode{
+ Chip: "southbridge/intel/i82801gx",
+ Comment: "Southbridge, FIXME: set gpiX_routing, gpe0_en and alt_gp_smi_en for EC support",
+ MissingParent: "southbridge",
+ Registers: map[string]string{
+ /* FIXME:XX should be a CMOS config */
+ "sata_ahci": "0x1",
+
+ "sata_ports_implemented": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0xf),
+ "ide_enable_primary": fmt.Sprintf("%d", (ideConfig>>1)&1),
+ "ide_enable_secondary": fmt.Sprintf("%d", (ideConfig>>3)&1),
+ "c4onc3_enable": fmt.Sprintf("%d", ((addr.ConfigDump[0xa0] >> 7) & 1)),
+ "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
+ "c3_latency": FormatHexLE16(FADT[98:100]),
+ "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB UHCI"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 1}, writeEmpty: true, additionalComment: "USB UHCI"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 2}, writeEmpty: true, additionalComment: "USB UHCI"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 3}, writeEmpty: true, additionalComment: "USB UHCI"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 7}, writeEmpty: true, additionalComment: "USB EHCI"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 1}, writeEmpty: true, additionalComment: "IDE Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ },
+ }
+
+ PutPCIChip(addr, cur)
+ PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
+
+ IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x00}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}}
+ IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x07}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x10, 0, 0, 0}}
+ IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1b}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0, 0, 0}}
+ IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1c}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x11, 0x10, 0x12, 0x13}}
+ IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1d}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x17, 0x13, 0x12, 0x10}}
+ IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1e}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x16, 0x14, 0, 0}}
+ IOAPICIRQs[PCIAddr{Bus: 0, Dev: 0x1f}] = IOAPICIRQ{APICID: 2, IRQNO: [4]int{0x12, 0x13, 0, 0x10}}
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/i82801gx/acpi/globalnvs.asl",
+ Comment: "global NVS and variables",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/i82801gx/acpi/platform.asl",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/i82801gx/acpi/sleepstates.asl",
+ })
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "southbridge/intel/i82801gx/acpi/ich7.asl",
+ })
+
+ ai := Create(ctx, "acpi/ich7_pci_irqs.asl")
+ defer ai.Close()
+
+ /* FIXME:XX hardcoded. */
+ ai.WriteString(
+ `/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 },
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 },
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 },
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 },
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 },
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 },
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 },
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 },
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }
+ })
+ } Else {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }
+ })
+}
+`)
+
+ ec := Create(ctx, "acpi/ec.asl")
+ defer ec.Close()
+ ec.WriteString("/* FIXME: Add EC support here. */")
+
+ at := Create(ctx, "acpi_tables.c")
+ defer at.Close()
+
+ at.WriteString(
+ `#include <stdint.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Enable both COM ports */
+ gnvs->cmap = 0x01;
+ gnvs->cmbp = 0x01;
+}
+`)
+
+ si := Create(ctx, "acpi/superio.asl")
+ defer si.Close()
+ si.WriteString("/* FIXME: Add superio support here. */")
+
+ ap := Create(ctx, "acpi/platform.asl")
+ defer ap.Close()
+
+ /* FIXME:XX hardcoded. */
+ ap.WriteString(
+ `Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Scope(\_SB)
+{
+ Method(_INI, 0)
+ {
+ \GOS()
+ }
+}
+`)
+
+
+
+ sh := Create(ctx, "smihandler.c")
+ defer sh.Close()
+
+ /* FIXME:XX hardcoded. */
+ sh.WriteString(
+ `
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <pc80/mc146818rtc.h>
+#include <delay.h>
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+ if (!pmbase)
+ return 0;
+
+ switch(data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* FIXME: Add EC support here */
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* FIXME: Add EC support here */
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+`)
+ mb := Create(ctx, "mainboard.c")
+ defer mb.Close()
+
+ /* FIXME:XX hardcoded. */
+ mb.WriteString(
+ `/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <northbridge/intel/i945/i945.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/x86/include/arch/acpigen.h>
+#include <smbios.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_init(device_t dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, INT15_5F35_CL_DISPLAY_DEFAULT, 3);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+`)
+
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x27b9, i82801gx{})
+ RegisterPCI(0x8086, 0x27c8, GenericPCI{})
+ RegisterPCI(0x8086, 0x27c9, GenericPCI{})
+ RegisterPCI(0x8086, 0x27ca, GenericPCI{})
+ RegisterPCI(0x8086, 0x27cb, GenericPCI{})
+ RegisterPCI(0x8086, 0x27cc, GenericPCI{})
+
+ RegisterPCI(0x8086, 0x27d0, GenericPCI{})
+ RegisterPCI(0x8086, 0x27d2, GenericPCI{})
+ RegisterPCI(0x8086, 0x27d4, GenericPCI{})
+ RegisterPCI(0x8086, 0x27d6, GenericPCI{})
+
+ RegisterPCI(0x8086, 0x2448, GenericPCI{})
+
+ RegisterPCI(0x8086, 0x27c5, GenericPCI{})
+ RegisterPCI(0x8086, 0x27c4, GenericPCI{})
+ RegisterPCI(0x8086, 0x27df, GenericPCI{})
+ RegisterPCI(0x8086, 0x27da, GenericPCI{MissingParent: "smbus"})
+}
diff --git a/util/autoport/i945.go b/util/autoport/i945.go
new file mode 100644
index 0000000..9a29002
--- /dev/null
+++ b/util/autoport/i945.go
@@ -0,0 +1,120 @@
+package main
+
+import (
+ "log"
+ "strings"
+)
+
+type i945mc struct {
+ variant string
+}
+
+func (i i945mc) Scan(ctx Context, addr PCIDevData) {
+
+ cpuModel := ctx.InfoSource.GetCPUModel()[0]
+ socket := ""
+ switch cpuModel >> 4 {
+ case 0x69, 0x6d, 0x6e, 0x6f:
+ socket = "mFCPGA478"
+ case 0x106c:
+ socket = "441"
+ default:
+ log.Fatalf("unsupported cpu: 0x%x", cpuModel)
+ }
+ DevTree = DevTreeNode{
+ Chip: "northbridge/intel/i945",
+ MissingParent: "northbridge",
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "gpu_hotplug": "0x00000220",
+ "gpu_lvds_use_spread_spectrum_clock": "1",
+ "gpu_lvds_is_dual_channel": "0",
+ "gpu_backlight": "0x1280128",
+ "gfx.ndid": "3",
+ "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu/intel/socket_" + socket,
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ },
+ },
+ },
+ },
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "VGA"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 1}, writeEmpty: true, additionalComment: "Display controller"},
+ },
+ },
+ },
+ }
+ PutPCIDev(addr, "Host bridge")
+
+ /* FIXME:XX Move part to northbridge? */
+ /* FIXME:XX some configs are unsupported. */
+ KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true
+ KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true
+ KconfigBool["VGA"] = true
+ KconfigBool["MAINBOARD_DO_EDID"] = true
+ KconfigBool["EARLY_CBMEM_INIT"] = true
+ KconfigBool["INTEL_EDID"] = true
+ KconfigBool["CPU_INTEL_SOCKET_"+strings.ToUpper(socket)] = true
+ KconfigBool["NORTHBRIDGE_INTEL_I945"] = true
+ KconfigBool["CHANNEL_XOR_RANDOMIZATION"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ KconfigHex["DCACHE_RAM_BASE"] = 0xffdf8000
+ KconfigHex["DCACHE_RAM_SIZE"] = 0x8000
+ KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000
+ KconfigInt["MAX_CPUS"] = 2
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "cpu/intel/model_6dx/acpi/cpu.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "northbridge/intel/i945/acpi/i945.asl",
+ })
+
+ KconfigBool["NORTHBRIDGE_INTEL_SUBTYPE_" + i.variant] = true
+
+ cs := Create(ctx, "cstates.c")
+ defer cs.Close()
+ AddRAMStageFile("cstates.c", "")
+
+ cs.WriteString(
+ `#include <arch/acpigen.h>
+#include <device/device.h>
+#include <northbridge/intel/i945/i945.h>
+
+/* FIXME: fill this. */
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
+`)
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x27a0, i945mc{variant:"I945GM"})
+ RegisterPCI(0x8086, 0x27ac, i945mc{variant:"I945GM"})
+ RegisterPCI(0x8086, 0x27a2, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ RegisterPCI(0x8086, 0x27ae, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ RegisterPCI(0x8086, 0x27a6, GenericPCI{Comment: "display controller"})
+}
diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go
new file mode 100644
index 0000000..8db428d
--- /dev/null
+++ b/util/autoport/log_maker.go
@@ -0,0 +1,85 @@
+package main
+
+import (
+ "io"
+ "io/ioutil"
+ "log"
+ "os"
+ "os/exec"
+ "strings"
+)
+
+func RunAndSave(output string, name string, arg ...string) {
+ cmd := exec.Command(name, arg...)
+
+ f, err := os.Create(output)
+ if err != nil {
+ log.Fatal(err)
+ }
+
+ cmd.Stdout = f
+ cmd.Stderr = f
+
+ err = cmd.Start()
+ if err != nil {
+ log.Fatal(err)
+ }
+ cmd.Wait()
+}
+
+func MakeLogs(outDir string) {
+ os.MkdirAll(outDir, 0700)
+ RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx")
+ RunAndSave(outDir+"/dmidecode.log", "dmidecode")
+ RunAndSave(outDir+"/acpidump.log", "acpidump")
+ /* FIXME:XX */
+ RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", "-a")
+
+ SysDir := "/sys/class/sound/card0/"
+ files, _ := ioutil.ReadDir(SysDir)
+ for _, f := range files {
+ if (strings.HasPrefix(f.Name(), "hw") || strings.HasPrefix(f.Name(), "hdaudio")) && f.IsDir() {
+ in, err := os.Open(SysDir + f.Name() + "/init_pin_configs")
+ defer in.Close()
+ if err != nil {
+ log.Fatal(err)
+ }
+ out, err := os.Create(outDir + "/pin_" + strings.Replace(f.Name(), "hdaudio", "hw", -1))
+ if err != nil {
+ log.Fatal(err)
+ }
+ defer out.Close()
+ io.Copy(out, in)
+ }
+ }
+
+ ProcDir := "/proc/asound/card0/"
+ files, _ = ioutil.ReadDir(ProcDir)
+ for _, f := range files {
+ if strings.HasPrefix(f.Name(), "codec#") && !f.IsDir() {
+ in, err := os.Open(ProcDir + f.Name())
+ defer in.Close()
+ if err != nil {
+ log.Fatal(err)
+ }
+ out, err := os.Create(outDir + "/" + f.Name())
+ if err != nil {
+ log.Fatal(err)
+ }
+ defer out.Close()
+ io.Copy(out, in)
+ }
+ }
+
+ in, err := os.Open("/proc/cpuinfo")
+ defer in.Close()
+ if err != nil {
+ log.Fatal(err)
+ }
+ out, err := os.Create(outDir + "/cpuinfo.log")
+ if err != nil {
+ log.Fatal(err)
+ }
+ defer out.Close()
+ io.Copy(out, in)
+}
diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go
new file mode 100644
index 0000000..2fcfbd1
--- /dev/null
+++ b/util/autoport/log_reader.go
@@ -0,0 +1,319 @@
+package main
+
+import (
+ "bufio"
+ "flag"
+ "fmt"
+ "log"
+ "os"
+ "strconv"
+ "strings"
+)
+
+type LogDevReader struct {
+ InputDirectory string
+ ACPITables map[string][]byte
+}
+
+func isXDigit(x uint8) bool {
+ if x >= '0' && x <= '9' {
+ return true
+ }
+ if x >= 'a' && x <= 'f' {
+ return true
+ }
+ if x >= 'A' && x <= 'F' {
+ return true
+ }
+ return false
+}
+
+type HexLine struct {
+ length uint
+ values [16]byte
+ start uint
+}
+
+func (l *LogDevReader) ReadHexLine(line string) (hex HexLine) {
+ hex.start = 0
+ line = strings.Trim(line, " ")
+ fmt.Sscanf(line, "%x:", &hex.start)
+ ll, _ := fmt.Sscanf(line, "%x: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x", &hex.start,
+ &hex.values[0], &hex.values[1], &hex.values[2],
+ &hex.values[3], &hex.values[4], &hex.values[5],
+ &hex.values[6], &hex.values[7], &hex.values[8],
+ &hex.values[9], &hex.values[10], &hex.values[11],
+ &hex.values[12], &hex.values[13], &hex.values[14],
+ &hex.values[15])
+ hex.length = uint(ll - 1)
+ return
+}
+
+func (l *LogDevReader) AssignHexLine(inp string, target []byte) []byte {
+ hex := l.ReadHexLine(inp)
+ if hex.start+hex.length > uint(len(target)) {
+ target = target[0 : hex.start+hex.length]
+ }
+ copy(target[hex.start:hex.start+hex.length], hex.values[0:hex.length])
+ return target
+}
+
+func (l *LogDevReader) GetACPI() (Tables map[string][]byte) {
+ if l.ACPITables != nil {
+ return l.ACPITables
+ }
+ l.ACPITables = Tables
+
+ file, err := os.Open(l.InputDirectory + "/acpidump.log")
+ if err != nil {
+ log.Fatal(err)
+ }
+ defer file.Close()
+
+ scanner := bufio.NewScanner(file)
+
+ Tables = map[string][]byte{}
+
+ curTable := ""
+ for scanner.Scan() {
+ line := scanner.Text()
+ switch {
+ case len(line) >= 6 && line[5] == '@':
+ curTable = line[0:4]
+ Tables[curTable] = make([]byte, 0, 100000)
+ case len(line) > 7 && line[0:2] == " " && isXDigit(line[2]) && isXDigit(line[3]) && isXDigit(line[4]) && isXDigit(line[5]) && line[6] == ':':
+ Tables[curTable] = l.AssignHexLine(line, Tables[curTable])
+ }
+ }
+
+ if err := scanner.Err(); err != nil {
+ log.Fatal(err)
+ }
+
+ return
+}
+
+func (l *LogDevReader) GetPCIList() (PCIList []PCIDevData) {
+ file, err := os.Open(l.InputDirectory + "/lspci.log")
+ if err != nil {
+ log.Fatal(err)
+ }
+ defer file.Close()
+
+ scanner := bufio.NewScanner(file)
+
+ PCIList = []PCIDevData{}
+
+ for scanner.Scan() {
+ line := scanner.Text()
+ switch {
+ case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])):
+ cur := PCIDevData{}
+ fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func)
+ lc := strings.LastIndex(line, ":")
+ li := strings.LastIndex(line[0:lc], "[")
+ if li < 0 {
+ continue
+ }
+ ven := 0
+ dev := 0
+ fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev)
+ cur.PCIDevID = uint16(dev)
+ cur.PCIVenID = uint16(ven)
+ cur.ConfigDump = make([]byte, 0x100, 0x1000)
+ PCIList = append(PCIList, cur)
+ case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':':
+ start := 0
+ fmt.Sscanf(line, "%x:", &start)
+ cur := &PCIList[len(PCIList)-1]
+ cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump)
+ }
+ }
+
+ if err := scanner.Err(); err != nil {
+ log.Fatal(err)
+ }
+
+ return
+}
+
+func (l *LogDevReader) GetInteltool() (ret InteltoolData) {
+ file, err := os.Open(l.InputDirectory + "/inteltool.log")
+ if err != nil {
+ log.Fatal(err)
+ }
+ defer file.Close()
+
+ scanner := bufio.NewScanner(file)
+ paragraph := ""
+ ret.GPIO = map[uint16]uint32{}
+ ret.RCBA = map[uint16]uint32{}
+ ret.IGD = map[uint32]uint32{}
+ for scanner.Scan() {
+ line := scanner.Text()
+ switch {
+ case len(line) > 7 && line[0] == '0' && line[1] == 'x' && line[6] == ':' && paragraph == "RCBA":
+ addr, value := 0, 0
+ fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value)
+ ret.RCBA[uint16(addr)] = uint32(value)
+ case len(line) > 9 && line[0] == '0' && line[1] == 'x' && line[8] == ':' && paragraph == "IGD":
+ addr, value := 0, 0
+ fmt.Sscanf(line, "0x%x: 0x%x", &addr, &value)
+ ret.IGD[uint32(addr)] = uint32(value)
+ case strings.Contains(line, "DEFAULT"):
+ continue
+ case strings.Contains(line, "DIFF"):
+ continue
+ case strings.HasPrefix(line, "gpiobase"):
+ addr, value := 0, 0
+ fmt.Sscanf(line, "gpiobase+0x%x: 0x%x", &addr, &value)
+ ret.GPIO[uint16(addr)] = uint32(value)
+ case strings.HasPrefix(line, "============="):
+ paragraph = strings.Trim(line, "= ")
+ }
+ }
+
+ if err := scanner.Err(); err != nil {
+ log.Fatal(err)
+ }
+ return
+}
+
+func (l *LogDevReader) GetDMI() (ret DMIData) {
+ file, err := os.Open(l.InputDirectory + "/dmidecode.log")
+ if err != nil {
+ log.Fatal(err)
+ }
+ defer file.Close()
+
+ scanner := bufio.NewScanner(file)
+ paragraph := ""
+ for scanner.Scan() {
+ line := scanner.Text()
+ if !strings.HasPrefix(line, "\t") {
+ paragraph = strings.TrimSpace(line)
+ continue
+ }
+ idx := strings.Index(line, ":")
+ if idx < 0 {
+ continue
+ }
+ name := strings.TrimSpace(line[0:idx])
+ value := strings.TrimSpace(line[idx+1:])
+ switch paragraph + ":" + name {
+ case "System Information:Manufacturer":
+ ret.Vendor = value
+ case "System Information:Product Name":
+ ret.Model = value
+ case "System Information:Version":
+ ret.Version = value
+ case "Chassis Information:Type":
+ ret.IsLaptop = (value == "Notebook" || value == "Laptop")
+ }
+ }
+
+ if err := scanner.Err(); err != nil {
+ log.Fatal(err)
+ }
+ return
+}
+
+func (l *LogDevReader) GetAzaliaCodecs() (ret []AzaliaCodec) {
+ for codecno := 0; codecno < 10; codecno++ {
+ cur := AzaliaCodec{CodecNo: codecno, PinConfig: map[int]uint32{}}
+ codec, err := os.Open(l.InputDirectory + "/codec#" + strconv.Itoa(codecno))
+ if err != nil {
+ continue
+ }
+ defer codec.Close()
+ pin, err := os.Open(l.InputDirectory + "/pin_hwC0D" + strconv.Itoa(codecno))
+ if err != nil {
+ continue
+ }
+ defer pin.Close()
+
+ scanner := bufio.NewScanner(codec)
+ for scanner.Scan() {
+ line := scanner.Text()
+ if strings.HasPrefix(line, "Codec:") {
+ fmt.Sscanf(line, "Codec: %s", &cur.Name)
+ continue
+ }
+ if strings.HasPrefix(line, "Vendor Id:") {
+ fmt.Sscanf(line, "Vendor Id: 0x%x", &cur.VendorID)
+ continue
+ }
+ if strings.HasPrefix(line, "Subsystem Id:") {
+ fmt.Sscanf(line, "Subsystem Id: 0x%x", &cur.SubsystemID)
+ continue
+ }
+ }
+
+ scanner = bufio.NewScanner(pin)
+ for scanner.Scan() {
+ line := scanner.Text()
+ addr := 0
+ val := uint32(0)
+ fmt.Sscanf(line, "0x%x 0x%x", &addr, &val)
+ cur.PinConfig[addr] = val
+ }
+ ret = append(ret, cur)
+ }
+ return
+}
+
+func (l *LogDevReader) GetCPUModel() (ret []uint32) {
+ file, err := os.Open(l.InputDirectory + "/cpuinfo.log")
+ if err != nil {
+ log.Fatal(err)
+ }
+ defer file.Close()
+
+ scanner := bufio.NewScanner(file)
+ ret = make([]uint32, 0, 100)
+ proc := 0
+ for scanner.Scan() {
+ line := scanner.Text()
+ sep := strings.Index(line, ":")
+ if sep < 0 {
+ continue
+ }
+ key := strings.TrimSpace(line[0:sep])
+ val := strings.TrimSpace(line[sep+1:])
+
+ if key == "processor" {
+ proc, _ := strconv.Atoi(val)
+ if len(ret) <= proc {
+ ret = ret[0 : proc+1]
+ }
+ continue
+ }
+ if key == "cpu family" {
+ family, _ := strconv.Atoi(val)
+ ret[proc] |= uint32(((family & 0xf) << 8) | ((family & 0xff0) << 16))
+ }
+ if key == "model" {
+ model, _ := strconv.Atoi(val)
+ ret[proc] |= uint32(((model & 0xf) << 4) | ((model & 0xf0) << 12))
+ }
+ if key == "stepping" {
+ stepping, _ := strconv.Atoi(val)
+ ret[proc] |= uint32(stepping & 0xf)
+ }
+ }
+
+ if err := scanner.Err(); err != nil {
+ log.Fatal(err)
+ }
+ return
+}
+
+var FlagLogInput = flag.String("input_log", ".", "Input log directory")
+var FlagLogMkLogs = flag.Bool("make_logs", false, "Dump logs")
+
+func MakeLogReader() *LogDevReader {
+ if *FlagLogMkLogs {
+ MakeLogs(*FlagLogInput)
+ }
+ return &LogDevReader{InputDirectory: *FlagLogInput}
+}
diff --git a/util/autoport/main.go b/util/autoport/main.go
new file mode 100644
index 0000000..be28b66
--- /dev/null
+++ b/util/autoport/main.go
@@ -0,0 +1,682 @@
+/* This is just an experiment. Full automatic porting
+ is probably not possible but a lot can be automated. */
+package main
+
+import (
+ "flag"
+ "fmt"
+ "log"
+ "os"
+ "sort"
+ "strings"
+)
+
+type PCIAddr struct {
+ Bus int
+ Dev int
+ Func int
+}
+
+type PCIDevData struct {
+ PCIAddr
+ PCIVenID uint16
+ PCIDevID uint16
+ ConfigDump []uint8
+}
+
+type PCIDevice interface {
+ Scan(ctx Context, addr PCIDevData)
+}
+
+type InteltoolData struct {
+ GPIO map[uint16]uint32
+ RCBA map[uint16]uint32
+ IGD map[uint32]uint32
+}
+
+type DMIData struct {
+ Vendor string
+ Model string
+ Version string
+ IsLaptop bool
+}
+
+type AzaliaCodec struct {
+ Name string
+ VendorID uint32
+ SubsystemID uint32
+ CodecNo int
+ PinConfig map[int]uint32
+}
+
+type DevReader interface {
+ GetPCIList() []PCIDevData
+ GetDMI() DMIData
+ GetInteltool() InteltoolData
+ GetAzaliaCodecs() []AzaliaCodec
+ GetACPI() map[string][]byte
+ GetCPUModel() []uint32
+}
+
+var ROMStageFiles map[string]string = map[string]string{}
+var RAMStageFiles map[string]string = map[string]string{}
+
+type Context struct {
+ MoboID string
+ KconfigName string
+ Vendor string
+ Model string
+ BaseDirectory string
+ InfoSource DevReader
+}
+
+type IOAPICIRQ struct {
+ APICID int
+ IRQNO [4]int
+}
+
+var IOAPICIRQs map[PCIAddr]IOAPICIRQ = map[PCIAddr]IOAPICIRQ{}
+var KconfigBool map[string]bool = map[string]bool{}
+var KconfigComment map[string]string = map[string]string{}
+var KconfigString map[string]string = map[string]string{}
+var KconfigStringUnquoted map[string]string = map[string]string{}
+var KconfigHex map[string]uint32 = map[string]uint32{}
+var KconfigInt map[string]int = map[string]int{}
+var ROMSizeKB = 0
+var ROMProtocol = ""
+var FlashROMSupport = ""
+
+func GetLE16(inp []byte) uint16 {
+ return uint16(inp[0])|(uint16(inp[1])<<8)
+}
+
+func FormatHexLE16(inp []byte) string {
+ return fmt.Sprintf("0x%04x", GetLE16(inp))
+}
+
+func FormatHex32(u uint32) string {
+ return fmt.Sprintf("0x%08x", u)
+}
+
+func FormatInt32(u uint32) string {
+ return fmt.Sprintf("%d", u)
+}
+
+func FormatHexLE32(d []uint8) string {
+ u := uint32(d[0]) | (uint32(d[1]) << 8) | (uint32(d[2]) << 16) | (uint32(d[3]) << 24)
+ return FormatHex32(u)
+}
+
+func FormatBool(inp bool) string {
+ if inp {
+ return "1"
+ } else {
+ return "0"
+ }
+}
+
+func sanitize(inp string) string {
+ result := strings.ToLower(inp)
+ result = strings.Replace(result, " ", "_", -1)
+ result = strings.Replace(result, ",", "_", -1)
+ for strings.HasSuffix(result, ".") {
+ result = result[0 : len(result)-1]
+ }
+ return result
+}
+
+func AddROMStageFile(Name string, Condition string) {
+ ROMStageFiles[Name] = Condition
+}
+
+func AddRAMStageFile(Name string, Condition string) {
+ RAMStageFiles[Name] = Condition
+}
+
+var FlagOutDir = flag.String("coreboot_dir", ".", "Resulting coreboot directory")
+
+func writeMF(mf *os.File, files map[string]string, category string) {
+ for file, condition := range files {
+ if condition == "" {
+ fmt.Fprintf(mf, "%s-y += %s\n", category, file)
+ } else {
+ fmt.Fprintf(mf, "%s-$(%s) += %s\n", category,
+ condition, file)
+ }
+ }
+}
+
+func Create(ctx Context, name string) *os.File {
+ li := strings.LastIndex(name, "/")
+ if li > 0 {
+ os.MkdirAll(ctx.BaseDirectory+"/"+name[0:li], 0700)
+ }
+ mf, err := os.Create(ctx.BaseDirectory + "/" + name)
+ if err != nil {
+ log.Fatal(err)
+ }
+ return mf
+}
+
+func RestorePCI16Simple(f *os.File, pcidev PCIDevData, addr uint16) {
+ fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x);\n",
+ pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
+ pcidev.ConfigDump[addr+1],
+ pcidev.ConfigDump[addr])
+}
+
+func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
+ fmt.Fprintf(f, " pci_write_config16(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
+ pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
+ pcidev.ConfigDump[addr+3],
+ pcidev.ConfigDump[addr+2],
+ pcidev.ConfigDump[addr+1],
+ pcidev.ConfigDump[addr])
+}
+
+func RestoreRCBA32(f *os.File, inteltool InteltoolData, addr uint16) {
+ fmt.Fprintf(f, "\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr])
+}
+
+type PCISlot struct {
+ PCIAddr
+ additionalComment string
+ writeEmpty bool
+}
+
+type DevTreeNode struct {
+ Bus int
+ Dev int
+ Func int
+ Disabled bool
+ Registers map[string]string
+ Children []DevTreeNode
+ PCISlots []PCISlot
+ PCIController bool
+ ChildPCIBus int
+ MissingParent string
+ SubVendor uint16
+ SubSystem uint16
+ Chip string
+ Comment string
+}
+
+var DevTree DevTreeNode
+var MissingChildren map[string][]DevTreeNode = map[string][]DevTreeNode{}
+var unmatchedPCIChips map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{}
+var unmatchedPCIDevices map[PCIAddr]DevTreeNode = map[PCIAddr]DevTreeNode{}
+
+func Offset(dt *os.File, offset int) {
+ for i := 0; i < offset; i++ {
+ fmt.Fprintf(dt, "\t")
+ }
+}
+
+func MatchDev(dev *DevTreeNode) {
+ for idx := range dev.Children {
+ MatchDev(&dev.Children[idx])
+ }
+
+ for _, slot := range dev.PCISlots {
+ slotChip, ok := unmatchedPCIChips[slot.PCIAddr]
+
+ if !ok {
+ continue
+ }
+
+ if slot.additionalComment != "" && slotChip.Comment != "" {
+ slotChip.Comment = slot.additionalComment + " " + slotChip.Comment
+ } else {
+ slotChip.Comment = slot.additionalComment + slotChip.Comment
+ }
+
+ delete(unmatchedPCIChips, slot.PCIAddr)
+ MatchDev(&slotChip)
+ dev.Children = append(dev.Children, slotChip)
+ }
+
+ if dev.PCIController {
+ for slot, slotDev := range unmatchedPCIChips {
+ if slot.Bus == dev.ChildPCIBus {
+ delete(unmatchedPCIChips, slot)
+ MatchDev(&slotDev)
+ dev.Children = append(dev.Children, slotDev)
+ }
+ }
+ }
+
+ for _, slot := range dev.PCISlots {
+ slotDev, ok := unmatchedPCIDevices[slot.PCIAddr]
+ if !ok {
+ if slot.writeEmpty {
+ dev.Children = append(dev.Children,
+ DevTreeNode{
+ Registers: map[string]string{},
+ Chip: "pci",
+ Bus: slot.Bus,
+ Dev: slot.Dev,
+ Func: slot.Func,
+ Comment: slot.additionalComment,
+ Disabled: true,
+ },
+ )
+ }
+ continue
+ }
+
+ if slot.additionalComment != "" && slotDev.Comment != "" {
+ slotDev.Comment = slot.additionalComment + " " + slotDev.Comment
+ } else {
+ slotDev.Comment = slot.additionalComment + slotDev.Comment
+ }
+
+ MatchDev(&slotDev)
+ dev.Children = append(dev.Children, slotDev)
+ delete(unmatchedPCIDevices, slot.PCIAddr)
+ }
+
+ if dev.MissingParent != "" {
+ for _, child := range MissingChildren[dev.MissingParent] {
+ MatchDev(&child)
+ dev.Children = append(dev.Children, child)
+ }
+ delete(MissingChildren, dev.MissingParent)
+ }
+
+ if dev.PCIController {
+ for slot, slotDev := range unmatchedPCIDevices {
+ if slot.Bus == dev.ChildPCIBus {
+ MatchDev(&slotDev)
+ dev.Children = append(dev.Children, slotDev)
+ delete(unmatchedPCIDevices, slot)
+ }
+ }
+ }
+}
+
+func writeOn(dt *os.File, dev DevTreeNode) {
+ if dev.Disabled {
+ fmt.Fprintf(dt, "off")
+ } else {
+ fmt.Fprintf(dt, "on")
+ }
+}
+
+func WriteDev(dt *os.File, offset int, dev DevTreeNode) {
+ Offset(dt, offset)
+ switch dev.Chip {
+ case "cpu_cluster", "lapic", "domain", "ioapic":
+ fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev)
+ writeOn(dt, dev)
+ case "pci":
+ fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func)
+ writeOn(dt, dev)
+ default:
+ fmt.Fprintf(dt, "chip %s", dev.Chip)
+ }
+ if dev.Comment != "" {
+ fmt.Fprintf(dt, " # %s", dev.Comment)
+ }
+ fmt.Fprintf(dt, "\n")
+ if dev.Chip == "pci" && dev.SubSystem != 0 && dev.SubVendor != 0 {
+ Offset(dt, offset+1)
+ fmt.Fprintf(dt, "subsystemid 0x%04x 0x%04x\n", dev.SubVendor, dev.SubSystem)
+ }
+
+ ioapic, ok := IOAPICIRQs[PCIAddr{Bus: dev.Bus, Dev: dev.Dev, Func: dev.Func}]
+ if dev.Chip == "pci" && ok {
+ for pin, irq := range ioapic.IRQNO {
+ if irq != 0 {
+ Offset(dt, offset+1)
+ fmt.Fprintf(dt, "ioapic_irq %d INT%c 0x%x\n", ioapic.APICID, 'A'+pin, irq)
+ }
+ }
+ }
+
+ keys := []string{}
+ for reg, _ := range dev.Registers {
+ keys = append(keys, reg)
+ }
+
+ sort.Strings(keys)
+
+ for _, reg := range keys {
+ val := dev.Registers[reg]
+ Offset(dt, offset+1)
+ fmt.Fprintf(dt, "register \"%s\" = \"%s\"\n", reg, val)
+ }
+
+ for _, child := range dev.Children {
+ WriteDev(dt, offset+1, child)
+ }
+
+ Offset(dt, offset)
+ fmt.Fprintf(dt, "end\n")
+}
+
+func PutChip(domain string, cur DevTreeNode) {
+ MissingChildren[domain] = append(MissingChildren[domain], cur)
+}
+
+func PutPCIChip(addr PCIDevData, cur DevTreeNode) {
+ unmatchedPCIChips[addr.PCIAddr] = cur
+}
+
+func PutPCIDevParent(addr PCIDevData, comment string, parent string) {
+ cur := DevTreeNode{
+ Registers: map[string]string{},
+ Chip: "pci",
+ Bus: addr.Bus,
+ Dev: addr.Dev,
+ Func: addr.Func,
+ MissingParent: parent,
+ Comment: comment,
+ }
+ if addr.ConfigDump[0xa] == 0x04 && addr.ConfigDump[0xb] == 0x06 {
+ cur.PCIController = true
+ cur.ChildPCIBus = int(addr.ConfigDump[0x19])
+
+ loopCtr := 0
+ for capPtr := addr.ConfigDump[0x34]; capPtr != 0; capPtr = addr.ConfigDump[capPtr + 1] {
+ /* Avoid hangs. There are only 0x100 different possible values for capPtr.
+ If we iterate longer than that, we're in endless loop. */
+ loopCtr++
+ if (loopCtr > 0x100) {
+ break
+ }
+ if addr.ConfigDump[capPtr] == 0x0d {
+ cur.SubVendor = GetLE16(addr.ConfigDump[capPtr+4:capPtr+6])
+ cur.SubSystem = GetLE16(addr.ConfigDump[capPtr+6:capPtr+8])
+ }
+ }
+ } else {
+ cur.SubVendor = GetLE16(addr.ConfigDump[0x2c:0x2e])
+ cur.SubSystem = GetLE16(addr.ConfigDump[0x2e:0x30])
+ }
+ unmatchedPCIDevices[addr.PCIAddr] = cur
+}
+
+func PutPCIDev(addr PCIDevData, comment string) {
+ PutPCIDevParent(addr, comment, "")
+}
+
+type GenericPCI struct {
+ Comment string
+ Bus0Subdiv string
+ MissingParent string
+}
+
+type GenericVGA struct {
+ GenericPCI
+}
+
+type DSDTInclude struct {
+ Comment string
+ File string
+}
+
+var DSDTIncludes []DSDTInclude
+var DSDTPCI0Includes []DSDTInclude
+
+func (g GenericPCI) Scan(ctx Context, addr PCIDevData) {
+ PutPCIDevParent(addr, g.Comment, g.MissingParent)
+}
+
+func (g GenericVGA) Scan(ctx Context, addr PCIDevData) {
+ KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x",
+ addr.PCIVenID,
+ addr.PCIDevID)
+ KconfigString["VGA_BIOS_FILE"] = fmt.Sprintf("pci%04x,%04x.rom",
+ addr.PCIVenID,
+ addr.PCIDevID)
+ PutPCIDevParent(addr, g.Comment, g.MissingParent)
+}
+
+func makeKconfigName(ctx Context) {
+ kn := Create(ctx, "Kconfig.name")
+ defer kn.Close()
+
+ fmt.Fprintf(kn, "config %s\n\tbool \"%s\"\n", ctx.KconfigName, ctx.Model)
+}
+
+func makeComment(name string) string {
+ cmt, ok := KconfigComment[name]
+ if !ok {
+ return ""
+ }
+ return " # " + cmt
+}
+
+func makeKconfig(ctx Context) {
+ kc := Create(ctx, "Kconfig")
+ defer kc.Close()
+
+ fmt.Fprintf(kc, "if %s\n\n", ctx.KconfigName)
+
+ fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS # dummy\n\tdef_bool y\n")
+ keys := []string{}
+ for name, val := range KconfigBool {
+ if val {
+ keys = append(keys, name)
+ }
+ }
+
+ sort.Strings(keys)
+
+ for _, name := range keys {
+ fmt.Fprintf(kc, "\tselect %s%s\n", name,makeComment(name))
+ }
+
+ keys = nil
+ for name, val := range KconfigBool {
+ if !val {
+ keys = append(keys, name)
+ }
+ }
+
+ sort.Strings(keys)
+
+ for _, name := range keys {
+ fmt.Fprintf(kc, `
+config %s%s
+ bool
+ default n
+`, name, makeComment(name))
+ }
+
+ keys = nil
+ for name, _ := range KconfigStringUnquoted {
+ keys = append(keys, name)
+ }
+
+ sort.Strings(keys)
+
+ for _, name := range keys {
+ fmt.Fprintf(kc, `
+config %s%s
+ string
+ default %s
+`, name, makeComment(name), KconfigStringUnquoted[name])
+ }
+
+ keys = nil
+ for name, _ := range KconfigString {
+ keys = append(keys, name)
+ }
+
+ sort.Strings(keys)
+
+ for _, name := range keys {
+ fmt.Fprintf(kc, `
+config %s%s
+ string
+ default "%s"
+`, name, makeComment(name), KconfigString[name])
+ }
+
+ keys = nil
+ for name, _ := range KconfigHex {
+ keys = append(keys, name)
+ }
+
+ sort.Strings(keys)
+
+ for _, name := range keys {
+ fmt.Fprintf(kc, `
+config %s%s
+ hex
+ default 0x%x
+`, name, makeComment(name), KconfigHex[name])
+ }
+
+ keys = nil
+ for name, _ := range KconfigInt {
+ keys = append(keys, name)
+ }
+
+ sort.Strings(keys)
+
+ for _, name := range keys {
+ fmt.Fprintf(kc, `
+config %s%s
+ int
+ default %d
+`, name, makeComment(name), KconfigInt[name])
+ }
+
+ fmt.Fprintf(kc, "endif\n")
+}
+
+func main() {
+ flag.Parse()
+
+ ctx := Context{}
+
+ ctx.InfoSource = MakeLogReader()
+
+ dmi := ctx.InfoSource.GetDMI()
+
+ ctx.Vendor = dmi.Vendor
+
+ if dmi.Vendor == "LENOVO" {
+ ctx.Model = dmi.Version
+ } else {
+ ctx.Model = dmi.Model
+ }
+
+ if dmi.IsLaptop {
+ KconfigBool["SYSTEM_TYPE_LAPTOP"] = true
+ }
+ ctx.MoboID = sanitize(ctx.Vendor) + "/" + sanitize(ctx.Model)
+ ctx.KconfigName = "BOARD_" + strings.ToUpper(sanitize(ctx.Vendor)+"_"+sanitize(ctx.Model))
+ ctx.BaseDirectory = *FlagOutDir + "/src/mainboard/" + ctx.MoboID
+ KconfigStringUnquoted["MAINBOARD_DIR"] = ctx.MoboID
+ KconfigString["MAINBOARD_PART_NUMBER"] = ctx.Model
+
+ os.MkdirAll(ctx.BaseDirectory, 0700)
+
+ ScanRoot(ctx)
+
+ if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 {
+ mf := Create(ctx, "Makefile.inc")
+ defer mf.Close()
+ writeMF(mf, ROMStageFiles, "romstage")
+ writeMF(mf, RAMStageFiles, "ramstage")
+ }
+
+ devtree := Create(ctx, "devicetree.cb")
+ defer devtree.Close()
+
+ MatchDev(&DevTree)
+ WriteDev(devtree, 0, DevTree)
+
+ bi := Create(ctx, "board_info.txt")
+ defer bi.Close()
+
+ fixme := ""
+
+ if dmi.IsLaptop {
+ bi.WriteString("Category: laptop\n")
+ } else {
+ bi.WriteString("Category: desktop\n")
+ fixme += "check category, "
+ }
+
+ missing := "ROM package, ROM socketed"
+
+ if ROMProtocol != "" {
+ fmt.Fprintf(bi, "ROM protocol: %s\n", ROMProtocol)
+ } else {
+ missing += ", ROM protocol"
+ }
+
+ if FlashROMSupport != "" {
+ fmt.Fprintf(bi, "Flashrom support: %s\n", FlashROMSupport)
+ } else {
+ missing += ", Flashrom support"
+ }
+
+ missing += ", Release year: 2012"
+
+ if fixme != "" {
+ fmt.Fprintf(bi, "FIXME: %s, put %s\n", fixme, missing)
+ } else {
+ fmt.Fprintf(bi, "FIXME: put %s\n", missing)
+ }
+
+ rs := Create(ctx, "romstage.c")
+ defer rs.Close()
+ rs.WriteString("/* dummy file */\n")
+
+ if ROMSizeKB == 0 {
+ KconfigBool["BOARD_ROMSIZE_KB_2048"] = true
+ KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this"
+ } else {
+ KconfigBool[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = true
+ }
+
+ makeKconfig(ctx)
+ makeKconfigName(ctx)
+
+ dsdt := Create(ctx, "dsdt.asl")
+ defer dsdt.Close()
+
+ dsdt.WriteString(
+ `DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+`)
+
+ for _, x := range DSDTIncludes {
+ if x.Comment != "" {
+ fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment)
+ }
+ fmt.Fprintf(dsdt, "\t#include <%s>\n", x.File)
+ }
+
+ dsdt.WriteString(`
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+`)
+ for _, x := range DSDTPCI0Includes {
+ if x.Comment != "" {
+ fmt.Fprintf(dsdt, "\t/* %s. */\n", x.Comment)
+ }
+ fmt.Fprintf(dsdt, "\t\t#include <%s>\n", x.File)
+ }
+ dsdt.WriteString(
+ ` }
+ }
+}
+`)
+
+}
diff --git a/util/autoport/rce823.go b/util/autoport/rce823.go
new file mode 100644
index 0000000..7c92109
--- /dev/null
+++ b/util/autoport/rce823.go
@@ -0,0 +1,39 @@
+package main
+
+import "fmt"
+
+type rce823 struct {
+ variant string
+}
+
+func (r rce823) Scan(ctx Context, addr PCIDevData) {
+ if addr.Dev == 0 && addr.Func == 0 {
+ cur := DevTreeNode{
+ Chip: "drivers/ricoh/rce822",
+ Comment: "Ricoh cardreader",
+ Registers: map[string]string{
+
+ "sdwppol": fmt.Sprintf("%d", (addr.ConfigDump[0xfb]&2)>>1),
+ "disable_mask": fmt.Sprintf("0x%x", addr.ConfigDump[0xcb]),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 0}, writeEmpty: false},
+ PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 1}, writeEmpty: false},
+ PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 2}, writeEmpty: false},
+ PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 3}, writeEmpty: false},
+ PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 4}, writeEmpty: false},
+ PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 5}, writeEmpty: false},
+ PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 6}, writeEmpty: false},
+ PCISlot{PCIAddr: PCIAddr{Bus: addr.Bus, Dev: 0x0, Func: 7}, writeEmpty: false},
+ },
+ }
+ PutPCIChip(addr, cur)
+ }
+ PutPCIDev(addr, "Ricoh SD card reader")
+ KconfigBool["DRIVERS_RICOH_RCE822"] = true
+}
+
+func init() {
+ RegisterPCI(0x1180, 0xe822, rce823{})
+ RegisterPCI(0x1180, 0xe823, rce823{})
+}
diff --git a/util/autoport/root.go b/util/autoport/root.go
new file mode 100644
index 0000000..60b5ccd
--- /dev/null
+++ b/util/autoport/root.go
@@ -0,0 +1,29 @@
+package main
+
+import "fmt"
+
+var supportedPCIDevices map[uint32]PCIDevice = map[uint32]PCIDevice{}
+var PCIMap map[PCIAddr]PCIDevData = map[PCIAddr]PCIDevData{}
+
+func ScanRoot(ctx Context) {
+ for _, pciDev := range ctx.InfoSource.GetPCIList() {
+ PCIMap[pciDev.PCIAddr] = pciDev
+ }
+ for _, pciDev := range ctx.InfoSource.GetPCIList() {
+ vendevid := (uint32(pciDev.PCIDevID) << 16) | uint32(pciDev.PCIVenID)
+
+ dev, ok := supportedPCIDevices[vendevid]
+ if !ok {
+ fmt.Printf("Unsupported PCI device %04x:%04x\n",
+ pciDev.PCIVenID, pciDev.PCIDevID)
+ dev = GenericPCI{Comment: fmt.Sprintf("Unsupported PCI device %04x:%04x",
+ pciDev.PCIVenID, pciDev.PCIDevID)}
+ }
+ dev.Scan(ctx, pciDev)
+ }
+}
+
+func RegisterPCI(VenID uint16, DevID uint16, dev PCIDevice) {
+ vendevid := (uint32(DevID) << 16) | uint32(VenID)
+ supportedPCIDevices[vendevid] = dev
+}
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
new file mode 100644
index 0000000..5b1149c
--- /dev/null
+++ b/util/autoport/sandybridge.go
@@ -0,0 +1,142 @@
+package main
+
+type sandybridgemc struct {
+ variant string
+}
+
+func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
+ inteltool := ctx.InfoSource.GetInteltool()
+ pchLVDS := inteltool.IGD[0xe1180]
+ dualChannel := pchLVDS & (3 << 2) == (3 << 2)
+ pipe := (pchLVDS >> 30) & 1
+ data_m1 := inteltool.IGD[0x60030 + 0x1000 * pipe] & 0xffffff
+ data_n1 := inteltool.IGD[0x60034 + 0x1000 * pipe]
+ link_m1 := inteltool.IGD[0x60040 + 0x1000 * pipe]
+ link_n1 := inteltool.IGD[0x60044 + 0x1000 * pipe]
+ data_factor := float32(data_m1) / float32(data_n1)
+ link_factor := float32(link_m1) / float32(link_n1)
+ num_lanes := uint32((link_factor / data_factor) * 18.0 / 8.0 + 0.5)
+ fp0 := inteltool.IGD[0xc6040 + 8 * pipe]
+ dpll := inteltool.IGD[0xc6014 + 4 * pipe]
+ pixel_m2 := fp0 & 0xff
+ pixel_m1 := (fp0 >> 8) & 0xff + 2
+ pixel_p1 := uint32(1)
+ for i := dpll & 0x1ffff; i != 0 && i & 1 == 0; i >>= 1 {
+ pixel_p1++
+ }
+ pixel_n := ((fp0 >> 16) & 0xff) + 2
+ pixel_frequency := float32(120000 * (5 * pixel_m1 + pixel_m2)) / float32(pixel_n * pixel_p1 * 7.0)
+ if !dualChannel {
+ pixel_frequency /= 2
+ }
+ link_frequency := pixel_frequency / link_factor
+ DevTree = DevTreeNode{
+ Chip: "northbridge/intel/sandybridge",
+ MissingParent: "northbridge",
+ Registers: map[string]string{
+ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
+ "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
+ "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
+ "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
+ "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
+ "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
+ "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
+ "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
+ "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
+ "gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200] >> 12) & 1 != 0),
+ "gfx.lvds_dual_channel": FormatBool(dualChannel),
+ "gfx.lvds_num_lanes": FormatInt32(num_lanes),
+ "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
+ /* FIXME:XX hardcoded. */
+ "gfx.ndid": "3",
+ "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu/intel/socket_rPGA989",
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ },
+ },
+
+ {
+ Chip: "cpu/intel/model_206ax",
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "pstate_coord_type": "0xfe",
+ "c1_acpower": "1",
+ "c2_acpower": "3",
+ "c3_acpower": "5",
+ "c1_battery": "1",
+ "c2_battery": "3",
+ "c3_battery": "5",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0xacac,
+ Disabled: true,
+ },
+ },
+ },
+ },
+ },
+
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ },
+ },
+ },
+ }
+
+ PutPCIDev(addr, "Host bridge")
+
+ /* FIXME:XX Move part to northbridge? */
+ /* FIXME:XX some configs are unsupported. */
+ KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true
+ KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true
+ KconfigBool[i.variant+"BRIDGE_LVDS"] = true
+
+ KconfigBool["VGA"] = true
+ KconfigBool["INTEL_EDID"] = true
+ KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true
+ KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE_NATIVE"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ KconfigBool["HAVE_IFD_BIN"] = false
+ KconfigBool["HAVE_ME_BIN"] = false
+
+ KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000
+ KconfigInt["MAX_CPUS"] = 8
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "cpu/intel/model_206ax/acpi/cpu.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "northbridge/intel/sandybridge/acpi/sandybridge.asl",
+ })
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"})
+ RegisterPCI(0x8086, 0x0166, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+}
1
0
New patch to review for coreboot: df32f75 bd82x6x: Move calling of finalize() on resume to southbridge code
by Vladimir Serbinenko 25 May '15
by Vladimir Serbinenko 25 May '15
25 May '15
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10293
-gerrit
commit df32f759ac3c91337ba4cd3769ae834109ce52f0
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu May 21 10:32:59 2015 +0200
bd82x6x: Move calling of finalize() on resume to southbridge code
Change-Id: I6416cd5780fbda0b3c2e236ce98a9f9a508e70c6
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 6 ------
src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c | 6 ------
src/mainboard/google/butterfly/mainboard.c | 8 --------
src/mainboard/google/link/mainboard.c | 6 ------
src/mainboard/google/parrot/mainboard.c | 4 ----
src/mainboard/google/stout/mainboard.c | 3 ---
src/mainboard/intel/emeraldlake2/mainboard.c | 8 --------
src/mainboard/kontron/ktqm77/mainboard.c | 6 ------
src/mainboard/lenovo/t420s/mainboard.c | 6 ------
src/mainboard/lenovo/t430s/mainboard.c | 6 ------
src/mainboard/lenovo/t520/mainboard.c | 6 ------
src/mainboard/lenovo/t530/mainboard.c | 6 ------
src/mainboard/lenovo/x220/mainboard.c | 6 ------
src/mainboard/lenovo/x230/mainboard.c | 6 ------
src/mainboard/samsung/lumpy/mainboard.c | 3 ---
src/mainboard/samsung/stumpy/mainboard.c | 8 --------
src/southbridge/intel/bd82x6x/lpc.c | 9 +++++++++
17 files changed, 9 insertions(+), 94 deletions(-)
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
index 142907a..6828330 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
@@ -36,12 +36,6 @@
#include <device/pci.h>
#include <cbfs.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
index 142907a..6828330 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
@@ -36,12 +36,6 @@
#include <device/pci.h>
#include <cbfs.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index bd2fbd5..7850a68 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -186,14 +186,6 @@ static void program_keyboard_type(u32 search_address, u32 search_length)
ec_mem_write(EC_KBID_REG, kbd_type);
}
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
-
-
static void mainboard_init(device_t dev)
{
u32 search_address = 0x0;
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 01ac22c..fc95f59 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -54,12 +54,6 @@ void mainboard_post(u8 value)
*/
}
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
#if CONFIG_VGA_ROM_RUN
static int int15_handler(void)
{
diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c
index 998cb3c..3f29312 100644
--- a/src/mainboard/google/parrot/mainboard.c
+++ b/src/mainboard/google/parrot/mainboard.c
@@ -39,15 +39,11 @@
void mainboard_suspend_resume(void)
{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-
/* Enable ACPI mode before OS resume */
outb(0xe1, 0xb2);
}
-
static void mainboard_init(device_t dev)
{
/* Initialize the Embedded Controller */
diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c
index fcae6e1..0d3d8e0 100644
--- a/src/mainboard/google/stout/mainboard.c
+++ b/src/mainboard/google/stout/mainboard.c
@@ -39,9 +39,6 @@
void mainboard_suspend_resume(void)
{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-
/* Stout EC needs to be put back in ACPI mode */
ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER);
}
diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c
index 19158d6..2e1ed36 100644
--- a/src/mainboard/intel/emeraldlake2/mainboard.c
+++ b/src/mainboard/intel/emeraldlake2/mainboard.c
@@ -33,14 +33,6 @@
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
-
-
// mainboard_enable is executed as first thing after
// enumerate_buses().
diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c
index 3594749..9999e2e 100644
--- a/src/mainboard/kontron/ktqm77/mainboard.c
+++ b/src/mainboard/kontron/ktqm77/mainboard.c
@@ -35,12 +35,6 @@
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
#if CONFIG_VGA_ROM_RUN
static int int15_handler(void)
{
diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c
index e9a400b..afe14ab 100644
--- a/src/mainboard/lenovo/t420s/mainboard.c
+++ b/src/mainboard/lenovo/t420s/mainboard.c
@@ -33,12 +33,6 @@
#include <pc80/keyboard.h>
#include <ec/lenovo/h8/h8.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
/* init spi */
diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c
index 49e828e..f759499 100644
--- a/src/mainboard/lenovo/t430s/mainboard.c
+++ b/src/mainboard/lenovo/t430s/mainboard.c
@@ -33,12 +33,6 @@
#include <pc80/keyboard.h>
#include <ec/lenovo/h8/h8.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
/* init spi */
diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c
index 609d616..7034c8a 100644
--- a/src/mainboard/lenovo/t520/mainboard.c
+++ b/src/mainboard/lenovo/t520/mainboard.c
@@ -38,12 +38,6 @@
#include <pc80/keyboard.h>
#include <ec/lenovo/h8/h8.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c
index a81b5b2..9cc0baf 100644
--- a/src/mainboard/lenovo/t530/mainboard.c
+++ b/src/mainboard/lenovo/t530/mainboard.c
@@ -38,12 +38,6 @@
#include <pc80/keyboard.h>
#include <ec/lenovo/h8/h8.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c
index 570e74a..c22744b 100644
--- a/src/mainboard/lenovo/x220/mainboard.c
+++ b/src/mainboard/lenovo/x220/mainboard.c
@@ -33,12 +33,6 @@
#include <pc80/keyboard.h>
#include <ec/lenovo/h8/h8.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c
index 8ea18de..dfbc244 100644
--- a/src/mainboard/lenovo/x230/mainboard.c
+++ b/src/mainboard/lenovo/x230/mainboard.c
@@ -34,12 +34,6 @@
#include <pc80/keyboard.h>
#include <ec/lenovo/h8/h8.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c
index e439d73..f34f887 100644
--- a/src/mainboard/samsung/lumpy/mainboard.c
+++ b/src/mainboard/samsung/lumpy/mainboard.c
@@ -38,9 +38,6 @@
void mainboard_suspend_resume(void)
{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-
/* Enable EC ACPI mode for the OS before resume */
send_ec_command(EC_SMI_DISABLE);
send_ec_command(EC_ACPI_ENABLE);
diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c
index 19158d6..2e1ed36 100644
--- a/src/mainboard/samsung/stumpy/mainboard.c
+++ b/src/mainboard/samsung/stumpy/mainboard.c
@@ -33,14 +33,6 @@
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
-void mainboard_suspend_resume(void)
-{
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
-}
-
-
-
// mainboard_enable is executed as first thing after
// enumerate_buses().
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 0ecd389..964b118 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -842,6 +842,14 @@ static void southbridge_fill_ssdt(void)
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
}
+static void lpc_final(struct device *dev)
+{
+ if (CONFIG_HAVE_SMI_HANDLER && acpi_is_wakeup_s3()) {
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+ }
+}
+
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
@@ -854,6 +862,7 @@ static struct device_operations device_ops = {
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
.init = lpc_init,
+ .final = lpc_final,
.enable = pch_lpc_enable,
.scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
1
0
25 May '15
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7472
-gerrit
commit d090cdfc4d50d464e8305fd39f5a3040bce21005
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Oct 31 09:16:31 2014 +0100
igd.asl rewrite
Old igd.asl had inconsistent addresses (between _DOD and actual device)
and ghost devices. Any of those is enough to make brightness on windows
fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous
copying of the same thing 6 times per chipset. Leave only hooking up and
chipset-specific part in chipset directory. Move NVS handling and ACPI-spec
parts to a common file.
Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/drivers/intel/gma/Kconfig | 4 +
src/drivers/intel/gma/Makefile.inc | 1 +
src/drivers/intel/gma/acpi.c | 135 +++++++
src/drivers/intel/gma/i915.h | 7 +
src/drivers/intel/gma/igd.asl | 113 ++++++
src/mainboard/apple/macbook21/acpi/video.asl | 50 ---
src/mainboard/apple/macbook21/acpi_tables.c | 7 -
src/mainboard/apple/macbook21/cmos.default | 1 -
src/mainboard/apple/macbook21/cmos.layout | 1 -
src/mainboard/apple/macbook21/devicetree.cb | 5 +-
src/mainboard/emulation/qemu-q35/mainboard.c | 14 +
src/mainboard/getac/p470/acpi/ec.asl | 2 +-
src/mainboard/getac/p470/acpi/video.asl | 43 ---
src/mainboard/getac/p470/acpi_tables.c | 8 -
src/mainboard/getac/p470/devicetree.cb | 3 +
src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 8 -
src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 4 +
.../gigabyte/ga-b75m-d3v/acpi/mainboard.asl | 47 ---
src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c | 8 -
src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb | 3 +
src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl | 1 -
src/mainboard/google/bolt/acpi_tables.c | 7 -
src/mainboard/google/bolt/devicetree.cb | 3 +
src/mainboard/google/butterfly/acpi_tables.c | 7 -
src/mainboard/google/butterfly/devicetree.cb | 3 +
src/mainboard/google/falco/acpi_tables.c | 7 -
src/mainboard/google/falco/devicetree.cb | 3 +
src/mainboard/google/link/acpi_tables.c | 8 -
src/mainboard/google/link/devicetree.cb | 3 +
src/mainboard/google/panther/acpi_tables.c | 7 -
src/mainboard/google/panther/devicetree.cb | 3 +
src/mainboard/google/parrot/acpi_tables.c | 7 -
src/mainboard/google/parrot/devicetree.cb | 3 +
src/mainboard/google/peppy/acpi_tables.c | 7 -
src/mainboard/google/peppy/devicetree.cb | 3 +
src/mainboard/google/slippy/acpi_tables.c | 7 -
src/mainboard/google/slippy/devicetree.cb | 3 +
src/mainboard/google/stout/acpi_tables.c | 7 -
src/mainboard/google/stout/devicetree.cb | 3 +
src/mainboard/ibase/mb899/acpi/video.asl | 42 --
src/mainboard/ibase/mb899/acpi_tables.c | 7 -
src/mainboard/ibase/mb899/devicetree.cb | 4 +
src/mainboard/intel/baskingridge/acpi_tables.c | 7 -
src/mainboard/intel/baskingridge/devicetree.cb | 3 +
src/mainboard/intel/cougar_canyon2/acpi_tables.c | 9 -
src/mainboard/intel/cougar_canyon2/devicetree.cb | 3 +
src/mainboard/intel/d945gclf/acpi/video.asl | 42 --
src/mainboard/intel/emeraldlake2/acpi_tables.c | 7 -
src/mainboard/intel/emeraldlake2/devicetree.cb | 3 +
src/mainboard/iwave/iWRainbowG6/acpi/video.asl | 43 ---
src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 8 -
src/mainboard/iwave/iWRainbowG6/devicetree.cb | 3 +
src/mainboard/kontron/986lcd-m/acpi/video.asl | 42 --
src/mainboard/kontron/986lcd-m/acpi_tables.c | 7 -
src/mainboard/kontron/986lcd-m/devicetree.cb | 3 +
src/mainboard/kontron/ktqm77/acpi_tables.c | 8 -
src/mainboard/kontron/ktqm77/devicetree.cb | 3 +
src/mainboard/lenovo/t420s/acpi_tables.c | 8 -
src/mainboard/lenovo/t420s/devicetree.cb | 2 +
src/mainboard/lenovo/t420s/dsdt.asl | 4 +-
src/mainboard/lenovo/t430s/acpi_tables.c | 8 -
src/mainboard/lenovo/t430s/devicetree.cb | 2 +
src/mainboard/lenovo/t430s/dsdt.asl | 4 +-
src/mainboard/lenovo/t520/acpi_tables.c | 7 -
src/mainboard/lenovo/t520/devicetree.cb | 3 +
src/mainboard/lenovo/t520/dsdt.asl | 5 +-
src/mainboard/lenovo/t530/acpi_tables.c | 7 -
src/mainboard/lenovo/t530/devicetree.cb | 3 +
src/mainboard/lenovo/t530/dsdt.asl | 5 +-
src/mainboard/lenovo/t60/acpi/video.asl | 24 +-
src/mainboard/lenovo/t60/acpi_tables.c | 7 -
src/mainboard/lenovo/t60/devicetree.cb | 3 +
src/mainboard/lenovo/t60/dsdt.asl | 10 +-
src/mainboard/lenovo/x200/acpi_tables.c | 7 -
src/mainboard/lenovo/x200/devicetree.cb | 3 +
src/mainboard/lenovo/x200/dsdt.asl | 4 +-
src/mainboard/lenovo/x201/acpi_tables.c | 7 -
src/mainboard/lenovo/x201/devicetree.cb | 3 +
src/mainboard/lenovo/x201/dsdt.asl | 5 +-
src/mainboard/lenovo/x220/acpi_tables.c | 6 -
src/mainboard/lenovo/x220/devicetree.cb | 3 +
src/mainboard/lenovo/x220/dsdt.asl | 5 +-
src/mainboard/lenovo/x230/acpi_tables.c | 6 -
src/mainboard/lenovo/x230/devicetree.cb | 3 +
src/mainboard/lenovo/x230/dsdt.asl | 5 +-
src/mainboard/lenovo/x60/acpi/video.asl | 54 ---
src/mainboard/lenovo/x60/acpi_tables.c | 7 -
src/mainboard/lenovo/x60/devicetree.cb | 3 +
src/mainboard/lenovo/x60/dsdt.asl | 6 +-
src/mainboard/packardbell/ms2290/acpi/ec.asl | 4 +-
src/mainboard/packardbell/ms2290/acpi_tables.c | 7 -
src/mainboard/packardbell/ms2290/devicetree.cb | 3 +
src/mainboard/packardbell/ms2290/dsdt.asl | 2 -
src/mainboard/roda/rk886ex/acpi/ec.asl | 2 +-
src/mainboard/roda/rk886ex/acpi/video.asl | 43 ---
src/mainboard/roda/rk886ex/acpi_tables.c | 7 -
src/mainboard/roda/rk886ex/devicetree.cb | 3 +
src/mainboard/roda/rk9/acpi_tables.c | 7 -
src/mainboard/roda/rk9/devicetree.cb | 3 +
src/mainboard/samsung/lumpy/acpi_tables.c | 7 -
src/mainboard/samsung/lumpy/devicetree.cb | 3 +
src/mainboard/samsung/stumpy/acpi_tables.c | 7 -
src/mainboard/samsung/stumpy/devicetree.cb | 3 +
src/northbridge/intel/fsp_sandybridge/Kconfig | 2 +
src/northbridge/intel/fsp_sandybridge/acpi/igd.asl | 326 ++--------------
src/northbridge/intel/fsp_sandybridge/chip.h | 4 +
src/northbridge/intel/fsp_sandybridge/gma.c | 22 ++
src/northbridge/intel/gm45/Kconfig | 1 +
src/northbridge/intel/gm45/acpi/igd.asl | 423 ++-------------------
src/northbridge/intel/gm45/gma.c | 22 ++
src/northbridge/intel/haswell/Kconfig | 1 +
src/northbridge/intel/haswell/acpi/igd.asl | 326 ++--------------
src/northbridge/intel/haswell/chip.h | 4 +
src/northbridge/intel/haswell/gma.c | 22 ++
src/northbridge/intel/i945/Kconfig | 1 +
src/northbridge/intel/i945/acpi/i945.asl | 6 -
src/northbridge/intel/i945/acpi/igd.asl | 329 ++--------------
src/northbridge/intel/i945/chip.h | 3 +
src/northbridge/intel/i945/gma.c | 22 ++
src/northbridge/intel/nehalem/Kconfig | 1 +
src/northbridge/intel/nehalem/acpi/igd.asl | 415 ++------------------
src/northbridge/intel/nehalem/gma.c | 22 ++
src/northbridge/intel/sandybridge/Kconfig | 4 +
src/northbridge/intel/sandybridge/acpi/igd.asl | 411 ++------------------
src/northbridge/intel/sandybridge/gma.c | 22 ++
src/northbridge/intel/sch/Kconfig | 1 +
src/northbridge/intel/sch/acpi/igd.asl | 325 ++--------------
src/northbridge/intel/sch/acpi/sch.asl | 6 -
src/northbridge/intel/sch/chip.h | 30 ++
src/northbridge/intel/sch/gma.c | 24 ++
src/southbridge/intel/bd82x6x/lpc.c | 4 +
src/southbridge/intel/fsp_bd82x6x/lpc.c | 6 +
src/southbridge/intel/i82801gx/lpc.c | 7 +
src/southbridge/intel/i82801ix/lpc.c | 6 +
src/southbridge/intel/ibexpeak/lpc.c | 3 +
src/southbridge/intel/lynxpoint/lpc.c | 6 +
src/southbridge/intel/sch/lpc.c | 6 +
137 files changed, 917 insertions(+), 3026 deletions(-)
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig
index f4c7e45..f726e6f 100644
--- a/src/drivers/intel/gma/Kconfig
+++ b/src/drivers/intel/gma/Kconfig
@@ -36,3 +36,7 @@ config INTEL_EDID
config INTEL_INT15
bool
default n
+
+config INTEL_GMA_ACPI
+ bool
+ default n
diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc
index 2459997..6bd9b71 100644
--- a/src/drivers/intel/gma/Makefile.inc
+++ b/src/drivers/intel/gma/Makefile.inc
@@ -23,3 +23,4 @@ ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c
ifeq ($(CONFIG_VGA_ROM_RUN),y)
ramstage-$(CONFIG_INTEL_INT15) += int15.c
endif
+ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c
\ No newline at end of file
diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c
new file mode 100644
index 0000000..c3a9b8a
--- /dev/null
+++ b/src/drivers/intel/gma/acpi.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <string.h>
+#include "i915.h"
+
+void
+drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf)
+{
+ size_t i;
+ const char *names[] = { "UNK", "VGA", "TV", "DVI", "LCD" };
+ int counters[ARRAY_SIZE(names)];
+
+ memset(counters, 0, sizeof(counters));
+
+ acpigen_write_scope("\\_SB.PCI0.GFX0");
+
+ /*
+ Method (_DOD, 0)
+ {
+ Return (Package() {
+ 0x5a5a5a5a,
+ 0x5a5a5a5a,
+ 0x5a5a5a5a
+ })
+ }
+ */
+ acpigen_write_method("_DOD", 0);
+ acpigen_emit_byte(0xa4); /* ReturnOp. */
+ acpigen_write_package(conf->ndid);
+
+ for (i = 0; i < conf->ndid; i++) {
+ acpigen_write_dword (conf->did[i] | 0x80010000);
+ }
+ acpigen_pop_len(); /* End Package. */
+ acpigen_pop_len(); /* End Method. */
+
+ for (i = 0; i < conf->ndid; i++) {
+ char name[10];
+ char *ptr;
+ int kind;
+ kind = (conf->did[i] >> 8) & 0xf;
+ if (kind >= ARRAY_SIZE(names)) {
+ kind = 0;
+ }
+ strcpy(name, names[kind]);
+ for (ptr = name; *ptr; ptr++);
+ *ptr++ = counters[kind] + '0';
+ *ptr++ = '\0';
+ counters[kind]++;
+ acpigen_write_device(name);
+ /* Name (_ADR, 0x0410) */
+ acpigen_write_name_dword("_ADR", conf->did[i] & 0xffff);
+
+ /* ACPI brightness for LCD. */
+ if (kind == 4) {
+ /*
+ Method (_BCL, 0, NotSerialized)
+ {
+ Return (^^XBCL())
+ }
+ */
+ acpigen_write_method("_BCL", 0);
+ acpigen_emit_byte(0xa4); /* ReturnOp. */
+ acpigen_emit_namestring("^^XBCL");
+ acpigen_pop_len();
+
+ /*
+ Method (_BCM, 1, NotSerialized)
+ {
+ ^^XBCM(Arg0)
+ }
+ */
+ acpigen_write_method("_BCM", 1);
+ acpigen_emit_namestring("^^XBCM");
+ acpigen_emit_byte(0x68); /* Arg0Op. */
+ acpigen_pop_len();
+
+ /*
+ Method (_BQC, 0, NotSerialized)
+ {
+ Return (^^XBQC())
+ }
+ */
+ acpigen_write_method("_BQC", 0);
+ acpigen_emit_byte(0xa4); /* ReturnOp. */
+ acpigen_emit_namestring("^^XBQC");
+ acpigen_pop_len();
+ }
+
+ /*
+ Method(_DCS, 0)
+ {
+ Return (^^XDCS(<device number>))
+ }
+ */
+ acpigen_write_method("_DCS", 0);
+ acpigen_emit_byte(0xa4); /* ReturnOp. */
+ acpigen_emit_namestring("^^XDCS");
+ acpigen_write_byte(i);
+ acpigen_pop_len();
+
+ /*
+ Method(_DGS, 0)
+ {
+ Return (^^XDGS(<device number>))
+ }
+ */
+ acpigen_write_method("_DGS", 0);
+ acpigen_emit_byte(0xa4); /* ReturnOp. */
+ acpigen_emit_namestring("^^XDGS");
+ acpigen_write_byte(i);
+ acpigen_pop_len();
+
+ /*
+ Method(_DSS, 1)
+ {
+ ^^XDSS(0x5a, Arg0)
+ }
+ */
+ acpigen_write_method("_DSS", 0);
+ acpigen_emit_namestring("^^XDSS");
+ acpigen_write_byte(i);
+ acpigen_emit_byte(0x68); /* Arg0Op. */
+ acpigen_pop_len();
+
+ acpigen_pop_len();
+ }
+
+ acpigen_pop_len();
+}
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index ef9e68e..37e2e49 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -292,8 +292,15 @@ struct i915_gpu_controller_info
int link_frequency_270_mhz;
int lvds_num_lanes;
u32 backlight;
+ int ndid;
+ u32 did[5];
};
+void
+drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf);
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void);
+
int i915lightup(unsigned int physbase, unsigned int mmio,
unsigned int gfx, unsigned int init_fb);
int panel_lightup(struct intel_dp *dp, unsigned int init_fb);
diff --git a/src/drivers/intel/gma/igd.asl b/src/drivers/intel/gma/igd.asl
new file mode 100644
index 0000000..31e8fec
--- /dev/null
+++ b/src/drivers/intel/gma/igd.asl
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+ External(LCD0, DeviceObj)
+
+ Name (BRCT, 0)
+
+ Method(BRID, 1, NotSerialized)
+ {
+ Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
+ If (LEqual (Local0, Ones))
+ {
+ Return (Subtract(SizeOf(BRIG), One))
+ }
+ Return (Local0)
+ }
+
+ Method (XBCL, 0, NotSerialized)
+ {
+ Store (1, BRCT)
+ Return (BRIG)
+ }
+
+ /* Display Output Switching */
+ Method (_DOS, 1)
+ {
+ /* Windows 2000 and Windows XP call _DOS to enable/disable
+ * Display Output Switching during init and while a switch
+ * is already active
+ */
+ Store (And(Arg0, 7), DSEN)
+ }
+
+ /* Using Notify is the right way. But Windows doesn't handle
+ it well. So use both method in a way to avoid double action.
+ */
+ Method (DECB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x87)
+ } Else {
+ Store (BRID (XBQC ()), Local0)
+ If (LNotEqual (Local0, 2))
+ {
+ Decrement (Local0)
+ }
+ XBCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+
+ Method (INCB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x86)
+ } Else {
+ Store (BRID (XBQC ()), Local0)
+ If (LNotEqual (Local0, Subtract(SizeOf(BRIG), One)))
+ {
+ Increment (Local0)
+ }
+ XBCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+
+ /* Device Current Status */
+ Method(XDCS, 1)
+ {
+ TRAP(1)
+ If (And(CSTE, ShiftLeft (1, Arg0))) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(XDGS, 1)
+ {
+ If (And(NSTE, ShiftLeft (1, Arg0))) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(XDSS, 2)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
diff --git a/src/mainboard/apple/macbook21/acpi/video.asl b/src/mainboard/apple/macbook21/acpi/video.asl
deleted file mode 100644
index 9b8750b..0000000
--- a/src/mainboard/apple/macbook21/acpi/video.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Device (DSPC)
-{
- Name (_ADR, 0x00020001)
- OperationRegion (DSPC, PCI_Config, 0x00, 0x100)
- Field (DSPC, ByteAcc, NoLock, Preserve)
- {
- Offset (0xf4),
- BRTC, 8
- }
-
- Method(BRTD, 0, NotSerialized)
- {
- Store(BRTC, Local0)
- if (LGreater (Local0, 15))
- {
- Subtract(Local0, 16, Local0)
- Store(Local0, BRTC)
- }
- }
-
- Method(BRTU, 0, NotSerialized)
- {
- Store (BRTC, Local0)
- if (LLess(Local0, 0xff))
- {
- Add (Local0, 16, Local0)
- Store(Local0, BRTC)
- }
- }
-}
diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c
index 64b1fc6..4e4cf1e 100644
--- a/src/mainboard/apple/macbook21/acpi_tables.c
+++ b/src/mainboard/apple/macbook21/acpi_tables.c
@@ -36,13 +36,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
index 0185e94..e0b992c 100644
--- a/src/mainboard/apple/macbook21/cmos.default
+++ b/src/mainboard/apple/macbook21/cmos.default
@@ -9,7 +9,6 @@ boot_default=0x40
cmos_defaults_loaded=Yes
lpt=Enable
volume=0x3
-tft_brightness=0xff
first_battery=Primary
bluetooth=Enable
wlan=Enable
diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout
index 3211f5c..5bb8a378 100644
--- a/src/mainboard/apple/macbook21/cmos.layout
+++ b/src/mainboard/apple/macbook21/cmos.layout
@@ -85,7 +85,6 @@ entries
1052 4 r 0 C1DRT1
1064 8 h 0 volume
-1072 8 h 0 tft_brightness
1080 1 e 9 first_battery
1081 1 e 1 bluetooth
1082 1 e 1 wwan
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index e70ca05..0430217 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -20,11 +20,14 @@
##
chip northbridge/intel/i945
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gpu_hotplug" = "0x00000220"
register "gpu_lvds_use_spread_spectrum_clock" = "1"
register "gpu_lvds_is_dual_channel" = "0"
- register "gpu_backlight" = "0x1280128"
+ register "gpu_backlight" = "0x1290128"
device cpu_cluster 0 on
chip cpu/intel/socket_mFCPGA478
diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c
index 30f9b3c..a7256a5 100644
--- a/src/mainboard/emulation/qemu-q35/mainboard.c
+++ b/src/mainboard/emulation/qemu-q35/mainboard.c
@@ -25,6 +25,7 @@
#include <pc80/keyboard.h>
#include <arch/io.h>
#include <console/console.h>
+#include <drivers/intel/gma/i915.h>
#define Q35_PAM0 0x90
@@ -33,6 +34,19 @@ static const unsigned char qemu_q35_irqs[] = {
10, 10, 11, 11,
};
+struct i915_gpu_controller_info gfx_controller_info = {
+ .ndid = 3,
+ .did = {
+ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005
+ }
+};
+
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ return &gfx_controller_info;
+}
+
static void qemu_nb_init(device_t dev)
{
/* Map memory at 0xc0000 - 0xfffff */
diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl
index 67a028e..e9d46e4 100644
--- a/src/mainboard/getac/p470/acpi/ec.asl
+++ b/src/mainboard/getac/p470/acpi/ec.asl
@@ -192,7 +192,7 @@ Device(EC0)
{
Store(0x3f, HOTK)
If(IGDS) {
- HKDS(10)
+ Notify (\_SB.PCI0.GFX0, 0x82)
} Else {
TRAP(0xE1)
}
diff --git a/src/mainboard/getac/p470/acpi/video.asl b/src/mainboard/getac/p470/acpi/video.asl
deleted file mode 100644
index 1c9ccfd..0000000
--- a/src/mainboard/getac/p470/acpi/video.asl
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
- // TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
- // TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
- // TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
- // TODO (no displays defined yet)
-}
diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index bc805dc..b6cd654 100644
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -37,14 +37,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* Enable COM port(s) */
gnvs->cmap = 0x01;
gnvs->cmbp = 0x00;
-
- /* IGD Displays */
- gnvs->ndid = 2;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000410;
- gnvs->did[2] = 0x80000320;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index f32dead..cbf7651 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -19,6 +19,9 @@
##
chip northbridge/intel/i945
+ # IGD Displays
+ register "gfx.ndid" = "2"
+ register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on
chip cpu/intel/socket_mFCPGA478
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
index 23a8a00..70eeeb2 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
@@ -56,14 +56,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
index 3c7641a..fa949e9 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
@@ -1,4 +1,8 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
device cpu_cluster 0 on
chip cpu/intel/socket_LGA1155
device lapic 0 on end
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
deleted file mode 100644
index 507dd7d..0000000
--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Method (BRTN, 1, Serialized)
-{
- If (LEqual (And (DID1, 0x0F00), 0x0400))
- {
- Notify (\_SB.PCI0.GFX0.DD01, Arg0)
- }
-
- If (LEqual (And (DID2, 0x0F00), 0x0400))
- {
- Notify (\_SB.PCI0.GFX0.DD02, Arg0)
- }
-
- If (LEqual (And (DID3, 0x0F00), 0x0400))
- {
- Notify (\_SB.PCI0.GFX0.DD03, Arg0)
- }
-
- If (LEqual (And (DID4, 0x0F00), 0x0400))
- {
- Notify (\_SB.PCI0.GFX0.DD04, Arg0)
- }
-
- If (LEqual (And (DID5, 0x0F00), 0x0400))
- {
- Notify (\_SB.PCI0.GFX0.DD05, Arg0)
- }
-}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
index 23a8a00..70eeeb2 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
@@ -56,14 +56,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
index 1c08359..369bc6f 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
device cpu_cluster 0 on
chip cpu/intel/socket_LGA1155
device lapic 0 on end
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
index 1ce6dd4..84a889a 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
@@ -9,7 +9,6 @@ DefinitionBlock(
{
// Some generic macros
#include "acpi/platform.asl"
- #include "acpi/mainboard.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
diff --git a/src/mainboard/google/bolt/acpi_tables.c b/src/mainboard/google/bolt/acpi_tables.c
index dba5348..42dcb07 100644
--- a/src/mainboard/google/bolt/acpi_tables.c
+++ b/src/mainboard/google/bolt/acpi_tables.c
@@ -66,13 +66,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
diff --git a/src/mainboard/google/bolt/devicetree.cb b/src/mainboard/google/bolt/devicetree.cb
index 1d1eab5..1acd781 100644
--- a/src/mainboard/google/bolt/devicetree.cb
+++ b/src/mainboard/google/bolt/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/haswell
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
index f5e87d1..bf0c0dc 100644
--- a/src/mainboard/google/butterfly/acpi_tables.c
+++ b/src/mainboard/google/butterfly/acpi_tables.c
@@ -54,13 +54,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
// TODO: MLR
// The firmware read/write status is a "virtual" switch and
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 90925b9..47d6a10 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/google/falco/acpi_tables.c b/src/mainboard/google/falco/acpi_tables.c
index 238b48d..8a6ef01 100644
--- a/src/mainboard/google/falco/acpi_tables.c
+++ b/src/mainboard/google/falco/acpi_tables.c
@@ -60,13 +60,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb
index 7a8e757..8cdb032 100644
--- a/src/mainboard/google/falco/devicetree.cb
+++ b/src/mainboard/google/falco/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/haswell
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index 36edf5b..3f5adea 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -64,14 +64,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 1;
- gnvs->did[0] = 0x80000000;
- gnvs->did[1] = 0x80000000;
- gnvs->did[2] = 0x00000000;
- gnvs->did[3] = 0x00000000;
- gnvs->did[4] = 0x00000000;
-
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 5333dfc..382a8c4 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "1"
+ register "gfx.did" = "{ 0x80000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/google/panther/acpi_tables.c b/src/mainboard/google/panther/acpi_tables.c
index 2876e02..c4efd7e 100644
--- a/src/mainboard/google/panther/acpi_tables.c
+++ b/src/mainboard/google/panther/acpi_tables.c
@@ -77,13 +77,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
// SuperIO is always RO
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index 2032fd4..af6043f 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/haswell
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Disable eDP Hotplug
register "gpu_dp_d_hotplug" = "0x00"
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index e2c2d4a..14d5420 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -55,13 +55,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = parrot_ec_running_ro() ?
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index a4baafd..034309f 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort B Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
diff --git a/src/mainboard/google/peppy/acpi_tables.c b/src/mainboard/google/peppy/acpi_tables.c
index 82c4666..47288aa 100644
--- a/src/mainboard/google/peppy/acpi_tables.c
+++ b/src/mainboard/google/peppy/acpi_tables.c
@@ -69,13 +69,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb
index 894d3ef..505b39e 100644
--- a/src/mainboard/google/peppy/devicetree.cb
+++ b/src/mainboard/google/peppy/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/haswell
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c
index dba5348..42dcb07 100644
--- a/src/mainboard/google/slippy/acpi_tables.c
+++ b/src/mainboard/google/slippy/acpi_tables.c
@@ -66,13 +66,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index f50882c..3d4c8c5 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/haswell
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index 89f249f..4fa736f 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -58,13 +58,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
gnvs->chromeos.vbt2 = get_recovery_mode_switch() ?
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 4ac89f6..cd33cd7 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/ibase/mb899/acpi/video.asl b/src/mainboard/ibase/mb899/acpi/video.asl
deleted file mode 100644
index e4f764c..0000000
--- a/src/mainboard/ibase/mb899/acpi/video.asl
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
- // TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
- // TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
- // TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
- // TODO (no displays defined yet)
-}
diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c
index 075aeec..5972382 100644
--- a/src/mainboard/ibase/mb899/acpi_tables.c
+++ b/src/mainboard/ibase/mb899/acpi_tables.c
@@ -36,13 +36,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index a26d7c2..77ceadd 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -1,4 +1,8 @@
chip northbridge/intel/i945
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
device cpu_cluster 0 on
chip cpu/intel/socket_mFCPGA478
device lapic 0 on end
diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c
index 5f82911..2f5e0cd 100644
--- a/src/mainboard/intel/baskingridge/acpi_tables.c
+++ b/src/mainboard/intel/baskingridge/acpi_tables.c
@@ -79,13 +79,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
#if CONFIG_CHROMEOS
/* Emerald Lake has no EC (?) */
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb
index cd341d1..a9cfb49 100644
--- a/src/mainboard/intel/baskingridge/devicetree.cb
+++ b/src/mainboard/intel/baskingridge/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/haswell
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort 1 Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/intel/cougar_canyon2/acpi_tables.c b/src/mainboard/intel/cougar_canyon2/acpi_tables.c
index f9c1e09..fce84fe 100644
--- a/src/mainboard/intel/cougar_canyon2/acpi_tables.c
+++ b/src/mainboard/intel/cougar_canyon2/acpi_tables.c
@@ -62,16 +62,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 1;
gnvs->s5u1 = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-
acpi_update_thermal_table(gnvs);
-
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb
index c386853..d7c6aab 100644
--- a/src/mainboard/intel/cougar_canyon2/devicetree.cb
+++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/fsp_sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort 1 Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/intel/d945gclf/acpi/video.asl b/src/mainboard/intel/d945gclf/acpi/video.asl
deleted file mode 100644
index 83bbabd..0000000
--- a/src/mainboard/intel/d945gclf/acpi/video.asl
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
- // TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
- // TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
- // TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
- // TODO (no displays defined yet)
-}
diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c
index bb6218a..1d7bcb0 100644
--- a/src/mainboard/intel/emeraldlake2/acpi_tables.c
+++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c
@@ -78,13 +78,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 1;
gnvs->s5u1 = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
acpi_update_thermal_table(gnvs);
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index e5a8ea0..0b3e788 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort 1 Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/video.asl b/src/mainboard/iwave/iWRainbowG6/acpi/video.asl
deleted file mode 100644
index 1c9ccfd..0000000
--- a/src/mainboard/iwave/iWRainbowG6/acpi/video.asl
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
- // TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
- // TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
- // TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
- // TODO (no displays defined yet)
-}
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
index 63d6c1e..ef7ad44 100644
--- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
+++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
@@ -40,14 +40,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs)
/* Enable both COM ports. */
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
-
- /* IGD Displays. */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb
index 84cfc4b..29e9e5e 100644
--- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb
+++ b/src/mainboard/iwave/iWRainbowG6/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sch
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on
chip cpu/intel/socket_441
diff --git a/src/mainboard/kontron/986lcd-m/acpi/video.asl b/src/mainboard/kontron/986lcd-m/acpi/video.asl
deleted file mode 100644
index e4f764c..0000000
--- a/src/mainboard/kontron/986lcd-m/acpi/video.asl
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
- // TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
- // TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
- // TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
- // TODO (no displays defined yet)
-}
diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c
index 075aeec..5972382 100644
--- a/src/mainboard/kontron/986lcd-m/acpi_tables.c
+++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c
@@ -36,13 +36,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index 6a5b221..b9ddf75 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/i945
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on
chip cpu/intel/socket_mFCPGA478
diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c
index 32e539f..54ff5d4 100644
--- a/src/mainboard/kontron/ktqm77/acpi_tables.c
+++ b/src/mainboard/kontron/ktqm77/acpi_tables.c
@@ -52,14 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 0;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-
acpi_update_thermal_table(gnvs);
}
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index 855fd5c..24306ef 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c
index 3133f9d..bcedb02 100644
--- a/src/mainboard/lenovo/t420s/acpi_tables.c
+++ b/src/mainboard/lenovo/t420s/acpi_tables.c
@@ -51,14 +51,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 7fd6a53..e43ac48 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -1,4 +1,6 @@
chip northbridge/intel/sandybridge
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl
index 94da7ba..820917e 100644
--- a/src/mainboard/lenovo/t420s/dsdt.asl
+++ b/src/mainboard/lenovo/t420s/dsdt.asl
@@ -20,8 +20,8 @@
*/
#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
#define HAVE_LCD_SCREEN 1
diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c
index 59fc7a6..041e4e3 100644
--- a/src/mainboard/lenovo/t430s/acpi_tables.c
+++ b/src/mainboard/lenovo/t430s/acpi_tables.c
@@ -37,14 +37,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index af3de6c..23bce4e 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -1,4 +1,6 @@
chip northbridge/intel/sandybridge
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl
index 94da7ba..820917e 100644
--- a/src/mainboard/lenovo/t430s/dsdt.asl
+++ b/src/mainboard/lenovo/t430s/dsdt.asl
@@ -20,8 +20,8 @@
*/
#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
#define HAVE_LCD_SCREEN 1
diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c
index abb6b31..bb0f1a4 100644
--- a/src/mainboard/lenovo/t520/acpi_tables.c
+++ b/src/mainboard/lenovo/t520/acpi_tables.c
@@ -51,13 +51,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index bf575d8..3688145 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl
index 94da7ba..02fdacf 100644
--- a/src/mainboard/lenovo/t520/dsdt.asl
+++ b/src/mainboard/lenovo/t520/dsdt.asl
@@ -20,11 +20,10 @@
*/
#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
-#define HAVE_LCD_SCREEN 1
DefinitionBlock(
"dsdt.aml",
diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c
index abb6b31..bb0f1a4 100644
--- a/src/mainboard/lenovo/t530/acpi_tables.c
+++ b/src/mainboard/lenovo/t530/acpi_tables.c
@@ -51,13 +51,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index d59524b..d4c5837 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl
index 94da7ba..02fdacf 100644
--- a/src/mainboard/lenovo/t530/dsdt.asl
+++ b/src/mainboard/lenovo/t530/dsdt.asl
@@ -20,11 +20,10 @@
*/
#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
-#define HAVE_LCD_SCREEN 1
DefinitionBlock(
"dsdt.aml",
diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl
index 1a7a596..31d5b04 100644
--- a/src/mainboard/lenovo/t60/acpi/video.asl
+++ b/src/mainboard/lenovo/t60/acpi/video.asl
@@ -20,35 +20,17 @@
#include "smi.h"
-Device (DSPC)
+Scope (\)
{
- Name (_ADR, 0x00020001)
- OperationRegion (DSPC, PCI_Config, 0x00, 0x100)
- Field (DSPC, ByteAcc, NoLock, Preserve)
- {
- Offset (0xf4),
- BRTC, 8
- }
-
Method(BRTD, 0, NotSerialized)
{
Trap(SMI_BRIGHTNESS_DOWN)
- Store(BRTC, Local0)
- if (LGreater (Local0, 15))
- {
- Subtract(Local0, 16, Local0)
- Store(Local0, BRTC)
- }
+ \_SB.PCI0.GFX0.DECB()
}
Method(BRTU, 0, NotSerialized)
{
Trap(SMI_BRIGHTNESS_UP)
- Store (BRTC, Local0)
- if (LLess(Local0, 0xff))
- {
- Add (Local0, 16, Local0)
- Store(Local0, BRTC)
- }
+ \_SB.PCI0.GFX0.INCB()
}
}
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c
index 64b1fc6..4e4cf1e 100644
--- a/src/mainboard/lenovo/t60/acpi_tables.c
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -36,13 +36,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 40ce3d8..719fa9a 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -20,6 +20,9 @@
##
chip northbridge/intel/i945
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on
chip cpu/intel/socket_mFCPGA478
diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl
index 92aac6c..b746b69 100644
--- a/src/mainboard/lenovo/t60/dsdt.asl
+++ b/src/mainboard/lenovo/t60/dsdt.asl
@@ -19,8 +19,8 @@
*/
#define THINKPAD_EC_GPE 28
-#define BRIGHTNESS_UP \DSPC.BRTU
-#define BRIGHTNESS_DOWN \DSPC.BRTD
+#define BRIGHTNESS_UP \BRTU
+#define BRIGHTNESS_DOWN \BRTD
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
DefinitionBlock(
@@ -45,6 +45,12 @@ DefinitionBlock(
// mainboard specific devices
#include "acpi/mainboard.asl"
+ Scope (\)
+ {
+ // backlight control, display switching, lid
+ #include "acpi/video.asl"
+ }
+
#include <cpu/intel/model_6dx/acpi/cpu.asl>
Scope (\_SB) {
diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c
index b699740..fa69e7a 100644
--- a/src/mainboard/lenovo/x200/acpi_tables.c
+++ b/src/mainboard/lenovo/x200/acpi_tables.c
@@ -40,13 +40,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
- gnvs->ndid = 0; /* Will use default of 0x00000400. */
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 09bc08f..cb4a021 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/gm45
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "0"
diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl
index 4320192..5545c94 100644
--- a/src/mainboard/lenovo/x200/dsdt.asl
+++ b/src/mainboard/lenovo/x200/dsdt.asl
@@ -19,8 +19,8 @@
*/
#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1
diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c
index 5c0d1fd..2dd9da8 100644
--- a/src/mainboard/lenovo/x201/acpi_tables.c
+++ b/src/mainboard/lenovo/x201/acpi_tables.c
@@ -33,11 +33,4 @@
void acpi_create_gnvs(global_nvs_t * gnvs)
{
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index d892926..0ab750e 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -20,6 +20,9 @@
##
chip northbridge/intel/nehalem
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
index 20d647e..eed397f 100644
--- a/src/mainboard/lenovo/x201/dsdt.asl
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -19,11 +19,10 @@
*/
#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
-#define HAVE_LCD_SCREEN 1
DefinitionBlock(
"dsdt.aml",
diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c
index abb6b31..75020ff 100644
--- a/src/mainboard/lenovo/x220/acpi_tables.c
+++ b/src/mainboard/lenovo/x220/acpi_tables.c
@@ -52,12 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u1 = 0;
/* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 6eb3b15..28e240a 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl
index 94da7ba..02fdacf 100644
--- a/src/mainboard/lenovo/x220/dsdt.asl
+++ b/src/mainboard/lenovo/x220/dsdt.asl
@@ -20,11 +20,10 @@
*/
#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
-#define HAVE_LCD_SCREEN 1
DefinitionBlock(
"dsdt.aml",
diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c
index abb6b31..75020ff 100644
--- a/src/mainboard/lenovo/x230/acpi_tables.c
+++ b/src/mainboard/lenovo/x230/acpi_tables.c
@@ -52,12 +52,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u1 = 0;
/* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 55677a3..88cf52d 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
index 94da7ba..02fdacf 100644
--- a/src/mainboard/lenovo/x230/dsdt.asl
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -20,11 +20,10 @@
*/
#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
-#define HAVE_LCD_SCREEN 1
DefinitionBlock(
"dsdt.aml",
diff --git a/src/mainboard/lenovo/x60/acpi/video.asl b/src/mainboard/lenovo/x60/acpi/video.asl
deleted file mode 100644
index ffb908c..0000000
--- a/src/mainboard/lenovo/x60/acpi/video.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include "smi.h"
-
-Device (DSPC)
-{
- Name (_ADR, 0x00020001)
- OperationRegion (DSPC, PCI_Config, 0x00, 0x100)
- Field (DSPC, ByteAcc, NoLock, Preserve)
- {
- Offset (0xf4),
- BRTC, 8
- }
-
- Method(BRTD, 0, NotSerialized)
- {
- Store(BRTC, Local0)
- if (LGreater (Local0, 15))
- {
- Subtract(Local0, 16, Local0)
- Store(Local0, BRTC)
- Trap(SMI_SAVE_CMOS)
- }
- }
-
- Method(BRTU, 0, NotSerialized)
- {
- Store (BRTC, Local0)
- if (LLess(Local0, 0xff))
- {
- Add (Local0, 16, Local0)
- Store(Local0, BRTC)
- Trap(SMI_SAVE_CMOS)
- }
- }
-}
diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c
index 64b1fc6..4e4cf1e 100644
--- a/src/mainboard/lenovo/x60/acpi_tables.c
+++ b/src/mainboard/lenovo/x60/acpi_tables.c
@@ -36,13 +36,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index e15f574..a3d31a6 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -20,6 +20,9 @@
##
chip northbridge/intel/i945
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gpu_hotplug" = "0x00000220"
register "gpu_lvds_use_spread_spectrum_clock" = "1"
diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl
index 92aac6c..40e5d05 100644
--- a/src/mainboard/lenovo/x60/dsdt.asl
+++ b/src/mainboard/lenovo/x60/dsdt.asl
@@ -18,9 +18,11 @@
* Foundation, Inc.
*/
+#include "smi.h"
+
#define THINKPAD_EC_GPE 28
-#define BRIGHTNESS_UP \DSPC.BRTU
-#define BRIGHTNESS_DOWN \DSPC.BRTD
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
DefinitionBlock(
diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl
index 7a73a78..f06aba7 100644
--- a/src/mainboard/packardbell/ms2290/acpi/ec.asl
+++ b/src/mainboard/packardbell/ms2290/acpi/ec.asl
@@ -121,12 +121,12 @@ Device(EC)
/* Decrease brightness. */
Method(_Q1D, 0, NotSerialized)
{
- \_SB.PCI0.GFX0.LCD0.DECB()
+ \_SB.PCI0.GFX0.DECB()
}
/* Increase brightness. */
Method(_Q1C, 0, NotSerialized)
{
- \_SB.PCI0.GFX0.LCD0.INCB()
+ \_SB.PCI0.GFX0.INCB()
}
#include "battery.asl"
diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c
index 001f488..73b9fff 100644
--- a/src/mainboard/packardbell/ms2290/acpi_tables.c
+++ b/src/mainboard/packardbell/ms2290/acpi_tables.c
@@ -33,12 +33,5 @@
void acpi_create_gnvs(global_nvs_t * gnvs)
{
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb
index 17e1a41..0231b4b 100644
--- a/src/mainboard/packardbell/ms2290/devicetree.cb
+++ b/src/mainboard/packardbell/ms2290/devicetree.cb
@@ -20,6 +20,9 @@
##
chip northbridge/intel/nehalem
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gpu_dp_b_hotplug" = "0x04"
register "gpu_dp_c_hotplug" = "0x04"
diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl
index 0911494..5fb43f3 100644
--- a/src/mainboard/packardbell/ms2290/dsdt.asl
+++ b/src/mainboard/packardbell/ms2290/dsdt.asl
@@ -18,8 +18,6 @@
* Foundation, Inc.
*/
-#define HAVE_LCD_SCREEN 1
-
DefinitionBlock(
"dsdt.aml",
"DSDT",
diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl
index fa13bbf..d033f46 100644
--- a/src/mainboard/roda/rk886ex/acpi/ec.asl
+++ b/src/mainboard/roda/rk886ex/acpi/ec.asl
@@ -97,8 +97,8 @@ Device(EC0)
Method (_Q12, 0)
{
Store("_Q12: Fn-F9 (Display Switch) pressed", Debug)
+ Notify (\_SB.PCI0.GFX0, 0x82)
// Store(1, TLST)
- // HKDS(10)
}
Method (_Q30, 0)
diff --git a/src/mainboard/roda/rk886ex/acpi/video.asl b/src/mainboard/roda/rk886ex/acpi/video.asl
deleted file mode 100644
index 1c9ccfd..0000000
--- a/src/mainboard/roda/rk886ex/acpi/video.asl
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
- // TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
- // TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
- // TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
- // TODO (no displays defined yet)
-}
diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c
index 64b1fc6..4e4cf1e 100644
--- a/src/mainboard/roda/rk886ex/acpi_tables.c
+++ b/src/mainboard/roda/rk886ex/acpi_tables.c
@@ -36,13 +36,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index a4ed87b..589abed 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -19,6 +19,9 @@
##
chip northbridge/intel/i945
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on
chip cpu/intel/socket_mFCPGA478
diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c
index b699740..fa69e7a 100644
--- a/src/mainboard/roda/rk9/acpi_tables.c
+++ b/src/mainboard/roda/rk9/acpi_tables.c
@@ -40,13 +40,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
- gnvs->ndid = 0; /* Will use default of 0x00000400. */
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb
index 2bd2358..003c08e 100644
--- a/src/mainboard/roda/rk9/devicetree.cb
+++ b/src/mainboard/roda/rk9/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/gm45
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
device cpu_cluster 0 on
chip cpu/intel/socket_BGA956
device lapic 0 on end
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
index 8271fc7..0e79348 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -80,13 +80,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
acpi_update_thermal_table(gnvs);
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 0372614..a632b27 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c
index 81eadd5..04e3bd0 100644
--- a/src/mainboard/samsung/stumpy/acpi_tables.c
+++ b/src/mainboard/samsung/stumpy/acpi_tables.c
@@ -79,13 +79,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 1;
gnvs->s5u1 = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
acpi_update_thermal_table(gnvs);
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 60b112b..df91a72 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -1,4 +1,7 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
# Enable DisplayPort 1 Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig
index ee1c58b..7922143 100644
--- a/src/northbridge/intel/fsp_sandybridge/Kconfig
+++ b/src/northbridge/intel/fsp_sandybridge/Kconfig
@@ -22,11 +22,13 @@ config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
bool
select CPU_INTEL_FSP_MODEL_206AX
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
bool
select CPU_INTEL_FSP_MODEL_306AX
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl
index 8ad70d7..df8a389 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl
+++ b/src/northbridge/intel/fsp_sandybridge/acpi/igd.asl
@@ -22,301 +22,57 @@ Device (GFX0)
{
Name (_ADR, 0x00020000)
- /* Display Output Switching */
- Method (_DOS, 1)
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
{
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
+ Offset (0x10),
+ BAR0, 64
}
- /* We try to support as many i945 systems as possible,
- * so keep the number of DIDs flexible.
- */
- Method (_DOD, 0)
+ OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
{
- If (LEqual(NDID, 1)) {
- Name(DOD1, Package() {
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD1, 0))
- Return(DOD1)
- }
-
- If (LEqual(NDID, 2)) {
- Name(DOD2, Package() {
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID2), Index(DOD2, 0))
- Store (Or(0x00010000, DID2), Index(DOD2, 1))
- Return(DOD2)
- }
-
- If (LEqual(NDID, 3)) {
- Name(DOD3, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID3), Index(DOD3, 0))
- Store (Or(0x00010000, DID3), Index(DOD3, 1))
- Store (Or(0x00010000, DID3), Index(DOD3, 2))
- Return(DOD3)
- }
-
- If (LEqual(NDID, 4)) {
- Name(DOD4, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID4), Index(DOD4, 0))
- Store (Or(0x00010000, DID4), Index(DOD4, 1))
- Store (Or(0x00010000, DID4), Index(DOD4, 2))
- Store (Or(0x00010000, DID4), Index(DOD4, 3))
- Return(DOD4)
- }
-
- If (LGreater(NDID, 4)) {
- Name(DOD5, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID5), Index(DOD5, 0))
- Store (Or(0x00010000, DID5), Index(DOD5, 1))
- Store (Or(0x00010000, DID5), Index(DOD5, 2))
- Store (Or(0x00010000, DID5), Index(DOD5, 3))
- Store (Or(0x00010000, DID5), Index(DOD5, 4))
- Return(DOD5)
- }
-
- /* Some error happened, but we have to return something */
- Return (Package() {0x00000400})
- }
-
- Device(DD01)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID1, 0)) {
- Return (1)
- } Else {
- Return (And(0xffff, DID1))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 1)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 1)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
- Device(DD02)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID2, 0)) {
- Return (2)
- } Else {
- Return (And(0xffff, DID2))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 2)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 2)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xc8250),
+ CR1, 32,
+ CR2, 32
}
-
- Device(DD03)
+ Name (BRIG, Package (0x12)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID3, 0)) {
- Return (3)
- } Else {
- Return (And(0xffff, DID3))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 4)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD04)
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (XBCM, 1, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID4, 0)) {
- Return (4)
- } Else {
- Return (And(0xffff, DID4))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 8)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (ShiftLeft (Arg0, 4), BCLV)
+ Store (0x80000000, CR1)
+ Store (0x061a061a, CR2)
}
-
- Device(DD05)
+ Method (XBQC, 0, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID5, 0)) {
- Return (5)
- } Else {
- Return (And(0xffff, DID5))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 16)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
}
-
+#include <drivers/intel/gma/igd.asl>
}
diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h
index 75d967e..6e823dc 100644
--- a/src/northbridge/intel/fsp_sandybridge/chip.h
+++ b/src/northbridge/intel/fsp_sandybridge/chip.h
@@ -17,6 +17,8 @@
* Foundation, Inc.
*/
+#include <drivers/intel/gma/i915.h>
+
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
@@ -38,4 +40,6 @@ struct northbridge_intel_fsp_sandybridge_config {
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
+
+ struct i915_gpu_controller_info gfx;
};
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c
index e86c478..26f1ae6 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.c
+++ b/src/northbridge/intel/fsp_sandybridge/gma.c
@@ -63,6 +63,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_fsp_sandybridge_config *chip = dev->chip_info;
+ return &chip->gfx;
+}
+
+static void gma_ssdt(void)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -71,6 +92,7 @@ static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_fill_ssdt_generator = gma_ssdt,
.init = pci_dev_init,
.scan_bus = 0,
.enable = 0,
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index aeef1eb..831e440 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -31,6 +31,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select VGA
select INTEL_EDID
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
config BOOTBLOCK_NORTHBRIDGE_INIT
string
diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl
index cb99694..696cc2b 100644
--- a/src/northbridge/intel/gm45/acpi/igd.asl
+++ b/src/northbridge/intel/gm45/acpi/igd.asl
@@ -26,10 +26,10 @@ Device (GFX0)
Field (GFXC, DWordAcc, NoLock, Preserve)
{
Offset (0x10),
- BAR0, 64
+ BAR0, 64
}
- OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
Field (GFRG, DWordAcc, NoLock, Preserve)
{
Offset (0x61250),
@@ -38,399 +38,40 @@ Device (GFX0)
BCLM, 16,
}
- /* Display Output Switching */
- Method (_DOS, 1)
+ Name (BRIG, Package (0x12)
{
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
- }
-
- /* We try to support as many GM45 systems as possible,
- * so keep the number of DIDs flexible.
- */
- Method (_DOD, 0)
- {
- If (LEqual(NDID, 1)) {
- Name(DOD1, Package() {
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD1, 0))
- Return(DOD1)
- }
-
- If (LEqual(NDID, 2)) {
- Name(DOD2, Package() {
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD2, 0))
- Store (Or(0x00010000, DID2), Index(DOD2, 1))
- Return(DOD2)
- }
-
- If (LEqual(NDID, 3)) {
- Name(DOD3, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD3, 0))
- Store (Or(0x00010000, DID2), Index(DOD3, 1))
- Store (Or(0x00010000, DID3), Index(DOD3, 2))
- Return(DOD3)
- }
-
- If (LEqual(NDID, 4)) {
- Name(DOD4, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD4, 0))
- Store (Or(0x00010000, DID2), Index(DOD4, 1))
- Store (Or(0x00010000, DID3), Index(DOD4, 2))
- Store (Or(0x00010000, DID4), Index(DOD4, 3))
- Return(DOD4)
- }
-
- If (LGreater(NDID, 4)) {
- Name(DOD5, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD5, 0))
- Store (Or(0x00010000, DID2), Index(DOD5, 1))
- Store (Or(0x00010000, DID3), Index(DOD5, 2))
- Store (Or(0x00010000, DID4), Index(DOD5, 3))
- Store (Or(0x00010000, DID5), Index(DOD5, 4))
- Return(DOD5)
- }
-
- /* Some error happened, but we have to return something */
- Return (Package() {0x00000400})
- }
-
- Device(DD01)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID1, 0)) {
- Return (1)
- } Else {
- Return (And(0xffff, DID1))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 1)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 1)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-#ifdef DISPLAY_DEVICE_2_IS_LCD_SCREEN
- Device (LCD0)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID2, 0)) {
- Return (2)
- } Else {
- Return (And(0xffff, DID2))
- }
- }
-
- Name (BRCT, 0)
-
- Name (BRIG, Package (0x12)
- {
- 0x61,
- 0x61,
- 0x2,
- 0x4,
- 0x5,
- 0x7,
- 0x9,
- 0xb,
- 0xd,
- 0x11,
- 0x14,
- 0x17,
- 0x1c,
- 0x20,
- 0x27,
- 0x31,
- 0x41,
- 0x61,
- })
-
- Method (_BCL, 0, NotSerialized)
- {
- Store (1, BRCT)
- Return (BRIG)
- }
-
- Method (_BCM, 1, NotSerialized)
- {
- Store (ShiftLeft (Arg0, 4), ^^BCLV)
- Store (0x80000000, ^^CR1)
- Store (0x0610, ^^BCLM)
- }
- Method (_BQC, 0, NotSerialized)
- {
- Store (^^BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
- }
-
- Method(BRID, 1, NotSerialized)
- {
- Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
- If (LEqual (Local0, Ones))
- {
- Return (0x11)
- }
- Return (Local0)
- }
-
- /* Using Notify is the right way. But Windows doesn't handle
- it well. So use both method in a way to avoid double action.
- */
- Method (DECB, 0, NotSerialized)
- {
- If (BRCT)
- {
- Notify (LCD0, 0x87)
- } Else {
- Store (BRID (_BQC ()), Local0)
- If (LNotEqual (Local0, 2))
- {
- Decrement (Local0)
- }
- _BCM (DerefOf (Index (BRIG, Local0)))
- }
- }
- Method (INCB, 0, NotSerialized)
- {
- If (BRCT)
- {
- Notify (LCD0, 0x86)
- } Else {
- Store (BRID (_BQC ()), Local0)
- If (LNotEqual (Local0, 0x11))
- {
- Increment (Local0)
- }
- _BCM (DerefOf (Index (BRIG, Local0)))
- }
- }
- }
-#else
- Device(DD02)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID2, 0)) {
- Return (2)
- } Else {
- Return (And(0xffff, DID2))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 2)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 2)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-#endif
-
- Device(DD03)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID3, 0)) {
- Return (3)
- } Else {
- Return (And(0xffff, DID3))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 4)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD04)
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (XBCM, 1, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID4, 0)) {
- Return (4)
- } Else {
- Return (And(0xffff, DID4))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 8)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (ShiftLeft (Arg0, 4), BCLV)
+ Store (0x80000000, CR1)
+ Store (0x0610, BCLM)
}
-
- Device(DD05)
+ Method (XBQC, 0, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID5, 0)) {
- Return (5)
- } Else {
- Return (And(0xffff, DID5))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 16)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
}
+#include <drivers/intel/gma/igd.asl>
}
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index fab7787..7cc59c8 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -491,6 +491,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_gm45_config *chip = dev->chip_info;
+ return &chip->gfx;
+}
+
+static void gma_ssdt(void)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -499,6 +520,7 @@ static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_fill_ssdt_generator = gma_ssdt,
.init = gma_func0_init,
.scan_bus = 0,
.enable = 0,
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 1eb297b..d320f72 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -27,6 +27,7 @@ config NORTHBRIDGE_INTEL_HASWELL
select INTEL_DDI
select INTEL_DP
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
if NORTHBRIDGE_INTEL_HASWELL
diff --git a/src/northbridge/intel/haswell/acpi/igd.asl b/src/northbridge/intel/haswell/acpi/igd.asl
index 8ad70d7..df8a389 100644
--- a/src/northbridge/intel/haswell/acpi/igd.asl
+++ b/src/northbridge/intel/haswell/acpi/igd.asl
@@ -22,301 +22,57 @@ Device (GFX0)
{
Name (_ADR, 0x00020000)
- /* Display Output Switching */
- Method (_DOS, 1)
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
{
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
+ Offset (0x10),
+ BAR0, 64
}
- /* We try to support as many i945 systems as possible,
- * so keep the number of DIDs flexible.
- */
- Method (_DOD, 0)
+ OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
{
- If (LEqual(NDID, 1)) {
- Name(DOD1, Package() {
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD1, 0))
- Return(DOD1)
- }
-
- If (LEqual(NDID, 2)) {
- Name(DOD2, Package() {
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID2), Index(DOD2, 0))
- Store (Or(0x00010000, DID2), Index(DOD2, 1))
- Return(DOD2)
- }
-
- If (LEqual(NDID, 3)) {
- Name(DOD3, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID3), Index(DOD3, 0))
- Store (Or(0x00010000, DID3), Index(DOD3, 1))
- Store (Or(0x00010000, DID3), Index(DOD3, 2))
- Return(DOD3)
- }
-
- If (LEqual(NDID, 4)) {
- Name(DOD4, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID4), Index(DOD4, 0))
- Store (Or(0x00010000, DID4), Index(DOD4, 1))
- Store (Or(0x00010000, DID4), Index(DOD4, 2))
- Store (Or(0x00010000, DID4), Index(DOD4, 3))
- Return(DOD4)
- }
-
- If (LGreater(NDID, 4)) {
- Name(DOD5, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID5), Index(DOD5, 0))
- Store (Or(0x00010000, DID5), Index(DOD5, 1))
- Store (Or(0x00010000, DID5), Index(DOD5, 2))
- Store (Or(0x00010000, DID5), Index(DOD5, 3))
- Store (Or(0x00010000, DID5), Index(DOD5, 4))
- Return(DOD5)
- }
-
- /* Some error happened, but we have to return something */
- Return (Package() {0x00000400})
- }
-
- Device(DD01)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID1, 0)) {
- Return (1)
- } Else {
- Return (And(0xffff, DID1))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 1)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 1)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
- Device(DD02)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID2, 0)) {
- Return (2)
- } Else {
- Return (And(0xffff, DID2))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 2)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 2)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xc8250),
+ CR1, 32,
+ CR2, 32
}
-
- Device(DD03)
+ Name (BRIG, Package (0x12)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID3, 0)) {
- Return (3)
- } Else {
- Return (And(0xffff, DID3))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 4)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD04)
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (XBCM, 1, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID4, 0)) {
- Return (4)
- } Else {
- Return (And(0xffff, DID4))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 8)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (ShiftLeft (Arg0, 4), BCLV)
+ Store (0x80000000, CR1)
+ Store (0x061a061a, CR2)
}
-
- Device(DD05)
+ Method (XBQC, 0, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID5, 0)) {
- Return (5)
- } Else {
- Return (And(0xffff, DID5))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 16)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
}
-
+#include <drivers/intel/gma/igd.asl>
}
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index 801e062..6ae3483 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -17,6 +17,8 @@
* Foundation, Inc.
*/
+#include <drivers/intel/gma/i915.h>
+
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
@@ -38,6 +40,8 @@ struct northbridge_intel_haswell_config {
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
+
+ struct i915_gpu_controller_info gfx;
};
extern struct chip_operations northbridge_intel_haswell_ops;
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 6faae25..f120670 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -487,6 +487,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_haswell_config *chip = dev->chip_info;
+ return &chip->gfx;
+}
+
+static void gma_ssdt(void)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -496,6 +517,7 @@ static struct device_operations gma_func0_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
+ .acpi_fill_ssdt_generator = gma_ssdt,
.scan_bus = 0,
.enable = 0,
.ops_pci = &gma_pci_ops,
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 1560d77..007c4f8 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -30,6 +30,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select LAPIC_MONOTONIC_TIMER
select VGA
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index 74302c9..2a4eb9f 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -99,9 +99,3 @@ Device (PDRC)
// Integrated graphics 0:2.0
#include "igd.asl"
-
-Scope (\)
-{
- // backlight control, display switching, lid
- #include "acpi/video.asl"
-}
diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl
index 8ad70d7..fb89e55 100644
--- a/src/northbridge/intel/i945/acpi/igd.asl
+++ b/src/northbridge/intel/i945/acpi/igd.asl
@@ -22,301 +22,52 @@ Device (GFX0)
{
Name (_ADR, 0x00020000)
- /* Display Output Switching */
- Method (_DOS, 1)
+ Name (BRIG, Package (0x12)
{
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
- }
-
- /* We try to support as many i945 systems as possible,
- * so keep the number of DIDs flexible.
- */
- Method (_DOD, 0)
- {
- If (LEqual(NDID, 1)) {
- Name(DOD1, Package() {
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD1, 0))
- Return(DOD1)
- }
-
- If (LEqual(NDID, 2)) {
- Name(DOD2, Package() {
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID2), Index(DOD2, 0))
- Store (Or(0x00010000, DID2), Index(DOD2, 1))
- Return(DOD2)
- }
-
- If (LEqual(NDID, 3)) {
- Name(DOD3, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID3), Index(DOD3, 0))
- Store (Or(0x00010000, DID3), Index(DOD3, 1))
- Store (Or(0x00010000, DID3), Index(DOD3, 2))
- Return(DOD3)
- }
-
- If (LEqual(NDID, 4)) {
- Name(DOD4, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID4), Index(DOD4, 0))
- Store (Or(0x00010000, DID4), Index(DOD4, 1))
- Store (Or(0x00010000, DID4), Index(DOD4, 2))
- Store (Or(0x00010000, DID4), Index(DOD4, 3))
- Return(DOD4)
- }
-
- If (LGreater(NDID, 4)) {
- Name(DOD5, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID5), Index(DOD5, 0))
- Store (Or(0x00010000, DID5), Index(DOD5, 1))
- Store (Or(0x00010000, DID5), Index(DOD5, 2))
- Store (Or(0x00010000, DID5), Index(DOD5, 3))
- Store (Or(0x00010000, DID5), Index(DOD5, 4))
- Return(DOD5)
- }
-
- /* Some error happened, but we have to return something */
- Return (Package() {0x00000400})
- }
-
- Device(DD01)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID1, 0)) {
- Return (1)
- } Else {
- Return (And(0xffff, DID1))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 1)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 1)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
- Device(DD02)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID2, 0)) {
- Return (2)
- } Else {
- Return (And(0xffff, DID2))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 2)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 2)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD03)
+ 0xf,
+ 0xf,
+ 0x0,
+ 0x1,
+ 0x2,
+ 0x3,
+ 0x4,
+ 0x5,
+ 0x6,
+ 0x7,
+ 0x8,
+ 0x9,
+ 0xa,
+ 0xb,
+ 0xc,
+ 0xd,
+ 0xe,
+ 0xf,
+ })
+
+ Method (XBCM, 1, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID3, 0)) {
- Return (3)
- } Else {
- Return (And(0xffff, DID3))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 4)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (Or(ShiftLeft (Arg0, 4), 0xf), ^^DSPC.BRTC)
+#ifdef SMI_SAVE_CMOS
+ Trap(SMI_SAVE_CMOS)
+#endif
}
-
- Device(DD04)
+ Method (XBQC, 0, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID4, 0)) {
- Return (4)
- } Else {
- Return (And(0xffff, DID4))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 8)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (^^DSPC.BRTC, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
}
+#include <drivers/intel/gma/igd.asl>
+}
-
- Device(DD05)
+Device (DSPC)
+{
+ Name (_ADR, 0x00020001)
+ OperationRegion (DSPC, PCI_Config, 0x00, 0x100)
+ Field (DSPC, ByteAcc, NoLock, Preserve)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID5, 0)) {
- Return (5)
- } Else {
- Return (And(0xffff, DID5))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 16)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Offset (0xf4),
+ BRTC, 8
}
-
-}
+}
\ No newline at end of file
diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h
index 9e25ecc..5706086 100644
--- a/src/northbridge/intel/i945/chip.h
+++ b/src/northbridge/intel/i945/chip.h
@@ -1,6 +1,9 @@
+#include <drivers/intel/gma/i915.h>
+
struct northbridge_intel_i945_config {
u32 gpu_hotplug;
u32 gpu_backlight;
int gpu_lvds_use_spread_spectrum_clock;
int gpu_lvds_is_dual_channel;
+ struct i915_gpu_controller_info gfx;
};
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index ebc2f1c..28f611f 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -488,6 +488,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_i945_config *chip = dev->chip_info;
+ return &chip->gfx;
+}
+
+static void gma_ssdt(void)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -497,6 +518,7 @@ static struct device_operations gma_func0_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
+ .acpi_fill_ssdt_generator = gma_ssdt,
.scan_bus = 0,
.enable = 0,
.disable = gma_func0_disable,
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index dcff12e..29997c7 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -26,6 +26,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
select INTEL_EDID
select TSC_MONOTONIC_TIMER
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
if NORTHBRIDGE_INTEL_NEHALEM
diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl
index 6c9959d..df8a389 100644
--- a/src/northbridge/intel/nehalem/acpi/igd.asl
+++ b/src/northbridge/intel/nehalem/acpi/igd.asl
@@ -26,10 +26,10 @@ Device (GFX0)
Field (GFXC, DWordAcc, NoLock, Preserve)
{
Offset (0x10),
- BAR0, 64
+ BAR0, 64
}
- OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
Field (GFRG, DWordAcc, NoLock, Preserve)
{
Offset (0x48254),
@@ -39,391 +39,40 @@ Device (GFX0)
CR2, 32
}
- /* Display Output Switching */
- Method (_DOS, 1)
+ Name (BRIG, Package (0x12)
{
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
- }
-
- /* We try to support as many i945 systems as possible,
- * so keep the number of DIDs flexible.
- */
- Method (_DOD, 0)
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (XBCM, 1, NotSerialized)
{
- If (LEqual(NDID, 1)) {
- Name(DOD1, Package() {
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD1, 0))
- Return(DOD1)
- }
-
- If (LEqual(NDID, 2)) {
- Name(DOD2, Package() {
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID2), Index(DOD2, 0))
- Store (Or(0x00010000, DID2), Index(DOD2, 1))
- Return(DOD2)
- }
-
- If (LEqual(NDID, 3)) {
- Name(DOD3, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID3), Index(DOD3, 0))
- Store (Or(0x00010000, DID3), Index(DOD3, 1))
- Store (Or(0x00010000, DID3), Index(DOD3, 2))
- Return(DOD3)
- }
-
- If (LEqual(NDID, 4)) {
- Name(DOD4, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID4), Index(DOD4, 0))
- Store (Or(0x00010000, DID4), Index(DOD4, 1))
- Store (Or(0x00010000, DID4), Index(DOD4, 2))
- Store (Or(0x00010000, DID4), Index(DOD4, 3))
- Return(DOD4)
- }
-
- If (LGreater(NDID, 4)) {
- Name(DOD5, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID5), Index(DOD5, 0))
- Store (Or(0x00010000, DID5), Index(DOD5, 1))
- Store (Or(0x00010000, DID5), Index(DOD5, 2))
- Store (Or(0x00010000, DID5), Index(DOD5, 3))
- Store (Or(0x00010000, DID5), Index(DOD5, 4))
- Return(DOD5)
- }
-
- /* Some error happened, but we have to return something */
- Return (Package() {0x00000400})
+ Store (ShiftLeft (Arg0, 4), BCLV)
+ Store (0x80000000, CR1)
+ Store (0x061a061a, CR2)
}
- Device(DD01)
+ Method (XBQC, 0, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID1, 0)) {
- Return (1)
- } Else {
- Return (And(0xffff, DID1))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 1)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 1)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
- Device(DD02)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID2, 0)) {
- Return (2)
- } Else {
- Return (And(0xffff, DID2))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 2)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 2)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD03)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID3, 0)) {
- Return (3)
- } Else {
- Return (And(0xffff, DID3))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 4)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD04)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID4, 0)) {
- Return (4)
- } Else {
- Return (And(0xffff, DID4))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 8)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD05)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID5, 0)) {
- Return (5)
- } Else {
- Return (And(0xffff, DID5))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 16)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-#ifdef HAVE_LCD_SCREEN
- Device (LCD0)
- {
- Name (_ADR, 0x0400)
- Name (BRCT, 0)
-
- Name (BRIG, Package (0x12)
- {
- 0x61,
- 0x61,
- 0x2,
- 0x4,
- 0x5,
- 0x7,
- 0x9,
- 0xb,
- 0xd,
- 0x11,
- 0x14,
- 0x17,
- 0x1c,
- 0x20,
- 0x27,
- 0x31,
- 0x41,
- 0x61,
- })
-
- Method (_BCL, 0, NotSerialized)
- {
- Store (1, BRCT)
- Return (BRIG)
- }
-
- Method (_BCM, 1, NotSerialized)
- {
- Store (ShiftLeft (Arg0, 4), ^^BCLV)
- Store (0x80000000, ^^CR1)
- Store (0x061a061a, ^^CR2)
- }
- Method (_BQC, 0, NotSerialized)
- {
- Store (^^BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
- }
-
- Method(BRID, 1, NotSerialized)
- {
- Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
- If (LEqual (Local0, Ones))
- {
- Return (0x11)
- }
- Return (Local0)
- }
-
- /* Using Notify is the right way. But Windows doesn't handle
- it well. So use both method in a way to avoid double action.
- */
- Method (DECB, 0, NotSerialized)
- {
- If (BRCT)
- {
- Notify (LCD0, 0x87)
- } Else {
- Store (BRID (_BQC ()), Local0)
- If (LNotEqual (Local0, 2))
- {
- Decrement (Local0)
- }
- _BCM (DerefOf (Index (BRIG, Local0)))
- }
- }
- Method (INCB, 0, NotSerialized)
- {
- If (BRCT)
- {
- Notify (LCD0, 0x86)
- } Else {
- Store (BRID (_BQC ()), Local0)
- If (LNotEqual (Local0, 0x11))
- {
- Increment (Local0)
- }
- _BCM (DerefOf (Index (BRIG, Local0)))
- }
- }
+ Store (BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
}
-#endif
+#include <drivers/intel/gma/igd.asl>
}
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index 2c1332c..d4217de 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -1071,6 +1071,27 @@ static void gma_read_resources(struct device *dev)
res->size = (resource_t) 0x10000000;
}
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_nehalem_config *chip = dev->chip_info;
+ return &chip->gfx;
+}
+
+static void gma_ssdt(void)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -1079,6 +1100,7 @@ static struct device_operations gma_func0_ops = {
.read_resources = gma_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_fill_ssdt_generator = gma_ssdt,
.init = gma_func0_init,
.scan_bus = 0,
.enable = 0,
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 56fbbaf..5c5215e 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -24,6 +24,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_206AX
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
bool
@@ -33,6 +34,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
select CPU_INTEL_MODEL_206AX
select HAVE_DEBUG_RAM_SETUP
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
@@ -41,6 +43,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
select MMCONF_SUPPORT_DEFAULT
select CPU_INTEL_MODEL_306AX
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
bool
@@ -50,6 +53,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
select CPU_INTEL_MODEL_306AX
select HAVE_DEBUG_RAM_SETUP
select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
diff --git a/src/northbridge/intel/sandybridge/acpi/igd.asl b/src/northbridge/intel/sandybridge/acpi/igd.asl
index 6c9959d..6b02765 100644
--- a/src/northbridge/intel/sandybridge/acpi/igd.asl
+++ b/src/northbridge/intel/sandybridge/acpi/igd.asl
@@ -39,391 +39,40 @@ Device (GFX0)
CR2, 32
}
- /* Display Output Switching */
- Method (_DOS, 1)
+ Name (BRIG, Package (0x12)
{
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
- }
-
- /* We try to support as many i945 systems as possible,
- * so keep the number of DIDs flexible.
- */
- Method (_DOD, 0)
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (XBCM, 1, NotSerialized)
{
- If (LEqual(NDID, 1)) {
- Name(DOD1, Package() {
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD1, 0))
- Return(DOD1)
- }
-
- If (LEqual(NDID, 2)) {
- Name(DOD2, Package() {
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID2), Index(DOD2, 0))
- Store (Or(0x00010000, DID2), Index(DOD2, 1))
- Return(DOD2)
- }
-
- If (LEqual(NDID, 3)) {
- Name(DOD3, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID3), Index(DOD3, 0))
- Store (Or(0x00010000, DID3), Index(DOD3, 1))
- Store (Or(0x00010000, DID3), Index(DOD3, 2))
- Return(DOD3)
- }
-
- If (LEqual(NDID, 4)) {
- Name(DOD4, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID4), Index(DOD4, 0))
- Store (Or(0x00010000, DID4), Index(DOD4, 1))
- Store (Or(0x00010000, DID4), Index(DOD4, 2))
- Store (Or(0x00010000, DID4), Index(DOD4, 3))
- Return(DOD4)
- }
-
- If (LGreater(NDID, 4)) {
- Name(DOD5, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID5), Index(DOD5, 0))
- Store (Or(0x00010000, DID5), Index(DOD5, 1))
- Store (Or(0x00010000, DID5), Index(DOD5, 2))
- Store (Or(0x00010000, DID5), Index(DOD5, 3))
- Store (Or(0x00010000, DID5), Index(DOD5, 4))
- Return(DOD5)
- }
-
- /* Some error happened, but we have to return something */
- Return (Package() {0x00000400})
+ Store (ShiftLeft (Arg0, 4), BCLV)
+ Store (0x80000000, CR1)
+ Store (0x061a061a, CR2)
}
- Device(DD01)
+ Method (XBQC, 0, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID1, 0)) {
- Return (1)
- } Else {
- Return (And(0xffff, DID1))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 1)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 1)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
- Device(DD02)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID2, 0)) {
- Return (2)
- } Else {
- Return (And(0xffff, DID2))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 2)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 2)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD03)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID3, 0)) {
- Return (3)
- } Else {
- Return (And(0xffff, DID3))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 4)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD04)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID4, 0)) {
- Return (4)
- } Else {
- Return (And(0xffff, DID4))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 8)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD05)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID5, 0)) {
- Return (5)
- } Else {
- Return (And(0xffff, DID5))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 16)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-#ifdef HAVE_LCD_SCREEN
- Device (LCD0)
- {
- Name (_ADR, 0x0400)
- Name (BRCT, 0)
-
- Name (BRIG, Package (0x12)
- {
- 0x61,
- 0x61,
- 0x2,
- 0x4,
- 0x5,
- 0x7,
- 0x9,
- 0xb,
- 0xd,
- 0x11,
- 0x14,
- 0x17,
- 0x1c,
- 0x20,
- 0x27,
- 0x31,
- 0x41,
- 0x61,
- })
-
- Method (_BCL, 0, NotSerialized)
- {
- Store (1, BRCT)
- Return (BRIG)
- }
-
- Method (_BCM, 1, NotSerialized)
- {
- Store (ShiftLeft (Arg0, 4), ^^BCLV)
- Store (0x80000000, ^^CR1)
- Store (0x061a061a, ^^CR2)
- }
- Method (_BQC, 0, NotSerialized)
- {
- Store (^^BCLV, Local0)
- ShiftRight (Local0, 4, Local0)
- Return (Local0)
- }
-
- Method(BRID, 1, NotSerialized)
- {
- Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
- If (LEqual (Local0, Ones))
- {
- Return (0x11)
- }
- Return (Local0)
- }
-
- /* Using Notify is the right way. But Windows doesn't handle
- it well. So use both method in a way to avoid double action.
- */
- Method (DECB, 0, NotSerialized)
- {
- If (BRCT)
- {
- Notify (LCD0, 0x87)
- } Else {
- Store (BRID (_BQC ()), Local0)
- If (LNotEqual (Local0, 2))
- {
- Decrement (Local0)
- }
- _BCM (DerefOf (Index (BRIG, Local0)))
- }
- }
- Method (INCB, 0, NotSerialized)
- {
- If (BRCT)
- {
- Notify (LCD0, 0x86)
- } Else {
- Store (BRID (_BQC ()), Local0)
- If (LNotEqual (Local0, 0x11))
- {
- Increment (Local0)
- }
- _BCM (DerefOf (Index (BRIG, Local0)))
- }
- }
+ Store (BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
}
-#endif
+#include <drivers/intel/gma/igd.asl>
}
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 7ff0e65..d7ad8fe 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -613,6 +613,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_sandybridge_config *chip = dev->chip_info;
+ return &chip->gfx;
+}
+
+static void gma_ssdt(void)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -621,6 +642,7 @@ static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_fill_ssdt_generator = gma_ssdt,
.init = gma_func0_init,
.scan_bus = 0,
.enable = 0,
diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig
index 19aad0b..3d20a26 100644
--- a/src/northbridge/intel/sch/Kconfig
+++ b/src/northbridge/intel/sch/Kconfig
@@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_SCH
select MMCONF_SUPPORT
select PER_DEVICE_ACPI_TABLES
select LATE_CBMEM_INIT
+ select INTEL_GMA_ACPI
if NORTHBRIDGE_INTEL_SCH
diff --git a/src/northbridge/intel/sch/acpi/igd.asl b/src/northbridge/intel/sch/acpi/igd.asl
index 8ad70d7..696cc2b 100644
--- a/src/northbridge/intel/sch/acpi/igd.asl
+++ b/src/northbridge/intel/sch/acpi/igd.asl
@@ -22,301 +22,56 @@ Device (GFX0)
{
Name (_ADR, 0x00020000)
- /* Display Output Switching */
- Method (_DOS, 1)
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
{
- /* Windows 2000 and Windows XP call _DOS to enable/disable
- * Display Output Switching during init and while a switch
- * is already active
- */
- Store (And(Arg0, 7), DSEN)
+ Offset (0x10),
+ BAR0, 64
}
- /* We try to support as many i945 systems as possible,
- * so keep the number of DIDs flexible.
- */
- Method (_DOD, 0)
+ OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
{
- If (LEqual(NDID, 1)) {
- Name(DOD1, Package() {
- 0xffffffff
- })
- Store (Or(0x00010000, DID1), Index(DOD1, 0))
- Return(DOD1)
- }
-
- If (LEqual(NDID, 2)) {
- Name(DOD2, Package() {
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID2), Index(DOD2, 0))
- Store (Or(0x00010000, DID2), Index(DOD2, 1))
- Return(DOD2)
- }
-
- If (LEqual(NDID, 3)) {
- Name(DOD3, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID3), Index(DOD3, 0))
- Store (Or(0x00010000, DID3), Index(DOD3, 1))
- Store (Or(0x00010000, DID3), Index(DOD3, 2))
- Return(DOD3)
- }
-
- If (LEqual(NDID, 4)) {
- Name(DOD4, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID4), Index(DOD4, 0))
- Store (Or(0x00010000, DID4), Index(DOD4, 1))
- Store (Or(0x00010000, DID4), Index(DOD4, 2))
- Store (Or(0x00010000, DID4), Index(DOD4, 3))
- Return(DOD4)
- }
-
- If (LGreater(NDID, 4)) {
- Name(DOD5, Package() {
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff,
- 0xffffffff
- })
- Store (Or(0x00010000, DID5), Index(DOD5, 0))
- Store (Or(0x00010000, DID5), Index(DOD5, 1))
- Store (Or(0x00010000, DID5), Index(DOD5, 2))
- Store (Or(0x00010000, DID5), Index(DOD5, 3))
- Store (Or(0x00010000, DID5), Index(DOD5, 4))
- Return(DOD5)
- }
-
- /* Some error happened, but we have to return something */
- Return (Package() {0x00000400})
- }
-
- Device(DD01)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID1, 0)) {
- Return (1)
- } Else {
- Return (And(0xffff, DID1))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 1)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 1)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
- Device(DD02)
- {
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID2, 0)) {
- Return (2)
- } Else {
- Return (And(0xffff, DID2))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 2)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 2)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Offset (0x61250),
+ CR1, 32,
+ BCLV, 16,
+ BCLM, 16,
}
-
- Device(DD03)
+ Name (BRIG, Package (0x12)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID3, 0)) {
- Return (3)
- } Else {
- Return (And(0xffff, DID3))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 4)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
- }
-
-
- Device(DD04)
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (XBCM, 1, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID4, 0)) {
- Return (4)
- } Else {
- Return (And(0xffff, DID4))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 8)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (ShiftLeft (Arg0, 4), BCLV)
+ Store (0x80000000, CR1)
+ Store (0x0610, BCLM)
}
-
- Device(DD05)
+ Method (XBQC, 0, NotSerialized)
{
- /* Device Unique ID */
- Method(_ADR, 0, Serialized)
- {
- If(LEqual(DID5, 0)) {
- Return (5)
- } Else {
- Return (And(0xffff, DID5))
- }
- }
-
- /* Device Current Status */
- Method(_DCS, 0)
- {
- TRAP(1)
- If (And(CSTE, 16)) {
- Return (0x1f)
- }
- Return(0x1d)
- }
-
- /* Query Device Graphics State */
- Method(_DGS, 0)
- {
- If (And(NSTE, 4)) {
- Return(1)
- }
- Return(0)
- }
-
- /* Device Set State */
- Method(_DSS, 1)
- {
- /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
- * display switch was completed
- */
- If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
- Store (NSTE, CSTE)
- }
- }
+ Store (BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
}
-
+#include <drivers/intel/gma/igd.asl>
}
diff --git a/src/northbridge/intel/sch/acpi/sch.asl b/src/northbridge/intel/sch/acpi/sch.asl
index 42b9f97..162232f 100644
--- a/src/northbridge/intel/sch/acpi/sch.asl
+++ b/src/northbridge/intel/sch/acpi/sch.asl
@@ -79,9 +79,3 @@ Device (PDRC)
// Integrated graphics 0:2.0
#include "igd.asl"
-
-Scope (\)
-{
- // backlight control, display switching, lid
- #include "acpi/video.asl"
-}
diff --git a/src/northbridge/intel/sch/chip.h b/src/northbridge/intel/sch/chip.h
new file mode 100644
index 0000000..33df6c5
--- /dev/null
+++ b/src/northbridge/intel/sch/chip.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef NORTHBRIDGE_INTEL_SCH_CHIP_H
+#define NORTHBRIDGE_INTEL_SCH_CHIP_H
+
+#include <drivers/intel/gma/i915.h>
+
+struct northbridge_intel_sch_config {
+ struct i915_gpu_controller_info gfx;
+};
+
+#endif /* NORTHBRIDGE_INTEL_SCH_CHIP_H */
diff --git a/src/northbridge/intel/sch/gma.c b/src/northbridge/intel/sch/gma.c
index 5728d19..5540eb1 100644
--- a/src/northbridge/intel/sch/gma.c
+++ b/src/northbridge/intel/sch/gma.c
@@ -21,6 +21,8 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <drivers/intel/gma/i915.h>
+#include "chip.h"
static void gma_func0_init(struct device *dev)
{
@@ -44,6 +46,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_sch_config *chip = dev->chip_info;
+ return &chip->gfx;
+}
+
+static void gma_ssdt(void)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -52,6 +75,7 @@ static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_fill_ssdt_generator = gma_ssdt,
.init = gma_func0_init,
.scan_bus = 0,
.enable = 0,
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 964b118..14b3920 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -678,6 +678,7 @@ static void southbridge_inject_dsdt(void)
opregion = igd_make_opregion();
if (gnvs) {
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs));
acpi_create_gnvs(gnvs);
@@ -686,6 +687,9 @@ static void southbridge_inject_dsdt(void)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
+ gnvs->ndid = gfx->ndid;
+ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
+
#if CONFIG_CHROMEOS
chromeos_init_vboot(&(gnvs->chromeos));
#endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index e707afa..73e11e8 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -640,11 +640,17 @@ static void southbridge_inject_dsdt(void)
opregion = igd_make_opregion();
if (gnvs) {
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+
memset(gnvs, 0, sizeof (*gnvs));
acpi_create_gnvs(gnvs);
/* IGD OpRegion Base Address */
gnvs->aslb = (u32)opregion;
+
+ gnvs->ndid = gfx->ndid;
+ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
+
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index ccaabba..31ea130 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -34,6 +34,7 @@
#include <arch/acpigen.h>
#include <cbmem.h>
#include <string.h>
+#include <drivers/intel/gma/i915.h>
#include "nvs.h"
#define NMI_OFF 0
@@ -617,12 +618,18 @@ static void southbridge_inject_dsdt(void)
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
if (gnvs) {
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+
memset(gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
acpi_create_gnvs(gnvs);
+
+ gnvs->ndid = gfx->ndid;
+ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
+
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index de936a3..3cc053b 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -37,6 +37,7 @@
#include "i82801ix.h"
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
+#include <drivers/intel/gma/i915.h>
#define NMI_OFF 0
@@ -544,8 +545,13 @@ static void southbridge_inject_dsdt(void)
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
if (gnvs) {
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs));
acpi_create_gnvs(gnvs);
+
+ gnvs->ndid = gfx->ndid;
+ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
+
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index c33f9d9..550ef30 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -671,6 +671,7 @@ static void southbridge_inject_dsdt(void)
opregion = igd_make_opregion();
if (gnvs) {
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs));
acpi_create_gnvs(gnvs);
@@ -678,6 +679,8 @@ static void southbridge_inject_dsdt(void)
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
+ gnvs->ndid = gfx->ndid;
+ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
/* IGD OpRegion Base Address */
gnvs->aslb = (u32)opregion;
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 6b2a522..c055da5 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -38,6 +38,7 @@
#include "pch.h"
#include <arch/acpigen.h>
#include <cbmem.h>
+#include <drivers/intel/gma/i915.h>
#define NMI_OFF 0
@@ -755,6 +756,8 @@ static void southbridge_inject_dsdt(void)
}
if (gnvs) {
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+
acpi_create_gnvs(gnvs);
gnvs->apic = 1;
@@ -768,6 +771,9 @@ static void southbridge_inject_dsdt(void)
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
+ gnvs->ndid = gfx->ndid;
+ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
+
acpi_save_gnvs((unsigned long)gnvs);
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c
index f06c149..e40b051 100644
--- a/src/southbridge/intel/sch/lpc.c
+++ b/src/southbridge/intel/sch/lpc.c
@@ -29,6 +29,7 @@
#include <cpu/cpu.h>
#include <cbmem.h>
#include <string.h>
+#include <drivers/intel/gma/i915.h>
#include "nvs.h"
#include "chip.h"
@@ -193,8 +194,13 @@ static void southbridge_inject_dsdt(void)
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
if (gnvs) {
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
+
+ gnvs->ndid = gfx->ndid;
+ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
+
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
1
0