coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: a592322 CBMEM console: Fix buffer without EARLY_CBMEM_INIT
by Kyösti Mälkki 26 May '15

26 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10301 -gerrit commit a59232232e05a8d17a7c57f044f334673faa7753 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 06:46:41 2015 +0300 CBMEM console: Fix buffer without EARLY_CBMEM_INIT On S3 resume, CBMEM_ID_CONSOLE from previous boot is found in ramstage, even when romstage did not create it. So buffer did not get cleared on S3 resume path. Also do not allocate for preram_cbmem_console in CAR when there are no means to back it up to ram. Change-Id: I175cebbb938adf2a7414703fefffb8da796e9fa9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/romstage.ld | 2 +- src/lib/cbmem_console.c | 7 ++----- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 27e8de1..ae7049b 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -65,7 +65,7 @@ SECTIONS * statically checked because the cache-as-ram region usage is * cpu/chipset dependent. */ _preram_cbmem_console = .; - _epreram_cbmem_console = . + 0xc00; + _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); } /* Global variables are not allowed in romstage diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 30bf439..e9607f3 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -225,11 +225,8 @@ void cbmemc_reinit(void) /* Need to reset the newly added cbmem console in ramstage * when there was no console in preram environment. */ - if (ENV_RAMSTAGE) { - cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); - if (cbm_cons_p == NULL) - flags |= CBMEMC_RESET; - } + if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) + flags |= CBMEMC_RESET; /* If CBMEM entry already existed, old contents is not altered. */ cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, size);

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Patch set updated for coreboot: aef3291 CBMEM: Fix S3 resume path without EARLY_CBMEM_INIT
by Kyösti Mälkki 26 May '15

26 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10299 -gerrit commit aef3291587302e8645588eeb184a3b73fa9117eb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 00:30:10 2015 +0300 CBMEM: Fix S3 resume path without EARLY_CBMEM_INIT Implementation for cbmem_find() did not work for boards without EARLY_CBMEM_INIT in romstage. This is required for S3 resume to work on AGESA plaforms. First broken with commit 0dff57d cbmem: switch over to imd-based cbmem Change-Id: I9c1a4f6839f5d90f825787baad2a3824a04b5bdc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 1 - src/lib/imd_cbmem.c | 15 ++++----------- 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 9ee5db4..30206b7 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -43,7 +43,6 @@ void set_top_of_ram(uint64_t ramtop) unsigned long __attribute__((weak)) get_top_of_ram(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index fc12c25..6255b18 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -96,9 +96,8 @@ static struct imd *imd_init_backing_with_recover(struct imd *backing) imd = imd_init_backing(backing); if (!ENV_RAMSTAGE) { - /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - imd_handle_init(imd, cbmem_top()); + imd_handle_init(imd, cbmem_top()); + /* Need to partially recover all the time outside of ramstage * because there's object storage outside of the stack. */ imd_handle_init_partial_recovery(imd); @@ -118,10 +117,7 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) struct imd imd_backing; imd = imd_init_backing(&imd_backing); - - /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - imd_handle_init(imd, cbmem_top()); + imd_handle_init(imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); @@ -157,10 +153,7 @@ int cbmem_initialize_id_size(u32 id, u64 size) struct imd imd_backing; imd = imd_init_backing(&imd_backing); - - /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - imd_handle_init(imd, cbmem_top()); + imd_handle_init(imd, cbmem_top()); if (imd_recover(imd)) return 1;

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New patch to review for coreboot: 2a6bd421 superio/fintek: Add support for Fintek F81866AD-I
by Fabian Kunkel 26 May '15

26 May '15

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10312 -gerrit commit 2a6bd42122f983eab5bde9a27bd9050a2d59c0be Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Tue May 26 15:37:54 2015 +0200 superio/fintek: Add support for Fintek F81866AD-I This patch adds support for the Fintek F81866AD-I SuperIO, which is very similar to the fintek/f81865f. This code adds some fan control support, inspired by fintek/f71869ad. Furthermore its possible to change the temp sensor type (thermistor or diode). Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Ibb5732f1ef475fe6ef18ad7521d22b977595c3d8 Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/superio/fintek/f81866d/Makefile.inc | 2 +- src/superio/fintek/f81866d/chip.h | 54 ++++++++++++++++++ src/superio/fintek/f81866d/f81866d.h | 4 +- src/superio/fintek/f81866d/f81866d_hwm.c | 71 +++++++++--------------- src/superio/fintek/f81866d/f81866d_temp_sensor.c | 47 ---------------- src/superio/fintek/f81866d/fintek_internal.h | 2 +- src/superio/fintek/f81866d/superio.c | 9 +-- 7 files changed, 88 insertions(+), 101 deletions(-) diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc index dd69894..2023b6c 100644 --- a/src/superio/fintek/f81866d/Makefile.inc +++ b/src/superio/fintek/f81866d/Makefile.inc @@ -1,6 +1,7 @@ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects ## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) ## @@ -19,6 +20,5 @@ ## Foundation, Inc. ## -ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_temp_sensor.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c diff --git a/src/superio/fintek/f81866d/chip.h b/src/superio/fintek/f81866d/chip.h new file mode 100644 index 0000000..9c9e799 --- /dev/null +++ b/src/superio/fintek/f81866d/chip.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_FINTEK_F81866D_CHIP_H +#define SUPERIO_FINTEK_F81866D_CHIP_H + +#include <stdint.h> + +struct superio_fintek_f81866d_config { + + /* AMD TSI */ + uint8_t hwm_amd_tsi_addr; + uint8_t hwm_amd_tsi_control; + + /* Fan control */ + uint8_t hwm_fan_select; + uint8_t hwm_fan_mode; + uint8_t hwm_fan3_control; + uint8_t hwm_fan2_temp_map_select; + + uint8_t hwm_fan2_bound1; + uint8_t hwm_fan2_bound2; + uint8_t hwm_fan2_bound3; + uint8_t hwm_fan2_bound4; + uint8_t hwm_fan2_seg1_speed; + uint8_t hwm_fan2_seg2_speed; + uint8_t hwm_fan2_seg3_speed; + uint8_t hwm_fan2_seg4_speed; + uint8_t hwm_fan2_seg5_speed; + + /* Temp sensor type */ + uint8_t hwm_temp_sens_type; +}; + +#endif /* SUPERIO_FINTEK_F81866D_CHIP_H */ diff --git a/src/superio/fintek/f81866d/f81866d.h b/src/superio/fintek/f81866d/f81866d.h index 055bb9e..70a33b6 100644 --- a/src/superio/fintek/f81866d/f81866d.h +++ b/src/superio/fintek/f81866d/f81866d.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) * @@ -21,7 +22,8 @@ /* * Datasheet: - * - Name: F81866D/A-I + * - Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P + * - Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html */ #ifndef SUPERIO_FINTEK_F81866_H diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index 073b371..bc24468 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) * @@ -28,9 +29,11 @@ #include <device/device.h> #include <device/pnp.h> #include "fintek_internal.h" +#include "chip.h" -// Set to AMD +/* Register addresses */ +// Choose between AMD and Intel #define HWM_AMD_TSI_ADDR 0x08 #define HWM_AMD_TSI_CONTROL_REG 0x0A @@ -41,39 +44,20 @@ #define HWM_FAN3_CONTROL 0x9A #define HWM_FAN_SEL 0x94 #define HWM_FAN_MODE 0x96 -#define HWM_FAN_FAST_FILTER 0x97 - -// Fan expected speed -#define HWM_FAN2_EX_SPEED1 0xB2 -#define HWM_FAN2_EX_SPEED2 0xB3 +#define HWM_FAN2_TEMP_MAP_SEL 0xBF -// 4 Boundries +// Fan 2 - 4 Boundries #define HWM_FAN2_BOUND1 0xB6 #define HWM_FAN2_BOUND2 0xB7 #define HWM_FAN2_BOUND3 0xB8 #define HWM_FAN2_BOUND4 0xB9 - -// 5 Segment Speeds +// Fan 2 - 5 Segment speeds #define HWM_FAN2_SEG1_SPEED_COUNT 0xBA #define HWM_FAN2_SEG2_SPEED_COUNT 0xBB #define HWM_FAN2_SEG3_SPEED_COUNT 0xBC #define HWM_FAN2_SEG4_SPEED_COUNT 0xBD #define HWM_FAN2_SEG5_SPEED_COUNT 0xBE -// FAN1 Temp Mapping -#define HWM_FAN2_TEMP_MAP_SEL 0xBF - -/* Defines freq. for fan control */ -#define PWM_220HZ_FAN3_CONTROL 0x20 -#define PWM_5KHZ_FAN3_CONTROL 0x20 -#define PWM_11KHZ_FAN3_CONTROL 0x00 -#define PWM_23KHZ_FAN3_CONTROL 0x00 - -#define PWM_220HZ_FAN2_MAP_SEL 0x3D -#define PWM_5KHZ_FAN2_MAP_SEL 0x1D -#define PWM_11KHZ_FAN2_MAP_SEL 0x3D -#define PWM_23KHZ_FAN2_MAP_SEL 0x1D - void f81866d_hwm_init(struct device *dev) { @@ -84,41 +68,40 @@ void f81866d_hwm_init(struct device *dev) return; } + const struct superio_fintek_f81866d_config *reg = dev->chip_info; u16 port = res->base; pnp_enter_conf_mode(dev); /* Use AMD TSI */ - pnp_write_index(port, HWM_AMD_TSI_ADDR, 0x98); - pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, 0x02); + pnp_write_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr); + pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control); - // Set temp1 sensor to thermistor - pnp_write_index(port, TEMP_SENS_TYPE_REG, 0x04); + /* Set temp1 sensor to thermistor */ + pnp_write_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type); /* Select FAN Type */ - pnp_write_index(port, HWM_FAN_SEL, 0xC0); // 0xC0 set FAN2 to PWM + pnp_write_index(port, HWM_FAN_SEL, reg->hwm_fan_select); /* Select FAN Mode*/ - pnp_write_index(port, HWM_FAN_MODE, 0xD5); // 0xD5 sets FAN1-3 to Auto RPM mode - - pnp_write_index(port, HWM_FAN_FAST_FILTER, 0x02); // Faster fan + pnp_write_index(port, HWM_FAN_MODE, reg->hwm_fan_mode); /* Set Boundries */ - pnp_write_index(port, HWM_FAN2_BOUND1, 0x3C); //60°C - pnp_write_index(port, HWM_FAN2_BOUND2, 0x32); //50°C - pnp_write_index(port, HWM_FAN2_BOUND3, 0x28); //40°C - pnp_write_index(port, HWM_FAN2_BOUND4, 0x1E); //30°C + pnp_write_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1); + pnp_write_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2); + pnp_write_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3); + pnp_write_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4); /* Set Speed */ - pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, 0xFF); // 100% - pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, 0xD9); // 85% - pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, 0xB2); // 70% - pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, 0x99); // 60% - pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, 0x80); // 50% - - /* Set temp follows */ - pnp_write_index(port, HWM_FAN3_CONTROL, PWM_220HZ_FAN3_CONTROL); - pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, PWM_220HZ_FAN2_MAP_SEL); + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed); + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed); + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed); + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed); + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed); + + /* Set Fan control freq */ + pnp_write_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control); + pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select); pnp_exit_conf_mode(dev); } diff --git a/src/superio/fintek/f81866d/f81866d_temp_sensor.c b/src/superio/fintek/f81866d/f81866d_temp_sensor.c deleted file mode 100644 index aaddd45..0000000 --- a/src/superio/fintek/f81866d/f81866d_temp_sensor.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <arch/io.h> -#include <device/device.h> -#include <device/pnp.h> -#include <console/console.h> -#include "fintek_internal.h" - -#define TEMP_SENS_TYPE_REG 0x6B - -void f81866d_temp_sensor(struct device *dev) -{ - struct resource *res = find_resource(dev, PNP_IDX_IO0); - - if (!res) { - printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); - return; - } - - u16 port = res->base; - - pnp_enter_conf_mode(dev); - - // Set temp1 sensor correct to thermistor - pnp_write_index(port, TEMP_SENS_TYPE_REG, 0x04); - - pnp_exit_conf_mode(dev); -} diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h index c198421..acd7532 100644 --- a/src/superio/fintek/f81866d/fintek_internal.h +++ b/src/superio/fintek/f81866d/fintek_internal.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) * @@ -25,7 +26,6 @@ #include <arch/io.h> #include <device/pnp.h> -void f81866d_temp_sensor(struct device *dev); void f81866d_hwm_init(struct device *dev); #endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */ diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index d12d241..a2245a0 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) * @@ -40,14 +41,8 @@ static void f81866d_init(struct device *dev) pc_keyboard_init(); break; case F81866D_HWM: - - #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - // Fixing temp sensor readout according data sheet - f81866d_temp_sensor(dev); - #else // Fixing temp sensor read out and init Fan control f81866d_hwm_init(dev); - #endif break; } } @@ -84,6 +79,6 @@ static void enable_dev(struct device *dev) } struct chip_operations superio_fintek_f81866d_ops = { - CHIP_NAME("Fintek F81866D Super I/O") + CHIP_NAME("Fintek F81866AD-I Super I/O") .enable_dev = enable_dev };

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Patch set updated for coreboot: 7c0dcce SuperIO: Add support for Fintek F81866D
by Fabian Kunkel 26 May '15

26 May '15

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10287 -gerrit commit 7c0dcce9e403b50e4a3e8e840793661b1685b4b8 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Mon May 25 17:04:28 2015 +0200 SuperIO: Add support for Fintek F81866D This patch adds support for the Fintek F81866D, which is very similar to the F81865. The F81866 adds some Fancontrol and correct temp sensor read out. Change-Id: Id2fc1119b37142f8101f71908e394ee69c45041d Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/superio/fintek/Kconfig | 4 + src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f81866d/Makefile.inc | 24 +++++ src/superio/fintek/f81866d/f81866d.h | 45 ++++++++ src/superio/fintek/f81866d/f81866d_hwm.c | 124 +++++++++++++++++++++++ src/superio/fintek/f81866d/f81866d_temp_sensor.c | 47 +++++++++ src/superio/fintek/f81866d/fintek_internal.h | 31 ++++++ src/superio/fintek/f81866d/superio.c | 89 ++++++++++++++++ 8 files changed, 365 insertions(+) diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index 2a7438b..5403e0a 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -54,3 +54,7 @@ config SUPERIO_FINTEK_F81216H config SUPERIO_FINTEK_F81865F bool select SUPERIO_FINTEK_COMMON_ROMSTAGE + +config SUPERIO_FINTEK_F81866D + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE \ No newline at end of file diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 60a7a04..40abb8a 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -28,3 +28,4 @@ subdirs-y += f71872 subdirs-y += f71889 subdirs-y += f81216h subdirs-y += f81865f +subdirs-y += f81866d diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc new file mode 100644 index 0000000..dd69894 --- /dev/null +++ b/src/superio/fintek/f81866d/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_temp_sensor.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c diff --git a/src/superio/fintek/f81866d/f81866d.h b/src/superio/fintek/f81866d/f81866d.h new file mode 100644 index 0000000..055bb9e --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* + * Datasheet: + * - Name: F81866D/A-I + */ + +#ifndef SUPERIO_FINTEK_F81866_H +#define SUPERIO_FINTEK_F81866_H + +/* Logical Device Numbers (LDN) */ +#define F81866D_FDC 0x00 /* Floppy */ +#define F81866D_SP1 0x10 /* UART1 */ +#define F81866D_SP2 0x11 /* UART2 */ +#define F81866D_SP3 0x12 /* UART3 */ +#define F81866D_SP4 0x13 /* UART4 */ +#define F81866D_SP5 0x14 /* UART3 */ +#define F81866D_SP6 0x15 /* UART4 */ +#define F81866D_PP 0x03 /* Parallel Port */ +#define F81866D_HWM 0x04 /* Hardware Monitor */ +#define F81866D_KBC 0x05 /* Keyboard/Mouse */ +#define F81866D_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81866D_WDT 0x07 /* Watchdog */ +#define F81866D_PME 0x0a /* Power Management Events (PME) */ + +#endif /* SUPERIO_FINTEK_F81866_H */ diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c new file mode 100644 index 0000000..073b371 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Setup only for Fan2 + * Todo: Add support for Fan1 and Fan3 + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" + + +// Set to AMD +#define HWM_AMD_TSI_ADDR 0x08 +#define HWM_AMD_TSI_CONTROL_REG 0x0A + +// Set temp sensors type +#define TEMP_SENS_TYPE_REG 0x6B + +// FAN prog sel +#define HWM_FAN3_CONTROL 0x9A +#define HWM_FAN_SEL 0x94 +#define HWM_FAN_MODE 0x96 +#define HWM_FAN_FAST_FILTER 0x97 + +// Fan expected speed +#define HWM_FAN2_EX_SPEED1 0xB2 +#define HWM_FAN2_EX_SPEED2 0xB3 + +// 4 Boundries +#define HWM_FAN2_BOUND1 0xB6 +#define HWM_FAN2_BOUND2 0xB7 +#define HWM_FAN2_BOUND3 0xB8 +#define HWM_FAN2_BOUND4 0xB9 + +// 5 Segment Speeds +#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA +#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB +#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC +#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD +#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE + +// FAN1 Temp Mapping +#define HWM_FAN2_TEMP_MAP_SEL 0xBF + +/* Defines freq. for fan control */ +#define PWM_220HZ_FAN3_CONTROL 0x20 +#define PWM_5KHZ_FAN3_CONTROL 0x20 +#define PWM_11KHZ_FAN3_CONTROL 0x00 +#define PWM_23KHZ_FAN3_CONTROL 0x00 + +#define PWM_220HZ_FAN2_MAP_SEL 0x3D +#define PWM_5KHZ_FAN2_MAP_SEL 0x1D +#define PWM_11KHZ_FAN2_MAP_SEL 0x3D +#define PWM_23KHZ_FAN2_MAP_SEL 0x1D + + +void f81866d_hwm_init(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + /* Use AMD TSI */ + pnp_write_index(port, HWM_AMD_TSI_ADDR, 0x98); + pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, 0x02); + + // Set temp1 sensor to thermistor + pnp_write_index(port, TEMP_SENS_TYPE_REG, 0x04); + + /* Select FAN Type */ + pnp_write_index(port, HWM_FAN_SEL, 0xC0); // 0xC0 set FAN2 to PWM + + /* Select FAN Mode*/ + pnp_write_index(port, HWM_FAN_MODE, 0xD5); // 0xD5 sets FAN1-3 to Auto RPM mode + + pnp_write_index(port, HWM_FAN_FAST_FILTER, 0x02); // Faster fan + + /* Set Boundries */ + pnp_write_index(port, HWM_FAN2_BOUND1, 0x3C); //60°C + pnp_write_index(port, HWM_FAN2_BOUND2, 0x32); //50°C + pnp_write_index(port, HWM_FAN2_BOUND3, 0x28); //40°C + pnp_write_index(port, HWM_FAN2_BOUND4, 0x1E); //30°C + + /* Set Speed */ + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, 0xFF); // 100% + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, 0xD9); // 85% + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, 0xB2); // 70% + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, 0x99); // 60% + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, 0x80); // 50% + + /* Set temp follows */ + pnp_write_index(port, HWM_FAN3_CONTROL, PWM_220HZ_FAN3_CONTROL); + pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, PWM_220HZ_FAN2_MAP_SEL); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/f81866d_temp_sensor.c b/src/superio/fintek/f81866d/f81866d_temp_sensor.c new file mode 100644 index 0000000..aaddd45 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_temp_sensor.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include "fintek_internal.h" + +#define TEMP_SENS_TYPE_REG 0x6B + +void f81866d_temp_sensor(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + // Set temp1 sensor correct to thermistor + pnp_write_index(port, TEMP_SENS_TYPE_REG, 0x04); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h new file mode 100644 index 0000000..c198421 --- /dev/null +++ b/src/superio/fintek/f81866d/fintek_internal.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_FINTEK_F81866D_INTERNAL_H +#define SUPERIO_FINTEK_F81866D_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f81866d_temp_sensor(struct device *dev); +void f81866d_hwm_init(struct device *dev); + +#endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */ diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c new file mode 100644 index 0000000..d12d241 --- /dev/null +++ b/src/superio/fintek/f81866d/superio.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f81866d.h" +#include "fintek_internal.h" + +static void f81866d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need extra code for serial, wdt etc. */ + case F81866D_KBC: + pc_keyboard_init(); + break; + case F81866D_HWM: + + #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + // Fixing temp sensor readout according data sheet + f81866d_temp_sensor(dev); + #else + // Fixing temp sensor read out and init Fan control + f81866d_hwm_init(dev); + #endif + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81866d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F81866D_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81866D_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, }, + { &ops, F81866D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81866D_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + { &ops, F81866D_GPIO, PNP_IRQ0, }, + { &ops, F81866D_PME, }, + { &ops, F81866D_WDT, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81866d_ops = { + CHIP_NAME("Fintek F81866D Super I/O") + .enable_dev = enable_dev +};

1 0

Patch merged into coreboot/master: 647456c AGESA f16kb: Fix PCI device notation
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit 647456c18ad969a0f3ddcdefaf3c9d4ea313bb20 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Mon May 25 17:16:02 2015 +0200 AGESA f16kb: Fix PCI device notation Old file defines wrong PCI devices (1.2 2.2 3.2 4.2 5.2). Wrong defines cause PCI devices not to be found in the pirq_data table. Example error output: PCI IRQ: Found device 0:02.01 using PIN A PCI Devfn (0x11) not found in pirq_data table PCI IRQ: Found device 0:02.02 using PIN B Found this device in pirq_data table entry 3 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x02 (INTC# ) INT_LINE : 0xA (IRQ 10) PCI IRQ: Found device 0:02.03 using PIN C PCI Devfn (0x13) not found in pirq_data table PCI IRQ: Found device 0:02.04 using PIN D PCI Devfn (0x14) not found in pirq_data table PCI IRQ: Found device 0:02.05 using PIN A PCI Devfn (0x15) not found in pirq_data table Patch fixes, that pirq_data entries for pci devices 2.1 - 2.5 get found. Change-Id: I4503433427f4ec90d022b65084c52077ba4f3511 Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Reviewed-on: http://review.coreboot.org/10289 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/10289 for details. -gerrit

1 0

Patch set updated for coreboot: 62958f3 Make acpi_fill_hest into parameter
by Vladimir Serbinenko 26 May '15

26 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7373 -gerrit commit 62958f3b5be759f53358623ca2a8195dca5df3c9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 13:36:18 2014 +0100 Make acpi_fill_hest into parameter This avoids the need to supply weak function and avoids associated risks of forgetting to link in relevant files. Change-Id: Ie96475babb4aa4ea8db49023af5b31bfa63b21dc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 8 ++------ src/arch/x86/include/arch/acpi.h | 4 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15rl/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 5 +++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 4 ++-- src/northbridge/amd/pi/00630F01/northbridge.c | 4 ++-- src/northbridge/amd/pi/00730F01/northbridge.c | 4 ++-- 10 files changed, 21 insertions(+), 24 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index bc2a0cc..bb994e2 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -554,11 +554,6 @@ static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } -unsigned long __attribute__((weak)) acpi_fill_hest(acpi_hest_t *hest) -{ - return (unsigned long)hest; -} - unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len) { acpi_header_t *header = &(hest->header); @@ -618,7 +613,8 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t * } /* ACPI 4.0 */ -void acpi_write_hest(acpi_hest_t *hest) +void acpi_write_hest(acpi_hest_t *hest, + unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)) { acpi_header_t *header = &(hest->header); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index eab125c..245599f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -546,10 +546,10 @@ unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment, u8 dev, u8 fn); +void acpi_write_hest(acpi_hest_t *hest, + unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)); -void acpi_write_hest(acpi_hest_t *hest); unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); -unsigned long acpi_fill_hest(acpi_hest_t *hest); void acpi_save_gnvs(u32 gnvs_address); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 70536ac..935e137 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -793,7 +793,7 @@ static void cpu_bus_init(device_t dev) /* North Bridge Structures */ -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -843,7 +843,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 3ff1515..355a458 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -815,7 +815,7 @@ static void northbridge_fill_ssdt_generator(void) acpigen_pop_len(); } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -845,7 +845,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index b251fc1..b2d8abd 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -483,7 +483,7 @@ static unsigned scan_chains(device_t dev, unsigned max) } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -534,7 +534,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 33fa927..1f11f1d 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -459,7 +459,7 @@ static void set_resources(struct device *dev) } } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -511,7 +511,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 1d2bd59..c39ebd1 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -458,7 +458,8 @@ static void nb_set_resources(device_t dev) } } -unsigned long acpi_fill_hest(acpi_hest_t *hest) + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -510,7 +511,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 2fa42ff..d1b06ec 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -459,7 +459,7 @@ static void set_resources(device_t dev) } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -511,7 +511,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index bfdfcb1..15892c6 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -453,7 +453,7 @@ static void set_resources(device_t dev) } } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -505,7 +505,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 14c7e10..c44c189 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -447,7 +447,7 @@ static void northbridge_init(struct device *dev) { } -unsigned long acpi_fill_hest(acpi_hest_t *hest) +static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; @@ -499,7 +499,7 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current); + acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length;

1 0

Patch set updated for coreboot: 9afea34 acpigen: Remove all explicit length tracking
by Vladimir Serbinenko 26 May '15

26 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7367 -gerrit commit 9afea34ea0851b6526925b4b65039e946952c1c9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 03:51:32 2014 +0100 acpigen: Remove all explicit length tracking Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 381 +++++++++++++-------------------- src/arch/x86/include/arch/acpigen.h | 72 +++---- src/cpu/intel/model_2065x/acpi.c | 16 +- src/cpu/intel/model_206ax/acpi.c | 16 +- src/soc/intel/broadwell/acpi.c | 20 +- src/soc/intel/fsp_baytrail/acpi.c | 14 +- src/southbridge/intel/lynxpoint/acpi.c | 8 +- 7 files changed, 212 insertions(+), 315 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 108d6c8..3aa823c 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -37,13 +37,12 @@ static char *gencurrent; char *len_stack[ACPIGEN_LENSTACK_SIZE]; int ltop = 0; -int acpigen_write_len_f(void) +void acpigen_write_len_f(void) { ASSERT(ltop < (ACPIGEN_LENSTACK_SIZE - 1)) len_stack[ltop++] = gencurrent; acpigen_emit_byte(0); acpigen_emit_byte(0); - return 2; } void acpigen_pop_len(void) @@ -69,31 +68,27 @@ char *acpigen_get_current(void) return gencurrent; } -int acpigen_emit_byte(unsigned char b) +void acpigen_emit_byte(unsigned char b) { (*gencurrent++) = b; - return 1; } -int acpigen_write_package(int nr_el) +void acpigen_write_package(int nr_el) { - int len; /* package op */ acpigen_emit_byte(0x12); - len = acpigen_write_len_f(); + acpigen_write_len_f(); acpigen_emit_byte(nr_el); - return len + 2; } -int acpigen_write_byte(unsigned int data) +void acpigen_write_byte(unsigned int data) { /* byte op */ acpigen_emit_byte(0xa); acpigen_emit_byte(data & 0xff); - return 2; } -int acpigen_write_dword(unsigned int data) +void acpigen_write_dword(unsigned int data) { /* dword op */ acpigen_emit_byte(0xc); @@ -101,10 +96,9 @@ int acpigen_write_dword(unsigned int data) acpigen_emit_byte((data >> 8) & 0xff); acpigen_emit_byte((data >> 16) & 0xff); acpigen_emit_byte((data >> 24) & 0xff); - return 5; } -int acpigen_write_qword(uint64_t data) +void acpigen_write_qword(uint64_t data) { /* qword op */ acpigen_emit_byte(0xe); @@ -116,40 +110,32 @@ int acpigen_write_qword(uint64_t data) acpigen_emit_byte((data >> 40) & 0xff); acpigen_emit_byte((data >> 48) & 0xff); acpigen_emit_byte((data >> 56) & 0xff); - return 9; } -int acpigen_write_name_byte(const char *name, uint8_t val) +void acpigen_write_name_byte(const char *name, uint8_t val) { - int len; - len = acpigen_write_name(name); - len += acpigen_write_byte(val); - return len; + acpigen_write_name(name); + acpigen_write_byte(val); } -int acpigen_write_name_dword(const char *name, uint32_t val) +void acpigen_write_name_dword(const char *name, uint32_t val) { - int len; - len = acpigen_write_name(name); - len += acpigen_write_dword(val); - return len; + acpigen_write_name(name); + acpigen_write_dword(val); } -int acpigen_write_name_qword(const char *name, uint64_t val) +void acpigen_write_name_qword(const char *name, uint64_t val) { - int len; - len = acpigen_write_name(name); - len += acpigen_write_qword(val); - return len; + acpigen_write_name(name); + acpigen_write_qword(val); } -int acpigen_emit_stream(const char *data, int size) +void acpigen_emit_stream(const char *data, int size) { int i; for (i = 0; i < size; i++) { acpigen_emit_byte(data[i]); } - return size; } /* @@ -161,39 +147,36 @@ int acpigen_emit_stream(const char *data, int size) * Check sections 5.3, 18.2.2 and 18.4 of ACPI spec 3.0 for details. */ -static int acpigen_emit_simple_namestring(const char *name) { - int i, len = 0; +static void acpigen_emit_simple_namestring(const char *name) { + int i; char ud[] = "____"; for (i = 0; i < 4; i++) { if ((name[i] == '\0') || (name[i] == '.')) { - len += acpigen_emit_stream(ud, 4 - i); + acpigen_emit_stream(ud, 4 - i); break; } else { - len += acpigen_emit_byte(name[i]); + acpigen_emit_byte(name[i]); } } - return len; } -static int acpigen_emit_double_namestring(const char *name, int dotpos) { - int len = 0; +static void acpigen_emit_double_namestring(const char *name, int dotpos) { /* mark dual name prefix */ - len += acpigen_emit_byte(0x2e); - len += acpigen_emit_simple_namestring(name); - len += acpigen_emit_simple_namestring(&name[dotpos + 1]); - return len; + acpigen_emit_byte(0x2e); + acpigen_emit_simple_namestring(name); + acpigen_emit_simple_namestring(&name[dotpos + 1]); } -static int acpigen_emit_multi_namestring(const char *name) { - int len = 0, count = 0; +static void acpigen_emit_multi_namestring(const char *name) { + int count = 0; unsigned char *pathlen; /* mark multi name prefix */ - len += acpigen_emit_byte(0x2f); - len += acpigen_emit_byte(0x0); + acpigen_emit_byte(0x2f); + acpigen_emit_byte(0x0); pathlen = ((unsigned char *) acpigen_get_current()) - 1; while (name[0] != '\0') { - len += acpigen_emit_simple_namestring(name); + acpigen_emit_simple_namestring(name); /* find end or next entity */ while ((name[0] != '.') && (name[0] != '\0')) name++; @@ -204,32 +187,30 @@ static int acpigen_emit_multi_namestring(const char *name) { } pathlen[0] = count; - return len; } -int acpigen_emit_namestring(const char *namepath) { +void acpigen_emit_namestring(const char *namepath) { int dotcount = 0, i; int dotpos = 0; - int len = 0; /* We can start with a '\'. */ if (namepath[0] == '\\') { - len += acpigen_emit_byte('\\'); + acpigen_emit_byte('\\'); namepath++; } /* And there can be any number of '^' */ while (namepath[0] == '^') { - len += acpigen_emit_byte('^'); + acpigen_emit_byte('^'); namepath++; } /* If we have only \\ or only ^...^. Then we need to put a null name (0x00). */ if(namepath[0] == '\0') { - len += acpigen_emit_byte(0x00); - return len; + acpigen_emit_byte(0x00); + return; } i = 0; @@ -242,58 +223,53 @@ int acpigen_emit_namestring(const char *namepath) { } if (dotcount == 0) { - len += acpigen_emit_simple_namestring(namepath); + acpigen_emit_simple_namestring(namepath); } else if (dotcount == 1) { - len += acpigen_emit_double_namestring(namepath, dotpos); + acpigen_emit_double_namestring(namepath, dotpos); } else { - len += acpigen_emit_multi_namestring(namepath); + acpigen_emit_multi_namestring(namepath); } - return len; } -int acpigen_write_name(const char *name) +void acpigen_write_name(const char *name) { - int len; /* name op */ - len = acpigen_emit_byte(0x8); - return len + acpigen_emit_namestring(name); + acpigen_emit_byte(0x8); + acpigen_emit_namestring(name); } -int acpigen_write_scope(const char *name) +void acpigen_write_scope(const char *name) { - int len; /* scope op */ - len = acpigen_emit_byte(0x10); - len += acpigen_write_len_f(); - return len + acpigen_emit_namestring(name); + acpigen_emit_byte(0x10); + acpigen_write_len_f(); + acpigen_emit_namestring(name); } -int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) +void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) { */ char pscope[16]; - int len; /* processor op */ acpigen_emit_byte(0x5b); acpigen_emit_byte(0x83); - len = acpigen_write_len_f(); + acpigen_write_len_f(); snprintf(pscope, sizeof (pscope), "\\_PR.CP%02d", (unsigned int) cpuindex); - len += acpigen_emit_namestring(pscope); + acpigen_emit_namestring(pscope); acpigen_emit_byte(cpuindex); acpigen_emit_byte(pblock_addr & 0xff); acpigen_emit_byte((pblock_addr >> 8) & 0xff); acpigen_emit_byte((pblock_addr >> 16) & 0xff); acpigen_emit_byte((pblock_addr >> 24) & 0xff); acpigen_emit_byte(pblock_len); - return 6 + 2 + len; } -int acpigen_write_empty_PCT(void) +void acpigen_write_empty_PCT(void) { /* Name (_PCT, Package (0x02) @@ -326,10 +302,10 @@ int acpigen_write_empty_PCT(void) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */ 0x00, 0x79, 0x00 }; - return acpigen_emit_stream(stream, ARRAY_SIZE(stream)); + acpigen_emit_stream(stream, ARRAY_SIZE(stream)); } -int acpigen_write_empty_PTC(void) +void acpigen_write_empty_PTC(void) { /* Name (_PTC, Package (0x02) @@ -353,7 +329,6 @@ int acpigen_write_empty_PTC(void) } }) */ - int len, nlen, rlen; acpi_addr_t addr = { .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = 0, @@ -365,55 +340,44 @@ int acpigen_write_empty_PTC(void) .addrh = 0, }; - nlen = acpigen_write_name("_PTC"); - len = acpigen_write_package(2); + acpigen_write_name("_PTC"); + acpigen_write_package(2); /* ControlRegister */ - rlen = acpigen_write_resourcetemplate_header(); - rlen += acpigen_write_register(&addr); - len += acpigen_write_resourcetemplate_footer(); - len += rlen; + acpigen_write_resourcetemplate_header(); + acpigen_write_register(&addr); + acpigen_write_resourcetemplate_footer(); /* StatusRegister */ - rlen = acpigen_write_resourcetemplate_header(); - rlen += acpigen_write_register(&addr); - len += acpigen_write_resourcetemplate_footer(); - len += rlen; + acpigen_write_resourcetemplate_header(); + acpigen_write_register(&addr); + acpigen_write_resourcetemplate_footer(); acpigen_pop_len(); - return len + nlen; } -int acpigen_write_method(const char *name, int nargs) +void acpigen_write_method(const char *name, int nargs) { - int len; - /* method op */ - len = acpigen_emit_byte(0x14); - len += acpigen_write_len_f(); - len += acpigen_emit_namestring(name); - len += acpigen_emit_byte(nargs & 7); - - return len; + acpigen_emit_byte(0x14); + acpigen_write_len_f(); + acpigen_emit_namestring(name); + acpigen_emit_byte(nargs & 7); } -int acpigen_write_device(const char *name) +void acpigen_write_device(const char *name) { - int len; - /* method op */ - len = acpigen_emit_byte(0x5b); - len += acpigen_emit_byte(0x82); - len += acpigen_write_len_f(); - len += acpigen_emit_namestring(name); - - return len; + acpigen_emit_byte(0x5b); + acpigen_emit_byte(0x82); + acpigen_write_len_f(); + acpigen_emit_namestring(name); } /* * Generates a func with max supported P-states. */ -int acpigen_write_PPC(u8 nr) +void acpigen_write_PPC(u8 nr) { /* Method (_PPC, 0, NotSerialized) @@ -421,23 +385,19 @@ int acpigen_write_PPC(u8 nr) Return (nr) } */ - int len; - len = acpigen_write_method("_PPC", 0); + acpigen_write_method("_PPC", 0); /* return */ acpigen_emit_byte(0xa4); /* arg */ - len += acpigen_write_byte(nr); - /* add all single bytes */ - len += 1; + acpigen_write_byte(nr); acpigen_pop_len(); - return len; } /* * Generates a func with max supported P-states saved * in the variable PPCM. */ -int acpigen_write_PPC_NVS(void) +void acpigen_write_PPC_NVS(void) { /* Method (_PPC, 0, NotSerialized) @@ -445,20 +405,15 @@ int acpigen_write_PPC_NVS(void) Return (PPCM) } */ - int len; - - len = acpigen_write_method("_PPC", 0); + acpigen_write_method("_PPC", 0); /* return */ acpigen_emit_byte(0xa4); /* arg */ - len += acpigen_emit_namestring("PPCM"); - /* add all single bytes */ - len += 1; + acpigen_emit_namestring("PPCM"); acpigen_pop_len(); - return len; } -int acpigen_write_TPC(const char *gnvs_tpc_limit) +void acpigen_write_TPC(const char *gnvs_tpc_limit) { /* // Sample _TPC method @@ -467,88 +422,68 @@ int acpigen_write_TPC(const char *gnvs_tpc_limit) Return (\TLVL) } */ - int len; - - len = acpigen_write_method("_TPC", 0); - len += acpigen_emit_byte(0xa4); /* ReturnOp */ - len += acpigen_emit_namestring(gnvs_tpc_limit); + acpigen_write_method("_TPC", 0); + acpigen_emit_byte(0xa4); /* ReturnOp */ + acpigen_emit_namestring(gnvs_tpc_limit); acpigen_pop_len(); - return len; } -int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, +void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status) { - int len; - len = acpigen_write_package(6); - len += acpigen_write_dword(coreFreq); - len += acpigen_write_dword(power); - len += acpigen_write_dword(transLat); - len += acpigen_write_dword(busmLat); - len += acpigen_write_dword(control); - len += acpigen_write_dword(status); - // pkglen without the len opcode + acpigen_write_package(6); + acpigen_write_dword(coreFreq); + acpigen_write_dword(power); + acpigen_write_dword(transLat); + acpigen_write_dword(busmLat); + acpigen_write_dword(control); + acpigen_write_dword(status); acpigen_pop_len(); printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n", coreFreq, power, control, status); - - return len; } -int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) +void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) { - int len, lenh, lenp; - lenh = acpigen_write_name("_PSD"); - lenp = acpigen_write_package(1); - len = acpigen_write_package(5); - len += acpigen_write_byte(5); // 5 values - len += acpigen_write_byte(0); // revision 0 - len += acpigen_write_dword(domain); - len += acpigen_write_dword(coordtype); - len += acpigen_write_dword(numprocs); + acpigen_write_name("_PSD"); + acpigen_write_package(1); + acpigen_write_package(5); + acpigen_write_byte(5); // 5 values + acpigen_write_byte(0); // revision 0 + acpigen_write_dword(domain); + acpigen_write_dword(coordtype); + acpigen_write_dword(numprocs); acpigen_pop_len(); - len += lenp; acpigen_pop_len(); - return len + lenh; } -int acpigen_write_CST_package_entry(acpi_cstate_t *cstate) +void acpigen_write_CST_package_entry(acpi_cstate_t *cstate) { - int len, len0; - char *start, *end; - - len0 = acpigen_write_package(4); - len = acpigen_write_resourcetemplate_header(); - start = acpigen_get_current(); + acpigen_write_package(4); + acpigen_write_resourcetemplate_header(); acpigen_write_register(&cstate->resource); - end = acpigen_get_current(); - len += end - start; - len += acpigen_write_resourcetemplate_footer(); - len += len0; - len += acpigen_write_dword(cstate->ctype); - len += acpigen_write_dword(cstate->latency); - len += acpigen_write_dword(cstate->power); + acpigen_write_resourcetemplate_footer(); + acpigen_write_dword(cstate->ctype); + acpigen_write_dword(cstate->latency); + acpigen_write_dword(cstate->power); acpigen_pop_len(); - return len; } -int acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) +void acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) { - int len, lenh, lenp, i; - lenh = acpigen_write_name("_CST"); - lenp = acpigen_write_package(nentries+1); - len = acpigen_write_dword(nentries); + int i; + acpigen_write_name("_CST"); + acpigen_write_package(nentries+1); + acpigen_write_dword(nentries); for (i = 0; i < nentries; i++) - len += acpigen_write_CST_package_entry(cstate + i); + acpigen_write_CST_package_entry(cstate + i); - len += lenp; acpigen_pop_len(); - return len + lenh; } -int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) +void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) { /* Sample _TSS package with 100% and 50% duty cycles @@ -558,48 +493,43 @@ int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) Package(){50, 520, 0, 0x18, 0) }) */ - int i, len, plen, nlen; + int i; acpi_tstate_t *tstate = tstate_list; - nlen = acpigen_write_name("_TSS"); - plen = acpigen_write_package(entries); + acpigen_write_name("_TSS"); + acpigen_write_package(entries); for (i = 0; i < entries; i++) { - len = acpigen_write_package(5); - len += acpigen_write_dword(tstate->percent); - len += acpigen_write_dword(tstate->power); - len += acpigen_write_dword(tstate->latency); - len += acpigen_write_dword(tstate->control); - len += acpigen_write_dword(tstate->status); + acpigen_write_package(5); + acpigen_write_dword(tstate->percent); + acpigen_write_dword(tstate->power); + acpigen_write_dword(tstate->latency); + acpigen_write_dword(tstate->control); + acpigen_write_dword(tstate->status); acpigen_pop_len(); tstate++; - plen += len; } acpigen_pop_len(); - return plen + nlen; } -int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) +void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) { - int len, lenh, lenp; - lenh = acpigen_write_name("_TSD"); - lenp = acpigen_write_package(1); - len = acpigen_write_package(5); - len += acpigen_write_byte(5); // 5 values - len += acpigen_write_byte(0); // revision 0 - len += acpigen_write_dword(domain); - len += acpigen_write_dword(coordtype); - len += acpigen_write_dword(numprocs); + acpigen_write_name("_TSD"); + acpigen_write_package(1); + acpigen_write_package(5); + acpigen_write_byte(5); // 5 values + acpigen_write_byte(0); // revision 0 + acpigen_write_dword(domain); + acpigen_write_dword(coordtype); + acpigen_write_dword(numprocs); acpigen_pop_len(); - len += lenp; acpigen_pop_len(); - return len + lenh; } -int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) +void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) { /* * acpi 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor @@ -621,10 +551,9 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) acpigen_emit_byte((size >> 8) & 0xff); acpigen_emit_byte((size >> 16) & 0xff); acpigen_emit_byte((size >> 24) & 0xff); - return 12; } -int acpigen_write_register(acpi_addr_t *addr) +void acpigen_write_register(acpi_addr_t *addr) { acpigen_emit_byte(0x82); /* Register Descriptor */ acpigen_emit_byte(0x0c); /* Register Length 7:0 */ @@ -641,10 +570,9 @@ int acpigen_write_register(acpi_addr_t *addr) acpigen_emit_byte((addr->addrh >> 8) & 0xff); acpigen_emit_byte((addr->addrh >> 16) & 0xff); acpigen_emit_byte((addr->addrh >> 24) & 0xff); - return 15; } -int acpigen_write_irq(u16 mask) +void acpigen_write_irq(u16 mask) { /* * acpi 3.0b section 6.4.2.1: IRQ Descriptor @@ -656,10 +584,9 @@ int acpigen_write_irq(u16 mask) acpigen_emit_byte(0x22); acpigen_emit_byte(mask & 0xff); acpigen_emit_byte((mask >> 8) & 0xff); - return 3; } -int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) +void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) { /* * acpi 4.0 section 6.4.2.6: I/O Port Descriptor @@ -681,28 +608,25 @@ int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) /* alignment for min base */ acpigen_emit_byte(align & 0xff); acpigen_emit_byte(len & 0xff); - return 8; } -int acpigen_write_resourcetemplate_header(void) +void acpigen_write_resourcetemplate_header(void) { - int len; /* * A ResourceTemplate() is a Buffer() with a * (Byte|Word|DWord) containing the length, followed by one or more * resource items, terminated by the end tag. * (small item 0xf, len 1) */ - len = acpigen_emit_byte(0x11); /* Buffer opcode */ - len += acpigen_write_len_f(); - len += acpigen_emit_byte(0x0b); /* Word opcode */ + acpigen_emit_byte(0x11); /* Buffer opcode */ + acpigen_write_len_f(); + acpigen_emit_byte(0x0b); /* Word opcode */ len_stack[ltop++] = acpigen_get_current(); - len += acpigen_emit_byte(0x00); - len += acpigen_emit_byte(0x00); - return len; + acpigen_emit_byte(0x00); + acpigen_emit_byte(0x00); } -int acpigen_write_resourcetemplate_footer(void) +void acpigen_write_resourcetemplate_footer(void) { char *p = len_stack[--ltop]; int len; @@ -722,7 +646,6 @@ int acpigen_write_resourcetemplate_footer(void) p[1] = (len >> 8) & 0xff; /* patch len field */ acpigen_pop_len(); - return 2; } static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, @@ -744,13 +667,9 @@ static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, } } -int acpigen_write_mainboard_resource_template(void) +void acpigen_write_mainboard_resource_template(void) { - int len; - char *start; - char *end; - len = acpigen_write_resourcetemplate_header(); - start = acpigen_get_current(); + acpigen_write_resourcetemplate_header(); /* Add reserved memory ranges. */ search_global_resources( @@ -764,20 +683,15 @@ int acpigen_write_mainboard_resource_template(void) IORESOURCE_IO | IORESOURCE_RESERVE, acpigen_add_mainboard_rsvd_io, 0); - end = acpigen_get_current(); - len += end-start; - len += acpigen_write_resourcetemplate_footer(); - return len; + acpigen_write_resourcetemplate_footer(); } -int acpigen_write_mainboard_resources(const char *scope, const char *name) +void acpigen_write_mainboard_resources(const char *scope, const char *name) { - int len; - len = acpigen_write_scope(scope); - len += acpigen_write_name(name); - len += acpigen_write_mainboard_resource_template(); + acpigen_write_scope(scope); + acpigen_write_name(name); + acpigen_write_mainboard_resource_template(); acpigen_pop_len(); - return len; } static int hex2bin(const char c) @@ -789,7 +703,7 @@ static int hex2bin(const char c) return c - '0'; } -int acpigen_emit_eisaid(const char *eisaid) +void acpigen_emit_eisaid(const char *eisaid) { u32 compact = 0; @@ -811,5 +725,4 @@ int acpigen_emit_eisaid(const char *eisaid) acpigen_emit_byte((compact >> 16) & 0xff); acpigen_emit_byte((compact >> 8) & 0xff); acpigen_emit_byte(compact & 0xff); - return 5; } diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 55bc87f..a3e65eb 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -25,47 +25,47 @@ #include <stdint.h> #include <arch/acpi.h> -int acpigen_write_len_f(void); +void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); char *acpigen_get_current(void); -int acpigen_write_package(int nr_el); -int acpigen_write_byte(unsigned int data); -int acpigen_emit_byte(unsigned char data); -int acpigen_emit_stream(const char *data, int size); -int acpigen_emit_namestring(const char *namepath); -int acpigen_emit_eisaid(const char *eisaid); -int acpigen_write_dword(unsigned int data); -int acpigen_write_qword(uint64_t data); -int acpigen_write_name(const char *name); -int acpigen_write_name_dword(const char *name, uint32_t val); -int acpigen_write_name_qword(const char *name, uint64_t val); -int acpigen_write_name_byte(const char *name, uint8_t val); -int acpigen_write_scope(const char *name); -int acpigen_write_method(const char *name, int nargs); -int acpigen_write_device(const char *name); -int acpigen_write_PPC(u8 nr); -int acpigen_write_PPC_NVS(void); -int acpigen_write_empty_PCT(void); -int acpigen_write_empty_PTC(void); -int acpigen_write_TPC(const char *gnvs_tpc_limit); -int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, +void acpigen_write_package(int nr_el); +void acpigen_write_byte(unsigned int data); +void acpigen_emit_byte(unsigned char data); +void acpigen_emit_stream(const char *data, int size); +void acpigen_emit_namestring(const char *namepath); +void acpigen_emit_eisaid(const char *eisaid); +void acpigen_write_dword(unsigned int data); +void acpigen_write_qword(uint64_t data); +void acpigen_write_name(const char *name); +void acpigen_write_name_dword(const char *name, uint32_t val); +void acpigen_write_name_qword(const char *name, uint64_t val); +void acpigen_write_name_byte(const char *name, uint8_t val); +void acpigen_write_scope(const char *name); +void acpigen_write_method(const char *name, int nargs); +void acpigen_write_device(const char *name); +void acpigen_write_PPC(u8 nr); +void acpigen_write_PPC_NVS(void); +void acpigen_write_empty_PCT(void); +void acpigen_write_empty_PTC(void); +void acpigen_write_TPC(const char *gnvs_tpc_limit); +void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; -int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -int acpigen_write_CST_package_entry(acpi_cstate_t *cstate); -int acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); -int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); -int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); -int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); -int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); -int acpigen_write_register(acpi_addr_t *addr); -int acpigen_write_resourcetemplate_header(void); -int acpigen_write_resourcetemplate_footer(void); -int acpigen_write_mainboard_resource_template(void); -int acpigen_write_mainboard_resources(const char *scope, const char *name); -int acpigen_write_irq(u16 mask); +void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); +void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); +void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); +void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); +void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); +void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); +void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); +void acpigen_write_register(acpi_addr_t *addr); +void acpigen_write_resourcetemplate_header(void); +void acpigen_write_resourcetemplate_footer(void); +void acpigen_write_mainboard_resource_template(void); +void acpigen_write_mainboard_resources(const char *scope, const char *name); +void acpigen_write_irq(u16 mask); int get_cst_entries(acpi_cstate_t **); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 1535823..1e4bb03 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -152,31 +152,27 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 30b19e9..47c958a 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -152,31 +152,27 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 153831b..67220c5 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -365,34 +365,30 @@ static acpi_tstate_t tss_table_coarse[] = { { 13, 125, 0, 0x19, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set a T-state limit that can be modified in NVS */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* * CPUID.(EAX=6):EAX[5] indicates support * for extended throttle levels. */ if (cpuid_eax(6) & (1 << 5)) - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_fine), tss_table_fine); else - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(tss_table_coarse), tss_table_coarse); - - return len; } -static int generate_C_state_entries(void) +static void generate_C_state_entries(void) { device_t dev = SA_DEV_ROOT; config_t *config = dev->chip_info; @@ -411,7 +407,7 @@ static int generate_C_state_entries(void) } /* Generate C-state tables */ - return acpigen_write_CST_package(map, ARRAY_SIZE(map)); + acpigen_write_CST_package(map, ARRAY_SIZE(map)); } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index e32d3de..1a0c0ce 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -361,24 +361,20 @@ static acpi_tstate_t baytrail_tss_table[] = { { 13, 125, 0, 0x12, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static void generate_T_state_entries(int core, int cores_per_package) { - int len; - /* Indicate SW_ALL coordination for T-states */ - len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); /* Indicate FFixedHW so OS will use MSR */ - len += acpigen_write_empty_PTC(); + acpigen_write_empty_PTC(); /* Set NVS controlled T-state limit */ - len += acpigen_write_TPC("\\TLVL"); + acpigen_write_TPC("\\TLVL"); /* Write TSS table for MSR access */ - len += acpigen_write_TSS_package( + acpigen_write_TSS_package( ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); - - return len; } static int calculate_power(int tdp, int p1_ratio, int ratio) diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 0f00a95..22f8921 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -57,18 +57,18 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } -static int acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) +static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) { char sio_name[5] = {}; snprintf(sio_name, sizeof (sio_name), "S%1uEN", id); - return acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); + acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); } void acpi_create_serialio_ssdt(acpi_header_t *ssdt) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - int id, len = 0; + int id; if (!gnvs) return; @@ -87,7 +87,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) /* Fill the SSDT with an entry for each SerialIO device */ for (id = 0; id < 8; id++) - len += acpi_create_serialio_ssdt_entry(id, gnvs); + acpi_create_serialio_ssdt_entry(id, gnvs); /* (Re)calculate length and checksum. */ current = (unsigned long)acpigen_get_current();

1 0

Patch set updated for coreboot: b91f6df acpigen: Remove acpigen_patch_len
by Vladimir Serbinenko 26 May '15

26 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7365 -gerrit commit b91f6df3ee1d4a01efdc3c7776a88e1cf583cf25 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 03:33:51 2014 +0100 acpigen: Remove acpigen_patch_len Change-Id: I77276342b3f44c7c845a10682ff1f15599c4c721 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 13 +------------ src/arch/x86/include/arch/acpigen.h | 1 - 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 0fb400e..108d6c8 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -22,7 +22,7 @@ /* * If you need to change this, change acpigen_write_f and - * acpigen_patch_len + * acpigen_pop_len */ #define ACPIGEN_MAXLEN 0xfff @@ -46,17 +46,6 @@ int acpigen_write_len_f(void) return 2; } -void acpigen_patch_len(int len) -{ - ASSERT(len <= ACPIGEN_MAXLEN) - ASSERT(ltop > 0) - char *p = len_stack[--ltop]; - /* generate store length for 0xfff max */ - p[0] = (0x40 | (len & 0xf)); - p[1] = (len >> 4 & 0xff); - -} - void acpigen_pop_len(void) { int len; diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index b84a979..55bc87f 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -26,7 +26,6 @@ #include <arch/acpi.h> int acpigen_write_len_f(void); -void acpigen_patch_len(int len); void acpigen_pop_len(void); void acpigen_set_current(char *curr); char *acpigen_get_current(void);

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Patch merged into coreboot/master: 8ac29e8 speedstep: Don't supply weak get_cst_entries.
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit 8ac29e89b6c1614d9eee3dfee3ea5977f6d0e4a9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 9 12:59:29 2014 +0100 speedstep: Don't supply weak get_cst_entries. This should be overriden by mobo even if it's no-op override. weak function in this case would only hide real problems. Change-Id: I30dd671eb605b490a51153d00ae308c4bdef3d05 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/7368 for details. -gerrit

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Patch merged into coreboot/master: 351fefc ACPI: slic support
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit 351fefc452ed70fe53ea84cb91a50bfb7abc6c0a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Oct 26 20:42:08 2014 +0100 ACPI: slic support Export SLIC table from file in CBFS. Change-Id: Id0e7fe0a49b9cd50b5e43cd15030e1c2098728ec Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7202 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7202 for details. -gerrit

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coreboot-gerrit May 2015