coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: e1fb052 CBMEM: Fix S3 resume path without EARLY_CBMEM_INIT
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit e1fb052ed70b0471ece637f37db01bde6d4b9076 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 00:30:10 2015 +0300 CBMEM: Fix S3 resume path without EARLY_CBMEM_INIT Implementation for cbmem_find() did not work for boards without EARLY_CBMEM_INIT in romstage. This is required for S3 resume to work on AGESA plaforms. First broken with commit 0dff57d cbmem: switch over to imd-based cbmem Change-Id: I9c1a4f6839f5d90f825787baad2a3824a04b5bdc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/10299 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10299 for details. -gerrit

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Patch merged into coreboot/master: 28d5ec9 x86: provide consistent cbmem_top() for CONFIG_LATE_CBMEM_INIT
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit 28d5ec9a7d8fe11175c8907cc6fa0305c469b194 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 26 11:15:45 2015 -0500 x86: provide consistent cbmem_top() for CONFIG_LATE_CBMEM_INIT For x86 systems employing CONFIG_LATE_CBMEM_INIT, set_top_of_ram() is called in ramstage to note the upper address of the 32-bit address space. This in turn is consumed by cbmem. However, in this scenario cbmem_top() cannot always be relied upon because get_top_of_ram() doesn't return the same value provided to set_top_of_ram(). To fix the inconsistency in ramstage save the value passed in to set_top_of_ram() and defer to it as the return value for cbmem_top(). Change-Id: Ida796fb836c59b9776019e7f8b3f2cd71156f0e5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10313 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10313 for details. -gerrit

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Patch merged into coreboot/master: aadf2b8 consoles: remove unused infrastructure
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit aadf2b8b59adec05a84e4884ba76bc2ebc4d9b00 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 21 14:54:18 2015 -0500 consoles: remove unused infrastructure The __console attribute as well as linker binding was dropped at some point. Kill of the dead code and infrastructure. Change-Id: I15e1fb4468fffe2e148ec9ac8539dfd958551807 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10279 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/10279 for details. -gerrit

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Patch set updated for coreboot: 07c8e0c x86: provide consistent cbmem_top() for CONFIG_LATE_CBMEM_INIT
by Aaron Durbin 26 May '15

26 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10313 -gerrit commit 07c8e0c1b6016fedf295c2ec031cc1348548b115 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 26 11:15:45 2015 -0500 x86: provide consistent cbmem_top() for CONFIG_LATE_CBMEM_INIT For x86 systems employing CONFIG_LATE_CBMEM_INIT, set_top_of_ram() is called in ramstage to note the upper address of the 32-bit address space. This in turn is consumed by cbmem. However, in this scenario cbmem_top() cannot always be relied upon because get_top_of_ram() doesn't return the same value provided to set_top_of_ram(). To fix the inconsistency in ramstage save the value passed in to set_top_of_ram() and defer to it as the return value for cbmem_top(). Change-Id: Ida796fb836c59b9776019e7f8b3f2cd71156f0e5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/cbmem.c | 20 +++++++++++++++++++- src/include/cbmem.h | 3 +++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 9ee5db4..f48e46a 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -34,10 +34,23 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ } +static void *ramtop_pointer; + void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); - cbmem_set_top((void*)(uintptr_t)ramtop); + ramtop_pointer = (void *)(uintptr_t)ramtop; + cbmem_set_top(ramtop_pointer); +} + +static inline void *saved_ramtop(void) +{ + return ramtop_pointer; +} +#else +static inline void *saved_ramtop(void) +{ + return NULL; } #endif /* !__PRE_RAM__ */ @@ -50,6 +63,11 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ + void *ptr = saved_ramtop(); + + if (ptr != NULL) + return ptr; + return (void *)get_top_of_ram(); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 20cc174..0a7ca89 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -221,6 +221,9 @@ void cbmem_list(void); * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. */ #if IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +/* Note that many of the current providers of get_top_of_ram() conditionally + * return 0 when the sleep type is non S3. i.e. cold and warm boots would + * return 0 from get_top_of_ram(). */ unsigned long get_top_of_ram(void); void set_top_of_ram(uint64_t ramtop); void backup_top_of_ram(uint64_t ramtop);

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Patch set updated for coreboot: 46ee141 timestamp: Fix collection without EARLY_CBMEM_INIT
by Aaron Durbin 26 May '15

26 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10300 -gerrit commit 46ee14121fcc6a6e4e3e78c93c309d25a3bd0e31 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 06:23:02 2015 +0300 timestamp: Fix collection without EARLY_CBMEM_INIT With LATE_CBMEM_INIT, do not search for the initial collection from CBMEM in ramstage. On S3 resume this would find the non-empty collection from previous run of ramstage. Start with an empty table instead. Remove a spurious error message as the stamps get stashed and will be copied to CBMEM later. Change-Id: Ib94049531c0ac23af25407bd2ca7644ee0163d69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/timestamp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 98ab243..8c82649 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -42,10 +42,8 @@ static void timestamp_real_init(uint64_t base) sizeof(struct timestamp_table) + MAX_TIMESTAMPS * sizeof(struct timestamp_entry)); - if (!tst) { - printk(BIOS_ERR, "ERROR: failed to allocate timestamp table\n"); + if (!tst) return; - } tst->base_time = base; tst->max_entries = MAX_TIMESTAMPS; @@ -142,10 +140,12 @@ void timestamp_init(uint64_t base) /* Copy of basetime, it is too early for CBMEM. */ car_set_var(ts_basetime, base); #else - struct timestamp_table* tst; + struct timestamp_table *tst = NULL; /* Locate and use an already existing table. */ - tst = cbmem_find(CBMEM_ID_TIMESTAMP); + if (!IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) + tst = cbmem_find(CBMEM_ID_TIMESTAMP); + if (tst) { car_set_var(ts_table_p, tst); return;

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Patch set updated for coreboot: de74212 CBMEM console: Fix buffer without EARLY_CBMEM_INIT
by Aaron Durbin 26 May '15

26 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10301 -gerrit commit de74212e5d1d6f61740ce90387da2b6bfb764473 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 06:46:41 2015 +0300 CBMEM console: Fix buffer without EARLY_CBMEM_INIT On S3 resume, CBMEM_ID_CONSOLE from previous boot is found in ramstage, even when romstage did not create it. So buffer did not get cleared on S3 resume path. Also do not allocate for preram_cbmem_console in CAR when there are no means to back it up to ram. Change-Id: I175cebbb938adf2a7414703fefffb8da796e9fa9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/romstage.ld | 2 +- src/lib/cbmem_console.c | 7 ++----- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 27e8de1..ae7049b 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -65,7 +65,7 @@ SECTIONS * statically checked because the cache-as-ram region usage is * cpu/chipset dependent. */ _preram_cbmem_console = .; - _epreram_cbmem_console = . + 0xc00; + _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); } /* Global variables are not allowed in romstage diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 30bf439..e9607f3 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -225,11 +225,8 @@ void cbmemc_reinit(void) /* Need to reset the newly added cbmem console in ramstage * when there was no console in preram environment. */ - if (ENV_RAMSTAGE) { - cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); - if (cbm_cons_p == NULL) - flags |= CBMEMC_RESET; - } + if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) + flags |= CBMEMC_RESET; /* If CBMEM entry already existed, old contents is not altered. */ cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, size);

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Patch set updated for coreboot: 1ff4c2f cbmem: remove cbmem_set_top()
by Aaron Durbin 26 May '15

26 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10314 -gerrit commit 1ff4c2fa2e61011321489d178ffa6400eaa7c1f6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 26 11:26:34 2015 -0500 cbmem: remove cbmem_set_top() Now that the users of cbmem_set_top() always provide a consistent cbmem_top() value there's no need to have cbmem_set_top() around. Therefore, delete it. Change-Id: I0c96e2b8b829eddbeb1fdf755ed59c51ea689d1b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/boot/cbmem.c | 1 - src/include/cbmem.h | 3 --- src/lib/imd_cbmem.c | 14 -------------- 3 files changed, 18 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index ad8aacb..a9127d7 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -40,7 +40,6 @@ void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); ramtop_pointer = (void *)(uintptr_t)ramtop; - cbmem_set_top(ramtop_pointer); } static inline void *saved_ramtop(void) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 0a7ca89..a8ab3cd 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -176,9 +176,6 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size); * below 4GiB. */ void *cbmem_top(void); -/* Set the top address for dynamic cbmem. Not for new designs. */ -void cbmem_set_top(void *ramtop); - /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original * size. */ diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 6255b18..d1ff57d 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -40,20 +40,6 @@ static inline struct imd *cbmem_get_imd(void) return NULL; } -/* - * x86 !CONFIG_EARLY_CBMEM_INIT platforms need to do the following in ramstage: - * 1. Call set_top_of_ram() which in turn calls cbmem_set_top(). - * 2. Provide a get_top_of_ram() implementation. - * - * CONFIG_EARLY_CBMEM_INIT platforms just need to provide cbmem_top(). - */ -void cbmem_set_top(void *ramtop) -{ - struct imd *imd = cbmem_get_imd(); - - imd_handle_init(imd, ramtop); -} - static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { return (const struct cbmem_entry *)e;

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Patch set updated for coreboot: e6f25cf CBMEM: Fix S3 resume path without EARLY_CBMEM_INIT
by Aaron Durbin 26 May '15

26 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10299 -gerrit commit e6f25cf80d4406edd9a44a5cc3ee27b5960f9a18 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 00:30:10 2015 +0300 CBMEM: Fix S3 resume path without EARLY_CBMEM_INIT Implementation for cbmem_find() did not work for boards without EARLY_CBMEM_INIT in romstage. This is required for S3 resume to work on AGESA plaforms. First broken with commit 0dff57d cbmem: switch over to imd-based cbmem Change-Id: I9c1a4f6839f5d90f825787baad2a3824a04b5bdc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 1 - src/lib/imd_cbmem.c | 15 ++++----------- 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index f48e46a..ad8aacb 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -56,7 +56,6 @@ static inline void *saved_ramtop(void) unsigned long __attribute__((weak)) get_top_of_ram(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index fc12c25..6255b18 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -96,9 +96,8 @@ static struct imd *imd_init_backing_with_recover(struct imd *backing) imd = imd_init_backing(backing); if (!ENV_RAMSTAGE) { - /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - imd_handle_init(imd, cbmem_top()); + imd_handle_init(imd, cbmem_top()); + /* Need to partially recover all the time outside of ramstage * because there's object storage outside of the stack. */ imd_handle_init_partial_recovery(imd); @@ -118,10 +117,7 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size) struct imd imd_backing; imd = imd_init_backing(&imd_backing); - - /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - imd_handle_init(imd, cbmem_top()); + imd_handle_init(imd, cbmem_top()); printk(BIOS_DEBUG, "CBMEM:\n"); @@ -157,10 +153,7 @@ int cbmem_initialize_id_size(u32 id, u64 size) struct imd imd_backing; imd = imd_init_backing(&imd_backing); - - /* Early cbmem init platforms need to always use cbmem_top(). */ - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - imd_handle_init(imd, cbmem_top()); + imd_handle_init(imd, cbmem_top()); if (imd_recover(imd)) return 1;

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New patch to review for coreboot: f011466 AGESA: Reduce SPI use by 24kB for S3 support
by Kyösti Mälkki 26 May '15

26 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10318 -gerrit commit f01146698345718d17522f52d32617e471599594 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 15:38:58 2015 +0300 AGESA: Reduce SPI use by 24kB for S3 support There is no need to backup VolatileStorage in SPI flash at all. At the time we need it, we have CBMEM available. Change-Id: If0ca57b314140a833d6d59fe9e236e07816f05a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/heapmanager.c | 1 - src/northbridge/amd/agesa/oem_s3.c | 32 ++++++++------------------------ 2 files changed, 8 insertions(+), 25 deletions(-) diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index 093d7cf..77c4454 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -49,7 +49,6 @@ void EmptyHeap(void) void ResumeHeap(void **heap, size_t *len) { void *base = GetHeapBase(); - memset(base, 0, BIOS_HEAP_SIZE); *heap = base; *len = BIOS_HEAP_SIZE; } diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 16426bc..dfc1ebc 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -27,17 +27,15 @@ typedef enum { S3DataTypeNonVolatile=0, ///< NonVolatile Data Type - S3DataTypeVolatile, ///< Volatile Data Type S3DataTypeMTRR ///< MTRR storage } S3_DATA_TYPE; /* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_VOLATILE_SIZE 0x6000 #define S3_DATA_MTRR_SIZE 0x1000 #define S3_DATA_NONVOLATILE_SIZE 0x1000 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE + (S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE #error "Please increase the value of S3_DATA_SIZE" #endif @@ -47,16 +45,12 @@ static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) u32 s3_data = CONFIG_S3_DATA_POS; switch (S3DataType) { - case S3DataTypeVolatile: - *pos = s3_data; - *len = S3_DATA_VOLATILE_SIZE; - break; case S3DataTypeMTRR: - *pos = s3_data + S3_DATA_VOLATILE_SIZE; + *pos = s3_data; *len = S3_DATA_MTRR_SIZE; break; case S3DataTypeNonVolatile: - *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE; + *pos = s3_data + S3_DATA_MTRR_SIZE; *len = S3_DATA_NONVOLATILE_SIZE; break; default: @@ -84,21 +78,13 @@ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams) AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams) { AMD_S3_PARAMS *dataBlock = &S3LateParams->S3DataBlock; - u32 pos, size; void *dst; size_t len; - /* TODO: Named volatile, do we need to save it over S3? */ - get_s3nv_data(S3DataTypeVolatile, &pos, &size); - void *src = (void *) (pos + sizeof(UINT32)); - ResumeHeap(&dst, &len); dataBlock->VolatileStorageSize = len; dataBlock->VolatileStorage = dst; - len = *(UINT32 *) pos; - memcpy(dst, src, len); - return AGESA_SUCCESS; } @@ -139,9 +125,6 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) if (HIGH_ROMSTAGE_STACK_SIZE) cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); - if (HIGH_MEMORY_SCRATCH) - cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH); - /* To be consumed in AmdInitResume. */ get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); if (size && dataBlock->NvStorageSize) @@ -149,10 +132,11 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) dataBlock->NvStorageSize); /* To be consumed in AmdS3LateRestore. */ - get_s3nv_data(S3DataTypeVolatile, &pos, &size); - if (size && dataBlock->VolatileStorageSize) - spi_SaveS3info(pos, size, dataBlock->VolatileStorage, - dataBlock->VolatileStorageSize); + char *heap = cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH); + if (heap) { + memset(heap, 0, HIGH_MEMORY_SCRATCH); + memcpy(heap, dataBlock->VolatileStorage, dataBlock->VolatileStorageSize); + } /* Collect MTRR setup. */ backup_mtrr(MTRRStorage, &MTRRStorageSize);

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New patch to review for coreboot: ce11306 AGESA: Separate HeapManager declarations from BiosCallOuts
by Kyösti Mälkki 26 May '15

26 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10317 -gerrit commit ce1130682543aee26ab519a4b4eabfe59b6b495b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 11:25:13 2015 +0300 AGESA: Separate HeapManager declarations from BiosCallOuts Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/heapmanager.c | 44 +++++++++++++++++++++++++------- src/cpu/amd/agesa/s3_resume.h | 3 +++ src/northbridge/amd/agesa/BiosCallOuts.h | 18 ------------- src/northbridge/amd/agesa/agesawrapper.c | 1 + src/northbridge/amd/agesa/oem_s3.c | 14 +++++----- 5 files changed, 47 insertions(+), 33 deletions(-) diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index b7c4984..093d7cf 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -1,31 +1,57 @@ #include "AGESA.h" #include "amdlib.h" -#include <northbridge/amd/agesa/BiosCallOuts.h> #include "heapManager.h" #include <cbmem.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> + #include <arch/acpi.h> #include <string.h> +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) + +/* BIOS_HEAP_START_ADDRESS is only for cold boots. */ +#define BIOS_HEAP_SIZE 0x30000 +#define BIOS_HEAP_START_ADDRESS 0x010000000 + +#else + +/* BIOS_HEAP_START_ADDRESS is only for cold boots. */ +#define BIOS_HEAP_SIZE 0x20000 +#define BIOS_HEAP_START_ADDRESS (BSP_STACK_BASE_ADDR - BIOS_HEAP_SIZE) + +#endif + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && (HIGH_MEMORY_SCRATCH < BIOS_HEAP_SIZE) #error Increase HIGH_MEMORY_SCRATCH allocation #endif -UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) +static void *GetHeapBase(void) { - UINT32 heap = BIOS_HEAP_START_ADDRESS; + void *heap = (void *)BIOS_HEAP_START_ADDRESS; if (acpi_is_wakeup_s3()) - heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH); + heap = cbmem_find(CBMEM_ID_RESUME_SCRATCH); return heap; } void EmptyHeap(void) { - void *BiosManagerPtr = (void *) GetHeapBase(NULL); - memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); + void *base = GetHeapBase(); + memset(base, 0, BIOS_HEAP_SIZE); +} + +void ResumeHeap(void **heap, size_t *len) +{ + void *base = GetHeapBase(); + memset(base, 0, BIOS_HEAP_SIZE); + *heap = base; + *len = BIOS_HEAP_SIZE; } #if (IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || \ @@ -94,7 +120,7 @@ static AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigP #endif AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { @@ -219,7 +245,7 @@ static AGESA_STATUS agesa_DeallocateBuffer(UINT32 Func, UINT32 Data, VOID *Confi AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; /* Find target node to deallocate in list of allocated nodes. @@ -330,7 +356,7 @@ static AGESA_STATUS agesa_LocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 97a2a21..579af73 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -26,6 +26,9 @@ void prepare_for_resume(void); void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); const void *OemS3Saved_MTRR_Storage(void); +void EmptyHeap(void); +void ResumeHeap(void **heap, size_t *len); + #define BSP_STACK_BASE_ADDR 0x30000 #if 1 diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h index cfe1852..e763b8c 100644 --- a/src/northbridge/amd/agesa/BiosCallOuts.h +++ b/src/northbridge/amd/agesa/BiosCallOuts.h @@ -24,24 +24,6 @@ #include "Porting.h" #include "AGESA.h" -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) - -#define BIOS_HEAP_START_ADDRESS 0x010000000 -#define BIOS_HEAP_SIZE 0x30000 - -#else - -#define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */ -#define BIOS_HEAP_SIZE 0x20000 - -#endif - - -UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); -void EmptyHeap(void); - AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index 8ad36c7..bfad605 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -23,6 +23,7 @@ #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> #include "heapManager.h" diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 779e28b..16426bc 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -22,7 +22,6 @@ #include <string.h> #include <cbmem.h> #include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <AGESA.h> @@ -85,18 +84,21 @@ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams) AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams) { AMD_S3_PARAMS *dataBlock = &S3LateParams->S3DataBlock; - AMD_CONFIG_PARAMS StdHeader; u32 pos, size; + void *dst; + size_t len; + /* TODO: Named volatile, do we need to save it over S3? */ get_s3nv_data(S3DataTypeVolatile, &pos, &size); - - u32 len = *(UINT32 *) pos; void *src = (void *) (pos + sizeof(UINT32)); - void *dst = (void *) GetHeapBase(&StdHeader); - memcpy(dst, src, len); + ResumeHeap(&dst, &len); dataBlock->VolatileStorageSize = len; dataBlock->VolatileStorage = dst; + + len = *(UINT32 *) pos; + memcpy(dst, src, len); + return AGESA_SUCCESS; }

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coreboot-gerrit May 2015