the following patch was just integrated into master:
commit 8104da771c579a092c576318509fe25df074f1ec
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Nov 9 03:33:51 2014 +0100
acpigen: Remove acpigen_patch_len
Change-Id: I77276342b3f44c7c845a10682ff1f15599c4c721
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/7365
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek(a)assembler.cz>
See http://review.coreboot.org/7365 for details.
-gerrit
the following patch was just integrated into master:
commit e1213d16f38c7950b2c70dfccccbb8d9c08a0ee9
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue May 26 18:43:02 2015 +0300
pcengines/apu1: Enable HAVE_ACPI_RESUME
Note: apu1c models do not support this. That we expose S3 in
ACPI table while it is not available, is a wider issue to solve.
Change-Id: I9b07550d0523593f51c1882a40cccd783115057b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/10315
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/10315 for details.
-gerrit
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10220
-gerrit
commit 70685f1c716a03fdedd85c86e02660abbae6b15a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri May 15 16:54:17 2015 -0500
pistashio: bump up romstage size
Making large changes in pieces is leading to a little bloat.
Bump up the romstage size temporarily so that jenkins will be
happy.
Change-Id: I6f9facb4ca488cf41741a3ed6d0ed7f66d4778b3
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 326a26b..b36d47e 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,8 +38,8 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 36K)
- PRERAM_CBFS_CACHE(0x1a00e000, 72K)
+ ROMSTAGE(0x1a005000, 40K)
+ PRERAM_CBFS_CACHE(0x1a00f000, 68K)
SRAM_END(0x1a020000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10222
-gerrit
commit 7084c98da8d5f3fc713418e14ce3087272565625
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri May 15 16:56:27 2015 -0500
Revert "pistashio: bump up romstage size"
This reverts commit 701211a6e57a17ea861b4ad682dca7416fc9050e.
Change-Id: Ib3e573548bff5c17ab30cfab3d833a2065d689c9
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index b36d47e..326a26b 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,8 +38,8 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 40K)
- PRERAM_CBFS_CACHE(0x1a00f000, 68K)
+ ROMSTAGE(0x1a005000, 36K)
+ PRERAM_CBFS_CACHE(0x1a00e000, 72K)
SRAM_END(0x1a020000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.