coreboot-gerrit May 2015

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Patch set updated for coreboot: dd4ff97 Intel Common SOC: Add romstage support
by Leroy P Leahy 26 May '15

26 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10050 -gerrit commit dd4ff974d439a34b5640dfd4bd9e2d25c2c795cd Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:24:54 2015 -0700 Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/common/Kconfig | 47 +++++ src/soc/intel/common/Makefile.inc | 16 +- src/soc/intel/common/fsp_ramstage.c | 333 ++++++++++++++++++++++++++++++++++ src/soc/intel/common/gma.h | 176 ++++++++++++++++++ src/soc/intel/common/hda_verb.c | 2 +- src/soc/intel/common/memmap.h | 33 ++++ src/soc/intel/common/mrc_cache.c | 4 +- src/soc/intel/common/raminit.c | 300 ++++++++++++++++++++++++++++++ src/soc/intel/common/ramstage.h | 39 ++++ src/soc/intel/common/romstage.c | 351 ++++++++++++++++++++++++++++++++++++ src/soc/intel/common/romstage.h | 103 +++++++++++ src/soc/intel/common/spi_loading.c | 152 ++++++++++++++++ src/soc/intel/common/stack.c | 168 +++++++++++++++++ src/soc/intel/common/stack.h | 35 ++++ src/soc/intel/common/stage_cache.c | 39 ++++ src/soc/intel/common/util.c | 68 +++++++ src/soc/intel/common/util.h | 28 +++ src/soc/intel/common/vbt.c | 47 +++++ 18 files changed, 1935 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8b5cef3..84eb202 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -3,6 +3,8 @@ config SOC_INTEL_COMMON help common code for Intel SOCs +if SOC_INTEL_COMMON + if HAVE_MRC config CACHE_MRC_SETTINGS @@ -27,6 +29,51 @@ endif # CACHE_MRC_SETTINGS endif # HAVE_MRC +config CHIPSET_RESERVED_MEM_BYTES + hex "Size in bytes of chipset reserved memory area" + default 0 + help + If insufficient documentation is available to determine the size of + the chipset reserved memory area by walking the chipset registers, + the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account + for the missing pieces of memory. The value specified in bytes is: + + value = TSEG base - top of low usable memory - (any sizes determined + by reading chipset registers) + +config FSP_CACHE_SIZE + hex "FSP Cache Size in bytes" + default 0 + help + Size of the region in SMM used to cache the FSP binary. This region + size value is used to split the SMM_RESERVED_SIZE config value + into a region specifically for FSP. The remaining region is for + ramstage. + +config SOC_INTEL_COMMON_FSP_RAM_INIT + bool "FSP: Use the common raminit.c module" + default n + depends on PLATFORM_USES_FSP1_1 + +config SOC_INTEL_COMMON_FSP_ROMSTAGE + bool + default n + config SOC_INTEL_COMMON_RESET bool default n + +config SOC_INTEL_COMMON_STACK + bool + default n + +config SOC_INTEL_COMMON_STAGE_CACHE + bool + default n + +config ROMSTAGE_RAM_STACK_SIZE + hex "Size of the romstage RAM stack in bytes" + default 0x5000 + depends on SOC_INTEL_COMMON_STACK + +endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 6d40aa7..4534013 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,10 +1,20 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c +romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c +romstage-$(CONFIG_GOP_SUPPORT) += vbt.c + +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c ramstage-y += hda_verb.c -ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c +ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c endif diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c new file mode 100644 index 0000000..a6c914f --- /dev/null +++ b/src/soc/intel/common/fsp_ramstage.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <cbmem.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp_util.h> +#include <lib.h> +#include <romstage_handoff.h> +#include <soc/intel/common/memmap.h> +#include <soc/intel/common/ramstage.h> +#include <stage_cache.h> +#include <timestamp.h> + +/* SOC initialization after FSP silicon init */ +__attribute__((weak)) void soc_after_silicon_init(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* + * SMM Memory Map: + * + * +--------------------------+ smm_region_size() ----. + * | FSP Cache | CONFIG_FSP_CACHE_SIZE | + * +--------------------------+ | + * | SMM Ramstage Cache | + CONFIG_SMM_RESERVED_SIZE + * +--------------------------+ ---------------------' + * | SMM Code | + * +--------------------------+ smm_base + * + */ + +void stage_cache_external_region(void **base, size_t *size) +{ + size_t cache_size; + u8 *cache_base; + + /* Determine the location of the ramstage cache */ + smm_region((void **)&cache_base, &cache_size); + *size = CONFIG_SMM_RESERVED_SIZE - CONFIG_FSP_CACHE_SIZE; + *base = &cache_base[cache_size - CONFIG_SMM_RESERVED_SIZE]; +} + +static void *smm_fsp_cache_base(size_t *size) +{ + size_t cache_size; + u8 *cache_base; + + /* Determine the location of the FSP cache */ + stage_cache_external_region((void **)&cache_base, &cache_size); + *size = CONFIG_FSP_CACHE_SIZE; + return &cache_base[cache_size]; +} + +/* Display SMM memory map */ +static void smm_memory_map(void) +{ + u8 *smm_base; + size_t smm_bytes; + size_t smm_code_bytes; + u8 *fsp_cache; + size_t fsp_cache_bytes; + u8 *ramstage_cache; + size_t ramstage_cache_bytes; + u8 *smm_reserved; + size_t smm_reserved_bytes; + + /* Locate the SMM regions */ + smm_region((void **)&smm_base, &smm_bytes); + fsp_cache = smm_fsp_cache_base(&fsp_cache_bytes); + stage_cache_external_region((void **)&ramstage_cache, &ramstage_cache_bytes); + smm_code_bytes = ramstage_cache - smm_base; + smm_reserved = fsp_cache + fsp_cache_bytes; + smm_reserved_bytes = smm_bytes - fsp_cache_bytes - ramstage_cache_bytes + - smm_code_bytes; + + /* Display the SMM regions */ + printk(BIOS_SPEW, "\nLocation SMM Memory Map Offset\n"); + if (smm_reserved_bytes) { + printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", + &smm_reserved[smm_reserved_bytes], (u32)smm_bytes); + printk(BIOS_SPEW, " | Other reserved region |\n"); + } + printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", + smm_reserved, (u32)(smm_reserved - smm_base)); + printk(BIOS_SPEW, " | FSP binary cache |\n"); + printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", + fsp_cache, (u32)(fsp_cache - smm_base)); + printk(BIOS_SPEW, " | ramstage cache |\n"); + printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", + ramstage_cache, (u32)(ramstage_cache - smm_base)); + printk(BIOS_SPEW, " | SMM code |\n"); + printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", + smm_base, 0); + printk(BIOS_ERR, "\nCONFIG_FSP_CACHE_SIZE: 0x%08x bytes\n\n", + CONFIG_FSP_CACHE_SIZE); +} + +struct smm_fsp_cache_header { + void *start; + size_t size; + FSP_INFO_HEADER *fih; +}; + +/* SoC implementation for caching support code. */ +static void soc_save_support_code(void *start, size_t size, + FSP_INFO_HEADER *fih) +{ + u8 *fsp_cache; + size_t fsp_cache_length; + struct smm_fsp_cache_header *header; + size_t smm_fsp_cache_length; + + if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP)) + smm_memory_map(); + + /* Locate the FSP cache in SMM */ + fsp_cache = smm_fsp_cache_base(&smm_fsp_cache_length); + + /* Initialize the FSP cache header */ + header = (struct smm_fsp_cache_header *)fsp_cache; + fsp_cache += sizeof(*header); + header->start = start; + header->size = size; + header->fih = fih; + + /* Validate the CONFIG_FSP_CACHE_SIZE value */ + fsp_cache_length = sizeof(*header) + size; + if (smm_fsp_cache_length < fsp_cache_length) { + printk(BIOS_ERR, "CONFIG_FSP_CACHE_SIZE < 0x%08x bytes\n", + (u32)fsp_cache_length); + die("ERROR: Insufficent space to cache FSP binary!\n"); + } + + /* Copy the FSP binary into the SMM region for safe keeping */ + memcpy(fsp_cache, start, size); +} + +/* SoC implementation for restoring support code after S3 resume. Returns + * previously passed fih pointer from soc_save_support_code(). */ +static FSP_INFO_HEADER *soc_restore_support_code(void) +{ + u8 *fsp_cache; + struct smm_fsp_cache_header *header; + size_t smm_fsp_cache_length; + + /* Locate the FSP cache in SMM */ + fsp_cache = smm_fsp_cache_base(&smm_fsp_cache_length); + + /* Get the FSP cache header */ + header = (struct smm_fsp_cache_header *)fsp_cache; + fsp_cache += sizeof(*header); + + /* Copy the FSP binary from the SMM region back into RAM */ + memcpy(header->start, fsp_cache, header->size); + + /* Return the FSP_INFO_HEADER address */ + return header->fih; +} + +static void fsp_run_silicon_init(struct romstage_handoff *handoff) +{ + FSP_INFO_HEADER *fsp_info_header; + FSP_SILICON_INIT fsp_silicon_init; + EFI_STATUS status; + UPD_DATA_REGION upd_data; + UPD_DATA_REGION *upd_ptr; + VPD_DATA_REGION *vpd_ptr; + + /* Find the FSP image */ + fsp_info_header = fsp_get_fih(); + if (fsp_info_header == NULL) { + printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n"); + return; + } + print_fsp_info(fsp_info_header); + + /* Initialize the UPD values */ + vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset + + fsp_info_header->ImageBase); + printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr); + upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + + fsp_info_header->ImageBase); + printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr); + memcpy(&upd_data, upd_ptr, sizeof(upd_data)); + soc_silicon_init_params(&upd_data); + /* Locate VBT and pass to FSP GOP */ + if (IS_ENABLED(CONFIG_GOP_SUPPORT)) + load_vbt(handoff->s3_resume, &upd_data); + mainboard_silicon_init_params(&upd_data); + + /* Display the UPD data */ + if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + soc_display_silicon_init_params(upd_ptr, &upd_data); + + /* Perform silicon initialization after RAM is configured */ + printk(BIOS_DEBUG, "Calling FspSiliconInit\n"); + fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase + + fsp_info_header->FspSiliconInitEntryOffset); + timestamp_add_now(TS_FSP_SILICON_INIT_START); + printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n", &upd_data, + fsp_silicon_init); + status = fsp_silicon_init(&upd_data); + timestamp_add_now(TS_FSP_SILICON_INIT_END); + printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + /* Verify the HOBs */ + const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; + void *hob_list_ptr = get_hob_list(); + int missing_hob = 0; + + if (hob_list_ptr == NULL) + die("ERROR - HOB pointer is NULL!\n"); + print_hob_type_structure(0, hob_list_ptr); + + /* + * Verify that FSP is generating the required HOBs: + * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 + * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit + * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit + * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit + * 7.5: EFI_PEI_GRAPHICS_INFO_HOB verified below + */ + if (NULL == get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) { + printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); + missing_hob = 1; + } + if (missing_hob) + die("ERROR - Missing one or more required FSP HOBs!\n"); +#endif + + soc_after_silicon_init(); +} + +static void fsp_cache_save(void) +{ + const struct cbmem_entry *fsp_entry; + FSP_INFO_HEADER *fih; + + fsp_entry = cbmem_entry_find(CBMEM_ID_REFCODE); + + if (fsp_entry == NULL) { + printk(BIOS_ERR, "ERROR: FSP not found in CBMEM.\n"); + return; + } + + fih = fsp_get_fih(); + + if (fih == NULL) { + printk(BIOS_ERR, "ERROR: No FIH found.\n"); + return; + } + + soc_save_support_code(cbmem_entry_start(fsp_entry), + cbmem_entry_size(fsp_entry), fih); +} + +static int fsp_find_and_relocate(void) +{ + struct cbfs_file *file; + void *fih; + + file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "fsp.bin"); + + if (file == NULL) { + printk(BIOS_ERR, "Couldn't find fsp.bin in CBFS.\n"); + return -1; + } + + fih = fsp_relocate(CBFS_SUBHEADER(file), ntohl(file->len)); + + fsp_update_fih(fih); + + return 0; +} + +void intel_silicon_init(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff != NULL && handoff->s3_resume) { + printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); + fsp_update_fih(soc_restore_support_code()); + } else { + fsp_find_and_relocate(); + printk(BIOS_DEBUG, "FSP: Saving binary in cache\n"); + fsp_cache_save(); + } + + fsp_run_silicon_init(handoff); +} + +/* Initialize the UPD parameters for SiliconInit */ +__attribute__((weak)) void mainboard_silicon_init_params( + UPD_DATA_REGION *upd_ptr) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +}; + +/* Display the UPD parameters for SiliconInit */ +__attribute__((weak)) void soc_display_silicon_init_params( + const UPD_DATA_REGION *original, UPD_DATA_REGION *upd_ptr) +{ + printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); + hexdump32(BIOS_SPEW, upd_ptr, sizeof(*upd_ptr)); +} + +/* Initialize the UPD parameters for SiliconInit */ +__attribute__((weak)) void soc_silicon_init_params(UPD_DATA_REGION *upd_ptr) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..9666147 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ + diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index c4cdb3d..ecd6c81 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -72,7 +72,7 @@ int hda_codec_detect(u8 *base) /* Clear the "State Change Status Register" STATESTS bits * for each of the "SDIN Stat Change Status Flag" - */ + */ write8(base + HDA_STATESTS_REG, 0xf); /* Turn off the link and poll RESET# bit until it reads back as 0 */ diff --git a/src/soc/intel/common/memmap.h b/src/soc/intel/common/memmap.h new file mode 100644 index 0000000..840b51e --- /dev/null +++ b/src/soc/intel/common/memmap.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_MEMMAP_H_ +#define _COMMON_MEMMAP_H_ + +#include <types.h> + +/* + * mmap_region_granluarity must to return a size which is a positive non-zero + * integer multiple of the SMM size when SMM is in use. When not using SMM, + * this value should be set to 8 MiB. + */ +size_t mmap_region_granluarity(void); +void smm_region(void **start, size_t *size); + +#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 9366aa5..a162cf4 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -149,7 +149,7 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(&region, cache); } -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE /* * romstage code @@ -326,4 +326,4 @@ static void update_mrc_cache(void *unused) BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif /* defined(__PRE_RAM__) */ +#endif /* ENV_ROMSTAGE */ diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c new file mode 100644 index 0000000..8bdf308 --- /dev/null +++ b/src/soc/intel/common/raminit.c @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <console/console.h> +#include <fsp_util.h> +#include <lib.h> /* hexdump */ +#include <reset.h> +#include <soc/intel/common/memmap.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <string.h> +#include <timestamp.h> + +void raminit(struct romstage_params *params) +{ + const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID; + EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root; + FSP_INFO_HEADER *fsp_header; + EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory; + FSP_MEMORY_INIT fsp_memory_init; + FSP_MEMORY_INIT_PARAMS fsp_memory_init_params; + const EFI_GUID fsp_reserved_guid = + FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID; + void *fsp_reserved_memory_area; + FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer; + void *hob_list_ptr; + const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + u32 *mrc_hob; + u32 fsp_reserved_bytes; + EFI_STATUS status; + struct pei_data *pei_ptr; + VPD_DATA_REGION *vpd_ptr; + UPD_DATA_REGION *upd_ptr; + UPD_DATA_REGION upd_data_buffer; + int fsp_verification_failure = 0; +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + unsigned long int data; + EFI_PEI_HOB_POINTERS hob_ptr; +#endif + + /* + * Find and copy the UPD region to the stack so the platform can modify + * the settings if needed. Modifications to the UPD buffer are done in + * the platform callback code. The platform callback code is also + * responsible for assigning the UpdDataRngPtr to this buffer if any + * updates are made. The default state is to leave the UpdDataRngPtr + * set to NULL. This indicates that the FSP code will use the UPD + * region in the FSP binary. + */ + post_code(0x34); + fsp_header = params->chipset_context; + vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + + fsp_header->ImageBase); + printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); + upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + + fsp_header->ImageBase); + printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr); + memcpy(&upd_data_buffer, upd_ptr, sizeof(upd_data_buffer)); + + /* Zero fill RT Buffer data and start populating fields. */ + memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer)); + pei_ptr = params->pei_data; + if (pei_ptr->boot_mode == SLEEP_STATE_S3) { + fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME; + } else if (pei_ptr->saved_data != NULL) { + fsp_rt_common_buffer.BootMode = + BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + } else { + fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION; + } + fsp_rt_common_buffer.UpdDataRgnPtr = &upd_data_buffer; + fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size(); + + /* Get any board specific changes */ + fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data; + fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer; + fsp_memory_init_params.HobListPtr = &hob_list_ptr; + + /* Update the UPD data */ + soc_memory_init_params(&upd_data_buffer); + mainboard_memory_init_params(params, &upd_data_buffer); + post_code(0x36); + + /* Display the UPD data */ + if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + soc_display_memory_init_params(upd_ptr, &upd_data_buffer); + + /* Call FspMemoryInit to initialize RAM */ + fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase + + fsp_header->FspMemoryInitEntryOffset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); + printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n", + fsp_memory_init_params.NvsBufferPtr); + printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n", + fsp_memory_init_params.RtBufferPtr); + printk(BIOS_SPEW, " 0x%p: HobListPtr\n", + fsp_memory_init_params.HobListPtr); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_memory_init(&fsp_memory_init_params); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + if (status != EFI_SUCCESS) + die("ERROR - FspMemoryInit failed to initialize memory!\n"); + + /* Locate the FSP reserved memory area */ + fsp_reserved_bytes = 0; + fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr); + if (fsp_memory == NULL) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, + "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + } else { + fsp_reserved_bytes = fsp_memory->ResourceLength; + printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n", + (unsigned long int)fsp_reserved_bytes); + } + + /* Display SMM area */ +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + char *smm_base; + size_t smm_size; + + smm_region((void **)&smm_base, &smm_size); + printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); + printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); +#endif + + /* Migrate CAR data */ + printk(BIOS_DEBUG, "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", + CONFIG_CHIPSET_RESERVED_MEM_BYTES); + printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); + if (pei_ptr->boot_mode != SLEEP_STATE_S3) { + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_reserved_bytes); + } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_reserved_bytes)) { +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + hard_reset(); +#endif + } + + /* Save the FSP runtime parameters. */ + fsp_set_runtime(params->chipset_context, hob_list_ptr); + + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr); + if (cbmem_root == NULL) { + fsp_verification_failure = 1; + printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n", + fsp_rt_common_buffer.BootLoaderTolumSize); + } + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + if (hob_list_ptr == NULL) + die("ERROR - HOB pointer is NULL!\n"); + + /* + * Verify that FSP is generating the required HOBs: + * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 + * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above + * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified below + * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above + * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit + */ + if (NULL != cbmem_root) { + printk(BIOS_DEBUG, + "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n", + cbmem_root); + data = cbmem_root->PhysicalStart; + printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); + data = cbmem_root->ResourceLength; + printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); + } + hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); + if (NULL == hob_ptr.Raw) { + printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); + fsp_verification_failure = + (params->pei_data->saved_data == NULL) ? 1 : 0; + } else { + printk(BIOS_DEBUG, + "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n", + hob_ptr.Raw); + } + if (fsp_memory != NULL) { + printk(BIOS_DEBUG, + "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n", + fsp_memory); + data = fsp_memory->PhysicalStart; + printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); + data = fsp_memory->ResourceLength; + printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); + } + + /* Verify all the HOBs are present */ + if (fsp_verification_failure) + printk(BIOS_DEBUG, + "ERROR - Missing one or more required FSP HOBs!\n"); + + /* Display the HOBs */ + print_hob_type_structure(0, hob_list_ptr); +#endif + + /* Get the address of the CBMEM region for the FSP reserved memory */ + fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); + printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n", + fsp_reserved_memory_area); + + /* Verify the order of CBMEM root and FSP memory */ + if ((fsp_memory != NULL) && (cbmem_root != NULL) && + (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, + "ERROR - FSP reserved memory above CBMEM root!\n"); + } + + /* Verify that the FSP memory was properly reserved */ + if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) || + (fsp_memory->PhysicalStart != + (unsigned int)fsp_reserved_memory_area))) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n"); +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + if (cbmem_root != NULL) { + size_t delta_bytes = (unsigned int)smm_base + - cbmem_root->PhysicalStart + - cbmem_root->ResourceLength; + printk(BIOS_DEBUG, + "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", + CONFIG_CHIPSET_RESERVED_MEM_BYTES); + printk(BIOS_DEBUG, + "0x%08x: Chipset reserved bytes reported by FSP\n", + (unsigned int)delta_bytes); + die("Please verify the chipset reserved size\n"); + } +#endif + } + + /* Verify the FSP 1.1 HOB interface */ + if (fsp_verification_failure) + die("ERROR - Coreboot's requirements not met by FSP binary!\n"); + + /* Display the memory configuration */ + report_memory_config(); + + /* Locate the memory configuration data to speed up the next reboot */ + mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); + if (mrc_hob == NULL) + printk(BIOS_DEBUG, + "Memory Configuration Data Hob not present\n"); + else { + pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob); + pei_ptr->data_to_save_size = ALIGN( + ((u32)GET_HOB_LENGTH(mrc_hob)), 16); + } +} + +/* Initialize the UPD parameters for MemoryInit */ +__attribute__((weak)) void mainboard_memory_init_params( + struct romstage_params *params, + UPD_DATA_REGION *upd_ptr) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Display the UPD parameters for MemoryInit */ +__attribute__((weak)) void soc_display_memory_init_params( + const UPD_DATA_REGION *original, UPD_DATA_REGION *upd_ptr) +{ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + hexdump32(BIOS_SPEW, upd_ptr, sizeof(*upd_ptr)); +} + +/* Initialize the UPD parameters for MemoryInit */ +__attribute__((weak)) void soc_memory_init_params(UPD_DATA_REGION *upd_ptr) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h new file mode 100644 index 0000000..d542154 --- /dev/null +++ b/src/soc/intel/common/ramstage.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _INTEL_COMMON_RAMSTAGE_H_ +#define _INTEL_COMMON_RAMSTAGE_H_ + +#include <fsp_util.h> +#include <soc/intel/common/util.h> +#include <stdint.h> + +/* Perform Intel silicon init. */ +void intel_silicon_init(void); +/* Called after the silicon init code has run. */ +void soc_after_silicon_init(void); +/* Initialize UPD data before SiliconInit call. */ +void soc_silicon_init_params(UPD_DATA_REGION *upd_ptr); +void mainboard_silicon_init_params(UPD_DATA_REGION *upd_ptr); +void soc_display_silicon_init_params(const UPD_DATA_REGION *original, + UPD_DATA_REGION *upd_ptr); +void load_vbt(uint8_t s3_resume, UPD_DATA_REGION *upd_ptr); + +#endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c new file mode 100644 index 0000000..c6f033b --- /dev/null +++ b/src/soc/intel/common/romstage.c @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <stdint.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/cbfs.h> +#include <arch/stages.h> +#include <arch/early_variables.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <elog.h> +#include <reset.h> +#include <romstage_handoff.h> +#include <soc/intel/common/mrc_cache.h> +#include <soc/pei_wrapper.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/spi.h> +#include <stage_cache.h> +#include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Entry from cache-as-ram.inc. */ +asmlinkage void *romstage_main(unsigned int bist, + uint32_t tsc_low, uint32_t tsc_high, + void *chipset_context) +{ + void *top_of_stack; + struct pei_data pei_data; + struct romstage_params params = { + .bist = bist, + .pei_data = &pei_data, + .chipset_context = chipset_context, + }; + + post_code(0x30); + + /* Save timestamp data */ + timestamp_init((((uint64_t)tsc_high) << 32) | (uint64_t)tsc_low); + timestamp_add_now(TS_START_ROMSTAGE); + + memset(&pei_data, 0, sizeof(pei_data)); + + /* Call into pre-console init code. */ + soc_pre_console_init(&params); + mainboard_pre_console_init(&params); + + /* Start console drivers */ + console_init(); + + /* Display parameters */ + printk(BIOS_SPEW, "bist: 0x%08x\n", bist); + printk(BIOS_SPEW, "tsc_low: 0x%08x\n", tsc_low); + printk(BIOS_SPEW, "tsc_hi: 0x%08x\n", tsc_high); + printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_MMCONF_BASE_ADDRESS); + printk(BIOS_INFO, "Using: %s\n", + IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) ? "FSP 1.1" : + (IS_ENABLED(CONFIG_HAVE_MRC) ? "MRC" : + "No Memory Support")); + + /* Display FSP banner */ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + print_fsp_info(params.chipset_context); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + + /* Get power state */ + params.power_state = fill_power_state(); + + /* Print useful platform information */ + report_platform_info(); + + /* Set CPU frequency to maximum */ + set_max_freq(); + + /* Perform SOC specific initialization. */ + soc_romstage_init(&params); + + /* Call into mainboard. */ + mainboard_romstage_entry(&params); + soc_after_ram_init(&params); + post_code(0x38); + + top_of_stack = setup_stack_and_mtrrs(); + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + + return top_of_stack; +} + +/* Entry from the mainboard. */ +void romstage_common(struct romstage_params *params) +{ + const struct mrc_saved_data *cache; + struct romstage_handoff *handoff; + struct pei_data *pei_data; + + post_code(0x32); + + timestamp_add_now(TS_BEFORE_INITRAM); + + pei_data = params->pei_data; + pei_data->boot_mode = params->power_state->prev_sleep_state; + +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) + if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) + boot_count_increment(); +#endif + + /* Perform remaining SOC initialization */ + soc_pre_ram_init(params); + post_code(0x33); + + /* Check recovery and MRC cache */ + params->pei_data->saved_data_size = 0; + params->pei_data->saved_data = NULL; + if (!params->pei_data->disable_saved_data) { + if (recovery_mode_enabled()) { + /* Recovery mode does not use MRC cache */ + printk(BIOS_DEBUG, + "Recovery mode: not using MRC cache.\n"); + } else if (!mrc_cache_get_current(&cache)) { + /* MRC cache found */ + params->pei_data->saved_data_size = cache->size; + params->pei_data->saved_data = &cache->data[0]; + } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) { + /* Waking from S3 and no cache. */ + printk(BIOS_DEBUG, + "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + hard_reset(); + } else { + printk(BIOS_DEBUG, "No MRC cache found.\n"); + mainboard_check_ec_image(params); + } + } + + /* Initialize RAM */ + raminit(params); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Save MRC output */ + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, + pei_data->data_to_save_size); + if (params->pei_data->boot_mode != SLEEP_STATE_S3) { + if (params->pei_data->data_to_save_size != 0 && + params->pei_data->data_to_save != NULL) { + mrc_cache_stash_data(params->pei_data->data_to_save, + params->pei_data->data_to_save_size); + } + } + + /* Save DIMM information */ + mainboard_save_dimm_info(params); + + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (params->power_state->prev_sleep_state == + SLEEP_STATE_S3); + else { + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + hard_reset(); + } + +#if IS_ENABLED(CONFIG_CHROMEOS) + /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */ + init_chromeos((params->power_state->prev_sleep_state == SLEEP_STATE_S3) + ? 2 : 0); +#endif +} + +asmlinkage void romstage_after_car(void *chipset_context) +{ + if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); + printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); + soc_after_temp_ram_exit(); + } + + timestamp_add_now(TS_END_ROMSTAGE); + + /* Load the ramstage. */ + copy_and_run(); + die("ERROR - Failed to load ramstage!"); +} + +/* Initialize the power state */ +__attribute__((weak)) struct chipset_power_state *fill_power_state(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return NULL; +} + +__attribute__((weak)) void mainboard_check_ec_image( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + struct pei_data *pei_data; + + pei_data = params->pei_data; + if (params->pei_data->boot_mode == SLEEP_STATE_S0) { + /* Ensure EC is running RO firmware. */ + google_chromeec_check_ec_image(EC_IMAGE_RO); + } +#endif +} + +/* Board initialization before the console is enabled */ +__attribute__((weak)) void mainboard_pre_console_init( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Board initialization before and after RAM is enabled */ +__attribute__((weak)) void mainboard_romstage_entry( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + + post_code(0x31); + + /* Initliaze memory */ + romstage_common(params); +} + +/* Used by MRC images to save DIMM information */ +__attribute__((weak)) void mainboard_save_dimm_info( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Get the memory configuration data */ +__attribute__((weak)) int mrc_cache_get_current( + const struct mrc_saved_data **cache) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +/* Save the memory configuration data */ +__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +/* Transition RAM from off or self-refresh to active */ +__attribute__((weak)) void raminit(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + post_code(0x34); + die("ERROR - No RAM initialization specified!\n"); +} + +void ramstage_cache_invalid(void) +{ +#if IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) + /* Perform cold reset on invalid ramstage cache. */ + hard_reset(); +#endif +} + +/* Display the memory configuration */ +__attribute__((weak)) void report_memory_config(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Display the platform configuration */ +__attribute__((weak)) void report_platform_info(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Choose top of stack and setup MTRRs */ +__attribute__((weak)) void *setup_stack_and_mtrrs(void) +{ + printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__); + die("ERROR - Must specify top of stack!\n"); + return NULL; +} + +/* Speed up the CPU to the maximum frequency */ +__attribute__((weak)) void set_max_freq(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after RAM is enabled */ +__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after temporary RAM is disabled */ +__attribute__((weak)) void soc_after_temp_ram_exit(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization before the console is enabled */ +__attribute__((weak)) void soc_pre_console_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization before RAM is enabled */ +__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after console is enabled */ +__attribute__((weak)) void soc_romstage_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Ensure the EC is in the right mode for recovery */ + google_chromeec_early_init(); +#endif +} diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h new file mode 100644 index 0000000..55c7a6f --- /dev/null +++ b/src/soc/intel/common/romstage.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_ROMSTAGE_H_ +#define _COMMON_ROMSTAGE_H_ + +#include <stdint.h> +#include <arch/cpu.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#include <fsp_util.h> +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ +#include <soc/intel/common/util.h> +#include <soc/pei_data.h> +#include <soc/pm.h> /* chip_power_state */ + +struct romstage_params { + unsigned long bist; + struct chipset_power_state *power_state; + struct pei_data *pei_data; + void *chipset_context; +}; + +/* + * FSP Boot Flow: + * 1. src/cpu/x86/16bit/reset.inc + * 2. src/cpu/x86/16bit/entry.inc + * 3. other modules + * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc + * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp + * 6. FSP binary/TempRamInit + * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return + * 8. src/soc/intel/common/romstage.c/romstage_main + * 9 src/soc/.../romstage/.../soc_pre_console_init + * 10 src/console/console.c/console_init + * 11 src/soc/.../romstage/.../soc_romstage_init + * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry + * 13. src/soc/intel/common/romstage.c/romstage_common + * 14 src/soc/.../romstage/.../soc_pre_raminit + * 15. FSP binary/MemoryInit + * 16. src/soc/intel/common/romstage.c/romstage_common - return + * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return + * 18. src/soc/intel/common/romstage.c/romstage_main - return + * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs + * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup + * after call to romstage_main + * 21. FSP binary/TempRamExit + * 22. src/soc/intel/common/romstage.c/romstage_after_car + * 23. FSP binary/SiliconInit + * 24. src/soc/intel/common/romstage.c/romstage_after_car - return + * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback + * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify + * 27. FSP binary/FspNotify + * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback + * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify + * 30. FSP binary/FspNotify + */ + +void mainboard_check_ec_image(struct romstage_params *params); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +void mainboard_memory_init_params(struct romstage_params *params, + UPD_DATA_REGION *upd_ptr); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ +void mainboard_pre_console_init(struct romstage_params *params); +void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_save_dimm_info(struct romstage_params *params); +void raminit(struct romstage_params *params); +void report_memory_config(void); +void report_platform_info(void); +asmlinkage void romstage_after_car(void *chipset_context); +void romstage_common(struct romstage_params *params); +asmlinkage void *romstage_main(unsigned int bist, uint32_t tsc_lo, + uint32_t tsc_high, void *chipset_context); +void *setup_stack_and_mtrrs(void); +void set_max_freq(void); +void soc_after_ram_init(struct romstage_params *params); +void soc_after_temp_ram_exit(void); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +void soc_display_memory_init_params(const UPD_DATA_REGION *original, + UPD_DATA_REGION *upd_ptr); +void soc_memory_init_params(UPD_DATA_REGION *upd_ptr); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ +void soc_pre_console_init(struct romstage_params *params); +void soc_pre_ram_init(struct romstage_params *params); +void soc_romstage_init(struct romstage_params *params); + +#endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/soc/intel/common/spi_loading.c b/src/soc/intel/common/spi_loading.c new file mode 100644 index 0000000..fe3522b --- /dev/null +++ b/src/soc/intel/common/spi_loading.c @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/byteorder.h> +#include <boot/coreboot_tables.h> +#include <cbmem.h> +#include <cbfs.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define CACHELINE_SIZE 64 +#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) +#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) + +static void *find_mirror_buffer(int len) +{ + int nentries; + int i; + struct lb_memory *mem; + void *buffer; + + len = ALIGN(len, 4096); + + mem = get_lb_mem(); + nentries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]); + + /* + * Find the highest RAM entry that accommodates the lenth provide + * while falling below 4GiB. + */ + buffer = NULL; + for (i = 0; i < nentries; i++) { + const uint64_t max_addr = 1ULL << 32; + uint64_t start; + uint64_t size; + struct lb_memory_range *r; + + r = &mem->map[i]; + + if (r->type != LB_MEM_RAM) + continue; + + start = unpack_lb64(r->start); + if (start >= max_addr) + continue; + + size = unpack_lb64(r->size); + if (size < len) + continue; + + /* Adjust size of buffer if range exceeds max address. */ + if (start + size > max_addr) + size = max_addr - start; + + if (size < len) + continue; + + buffer = (void *)(uintptr_t)(start + size - len); + } + + return buffer; +} + +/* + * Mirror the payload file to the default SMM location if it is small enough. + * The default SMM region can be used since no one is using the memory at this + * location at this stage in the boot. + */ +static void *spi_mirror(void *file_start, int file_len) +{ + int alignment_diff; + char *src; + char *dest; + + alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); + + /* + * Adjust file length so that the start and end points are aligned to a + * cacheline. Coupled with the ROM caching in the CPU the SPI hardware + * will read and cache full length cachelines. It will also prefetch + * data as well. Once things are mirrored in memory all accesses should + * hit the CPUs cache. + */ + file_len += alignment_diff; + file_len = ALIGN(file_len, CACHELINE_SIZE); + + printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); + + dest = find_mirror_buffer(file_len); + + /* + * Just pass back the pointer to ROM space if a buffer could not + * be found to mirror into. + */ + if (dest == NULL) + return file_start; + + src = (void *)(CACHELINE_MASK & (long)file_start); + /* + * Note that if mempcy is not using 32-bit moves the performance will + * degrade because the SPI hardware prefetchers look for + * cacheline-aligned 32-bit accesses to kick in. + */ + memcpy(dest, src, file_len); + + /* Provide pointer into mirrored space. */ + return &dest[alignment_diff]; +} + +void *cbfs_load_payload(struct cbfs_media *media, const char *name) +{ + int file_len; + void *file_start; + struct cbfs_file *file; + + file_start = vboot_get_payload(&file_len); + + if (file_start != NULL) + return spi_mirror(file_start, file_len); + + file = cbfs_get_file(media, name); + + if (file == NULL) + return NULL; + + if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) + return NULL; + + file_len = ntohl(file->len); + + file_start = CBFS_SUBHEADER(file); + + return spi_mirror(file_start, file_len); +} diff --git a/src/soc/intel/common/stack.c b/src/soc/intel/common/stack.c new file mode 100644 index 0000000..03cf30c --- /dev/null +++ b/src/soc/intel/common/stack.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include "memmap.h" +#include "romstage.h" +#include "stack.h" +#include <stdlib.h> + +const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; + +/* + * Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. + */ +static unsigned long choose_top_of_stack(void) +{ + unsigned long stack_top; + + /* cbmem_add() does a find() before add(). */ + stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, + romstage_ram_stack_size); + stack_top += romstage_ram_stack_size; + return stack_top; +} + +/* + * setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void *setup_stack_and_mtrrs(void) +{ + size_t alignment; + uint32_t aligned_ram; + uint32_t mtrr_mask_upper; + int num_mtrrs; + uint32_t *slot; + unsigned long top_of_stack; + + /* Top of stack needs to be aligned to a 8-byte boundary. */ + top_of_stack = choose_top_of_stack(); + slot = (void *)top_of_stack; + num_mtrrs = 0; + + /* + * The upper bits of the MTRR mask need to set according to the number + * of physical address bits. + */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + + /* + * The order for each MTRR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * +0: Number of MTRRs + * +4: MTRR base 0 31:0 + * +8: MTRR base 0 63:32 + * +12: MTRR mask 0 31:0 + * +16: MTRR mask 0 63:32 + * +20: MTRR base 1 31:0 + * +24: MTRR base 1 63:32 + * +28: MTRR mask 1 31:0 + * +32: MTRR mask 1 63:32 + */ + + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + /* + * Cache the stack and the other CBMEM entries as well as part or all + * of the FSP reserved memory region. + */ + alignment = mmap_region_granluarity(); + aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size, + alignment); + + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); + num_mtrrs++; + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + void *smm_base; + size_t smm_size; + uint32_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uint32_t)smm_base; + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + num_mtrrs++; +#endif + + /* + * Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + slot = stack_push32(slot, num_mtrrs); + return slot; +} + diff --git a/src/soc/intel/common/stack.h b/src/soc/intel/common/stack.h new file mode 100644 index 0000000..850a070 --- /dev/null +++ b/src/soc/intel/common/stack.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_STACK_H_ +#define _COMMON_STACK_H_ + +#include <stdint.h> + +static inline void *stack_push32(void *stack, uint32_t value) +{ + uint32_t *stack32 = stack; + + stack32 = &stack32[-1]; + *stack32 = value; + return stack32; +} + +#endif /* _COMMON_STACK_H_ */ diff --git a/src/soc/intel/common/stage_cache.c b/src/soc/intel/common/stage_cache.c new file mode 100644 index 0000000..2dd4e47 --- /dev/null +++ b/src/soc/intel/common/stage_cache.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <soc/intel/common/memmap.h> +#include <soc/smm.h> +#include <stage_cache.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + size_t smm_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* + * The ramstage cache lives in the TSEG region. + * The top of ram is defined to be the TSEG base address. + */ + smm_region((void **)&smm_base, &smm_size); + *size = cache_size; + *base = (void *)(&smm_base[smm_size - cache_size]); +} diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c new file mode 100644 index 0000000..65b5500 --- /dev/null +++ b/src/soc/intel/common/util.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <soc/intel/common/util.h> + +void soc_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new) +{ + if (old == new) { + switch (size) { + case 1: + printk(BIOS_SPEW, " 0x%02llx: %s\n", new, name); + break; + + case 2: + printk(BIOS_SPEW, " 0x%04llx: %s\n", new, name); + break; + + case 4: + printk(BIOS_SPEW, " 0x%08llx: %s\n", new, name); + break; + + case 8: + printk(BIOS_SPEW, " 0x%016llx: %s\n", new, name); + break; + } + } else { + switch (size) { + case 1: + printk(BIOS_SPEW, " 0x%02llx --> 0x%02llx: %s\n", old, + new, name); + break; + + case 2: + printk(BIOS_SPEW, " 0x%04llx --> 0x%04llx: %s\n", old, + new, name); + break; + + case 4: + printk(BIOS_SPEW, " 0x%08llx --> 0x%08llx: %s\n", old, + new, name); + break; + + case 8: + printk(BIOS_SPEW, " 0x%016llx --> 0x%016llx: %s\n", + old, new, name); + break; + } + } +} diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h new file mode 100644 index 0000000..ec1cf17 --- /dev/null +++ b/src/soc/intel/common/util.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _INTEL_COMMON_UTIL_H_ +#define _INTEL_COMMON_UTIL_H_ + +#include <stdint.h> + +void soc_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new); + +#endif /* _INTEL_COMMON_UTIL_H_ */ diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c new file mode 100644 index 0000000..40d9874 --- /dev/null +++ b/src/soc/intel/common/vbt.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <fsp_util.h> +#include <lib.h> +#include <soc/intel/common/ramstage.h> +#include <string.h> + +/* Locate VBT and pass it to FSP GOP */ +void load_vbt(uint8_t s3_resume, UPD_DATA_REGION *upd_ptr) +{ + const optionrom_vbt_t *vbt_data; + uint32_t vbt_len; + + /* Check boot mode - for S3 resume path VBT loading is not needed */ + if (s3_resume) { + vbt_data = NULL; + printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); + } else { + /* Get VBT data */ + vbt_data = fsp_get_vbt(&vbt_len); + if (vbt_data != NULL) + printk(BIOS_DEBUG, "Passing VBT to GOP\n"); + else + printk(BIOS_DEBUG, "VBT not found!\n"); + } + upd_ptr->PcdGraphicsConfigPtr = (u32)vbt_data; +}

1 0

Patch set updated for coreboot: 16b0136 mainboard/google/cyan: Cyan board support
by Leroy P Leahy 26 May '15

26 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10182 -gerrit commit 16b0136b50d5c737e9d246563e013c97a401e0b8 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 11 17:24:31 2015 -0700 mainboard/google/cyan: Cyan board support Add initial files for the cyan board. BRANCH=none BUG=None Test=Build and run on cyan Change-Id: I935839be033c25e197e78fbee306104b4162a99a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/google/cyan/Kconfig | 62 +++++ src/mainboard/google/cyan/Kconfig.name | 2 + src/mainboard/google/cyan/Makefile.inc | 33 +++ src/mainboard/google/cyan/acpi/chromeos.asl | 37 +++ src/mainboard/google/cyan/acpi/dptf.asl | 93 +++++++ src/mainboard/google/cyan/acpi/ec.asl | 25 ++ src/mainboard/google/cyan/acpi/mainboard.asl | 266 +++++++++++++++++++++ src/mainboard/google/cyan/acpi/superio.asl | 34 +++ src/mainboard/google/cyan/acpi_tables.c | 69 ++++++ src/mainboard/google/cyan/chromeos.c | 142 +++++++++++ src/mainboard/google/cyan/cmos.layout | 140 +++++++++++ src/mainboard/google/cyan/com_init.c | 48 ++++ src/mainboard/google/cyan/devicetree.cb | 139 +++++++++++ src/mainboard/google/cyan/dsdt.asl | 58 +++++ src/mainboard/google/cyan/ec.c | 55 +++++ src/mainboard/google/cyan/ec.h | 69 ++++++ src/mainboard/google/cyan/fadt.c | 51 ++++ src/mainboard/google/cyan/gpio.c | 266 +++++++++++++++++++++ src/mainboard/google/cyan/irqroute.c | 23 ++ src/mainboard/google/cyan/irqroute.h | 64 +++++ src/mainboard/google/cyan/mainboard.c | 27 +++ src/mainboard/google/cyan/onboard.h | 81 +++++++ src/mainboard/google/cyan/ramstage.c | 26 ++ src/mainboard/google/cyan/romstage.c | 48 ++++ src/mainboard/google/cyan/smihandler.c | 166 +++++++++++++ src/mainboard/google/cyan/spd/Makefile.inc | 42 ++++ .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 +++ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 +++ src/mainboard/google/cyan/spd/spd.c | 115 +++++++++ src/mainboard/google/cyan/w25q64.c | 75 ++++++ 31 files changed, 2352 insertions(+) diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig new file mode 100644 index 0000000..dd4543c --- /dev/null +++ b/src/mainboard/google/cyan/Kconfig @@ -0,0 +1,62 @@ +if BOARD_GOOGLE_CYAN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ALWAYS_LOAD_OPROM + select BOARD_ROMSIZE_KB_8192 +# select ENABLE_BUILTIN_COM1 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_BRASWELL + select VIRTUAL_DEV_SWITCH + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory configuration data. + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory SPD data. + +config DYNAMIC_VNN_SUPPORT + bool "Enables support for Dynamic VNN" + default n + +config MAINBOARD_DIR + string + default google/cyan + +config MAINBOARD_PART_NUMBER + string + default "Cyan" + +config MAINBOARD_VENDOR + string + default "Google" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +if !CONFIG_GOP_SUPPORT +config VGA_BIOS_FILE + string + default "3rdparty/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT + default "3rdparty/mainboard/intel/strago/vgabios.bin" if !C0_DISP_SUPPORT + +config VGA_BIOS_ID + string + default "8086,22b1" if C0_DISP_SUPPORT + default "8086,22b0" if !C0_DISP_SUPPORT +endif + +endif # BOARD_GOOGLE_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name new file mode 100644 index 0000000..a4562d3 --- /dev/null +++ b/src/mainboard/google/cyan/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_CYAN + bool "Cyan" diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc new file mode 100755 index 0000000..f1b501f --- /dev/null +++ b/src/mainboard/google/cyan/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += spd + +romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += irqroute.c +ramstage-y += ramstage.c +ramstage-y += w25q64.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl new file mode 100644 index 0000000..04edefa --- /dev/null +++ b/src/mainboard/google/cyan/acpi/chromeos.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: We need to encode gpios within the 3 separate banks + * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded + * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. + */ + +Name(OIPG, Package() { + /* No physical recovery button */ + Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, + Package () { 0x0003, 1, 0x2006, "Braswell" }, +}) diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl new file mode 100755 index 0000000..67bdbb4 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/braswell/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl new file mode 100644 index 0000000..5736c27 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/cyan/ec.h> + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl new file mode 100755 index 0000000..831453d --- /dev/null +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <mainboard/google/cyan/onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + +Scope (\_SB.I2C1) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen ") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x10, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { CYAN_TOUCH_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.I2C2) +{ + /* Maxim Audio Codec */ + Device (MAXM) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } + Device (TISW) /* TI Switch driver I2C */ + { + Name (_ADR, 0) + Name (_HID, TI_SWITCH_HID) + Name (_CID, TI_SWITCH_CID) + Name (_DDN, TI_SWITCH_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { CYAN_JACK_TI_GPIO_INDEX } + + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + } +} + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C5", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C6", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_TRACKPAD_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX } + }) +} + +Scope (\_SB.GPNC) +{ + Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_SCI_GPIO_INDEX } + }) + Return (RBUF) + } + + Method (_E0F, 0, NotSerialized) // _Exx: Edge-Triggered GPE + { + } +} diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl new file mode 100755 index 0000000..018fdb0 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/cyan/ec.h> +#include <mainboard/google/cyan/onboard.h> + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Override default IRQ settings */ +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\ + BOARD_I8042_IRQ} + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c new file mode 100755 index 0000000..3c2a7ba --- /dev/null +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <string.h> +#include <types.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 1; + + /* Enable DPTF */ + gnvs->dpte = 1; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c new file mode 100644 index 0000000..07de630 --- /dev/null +++ b/src/mainboard/google/cyan/chromeos.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#endif +#include <soc/gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ +#define WP_STATUS_PAD 36 + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static int get_lid_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + return !!(ec_switches & EC_SWITCH_LID_OPEN); +#else + /* Default to force open. */ + return 1; +#endif +} + +static void fill_lb_gpio(struct lb_gpio *gpio, int port, int polarity, + const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = port; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + recovery_mode_enabled()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif /* ENV_RAMSTAGE */ + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + u32 ec_events; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +#else + return 0; +#endif +} + +int clear_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + const uint32_t kb_rec_mask = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + /* Unconditionally clear the EC recovery request. */ + return google_chromeec_clear_events_b(kb_rec_mask); +#else + return 0; +#endif +} + +int get_write_protect_state(void) +{ + /* + * The vboot loader queries this function in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. The + * hardware defaults to an input but there is a 20K pulldown. Externally + * there is a 10K pullup. Disable the internal pull in romstage so that + * there isn't any ambiguity in the reading. + */ +#if ENV_ROMSTAGE + ssus_disable_internal_pull(WP_STATUS_PAD); +#endif + + /* WP is enabled when the pin is reading high. */ + return ssus_get_gpio(WP_STATUS_PAD); +} diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout new file mode 100644 index 0000000..18bf4ce --- /dev/null +++ b/src/mainboard/google/cyan/cmos.layout @@ -0,0 +1,140 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c new file mode 100644 index 0000000..b07b205 --- /dev/null +++ b/src/mainboard/google/cyan/com_init.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void mainboard_pre_console_init(struct romstage_params *params) +{ + uint32_t reg; + uint32_t *pad_config_reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* + * Set up the pads to select the UART function for Cyan + * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Set Mode 2 for UART0_RXD + * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD + */ + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); + + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); +} diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb new file mode 100755 index 0000000..490e8ef --- /dev/null +++ b/src/mainboard/google/cyan/devicetree.cb @@ -0,0 +1,139 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "1" + register "PcdEnableAzalia" = "1" + register "PcdEnableSata" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "1" + register "PcdEnableI2C3" = "1" + register "PcdEnableI2C4" = "1" + register "PcdEnableI2C5" = "1" + register "PcdEnableI2C6" = "1" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "SVID_CONFIG3" + register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdPciClkSsc" = "1" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 on end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 on end # 8086 22c3 - I2C Port 3 + device pci 18.4 on end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 on end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 on end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 on end # 8086 2290 - SPI 2 + device pci 1e.7 on end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl new file mode 100755 index 0000000..9f1db24 --- /dev/null +++ b/src/mainboard/google/cyan/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, /* DSDT revision: ACPI v5.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/braswell/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/braswell/acpi/globalnvs.asl> + + #include <soc/intel/braswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* #include <soc/intel/braswell/acpi/northcluster.asl> */ + #include <soc/intel/braswell/acpi/southcluster.asl> + #include <soc/intel/braswell/acpi/dptf/cpu.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/braswell/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c new file mode 100755 index 0000000..e233408 --- /dev/null +++ b/src/mainboard/google/cyan/ec.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" +#include <vendorcode/google/chromeos/chromeos.h> +#include <types.h> + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Restore SCI event mask on resume. */ + if (acpi_slp_type == 3) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + /* Clear wake events, these are enabled on entry to sleep */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + google_chromeec_set_wake_mask(0); +#endif + + post_code(0xf1); +} diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h new file mode 100755 index 0000000..7e70d48 --- /dev/null +++ b/src/mainboard/google/cyan/ec.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +/* GPIO_S0_000 is EC_SCI#, but it is bit 16 in GPE_STS */ +#define EC_SCI_GPI 16 +/* GPIO_S5_07 is EC_SMI#, but it is bit 19 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 19 + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c new file mode 100644 index 0000000..45a680a --- /dev/null +++ b/src/mainboard/google/cyan/fadt.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c new file mode 100644 index 0000000..09b31a2 --- /dev/null +++ b/src/mainboard/google/cyan/gpio.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERTB */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + Native_M5, /* 00 GPIO_DFX0 */ + Native_M5, /* 01 GPIO_DFX3 */ + Native_M1, /* 02 GPIO_DFX7 */ + Native_M5, /* 03 GPIO_DFX1 */ + Native_M1, /* 04 GPIO_DFX5 */ + Native_M1, /* 05 GPIO_DFX4 */ + GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), + /* 06 GPIO_DFX8 */ + Native_M5, /* 07 GPIO_DFX2 */ + Native_M8, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + GPIO_NC, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/cyan/irqroute.c b/src/mainboard/google/cyan/irqroute.c new file mode 100644 index 0000000..83207d9 --- /dev/null +++ b/src/mainboard/google/cyan/irqroute.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/google/cyan/irqroute.h b/src/mainboard/google/cyan/irqroute.h new file mode 100644 index 0000000..5353d42 --- /dev/null +++ b/src/mainboard/google/cyan/irqroute.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +#define TPAD_IRQ_OFFSET 0 +#define TOUCH_IRQ_OFFSET 1 +#define I8042_IRQ_OFFSET 2 +#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +#define TPAD_IRQ_GPIO 55 +#define TOUCH_IRQ_GPIO 72 +#define I8042_IRQ_GPIO 101 +#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c new file mode 100755 index 0000000..f155a04 --- /dev/null +++ b/src/mainboard/google/cyan/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootstate.h> +#include <device/device.h> +#include <soc/gpio.h> + +struct chip_operations mainboard_ops = { +}; diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h new file mode 100755 index 0000000..00ff28e --- /dev/null +++ b/src/mainboard/google/cyan/onboard.h @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include "irqroute.h" + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* + * gpio based irq for kbd, 17th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 18 + */ +/* ToDO: change kbd irq to gpio bank index */ +#define CYAN_KBD_IRQ 182 + + +/* SCI: Gpio index in N bank */ +#define CYAN_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define CYAN_TRACKPAD_GPIO_INDEX 18 +/* Touch: Gpio index in SW bank */ +#define CYAN_TOUCH_GPIO_INDEX 76 +/* TI Audio: Gpio index in SW bank */ +#define CYAN_JACK_TI_GPIO_INDEX 34 +/* MAXIM Audio: Gpio index in SE bank */ +#define CYAN_JACK_MAXIM_GPIO_INDEX 77 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ + +#define BOARD_I8042_IRQ CYAN_KBD_IRQ +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "193C9890" +#define AUDIO_CODEC_CID "193C9890" +#define AUDIO_CODEC_DDN "Maxim 98090 Codec " +#define AUDIO_CODEC_I2C_ADDR 0x10 + +#define TI_SWITCH_HID "104C227E" +#define TI_SWITCH_CID "104C227E" +#define TI_SWITCH_DDN "TI SWITCH " +#define TI_SWITCH_I2C_ADDR 0x3B +#endif diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c new file mode 100644 index 0000000..80df958 --- /dev/null +++ b/src/mainboard/google/cyan/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(UPD_DATA_REGION *upd_ptr) +{ + if (IS_ENABLED(CONFIG_DYNAMIC_VNN_SUPPORT)) + upd_ptr->ChvSvidConfig = SVID_CONFIG1; +} diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c new file mode 100755 index 0000000..a6d7e36 --- /dev/null +++ b/src/mainboard/google/cyan/romstage.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data *ps = rp->pei_data; + + mainboard_fill_spd_data(ps); + + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +} + +void mainboard_memory_init_params( + struct romstage_params *params, + UPD_DATA_REGION *upd_ptr) +{ + /* Update SPD data */ + upd_ptr->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + upd_ptr->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + upd_ptr->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c new file mode 100644 index 0000000..5af0421 --- /dev/null +++ b/src/mainboard/google/cyan/smihandler.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#include <elog.h> +#include <soc/nvs.h> +#include <soc/pm.h> + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +static uint8_t mainboard_smi_ec(void) +{ + uint8_t cmd = google_chromeec_get_event(); + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt; + +#if IS_ENABLED(CONFIG_ELOG_GSMI) + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); + outl(pm1_cnt, pmbase + PM1_CNT); + break; + } + + return cmd; +} +#endif + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +#endif +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); +#endif + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case 5: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); +#endif + break; + } + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0) + ; +#endif +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); +#endif + break; + case APM_CNT_ACPI_DISABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); +#endif + break; + } + return 0; +} diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc new file mode 100644 index 0000000..4b4bff6 --- /dev/null +++ b/src/mainboard/google/cyan/spd/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex new file mode 100644 index 0000000..ff4fd29 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 ff ab +48 4d 54 34 32 35 53 36 +41 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex new file mode 100644 index 0000000..fdd1a43 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex @@ -0,0 +1,32 @@ +92 13 0B 03 04 19 02 02 +03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 +00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 +43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex new file mode 100644 index 0000000..e0b0ac5 --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 +88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 +34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c new file mode 100644 index 0000000..01f4dd7 --- /dev/null +++ b/src/mainboard/google/cyan/spd/spd.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> + +#define SPD_SIZE 256 +#define SATA_GP3_PAD_CFG0 0x5828 +#define I2C3_SCL_PAD_CFG0 0x5438 +#define MF_PLT_CLK1_PAD_CFG0 0x4410 +#define I2C3_SDA_PAD_CFG0 0x5420 + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ +static const uint32_t dual_channel_config = (1 << 0); + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; + ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) + << 2; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; + + /* + * There are only 2 SPDs supported on Cyan Board: + * Samsung 4G:0000 & Hynix 2G:0011 + */ + + /* + * RAMID0 on the first boot does not read the correct value,so checking + * bit 1 is enough as WA + */ + if (ram_id > 0) + ram_id = 3; + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + + if (ram_id >= total_spds) + return NULL; + + /* Single channel configs */ + if (dual_channel_config & (1 << ram_id)) + *dual = 1; + + return &spd_file_content[SPD_SIZE * ram_id]; +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + struct cbfs_file *spd_file; + void *spd_content; + int dual_channel = 0; + + /* Find the SPD data in CBFS. */ + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), + ntohl(spd_file->len) / SPD_SIZE, + &dual_channel); + if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_SIZE); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + ps->spd_data_ch0 = spd_content; + ps->spd_ch0_config = 1; + if (dual_channel) { + ps->spd_data_ch1 = spd_content; + ps->spd_ch1_config = 1; + } else { + ps->spd_ch1_config = 2; + } + } +} diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c new file mode 100644 index 0000000..4399d88 --- /dev/null +++ b/src/mainboard/google/cyan/w25q64.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/spi.h> +#include <string.h> + +/* + * SPI lockdown configuration W25Q64FW. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +}

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Patch merged into coreboot/master: 4e50cdd vboot: move to region_devices
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit 4e50cdd979c03a0d64cc1b4c9ada45822aa6d346 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 15 23:25:46 2015 -0500 vboot: move to region_devices Now that vboot is using offsets for everything remove the pass through vboot_get_region() and use region_devices as first class citizens. Change-Id: I1a86f3725e5bce38e6ca31e9641b1a8f4ac50e96 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10225 for details. -gerrit

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Patch merged into coreboot/master: 0424c95 fmap: new API using region_device
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit 0424c95a6dafdb65070538d6c5aa394b75eb9850 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Mar 28 23:56:22 2015 -0500 fmap: new API using region_device Instead of being pointer based use the region infrastrucutre. Additionally, this removes the need for arch-specific compilation paths. The users of the new API can use the region APIs to memory map or read the region provided by the new fmap API. Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9170 for details. -gerrit

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Patch merged into coreboot/master: b6981c0 vboot: use only offsets for tracking firmware components
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit b6981c0f9c4ce89c4209c14fb326a414096f2ff1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 15 15:57:51 2015 -0500 vboot: use only offsets for tracking firmware components Because of the fmap API returning pointers to represent regions within the boot device a vboot_region structure was used to track the case where offsets could be pointers on x86 but not on !x86. Normalize this tracking to use offsets only as it provides consistency in the code. Change-Id: I63c08b31ace3bd0e66ebc17e308f87eb5f857c86 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10221 for details. -gerrit

1 0

Patch merged into coreboot/master: b59eaf6 cbfs: remove unused CBFS_HEADER_ROM_OFFSET option
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit b59eaf6ca88267baf28cb318117696df1fb03fee Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 15 13:55:08 2015 -0500 cbfs: remove unused CBFS_HEADER_ROM_OFFSET option The CBFS_HEADER_ROM_OFFSET went away. Remove remaining defintions that are not used. Change-Id: Ibedce988143f0b7167cea1b27de5b33698b5d82b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10217 for details. -gerrit

1 0

Patch merged into coreboot/master: c6588c5 coreboot: introduce boot_device
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit c6588c5af94e568bddd8111c3fca736f464042cf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 15 13:15:34 2015 -0500 coreboot: introduce boot_device The boot_device is a region_device that represents the device from which coreboot retrieves and boots its stages. The existing cbfs implementations use the boot_device as the intermediary for accessing the CBFS region. Also, there's currently only support for a read-only view of the boot_device. i.e. one cannot write to the boot_device using this view. However, a writable boot_device could be added in the future. Change-Id: Ic0da796ab161b8025c90631be3423ba6473ad31c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10216 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10216 for details. -gerrit

1 0

Patch merged into coreboot/master: def0fb5 pistashio: bump up romstage size
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit def0fb57dfd91e6599c622a7b2769164a5c02ef0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 15 16:54:17 2015 -0500 pistashio: bump up romstage size Making large changes in pieces is leading to a little bloat. Bump up the romstage size temporarily so that jenkins will be happy. Change-Id: I6f9facb4ca488cf41741a3ed6d0ed7f66d4778b3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10220 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10220 for details. -gerrit

1 0

Patch set updated for coreboot: 4a2457b cbmem: CBMEM_INIT_HOOK() API
by Marc Jones 26 May '15

26 May '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7878 -gerrit commit 4a2457bac778b1313c085d2cc5ef83a2e9a08399 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 7 04:48:43 2015 +0200 cbmem: CBMEM_INIT_HOOK() API Squashed two changes from chromium.git. Note that timestamps still don't work for non-x86, but that can be a follow-on change. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/arm64/include/arch/early_variables.h | 1 - src/arch/x86/boot/cbmem.c | 22 ---------------------- src/arch/x86/boot/gdt.c | 3 ++- src/arch/x86/include/arch/early_variables.h | 14 +------------- src/arch/x86/init/romstage.ld | 9 ++++----- src/cpu/x86/car.c | 18 +++--------------- src/drivers/usb/ehci_debug.c | 2 +- src/include/cbmem.h | 22 ++++++++++++++++++++++ src/include/console/cbmem_console.h | 6 ------ src/include/cpu/x86/gdt.h | 3 --- src/include/timestamp.h | 2 -- src/lib/cbmem_common.c | 19 +++++++------------ src/lib/cbmem_console.c | 7 +++---- src/lib/ramstage.ld | 3 +++ src/lib/rmodule.ld | 3 +++ src/lib/romstage.ld | 6 ++++-- src/lib/timestamp.c | 7 ++++--- src/soc/intel/baytrail/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/power_state.c | 2 +- src/soc/nvidia/tegra132/romstage.c | 2 -- 21 files changed, 59 insertions(+), 95 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 725650a..5e09448 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 725650a..5e09448 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index a9127d7..e279db9 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -20,12 +20,6 @@ #include <cbmem.h> #include <arch/acpi.h> -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <arch/early_variables.h> -#include <cpu/x86/gdt.h> -#include <console/cbmem_console.h> -#include <timestamp.h> - #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) @@ -71,22 +65,6 @@ void *cbmem_top(void) #endif /* LATE_CBMEM_INIT */ -void cbmem_run_init_hooks(void) -{ - /* Migrate car.global_data. */ - car_migrate_variables(); - -#if !defined(__PRE_RAM__) - /* Relocate CBMEM console. */ - cbmemc_reinit(); - - /* Relocate timestamps stash. */ - timestamp_reinit(); - - move_gdt(); -#endif -} - /* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c index 9d9517a..e13d3bc 100644 --- a/src/arch/x86/boot/gdt.c +++ b/src/arch/x86/boot/gdt.c @@ -32,7 +32,7 @@ struct gdtarg { /* Copy GDT to new location and reload it. * FIXME: We only do this for BSP CPU. */ -void move_gdt(void) +static void move_gdt(void) { void *newgdt; u16 num_gdt_bytes = (u32)&gdt_end - (u32)&gdt; @@ -55,3 +55,4 @@ void move_gdt(void) __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); printk(BIOS_DEBUG, "ok\n"); } +RAMSTAGE_CBMEM_INIT_HOOK(move_gdt) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index bfb1201..85bdc80 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -29,13 +29,6 @@ asm(".previous"); #define CAR_GLOBAL __attribute__((used,section(".car.global_data#"))) #endif /* __clang__ */ -#define CAR_MIGRATE_ATTR __attribute__ ((used,section (".car.migrate"))) - -/* Call migrate_fn_() when CAR globals are migrated. */ -#define CAR_MIGRATE(migrate_fn_) \ - static void (* const migrate_fn_ ## _ptr)(void) CAR_MIGRATE_ATTR = \ - migrate_fn_; - /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); @@ -50,17 +43,12 @@ void *car_sync_var_ptr(void *var); #define car_set_var(var, val) \ do { car_get_var(var) = (val); } while(0) -/* Migrate the CAR variables to memory. */ -void car_migrate_variables(void); - #else #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_sync_var(var) (var) -#define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } +#define car_set_var(var, val) do { (var) = (val); } while (0); #endif #endif diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index ae7049b..74e665f 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -34,15 +34,14 @@ SECTIONS *(.text); *(.text.*); *(.rom.data); + . = ALIGN(4); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); *(.rom.data.*); . = ALIGN(16); - _car_migrate_start = .; - KEEP(*(.car.migrate)); - LONG(0); - _car_migrate_end = .; - . = ALIGN(16); _erom = .; } diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 165a0e6..ffcf0db 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -136,21 +136,9 @@ static void do_car_migrate_variables(void) car_migrated = ~0; } -static void do_car_migrate_hooks(void) +static void car_migrate_variables(void) { - car_migration_func_t *migrate_func; - /* Call all the migration functions. */ - migrate_func = &_car_migrate_start; - while (*migrate_func != NULL) { - (*migrate_func)(); - migrate_func++; - } -} - -void car_migrate_variables(void) -{ - if (!IS_ENABLED(PLATFORM_USES_FSP1_0)) + if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE) && !IS_ENABLED(PLATFORM_USES_FSP1_0)) do_car_migrate_variables(); - - do_car_migrate_hooks(); } +ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 68fd0fa..a6de8b2 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -682,7 +682,7 @@ static void migrate_ehci_debug(void) memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); car_set_var(glob_dbg_info_p, dbg_info_cbmem); } -CAR_MIGRATE(migrate_ehci_debug); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug); #endif int dbgp_ep_is_active(struct dbgp_pipe *pipe) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a8ab3cd..e6e976c 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -203,6 +203,7 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +typedef void (* const cbmem_init_hook_t)(void); void cbmem_run_init_hooks(void); void cbmem_fail_resume(void); @@ -213,6 +214,27 @@ void cbmem_add_bootmem(void); void cbmem_list(void); #endif /* __PRE_RAM__ */ +#include <rules.h> +#if ENV_RAMSTAGE +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#elif ENV_ROMSTAGE +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#else +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#endif /* ENV_RAMSTAGE */ + + /* These are for compatibility with old boards only. Any new chipset and board * must implement cbmem_top() for both romstage and ramstage to support * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index e9ec66e..06013f2 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -25,12 +25,6 @@ void cbmemc_init(void); void cbmemc_tx_byte(unsigned char data); -#if CONFIG_CONSOLE_CBMEM -void cbmemc_reinit(void); -#else -static inline void cbmemc_reinit(void) {} -#endif - #define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ (ENV_RAMSTAGE || (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) && \ (ENV_ROMSTAGE || (ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE)))) diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index 8525a3c..a96b0e4 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -28,7 +28,4 @@ extern char _secondary_gdt_addr[]; extern char _secondary_start[]; extern char _secondary_start_end[]; -/* Defined in src/arch/x86/boot/gdt.c */ -void move_gdt(void); - #endif /* CPU_X86_GDT */ diff --git a/src/include/timestamp.h b/src/include/timestamp.h index d9afeea..a248ea4 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -92,12 +92,10 @@ enum timestamp_id { void timestamp_init(uint64_t base); void timestamp_add(enum timestamp_id id, uint64_t ts_time); void timestamp_add_now(enum timestamp_id id); -void timestamp_reinit(void); #else #define timestamp_init(base) #define timestamp_add(id, time) #define timestamp_add_now(id) -#define timestamp_reinit() #endif /* Implemented by the architecture code */ diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index e9beb5f..e0c5a89 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -24,26 +24,21 @@ #include <arch/acpi.h> #endif -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <console/cbmem_console.h> -#include <timestamp.h> +extern cbmem_init_hook_t _cbmem_init_hooks; +extern cbmem_init_hook_t _ecbmem_init_hooks; - -/* FIXME: Replace with CBMEM_INIT_HOOKS API. */ -#if !IS_ENABLED(CONFIG_ARCH_X86) void cbmem_run_init_hooks(void) { - /* Relocate CBMEM console. */ - cbmemc_reinit(); - - /* Relocate timestamps stash. */ - timestamp_reinit(); + cbmem_init_hook_t *init_hook_ptr = &_cbmem_init_hooks; + while (init_hook_ptr != &_ecbmem_init_hooks) { + (*init_hook_ptr)(); + init_hook_ptr++; + } } void __attribute__((weak)) cbmem_fail_resume(void) { } -#endif #if ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) static void init_cbmem_post_device(void *unused) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index e9607f3..4866454 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -208,7 +208,7 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p, new_cons_p->buffer_cursor = cursor; } -void cbmemc_reinit(void) +static void cbmemc_reinit(void) { struct cbmem_console *cbm_cons_p; const size_t size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE; @@ -233,6 +233,8 @@ void cbmemc_reinit(void) init_console_ptr(cbm_cons_p, size, flags); } +ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) #if IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART) void cbmem_dump_console(void) @@ -249,6 +251,3 @@ void cbmem_dump_console(void) uart_tx_byte(0, cbm_cons_p->buffer_body[cursor]); } #endif - -/* Call cbmemc_reinit() at CAR migration time. */ -CAR_MIGRATE(cbmemc_reinit) diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld index 30b18a7..402f495 100644 --- a/src/lib/ramstage.ld +++ b/src/lib/ramstage.ld @@ -64,6 +64,9 @@ LONG(0); LONG(0); _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata) *(.rodata.*) diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 70a2d3d..0e9c880 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -55,6 +55,9 @@ SECTIONS LONG(0); LONG(0); _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; . = ALIGN(8); diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld index 34e76c0..ef00d48 100644 --- a/src/lib/romstage.ld +++ b/src/lib/romstage.ld @@ -29,12 +29,14 @@ } : to_load .data . : { + . = ALIGN(8); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); *(.data); *(.data.*); - _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0; - _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0; . = ALIGN(8); } diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 8c82649..3b886b6 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -157,7 +157,7 @@ void timestamp_init(uint64_t base) #endif } -void timestamp_reinit(void) +static void timestamp_reinit(void) { if (!timestamp_should_run()) return; @@ -172,8 +172,9 @@ void timestamp_reinit(void) timestamp_do_sync(); } -/* Call timestamp_reinit at CAR migration time. */ -CAR_MIGRATE(timestamp_reinit) +/* Call timestamp_reinit CBMEM init hooks. */ +ROMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) /* Provide default timestamp implementation using monotonic timer. */ uint64_t __attribute__((weak)) timestamp_get(void) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index bfc8678..d69d2ab 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -157,7 +157,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) static struct chipset_power_state *fill_power_state(void) { diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 22ec8a6..ce52b49 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -50,7 +50,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) /* Return 0, 3, or 5 to indicate the previous sleep state. */ static int prev_sleep_state(struct chipset_power_state *ps) diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index fedc1d4..6476e06 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -76,8 +76,6 @@ void romstage(void) romstage_mainboard_init(); - cbmemc_reinit(); - run_ramstage(); }

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Patch set updated for coreboot: ada6e09 AGESA: Separate HeapManager declarations from BiosCallOuts
by Kyösti Mälkki 26 May '15

26 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10317 -gerrit commit ada6e09800c37a0dfe9b598e4b371d23078f92e3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 11:25:13 2015 +0300 AGESA: Separate HeapManager declarations from BiosCallOuts Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/heapmanager.c | 40 ++++++++++++++++++++----- src/cpu/amd/agesa/s3_resume.h | 4 +++ src/northbridge/amd/agesa/BiosCallOuts.h | 18 ----------- src/northbridge/amd/agesa/agesawrapper.c | 1 + src/northbridge/amd/agesa/oem_s3.c | 14 +++++---- src/southbridge/amd/agesa/hudson/agesawrapper.c | 8 +++-- 6 files changed, 51 insertions(+), 34 deletions(-) diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index b3af18c..52a4e50 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -10,24 +10,48 @@ #include <arch/acpi.h> #include <string.h> +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) + +/* BIOS_HEAP_START_ADDRESS is only for cold boots. */ +#define BIOS_HEAP_SIZE 0x30000 +#define BIOS_HEAP_START_ADDRESS 0x010000000 + +#else + +/* BIOS_HEAP_START_ADDRESS is only for cold boots. */ +#define BIOS_HEAP_SIZE 0x20000 +#define BIOS_HEAP_START_ADDRESS (BSP_STACK_BASE_ADDR - BIOS_HEAP_SIZE) + +#endif + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && (HIGH_MEMORY_SCRATCH < BIOS_HEAP_SIZE) #error Increase HIGH_MEMORY_SCRATCH allocation #endif -UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) +void *GetHeapBase(void) { - UINT32 heap = BIOS_HEAP_START_ADDRESS; + void *heap = (void *)BIOS_HEAP_START_ADDRESS; if (acpi_is_wakeup_s3()) - heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH); + heap = cbmem_find(CBMEM_ID_RESUME_SCRATCH); return heap; } void EmptyHeap(void) { - void *BiosManagerPtr = (void *) GetHeapBase(NULL); - memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); + void *base = GetHeapBase(); + memset(base, 0, BIOS_HEAP_SIZE); +} + +void ResumeHeap(void **heap, size_t *len) +{ + void *base = GetHeapBase(); + memset(base, 0, BIOS_HEAP_SIZE); + *heap = base; + *len = BIOS_HEAP_SIZE; } #if (IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || \ @@ -96,7 +120,7 @@ static AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigP #endif AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { @@ -221,7 +245,7 @@ static AGESA_STATUS agesa_DeallocateBuffer(UINT32 Func, UINT32 Data, VOID *Confi AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; /* Find target node to deallocate in list of allocated nodes. @@ -332,7 +356,7 @@ static AGESA_STATUS agesa_LocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 97a2a21..8a855e2 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -26,6 +26,10 @@ void prepare_for_resume(void); void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); const void *OemS3Saved_MTRR_Storage(void); +void *GetHeapBase(void); +void EmptyHeap(void); +void ResumeHeap(void **heap, size_t *len); + #define BSP_STACK_BASE_ADDR 0x30000 #if 1 diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h index cfe1852..e763b8c 100644 --- a/src/northbridge/amd/agesa/BiosCallOuts.h +++ b/src/northbridge/amd/agesa/BiosCallOuts.h @@ -24,24 +24,6 @@ #include "Porting.h" #include "AGESA.h" -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) || \ - IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) - -#define BIOS_HEAP_START_ADDRESS 0x010000000 -#define BIOS_HEAP_SIZE 0x30000 - -#else - -#define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */ -#define BIOS_HEAP_SIZE 0x20000 - -#endif - - -UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); -void EmptyHeap(void); - AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index 8ad36c7..bfad605 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -23,6 +23,7 @@ #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> #include "heapManager.h" diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index 779e28b..16426bc 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -22,7 +22,6 @@ #include <string.h> #include <cbmem.h> #include <cpu/amd/agesa/s3_resume.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <AGESA.h> @@ -85,18 +84,21 @@ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams) AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams) { AMD_S3_PARAMS *dataBlock = &S3LateParams->S3DataBlock; - AMD_CONFIG_PARAMS StdHeader; u32 pos, size; + void *dst; + size_t len; + /* TODO: Named volatile, do we need to save it over S3? */ get_s3nv_data(S3DataTypeVolatile, &pos, &size); - - u32 len = *(UINT32 *) pos; void *src = (void *) (pos + sizeof(UINT32)); - void *dst = (void *) GetHeapBase(&StdHeader); - memcpy(dst, src, len); + ResumeHeap(&dst, &len); dataBlock->VolatileStorageSize = len; dataBlock->VolatileStorage = dst; + + len = *(UINT32 *) pos; + memcpy(dst, src, len); + return AGESA_SUCCESS; } diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c index a7e4289..b98d7b4 100644 --- a/src/southbridge/amd/agesa/hudson/agesawrapper.c +++ b/src/southbridge/amd/agesa/hudson/agesawrapper.c @@ -41,13 +41,17 @@ extern UINT8 picr_data[0x54], intr_data[0x54]; +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#error Use of GetHeapBase() is incorrect or at least suspicious +#endif + AGESA_STATUS agesawrapper_fchs3earlyrestore (void) { FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader; StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10; StdHeader.AltImageBasePtr = 0; StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; StdHeader.Func = 0; @@ -67,7 +71,7 @@ AGESA_STATUS agesawrapper_fchs3laterestore (void) UINT8 byte; StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.HeapBasePtr = (uintptr_t) GetHeapBase() + 0x10; StdHeader.AltImageBasePtr = 0; StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; StdHeader.Func = 0;

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coreboot-gerrit May 2015