coreboot-gerrit May 2015

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Patch merged into coreboot/master: b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts
by gerrit＠coreboot.org 27 May '15

27 May '15

the following patch was just integrated into master: commit b1fcbf364f0d81b8d28755055ae9558af2f4b712 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 11:25:13 2015 +0300 AGESA: Separate HeapManager declarations from BiosCallOuts Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/10317 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/10317 for details. -gerrit

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Patch merged into coreboot/master: f728408 AGESA: Split S3 backup in CBMEM
by gerrit＠coreboot.org 27 May '15

27 May '15

the following patch was just integrated into master: commit f7284089e3657c66efeeb180a1f101a60d832901 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 26 10:12:45 2015 +0300 AGESA: Split S3 backup in CBMEM Use separate CBMEM allocations for stack and heap on S3 resume path. The allocation of HIGH_SCRATCH_MEMORY is specific to AGESA and is moved out of globals and ACPI. This region is a replacement for BIOS_HEAP_SIZE used on non-resume paths. Change-Id: I6658ce1c06964de5cf13b4e3c84d571f46ce76f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/10316 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10316 for details. -gerrit

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New patch to review for coreboot: 9acee9d Copy gizmosphere/gizmo2 as bap/ode_e20XX
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10320 -gerrit commit 9acee9d6649f61d425f6bc7dc2d5800b0360910a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 27 12:44:16 2015 +0300 Copy gizmosphere/gizmo2 as bap/ode_e20XX Change-Id: I54a4719c571e18eb38a47e50ea69a4a85195d4dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/bap/Kconfig | 16 + src/mainboard/bap/Kconfig.name | 2 + src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 221 ++++++++++ src/mainboard/bap/ode_e20XX/Kconfig | 68 +++ src/mainboard/bap/ode_e20XX/Kconfig.name | 2 + src/mainboard/bap/ode_e20XX/Makefile.inc | 47 +++ .../bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex | 235 +++++++++++ src/mainboard/bap/ode_e20XX/OptionsIds.h | 63 +++ src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c | 155 +++++++ src/mainboard/bap/ode_e20XX/acpi/AmdImc.asl | 114 +++++ src/mainboard/bap/ode_e20XX/acpi/gpe.asl | 78 ++++ src/mainboard/bap/ode_e20XX/acpi/ide.asl | 250 +++++++++++ src/mainboard/bap/ode_e20XX/acpi/mainboard.asl | 41 ++ src/mainboard/bap/ode_e20XX/acpi/routing.asl | 197 +++++++++ src/mainboard/bap/ode_e20XX/acpi/sata.asl | 150 +++++++ src/mainboard/bap/ode_e20XX/acpi/si.asl | 27 ++ src/mainboard/bap/ode_e20XX/acpi/sleep.asl | 97 +++++ src/mainboard/bap/ode_e20XX/acpi/superio.asl | 20 + src/mainboard/bap/ode_e20XX/acpi/thermal.asl | 20 + src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl | 132 ++++++ src/mainboard/bap/ode_e20XX/acpi_tables.c | 60 +++ src/mainboard/bap/ode_e20XX/board_info.txt | 1 + src/mainboard/bap/ode_e20XX/buildOpts.c | 466 +++++++++++++++++++++ src/mainboard/bap/ode_e20XX/cmos.layout | 79 ++++ src/mainboard/bap/ode_e20XX/devicetree.cb | 64 +++ src/mainboard/bap/ode_e20XX/dsdt.asl | 91 ++++ src/mainboard/bap/ode_e20XX/irq_tables.c | 107 +++++ src/mainboard/bap/ode_e20XX/mainboard.c | 137 ++++++ src/mainboard/bap/ode_e20XX/mptable.c | 169 ++++++++ src/mainboard/bap/ode_e20XX/romstage.c | 118 ++++++ 30 files changed, 3227 insertions(+) diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig new file mode 100644 index 0000000..17b85bf --- /dev/null +++ b/src/mainboard/bap/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_BAP + +choice + prompt "Mainboard model" + +source "src/mainboard/bap/*/Kconfig.name" + +endchoice + +source "src/mainboard/bap/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "BAP" + +endif # VENDOR_BAP diff --git a/src/mainboard/bap/Kconfig.name b/src/mainboard/bap/Kconfig.name new file mode 100644 index 0000000..d923316 --- /dev/null +++ b/src/mainboard/bap/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_BAP + bool "BAP" diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c new file mode 100644 index 0000000..953eb40 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -0,0 +1,221 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif +#include <stdlib.h> + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * ALC272 Verb Table + */ +const CODEC_ENTRY Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, // - SPDIF_OUT2 + {0x12, 0x411111F0}, // - DMIC_1/2 + {0x13, 0x411111F0}, // - DMIC_3/4 + {0x14, 0x411111F0}, // Port D - LOUT1 + {0x15, 0x01011050}, // Port A - LOUT2 Explorer 2x DAC + {0x16, 0x411111F0}, // + {0x17, 0x411111F0}, // Port H - MONO + {0x18, 0x01a11840}, // Port B - MIC1 + {0x19, 0x411111F0}, // Port F - MIC2 + {0x1a, 0x01811030}, // Port C - LINE1 + {0x1b, 0x01811020}, // Port E - LINE2 Explorer 2x ADC + {0x1d, 0x40130605}, // - PCBEEP + {0x1e, 0x411111F0}, // - SPDIF_OUT1 + {0x21, 0x01211010}, // Port I - HPOUT + {0xff, 0xffffffff} +}; + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* Hardware Monitor Fan Control + * Hardware limitation: + * HWM failed to read the input temperture vi I2C, + * if other software switch the I2C switch by mistake or intention. + * We recommend to using IMC to control Fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + /* Enable IMC fan control. the recommand way */ +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + + imc_reg_init(); + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 50; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 45; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 40; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 99; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 98; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, + * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. + * so we remove it from AGESA code. Please Seee FchInitLateHwm. + */ + +#else /* HWM fan control, the way not recommand */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + + /* Fan Control */ + oem_fan_control(FchParams_env); + + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_env->Usb.Xhci1Enable = FALSE; + + /* sata configuration */ + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig new file mode 100644 index 0000000..94ad97b --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -0,0 +1,68 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2013-2014 Sage Electronic Engineering +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +if BOARD_ODE_E20XX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY16_KB + select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + select SPD_CACHE + +config MAINBOARD_DIR + string + default bap/ode_e20XX + +config MAINBOARD_PART_NUMBER + string + default "ODE_E20XX" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default y + +endif # BOARD_ODE_E20XX diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name new file mode 100644 index 0000000..a482846 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ODE_E20XX + bool "ODE_e20xx" diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc new file mode 100644 index 0000000..6bbb85a --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Sage Electronic Engineering, LLC +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = Micron_MT41J128M16JT + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex b/src/mainboard/bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex new file mode 100644 index 0000000..08736f6 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex @@ -0,0 +1,235 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Sage Electronic Engineering, LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. + +# Gizmo2 has 1GB using 4 Micron_MT41J128M16JT-125 chips +# The datasheet is available at: +# http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb_DDR3_SDRAM.pdf + +# SPD contents for Gizmo2 2GB DDR3 (1600MHz PC3-12800) soldered down + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +11 + +# 1 SPD Revision - +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +03 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +11 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5/2 = 2.5ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +FE 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6E = 13.75ns - DDR3-1600K +6E + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.75ns - DDR3-1600K +6E + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C = 7.5ns +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6E = 13.75ns - DDR3-1600K +6E + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x118 = 35ns - DDR3-1600 (see byte 21) +18 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x186 = 48.75ns - DDR3-1600K +86 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +00 05 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x0140 = 40ns - DDR3-1600, 2 KB page size +01 40 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +05 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 - 59 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +00 + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +00 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +00 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 116 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +00 01 + +# 119 Module ID: Module Manufacturing Location - oem specified +# 120 Module ID: Module Manufacture Year in BCD +# 0x13 = 2013 +00 13 + +# 121 Module ID: Module Manufacture week +# 0x12 = 12th week +12 + +# 122 - 125: Module Serial Number +53 41 47 45 + +# 126 - 127: Cyclical Redundancy Code +00 00 diff --git a/src/mainboard/bap/ode_e20XX/OptionsIds.h b/src/mainboard/bap/ode_e20XX/OptionsIds.h new file mode 100644 index 0000000..bbdcd5f --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/OptionsIds.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c new file mode 100644 index 0000000..66bebc2 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Filecode.h" + +#include <northbridge/amd/agesa/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList [] = { + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + }, + /* DP1 to high-speed edge connector */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + /* GNB PCIe topology Porting */ + + /* */ + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ + /* */ + AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); + InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; + return AGESA_SUCCESS; +} + +static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; + return AGESA_SUCCESS; +} + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, + .InitMid = OemInitMid, +}; diff --git a/src/mainboard/bap/ode_e20XX/acpi/AmdImc.asl b/src/mainboard/bap/ode_e20XX/acpi/AmdImc.asl new file mode 100644 index 0000000..88d3381 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/AmdImc.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/bap/ode_e20XX/acpi/gpe.asl b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl new file mode 100644 index 0000000..33aab24 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/ide.asl b/src/mainboard/bap/ode_e20XX/acpi/ide.asl new file mode 100644 index 0000000..dfb4158 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/ide.asl @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* No IDE functionality */ + +#if 0 +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + /* save total time of primary PIO master timing to PIO spd0 */ + Store(GTTM(PPTM), PSD0) + /* save total time of primary PIO slave Timing to PIO spd1 */ + Store(GTTM(PPTS), PSD1) + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} +#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl new file mode 100644 index 0000000..da4f11a --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/bap/ode_e20XX/acpi/routing.asl b/src/mainboard/bap/ode_e20XX/acpi/routing.asl new file mode 100644 index 0000000..cf5bae2 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/routing.asl @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) diff --git a/src/mainboard/bap/ode_e20XX/acpi/sata.asl b/src/mainboard/bap/ode_e20XX/acpi/sata.asl new file mode 100644 index 0000000..9a96a9d --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/sata.asl @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* No SATA functionality */ + +#if 0 +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} +#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi/si.asl b/src/mainboard/bap/ode_e20XX/acpi/si.asl new file mode 100644 index 0000000..2ec5fb6 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/si.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/sleep.asl b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl new file mode 100644 index 0000000..6a2cef9 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + Store(1,USBS) + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/superio.asl b/src/mainboard/bap/ode_e20XX/acpi/superio.asl new file mode 100644 index 0000000..97304f9 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/superio.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/thermal.asl b/src/mainboard/bap/ode_e20XX/acpi/thermal.asl new file mode 100644 index 0000000..4c24d96 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/thermal.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* No thermal zone functionality */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl new file mode 100644 index 0000000..07ca7b4 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ + +#if 0 /* TODO: Update */ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} +#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c new file mode 100644 index 0000000..6c061e0 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi_tables.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam16.h> + +#include <northbridge/amd/agesa/agesawrapper.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/bap/ode_e20XX/board_info.txt b/src/mainboard/bap/ode_e20XX/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c new file mode 100644 index 0000000..ab9a18a --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -0,0 +1,466 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "AGESA.h" +//#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE +#define INSTALL_FM2_SOCKET_SUPPORT FALSE + + +#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE + #undef INSTALL_FT3_SOCKET_SUPPORT + #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #endif +#endif + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CDIT TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE + +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled +#define BLDCFG_IOMMU_SUPPORT FALSE +#define OPTION_GFX_INIT_SVIEW FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife + +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL +#define BLDCFG_CFG_ABM_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +#ifdef PCIEX_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) +#endif + +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList + +//#include "KeralaInstall.h" + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +//#define DDR400_FREQUENCY 200 ///< DDR 400 +//#define DDR533_FREQUENCY 266 ///< DDR 533 +//#define DDR667_FREQUENCY 333 ///< DDR 667 +//#define DDR800_FREQUENCY 400 ///< DDR 800 +//#define DDR1066_FREQUENCY 533 ///< DDR 1066 +//#define DDR1333_FREQUENCY 667 ///< DDR 1333 +//#define DDR1600_FREQUENCY 800 ///< DDR 1600 +//#define DDR1866_FREQUENCY 933 ///< DDR 1866 +//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +// +///* QUANDRANK_TYPE*/ +//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +// +///* USER_MEMORY_TIMING_MODE */ +//#define TIMING_MODE_AUTO 0 ///< Use best rate possible +//#define TIMING_MODE_LIMITED 1 ///< Set user top limit +//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +// +///* POWER_DOWN_MODE */ +//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 + +GPIO_CONTROL gizmo2_gpio[] = { + {183, Function1, GpioIn | GpioOutEnB | PullUpB}, + {-1} +}; +//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket + // + + #define SEED_WL 0x0E + WRITE_LEVELING_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL, + SEED_WL), + + #define SEED_A 0x12 + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + MOTHER_BOARD_LAYERS (LAYERS_6), + + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout new file mode 100644 index 0000000..50750a8 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/cmos.layout @@ -0,0 +1,79 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb new file mode 100644 index 0000000..34c2fd4 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -0,0 +1,64 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# +chip northbridge/amd/agesa/family16kb/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # PCIe GFX Bridge + device pci 2.2 on end # PCIe GPP mini PCIe + device pci 2.3 on end # PCIe LAN + device pci 2.4 on end # PCIe x2 to high speed edge connector + device pci 2.5 on end # PCIe x2 to high speed edge connector + end #chip northbridge/amd/agesa/family16kb + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl new file mode 100644 index 0000000..3f1aa8b --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c new file mode 100644 index 0000000..33ce343 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/irq_tables.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam16.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c new file mode 100644 index 0000000..ab1bb8b --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <northbridge/amd/agesa/family16kb/pci_devs.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/agesawrapper.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ + [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* SATA */ + [0x41] = 0x0F, +}; + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* SATA */ + [0x41] = 0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ +}; + +const u8 *picr_data = mainboard_picr_data; +const u8 *intr_data = mainboard_intr_data; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c new file mode 100644 index 0000000..5ead389 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/mptable.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam16.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); + + /* PCI_SLOT 1 */ + PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); + PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); + PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); + + /* PCI_SLOT 2 */ + PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); + PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); + + PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); + PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c new file mode 100644 index 0000000..4cfca8e --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> +#include "cbmem.h" + + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA + * even though the register is not documented in the Kabini BKDG. + * Otherwise the serial output is bad code. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + amd_initmmio(); + + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + + hudson_lpc_port80(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + int i; + for(i = 0; i < 200000; i++) + val = inb(0xcd6); + + post_code(0x37); + agesawrapper_amdinitreset(); + post_code(0x38); + printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); + + post_code(0x39); + + agesawrapper_amdinitearly(); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + post_code(0x41); + agesawrapper_amdinitenv(); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + amd_initcpuio(); + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

Patch set updated for coreboot: bb9869f SuperIO: Add support for Fintek F81866D
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10287 -gerrit commit bb9869f9406c017d2f95a926f792e44867c5dec8 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Mon May 25 17:04:28 2015 +0200 SuperIO: Add support for Fintek F81866D This patch adds support for the Fintek F81866D, which is very similar to the F81865. The F81866 adds some Fancontrol and correct temp sensor read out. Change-Id: Id2fc1119b37142f8101f71908e394ee69c45041d Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/superio/fintek/Kconfig | 4 + src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f81866d/Makefile.inc | 24 +++++ src/superio/fintek/f81866d/f81866d.h | 45 ++++++++ src/superio/fintek/f81866d/f81866d_hwm.c | 124 +++++++++++++++++++++++ src/superio/fintek/f81866d/f81866d_temp_sensor.c | 47 +++++++++ src/superio/fintek/f81866d/fintek_internal.h | 31 ++++++ src/superio/fintek/f81866d/superio.c | 89 ++++++++++++++++ 8 files changed, 365 insertions(+) diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index 2a7438b..5403e0a 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -54,3 +54,7 @@ config SUPERIO_FINTEK_F81216H config SUPERIO_FINTEK_F81865F bool select SUPERIO_FINTEK_COMMON_ROMSTAGE + +config SUPERIO_FINTEK_F81866D + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE \ No newline at end of file diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 60a7a04..40abb8a 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -28,3 +28,4 @@ subdirs-y += f71872 subdirs-y += f71889 subdirs-y += f81216h subdirs-y += f81865f +subdirs-y += f81866d diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc new file mode 100644 index 0000000..dd69894 --- /dev/null +++ b/src/superio/fintek/f81866d/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_temp_sensor.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c diff --git a/src/superio/fintek/f81866d/f81866d.h b/src/superio/fintek/f81866d/f81866d.h new file mode 100644 index 0000000..055bb9e --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* + * Datasheet: + * - Name: F81866D/A-I + */ + +#ifndef SUPERIO_FINTEK_F81866_H +#define SUPERIO_FINTEK_F81866_H + +/* Logical Device Numbers (LDN) */ +#define F81866D_FDC 0x00 /* Floppy */ +#define F81866D_SP1 0x10 /* UART1 */ +#define F81866D_SP2 0x11 /* UART2 */ +#define F81866D_SP3 0x12 /* UART3 */ +#define F81866D_SP4 0x13 /* UART4 */ +#define F81866D_SP5 0x14 /* UART3 */ +#define F81866D_SP6 0x15 /* UART4 */ +#define F81866D_PP 0x03 /* Parallel Port */ +#define F81866D_HWM 0x04 /* Hardware Monitor */ +#define F81866D_KBC 0x05 /* Keyboard/Mouse */ +#define F81866D_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81866D_WDT 0x07 /* Watchdog */ +#define F81866D_PME 0x0a /* Power Management Events (PME) */ + +#endif /* SUPERIO_FINTEK_F81866_H */ diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c new file mode 100644 index 0000000..073b371 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Setup only for Fan2 + * Todo: Add support for Fan1 and Fan3 + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" + + +// Set to AMD +#define HWM_AMD_TSI_ADDR 0x08 +#define HWM_AMD_TSI_CONTROL_REG 0x0A + +// Set temp sensors type +#define TEMP_SENS_TYPE_REG 0x6B + +// FAN prog sel +#define HWM_FAN3_CONTROL 0x9A +#define HWM_FAN_SEL 0x94 +#define HWM_FAN_MODE 0x96 +#define HWM_FAN_FAST_FILTER 0x97 + +// Fan expected speed +#define HWM_FAN2_EX_SPEED1 0xB2 +#define HWM_FAN2_EX_SPEED2 0xB3 + +// 4 Boundries +#define HWM_FAN2_BOUND1 0xB6 +#define HWM_FAN2_BOUND2 0xB7 +#define HWM_FAN2_BOUND3 0xB8 +#define HWM_FAN2_BOUND4 0xB9 + +// 5 Segment Speeds +#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA +#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB +#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC +#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD +#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE + +// FAN1 Temp Mapping +#define HWM_FAN2_TEMP_MAP_SEL 0xBF + +/* Defines freq. for fan control */ +#define PWM_220HZ_FAN3_CONTROL 0x20 +#define PWM_5KHZ_FAN3_CONTROL 0x20 +#define PWM_11KHZ_FAN3_CONTROL 0x00 +#define PWM_23KHZ_FAN3_CONTROL 0x00 + +#define PWM_220HZ_FAN2_MAP_SEL 0x3D +#define PWM_5KHZ_FAN2_MAP_SEL 0x1D +#define PWM_11KHZ_FAN2_MAP_SEL 0x3D +#define PWM_23KHZ_FAN2_MAP_SEL 0x1D + + +void f81866d_hwm_init(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + /* Use AMD TSI */ + pnp_write_index(port, HWM_AMD_TSI_ADDR, 0x98); + pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, 0x02); + + // Set temp1 sensor to thermistor + pnp_write_index(port, TEMP_SENS_TYPE_REG, 0x04); + + /* Select FAN Type */ + pnp_write_index(port, HWM_FAN_SEL, 0xC0); // 0xC0 set FAN2 to PWM + + /* Select FAN Mode*/ + pnp_write_index(port, HWM_FAN_MODE, 0xD5); // 0xD5 sets FAN1-3 to Auto RPM mode + + pnp_write_index(port, HWM_FAN_FAST_FILTER, 0x02); // Faster fan + + /* Set Boundries */ + pnp_write_index(port, HWM_FAN2_BOUND1, 0x3C); //60°C + pnp_write_index(port, HWM_FAN2_BOUND2, 0x32); //50°C + pnp_write_index(port, HWM_FAN2_BOUND3, 0x28); //40°C + pnp_write_index(port, HWM_FAN2_BOUND4, 0x1E); //30°C + + /* Set Speed */ + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, 0xFF); // 100% + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, 0xD9); // 85% + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, 0xB2); // 70% + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, 0x99); // 60% + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, 0x80); // 50% + + /* Set temp follows */ + pnp_write_index(port, HWM_FAN3_CONTROL, PWM_220HZ_FAN3_CONTROL); + pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, PWM_220HZ_FAN2_MAP_SEL); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/f81866d_temp_sensor.c b/src/superio/fintek/f81866d/f81866d_temp_sensor.c new file mode 100644 index 0000000..aaddd45 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_temp_sensor.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include "fintek_internal.h" + +#define TEMP_SENS_TYPE_REG 0x6B + +void f81866d_temp_sensor(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + // Set temp1 sensor correct to thermistor + pnp_write_index(port, TEMP_SENS_TYPE_REG, 0x04); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h new file mode 100644 index 0000000..c198421 --- /dev/null +++ b/src/superio/fintek/f81866d/fintek_internal.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_FINTEK_F81866D_INTERNAL_H +#define SUPERIO_FINTEK_F81866D_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f81866d_temp_sensor(struct device *dev); +void f81866d_hwm_init(struct device *dev); + +#endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */ diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c new file mode 100644 index 0000000..d12d241 --- /dev/null +++ b/src/superio/fintek/f81866d/superio.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f81866d.h" +#include "fintek_internal.h" + +static void f81866d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need extra code for serial, wdt etc. */ + case F81866D_KBC: + pc_keyboard_init(); + break; + case F81866D_HWM: + + #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + // Fixing temp sensor readout according data sheet + f81866d_temp_sensor(dev); + #else + // Fixing temp sensor read out and init Fan control + f81866d_hwm_init(dev); + #endif + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81866d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F81866D_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81866D_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, }, + { &ops, F81866D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81866D_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + { &ops, F81866D_GPIO, PNP_IRQ0, }, + { &ops, F81866D_PME, }, + { &ops, F81866D_WDT, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81866d_ops = { + CHIP_NAME("Fintek F81866D Super I/O") + .enable_dev = enable_dev +};

1 0

Patch set updated for coreboot: 589f19a mainboard/bap: Add support for BAP ODE E20XX
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10288 -gerrit commit 589f19ac4ec34187d13b7ad689c9093359ff4233 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Mon May 25 17:08:17 2015 +0200 mainboard/bap: Add support for BAP ODE E20XX Adding new board based on AMD Kabini. Most of the code is copied from gizmosphere/gizmo2 Board is developed by BAP - Bruhnspace Advanced Projects: http://www.unibap.com/ (Site is under construction) Special on this board is: -Soldered down memory -SuperIO Fintek F81866D Known bugs: -S3 doesnt work -Serial ports only works for the first boot. Needs power cut. Tested with: -SeaBios as Payload -Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1 -Windows 8 64Bit Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex | 283 +++++++++++++++++++++ src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e20XX/Kconfig | 4 +- src/mainboard/bap/ode_e20XX/Kconfig.name | 2 +- src/mainboard/bap/ode_e20XX/Makefile.inc | 4 +- .../bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex | 235 ----------------- src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c | 32 ++- src/mainboard/bap/ode_e20XX/acpi/routing.asl | 2 +- src/mainboard/bap/ode_e20XX/acpi/superio.asl | 38 ++- src/mainboard/bap/ode_e20XX/devicetree.cb | 67 ++++- src/mainboard/bap/ode_e20XX/romstage.c | 18 +- 11 files changed, 415 insertions(+), 272 deletions(-) diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex new file mode 100644 index 0000000..df1f1f0 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex @@ -0,0 +1,283 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +# BAP ODE E20XX has 2GB ram soldered down on the Q7 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +92 + +# 1 SPD Revision - +# 0x10 = Revision 1.0 +12 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[7:5]: reserved +08 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5/2 = 2.5ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C = 7.5ns +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x118 = 35ns - DDR3-1600 (see byte 21) +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x186 = 48.75ns - DDR3-1600K +89 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +20 08 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x0140 = 40ns - DDR3-1600, 2 KB page size +01 68 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +01 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 - 59 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +0f + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +11 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +22 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 116 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +80 AD + +# 119 Module ID: Module Manufacturing Location - oem specified +# 120 Module ID: Module Manufacture Year in BCD +# 0x13 = 2013 +01 00 + +# 121 Module ID: Module Manufacture week +# 0x12 = 12th week +00 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +D4 51 + +# Coreboot is only interested in the first 128 values +#128 - 135 +48 4d 54 34 32 35 53 36 + +#136 - 143 +4d 46 52 36 43 2d 48 39 + +#144 - 151 +20 20 4e 30 80 ad 00 00 + +#152 - 159 +00 00 00 00 00 00 00 00 + +#160 - 167 +00 00 00 00 00 00 00 00 + +#168 - 175 +00 00 00 00 00 00 00 00 + +#176 - 183 +00 00 00 00 00 00 00 00 + +#184 - 191 +00 00 00 00 00 00 00 00 + +#192 - 199 +00 00 00 00 00 00 00 00 + +#200 - 207 +00 00 00 00 00 00 00 00 + +#208 - 215 +00 00 00 00 00 00 00 00 + +#216 - 223 +00 00 00 00 00 00 00 00 + +#224 - 231 +00 00 00 00 00 00 00 00 + +#232 - 239 +00 00 00 00 00 00 00 00 + +#240 - 247 +00 00 00 00 00 00 00 00 + +#248 - 255 +00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 953eb40..2faf6cd 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "AGESA.h" diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 94ad97b..177238c 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -15,7 +15,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc. +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # if BOARD_ODE_E20XX @@ -28,9 +28,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA + select SUPERIO_FINTEK_F81866D select SPD_CACHE config MAINBOARD_DIR diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name index a482846..8ff2d9b 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig.name +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -1,2 +1,2 @@ config BOARD_ODE_E20XX - bool "ODE_e20xx" + bool "ODE_e20xx" \ No newline at end of file diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 6bbb85a..f89e13a 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -15,7 +15,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc. +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # romstage-y += buildOpts.c @@ -30,7 +30,7 @@ ramstage-y += PlatformGnbPcie.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_MT41J128M16JT +SPD_SOURCES = BAP_Q7 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex b/src/mainboard/bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex deleted file mode 100644 index 08736f6..0000000 --- a/src/mainboard/bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex +++ /dev/null @@ -1,235 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc. - -# Gizmo2 has 1GB using 4 Micron_MT41J128M16JT-125 chips -# The datasheet is available at: -# http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb_DDR3_SDRAM.pdf - -# SPD contents for Gizmo2 2GB DDR3 (1600MHz PC3-12800) soldered down - -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x10 = Revision 1.0 -10 - -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -03 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 2 = 14 Row Address Bits -# bits[7:6]: reserved -11 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 2 = 16 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -02 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 0 = 0 bits (no bus width extension) -# bits[7:5]: reserved -03 - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x02 divisor -# bits[7:4]: 0x05 dividend -# 5/2 = 2.5ps -52 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) -0A - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# Cas Latencies of 11 - 5 are supported -FE 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x3C = 7.5ns -3C - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x6E = 13.75ns - DDR3-1600K -6E - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x118 = 35ns - DDR3-1600 (see byte 21) -18 - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x186 = 48.75ns - DDR3-1600K -86 - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x500 = 160ns - for 2 Gigabit chips -00 05 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x0140 = 40ns - DDR3-1600, 2 KB page size -01 40 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 1 = DLL Off mode supported -83 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 1 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -05 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 0 = Signal Loading not specified -# bits[3:2]: reserved -# bits[6:4]: 0 = Die count not specified -# bit7 : 0 = Standard Monolithic DRAM Device -00 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 - 59 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 116 (reserved) -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x0001 = AMD -00 01 - -# 119 Module ID: Module Manufacturing Location - oem specified -# 120 Module ID: Module Manufacture Year in BCD -# 0x13 = 2013 -00 13 - -# 121 Module ID: Module Manufacture week -# 0x12 = 12th week -12 - -# 122 - 125: Module Serial Number -53 41 47 45 - -# 126 - 127: Cyclical Redundancy Code -00 00 diff --git a/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c index 66bebc2..fc0ec89 100644 --- a/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c +++ b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "AGESA.h" @@ -32,20 +32,20 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x01, 0) + AspmL0sL1, 0x01, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x02, 0) + AspmL0sL1, 0x02, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -55,7 +55,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x03, 0) + AspmL0sL1, 0x03, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -65,17 +65,17 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x04, 0) + AspmL0sL1, 0x04, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { - DESCRIPTOR_TERMINATE_LIST, + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x05, 0) + AspmL0sL1, 0x05, 0) } }; @@ -84,13 +84,19 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, /* DP1 to high-speed edge connector */ { - DESCRIPTOR_TERMINATE_LIST, + 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) }, }; diff --git a/src/mainboard/bap/ode_e20XX/acpi/routing.asl b/src/mainboard/bap/ode_e20XX/acpi/routing.asl index cf5bae2..73a040f 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/routing.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/routing.asl @@ -193,5 +193,5 @@ Name(APS8, Package(){ Package(){0x0000FFFF, 0, 0, 16 }, Package(){0x0000FFFF, 1, 0, 17 }, Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, }) diff --git a/src/mainboard/bap/ode_e20XX/acpi/superio.asl b/src/mainboard/bap/ode_e20XX/acpi/superio.asl index 97304f9..3a3ccdf 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/superio.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/superio.asl @@ -1,11 +1,13 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -17,4 +19,34 @@ * Foundation, Inc. */ -/* No Super I/O device or functionality yet */ +/* SuperIO support for Windows */ + +Device (UAR1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) +} + +Device (UAR2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3} + }) +} diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb index 34c2fd4..fb00813 100644 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -9,7 +9,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -32,11 +32,11 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # PCIe GFX Bridge - device pci 2.2 on end # PCIe GPP mini PCIe - device pci 2.3 on end # PCIe LAN - device pci 2.4 on end # PCIe x2 to high speed edge connector - device pci 2.5 on end # PCIe x2 to high speed edge connector + device pci 2.1 on end # x4 PCIe Slot + device pci 2.2 on end # PCIe Q7 Realtek GBit LAN + device pci 2.3 on end # PCIe CB Realtek GBit LAN + device pci 2.4 on end # PCIe BAP FPGA + device pci 2.5 on end # PCIe BAP FPGA (unused, for 050T) end #chip northbridge/amd/agesa/family16kb chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus @@ -48,7 +48,60 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 13.2 on end # USB device pci 14.0 on end # SM device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81866d + register "hwm_amd_tsi_addr" = "0x98" # Set to AMD + register "hwm_amd_tsi_control" = "0x02" # Set to AMD + register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM + register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode + register "hwm_fan3_control" = "0x00" # Fan control 23kHz + register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz + register "hwm_fan2_bound1" = "0x3C" # 60°C + register "hwm_fan2_bound2" = "0x32" # 50°C + register "hwm_fan2_bound3" = "0x28" # 40°C + register "hwm_fan2_bound4" = "0x1E" # 30°C + register "hwm_fan2_seg1_speed" = "0xFF" # 100% + register "hwm_fan2_seg2_speed" = "0xD9" # 85% + register "hwm_fan2_seg3_speed" = "0xB2" # 70% + register "hwm_fan2_seg4_speed" = "0x99" # 60% + register "hwm_fan2_seg5_speed" = "0x80" # 50% + register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # Hardware Monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.7 on end # WDT + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 off # COM3 + end + device pnp 4e.13 off # COM4 + end + device pnp 4e.14 off # COM5 + end + device pnp 4e.15 off # COM6 + end + end # f81866d + end #LPC device pci 14.7 on end # SD end #chip southbridge/amd/hudson diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index 4cfca8e..be065b2 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -2,10 +2,13 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -35,20 +38,18 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <cpu/amd/agesa/s3_resume.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> #include "cbmem.h" +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); + // All cores: set pstate 7 (800 MHz) early to save power + __writemsr (0xc0010062, 7); amd_initmmio(); @@ -62,6 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); post_code(0x31); + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); console_init(); }

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Patch set updated for coreboot: 7b546e0 mainboard/bap: Add support for BAP ODE E20XX
by Fabian Kunkel 27 May '15

27 May '15

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10288 -gerrit commit 7b546e0ee17e971edac6b3b3f213bb44b5f7e7a4 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Mon May 25 17:08:17 2015 +0200 mainboard/bap: Add support for BAP ODE E20XX Adding new board based on AMD Kabini. Most of the code is copied from gizmosphere/gizmo2 Board is developed by BAP - Bruhnspace Advanced Projects: http://www.unibap.com/ (Site is under construction) Special on this board is: -Soldered down memory -SuperIO Fintek F81866D Known bugs: -S3 doesnt work -Serial ports only works for the first boot. Needs power cut. Tested with: -SeaBios as Payload -Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1 -Windows 8 64Bit Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/mainboard/bap/Kconfig | 36 ++ src/mainboard/bap/Kconfig.name | 2 + src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex | 283 +++++++++++++++ src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 221 ++++++++++++ src/mainboard/bap/ode_e20XX/Kconfig | 70 ++++ src/mainboard/bap/ode_e20XX/Kconfig.name | 2 + src/mainboard/bap/ode_e20XX/Makefile.inc | 47 +++ src/mainboard/bap/ode_e20XX/OptionsIds.h | 63 ++++ src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c | 161 +++++++++ src/mainboard/bap/ode_e20XX/acpi/AmdImc.asl | 114 ++++++ src/mainboard/bap/ode_e20XX/acpi/gpe.asl | 78 +++++ src/mainboard/bap/ode_e20XX/acpi/ide.asl | 250 +++++++++++++ src/mainboard/bap/ode_e20XX/acpi/mainboard.asl | 41 +++ src/mainboard/bap/ode_e20XX/acpi/routing.asl | 197 +++++++++++ src/mainboard/bap/ode_e20XX/acpi/sata.asl | 150 ++++++++ src/mainboard/bap/ode_e20XX/acpi/si.asl | 27 ++ src/mainboard/bap/ode_e20XX/acpi/sleep.asl | 97 +++++ src/mainboard/bap/ode_e20XX/acpi/superio.asl | 52 +++ src/mainboard/bap/ode_e20XX/acpi/thermal.asl | 20 ++ src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl | 132 +++++++ src/mainboard/bap/ode_e20XX/acpi_tables.c | 60 ++++ src/mainboard/bap/ode_e20XX/board_info.txt | 1 + src/mainboard/bap/ode_e20XX/buildOpts.c | 466 +++++++++++++++++++++++++ src/mainboard/bap/ode_e20XX/cmos.layout | 79 +++++ src/mainboard/bap/ode_e20XX/devicetree.cb | 117 +++++++ src/mainboard/bap/ode_e20XX/dsdt.asl | 91 +++++ src/mainboard/bap/ode_e20XX/irq_tables.c | 107 ++++++ src/mainboard/bap/ode_e20XX/mainboard.c | 137 ++++++++ src/mainboard/bap/ode_e20XX/mptable.c | 169 +++++++++ src/mainboard/bap/ode_e20XX/romstage.c | 120 +++++++ 30 files changed, 3390 insertions(+) diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig new file mode 100644 index 0000000..d72f131 --- /dev/null +++ b/src/mainboard/bap/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## +if VENDOR_BAP + +choice + prompt "Mainboard model" + +config BOARD_ODE_E20XX + bool "ODE_E20XX" + +endchoice + +source "src/mainboard/bap/ode_e20XX/Kconfig" + +config MAINBOARD_VENDOR + string + default "BAP" + +endif # VENDOR_BAP diff --git a/src/mainboard/bap/Kconfig.name b/src/mainboard/bap/Kconfig.name new file mode 100644 index 0000000..d923316 --- /dev/null +++ b/src/mainboard/bap/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_BAP + bool "BAP" diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex new file mode 100644 index 0000000..df1f1f0 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex @@ -0,0 +1,283 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +# BAP ODE E20XX has 2GB ram soldered down on the Q7 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +92 + +# 1 SPD Revision - +# 0x10 = Revision 1.0 +12 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[7:5]: reserved +08 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5/2 = 2.5ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C = 7.5ns +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x118 = 35ns - DDR3-1600 (see byte 21) +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x186 = 48.75ns - DDR3-1600K +89 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +20 08 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x0140 = 40ns - DDR3-1600, 2 KB page size +01 68 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +01 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 - 59 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +0f + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +11 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +22 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 116 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +80 AD + +# 119 Module ID: Module Manufacturing Location - oem specified +# 120 Module ID: Module Manufacture Year in BCD +# 0x13 = 2013 +01 00 + +# 121 Module ID: Module Manufacture week +# 0x12 = 12th week +00 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +D4 51 + +# Coreboot is only interested in the first 128 values +#128 - 135 +48 4d 54 34 32 35 53 36 + +#136 - 143 +4d 46 52 36 43 2d 48 39 + +#144 - 151 +20 20 4e 30 80 ad 00 00 + +#152 - 159 +00 00 00 00 00 00 00 00 + +#160 - 167 +00 00 00 00 00 00 00 00 + +#168 - 175 +00 00 00 00 00 00 00 00 + +#176 - 183 +00 00 00 00 00 00 00 00 + +#184 - 191 +00 00 00 00 00 00 00 00 + +#192 - 199 +00 00 00 00 00 00 00 00 + +#200 - 207 +00 00 00 00 00 00 00 00 + +#208 - 215 +00 00 00 00 00 00 00 00 + +#216 - 223 +00 00 00 00 00 00 00 00 + +#224 - 231 +00 00 00 00 00 00 00 00 + +#232 - 239 +00 00 00 00 00 00 00 00 + +#240 - 247 +00 00 00 00 00 00 00 00 + +#248 - 255 +00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c new file mode 100644 index 0000000..2faf6cd --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -0,0 +1,221 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif +#include <stdlib.h> + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * ALC272 Verb Table + */ +const CODEC_ENTRY Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, // - SPDIF_OUT2 + {0x12, 0x411111F0}, // - DMIC_1/2 + {0x13, 0x411111F0}, // - DMIC_3/4 + {0x14, 0x411111F0}, // Port D - LOUT1 + {0x15, 0x01011050}, // Port A - LOUT2 Explorer 2x DAC + {0x16, 0x411111F0}, // + {0x17, 0x411111F0}, // Port H - MONO + {0x18, 0x01a11840}, // Port B - MIC1 + {0x19, 0x411111F0}, // Port F - MIC2 + {0x1a, 0x01811030}, // Port C - LINE1 + {0x1b, 0x01811020}, // Port E - LINE2 Explorer 2x ADC + {0x1d, 0x40130605}, // - PCBEEP + {0x1e, 0x411111F0}, // - SPDIF_OUT1 + {0x21, 0x01211010}, // Port I - HPOUT + {0xff, 0xffffffff} +}; + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* Hardware Monitor Fan Control + * Hardware limitation: + * HWM failed to read the input temperture vi I2C, + * if other software switch the I2C switch by mistake or intention. + * We recommend to using IMC to control Fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + /* Enable IMC fan control. the recommand way */ +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + + imc_reg_init(); + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 50; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 45; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 40; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 99; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 98; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, + * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. + * so we remove it from AGESA code. Please Seee FchInitLateHwm. + */ + +#else /* HWM fan control, the way not recommand */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; + + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + + /* Fan Control */ + oem_fan_control(FchParams_env); + + /* XHCI configuration */ + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_env->Usb.Xhci1Enable = FALSE; + + /* sata configuration */ + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig new file mode 100644 index 0000000..177238c --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -0,0 +1,70 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2013-2014 Sage Electronic Engineering +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_ODE_E20XX + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_AGESA_FAMILY16_KB + select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + select SUPERIO_FINTEK_F81866D + select SPD_CACHE + +config MAINBOARD_DIR + string + default bap/ode_e20XX + +config MAINBOARD_PART_NUMBER + string + default "ODE_E20XX" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default y + +endif # BOARD_ODE_E20XX diff --git a/src/mainboard/bap/ode_e20XX/Kconfig.name b/src/mainboard/bap/ode_e20XX/Kconfig.name new file mode 100644 index 0000000..8ff2d9b --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ODE_E20XX + bool "ODE_e20xx" \ No newline at end of file diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc new file mode 100644 index 0000000..f89e13a --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Sage Electronic Engineering, LLC +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c + +## DIMM SPD for on-board memory +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = BAP_Q7 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/bap/ode_e20XX/OptionsIds.h b/src/mainboard/bap/ode_e20XX/OptionsIds.h new file mode 100644 index 0000000..bbdcd5f --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/OptionsIds.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c new file mode 100644 index 0000000..fc0ec89 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Filecode.h" + +#include <northbridge/amd/agesa/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList [] = { + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugBasic, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmL0sL1, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugBasic, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmL0sL1, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmL0sL1, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmL0sL1, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugBasic, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmL0sL1, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 to high-speed edge connector */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ + +static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + /* GNB PCIe topology Porting */ + + /* */ + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ + /* */ + AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + ASSERT(Status == AGESA_SUCCESS); + + PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); + InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; + return AGESA_SUCCESS; +} + +static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; + return AGESA_SUCCESS; +} + +const struct OEM_HOOK OemCustomize = { + .InitEarly = OemInitEarly, + .InitMid = OemInitMid, +}; diff --git a/src/mainboard/bap/ode_e20XX/acpi/AmdImc.asl b/src/mainboard/bap/ode_e20XX/acpi/AmdImc.asl new file mode 100644 index 0000000..88d3381 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/AmdImc.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/bap/ode_e20XX/acpi/gpe.asl b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl new file mode 100644 index 0000000..33aab24 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/ide.asl b/src/mainboard/bap/ode_e20XX/acpi/ide.asl new file mode 100644 index 0000000..dfb4158 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/ide.asl @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* No IDE functionality */ + +#if 0 +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + /* save total time of primary PIO master timing to PIO spd0 */ + Store(GTTM(PPTM), PSD0) + /* save total time of primary PIO slave Timing to PIO spd1 */ + Store(GTTM(PPTS), PSD1) + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} +#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl new file mode 100644 index 0000000..da4f11a --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/mainboard.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/bap/ode_e20XX/acpi/routing.asl b/src/mainboard/bap/ode_e20XX/acpi/routing.asl new file mode 100644 index 0000000..73a040f --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/routing.asl @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, +}) diff --git a/src/mainboard/bap/ode_e20XX/acpi/sata.asl b/src/mainboard/bap/ode_e20XX/acpi/sata.asl new file mode 100644 index 0000000..9a96a9d --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/sata.asl @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* No SATA functionality */ + +#if 0 +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} +#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi/si.asl b/src/mainboard/bap/ode_e20XX/acpi/si.asl new file mode 100644 index 0000000..2ec5fb6 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/si.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/sleep.asl b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl new file mode 100644 index 0000000..6a2cef9 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/sleep.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + Store(1,USBS) + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/superio.asl b/src/mainboard/bap/ode_e20XX/acpi/superio.asl new file mode 100644 index 0000000..3a3ccdf --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/superio.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* SuperIO support for Windows */ + +Device (UAR1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) +} + +Device (UAR2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3} + }) +} diff --git a/src/mainboard/bap/ode_e20XX/acpi/thermal.asl b/src/mainboard/bap/ode_e20XX/acpi/thermal.asl new file mode 100644 index 0000000..4c24d96 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/thermal.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* No thermal zone functionality */ diff --git a/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl new file mode 100644 index 0000000..07ca7b4 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi/usb_oc.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ + +#if 0 /* TODO: Update */ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} +#endif diff --git a/src/mainboard/bap/ode_e20XX/acpi_tables.c b/src/mainboard/bap/ode_e20XX/acpi_tables.c new file mode 100644 index 0000000..6c061e0 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/acpi_tables.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam16.h> + +#include <northbridge/amd/agesa/agesawrapper.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/bap/ode_e20XX/board_info.txt b/src/mainboard/bap/ode_e20XX/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c new file mode 100644 index 0000000..ab9a18a --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -0,0 +1,466 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> +#include "AGESA.h" +//#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE +#define INSTALL_FM2_SOCKET_SUPPORT FALSE + + +#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE + #undef INSTALL_FT3_SOCKET_SUPPORT + #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #endif +#endif + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CDIT TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE + +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled +#define BLDCFG_IOMMU_SUPPORT FALSE +#define OPTION_GFX_INIT_SVIEW FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife + +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL +#define BLDCFG_CFG_ABM_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +#ifdef PCIEX_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) +#endif + +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList + +//#include "KeralaInstall.h" + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +//#define DDR400_FREQUENCY 200 ///< DDR 400 +//#define DDR533_FREQUENCY 266 ///< DDR 533 +//#define DDR667_FREQUENCY 333 ///< DDR 667 +//#define DDR800_FREQUENCY 400 ///< DDR 800 +//#define DDR1066_FREQUENCY 533 ///< DDR 1066 +//#define DDR1333_FREQUENCY 667 ///< DDR 1333 +//#define DDR1600_FREQUENCY 800 ///< DDR 1600 +//#define DDR1866_FREQUENCY 933 ///< DDR 1866 +//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +// +///* QUANDRANK_TYPE*/ +//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +// +///* USER_MEMORY_TIMING_MODE */ +//#define TIMING_MODE_AUTO 0 ///< Use best rate possible +//#define TIMING_MODE_LIMITED 1 ///< Set user top limit +//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +// +///* POWER_DOWN_MODE */ +//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 + +GPIO_CONTROL gizmo2_gpio[] = { + {183, Function1, GpioIn | GpioOutEnB | PullUpB}, + {-1} +}; +//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket + // + + #define SEED_WL 0x0E + WRITE_LEVELING_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL, + SEED_WL), + + #define SEED_A 0x12 + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + MOTHER_BOARD_LAYERS (LAYERS_6), + + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout new file mode 100644 index 0000000..50750a8 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/cmos.layout @@ -0,0 +1,79 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb new file mode 100644 index 0000000..fb00813 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -0,0 +1,117 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# +chip northbridge/amd/agesa/family16kb/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe Slot + device pci 2.2 on end # PCIe Q7 Realtek GBit LAN + device pci 2.3 on end # PCIe CB Realtek GBit LAN + device pci 2.4 on end # PCIe BAP FPGA + device pci 2.5 on end # PCIe BAP FPGA (unused, for 050T) + end #chip northbridge/amd/agesa/family16kb + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81866d + register "hwm_amd_tsi_addr" = "0x98" # Set to AMD + register "hwm_amd_tsi_control" = "0x02" # Set to AMD + register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM + register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode + register "hwm_fan3_control" = "0x00" # Fan control 23kHz + register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz + register "hwm_fan2_bound1" = "0x3C" # 60°C + register "hwm_fan2_bound2" = "0x32" # 50°C + register "hwm_fan2_bound3" = "0x28" # 40°C + register "hwm_fan2_bound4" = "0x1E" # 30°C + register "hwm_fan2_seg1_speed" = "0xFF" # 100% + register "hwm_fan2_seg2_speed" = "0xD9" # 85% + register "hwm_fan2_seg3_speed" = "0xB2" # 70% + register "hwm_fan2_seg4_speed" = "0x99" # 60% + register "hwm_fan2_seg5_speed" = "0x80" # 50% + register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # Hardware Monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.7 on end # WDT + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 off # COM3 + end + device pnp 4e.13 off # COM4 + end + device pnp 4e.14 off # COM5 + end + device pnp 4e.15 off # COM6 + end + end # f81866d + end #LPC + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl new file mode 100644 index 0000000..3f1aa8b --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/bap/ode_e20XX/irq_tables.c b/src/mainboard/bap/ode_e20XX/irq_tables.c new file mode 100644 index 0000000..33ce343 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/irq_tables.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam16.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c new file mode 100644 index 0000000..ab1bb8b --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <northbridge/amd/agesa/family16kb/pci_devs.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/agesawrapper.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ + [0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-C */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, + /* SATA */ + [0x41] = 0x0F, +}; + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* SATA */ + [0x41] = 0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ +}; + +const u8 *picr_data = mainboard_picr_data; +const u8 *intr_data = mainboard_intr_data; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c new file mode 100644 index 0000000..5ead389 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/mptable.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam16.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); + PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); + + /* PCI_SLOT 1 */ + PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); + PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); + PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); + + /* PCI_SLOT 2 */ + PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); + PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); + PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); + + PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); + PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c new file mode 100644 index 0000000..be065b2 --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> +#include "cbmem.h" + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + // All cores: set pstate 7 (800 MHz) early to save power + __writemsr (0xc0010062, 7); + + amd_initmmio(); + + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + + hudson_lpc_port80(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + int i; + for(i = 0; i < 200000; i++) + val = inb(0xcd6); + + post_code(0x37); + agesawrapper_amdinitreset(); + post_code(0x38); + printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); + + post_code(0x39); + + agesawrapper_amdinitearly(); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + agesawrapper_amdinitpost(); + post_code(0x41); + agesawrapper_amdinitenv(); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + agesawrapper_amdinitresume(); + + amd_initcpuio(); + agesawrapper_amds3laterestore(); + + post_code(0x61); + prepare_for_resume(); + } + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

Patch set updated for coreboot: 3347ed5 superio/fintek: Add support for Fintek F81866AD-I
by Fabian Kunkel 27 May '15

27 May '15

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10287 -gerrit commit 3347ed581f013605cd733ddc37bc96fc6bbb62d6 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Mon May 25 17:04:28 2015 +0200 superio/fintek: Add support for Fintek F81866AD-I This patch adds support for the Fintek F81866AD-I SuperIO, which is very similar to the fintek/f81865f. This code adds some fan control support, inspired by fintek/f71869ad. Furthermore its possible to change the temp sensor type (thermistor or diode). Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Id2fc1119b37142f8101f71908e394ee69c45041d Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/superio/fintek/Kconfig | 4 + src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f81866d/Makefile.inc | 24 ++++++ src/superio/fintek/f81866d/chip.h | 54 ++++++++++++++ src/superio/fintek/f81866d/f81866d.h | 47 ++++++++++++ src/superio/fintek/f81866d/f81866d_hwm.c | 107 +++++++++++++++++++++++++++ src/superio/fintek/f81866d/fintek_internal.h | 31 ++++++++ src/superio/fintek/f81866d/superio.c | 84 +++++++++++++++++++++ 8 files changed, 352 insertions(+) diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index 2a7438b..5403e0a 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -54,3 +54,7 @@ config SUPERIO_FINTEK_F81216H config SUPERIO_FINTEK_F81865F bool select SUPERIO_FINTEK_COMMON_ROMSTAGE + +config SUPERIO_FINTEK_F81866D + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE \ No newline at end of file diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 60a7a04..40abb8a 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -28,3 +28,4 @@ subdirs-y += f71872 subdirs-y += f71889 subdirs-y += f81216h subdirs-y += f81865f +subdirs-y += f81866d diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc new file mode 100644 index 0000000..2023b6c --- /dev/null +++ b/src/superio/fintek/f81866d/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c diff --git a/src/superio/fintek/f81866d/chip.h b/src/superio/fintek/f81866d/chip.h new file mode 100644 index 0000000..9c9e799 --- /dev/null +++ b/src/superio/fintek/f81866d/chip.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_FINTEK_F81866D_CHIP_H +#define SUPERIO_FINTEK_F81866D_CHIP_H + +#include <stdint.h> + +struct superio_fintek_f81866d_config { + + /* AMD TSI */ + uint8_t hwm_amd_tsi_addr; + uint8_t hwm_amd_tsi_control; + + /* Fan control */ + uint8_t hwm_fan_select; + uint8_t hwm_fan_mode; + uint8_t hwm_fan3_control; + uint8_t hwm_fan2_temp_map_select; + + uint8_t hwm_fan2_bound1; + uint8_t hwm_fan2_bound2; + uint8_t hwm_fan2_bound3; + uint8_t hwm_fan2_bound4; + uint8_t hwm_fan2_seg1_speed; + uint8_t hwm_fan2_seg2_speed; + uint8_t hwm_fan2_seg3_speed; + uint8_t hwm_fan2_seg4_speed; + uint8_t hwm_fan2_seg5_speed; + + /* Temp sensor type */ + uint8_t hwm_temp_sens_type; +}; + +#endif /* SUPERIO_FINTEK_F81866D_CHIP_H */ diff --git a/src/superio/fintek/f81866d/f81866d.h b/src/superio/fintek/f81866d/f81866d.h new file mode 100644 index 0000000..70a33b6 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* + * Datasheet: + * - Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P + * - Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html + */ + +#ifndef SUPERIO_FINTEK_F81866_H +#define SUPERIO_FINTEK_F81866_H + +/* Logical Device Numbers (LDN) */ +#define F81866D_FDC 0x00 /* Floppy */ +#define F81866D_SP1 0x10 /* UART1 */ +#define F81866D_SP2 0x11 /* UART2 */ +#define F81866D_SP3 0x12 /* UART3 */ +#define F81866D_SP4 0x13 /* UART4 */ +#define F81866D_SP5 0x14 /* UART3 */ +#define F81866D_SP6 0x15 /* UART4 */ +#define F81866D_PP 0x03 /* Parallel Port */ +#define F81866D_HWM 0x04 /* Hardware Monitor */ +#define F81866D_KBC 0x05 /* Keyboard/Mouse */ +#define F81866D_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81866D_WDT 0x07 /* Watchdog */ +#define F81866D_PME 0x0a /* Power Management Events (PME) */ + +#endif /* SUPERIO_FINTEK_F81866_H */ diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c new file mode 100644 index 0000000..bc24468 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Setup only for Fan2 + * Todo: Add support for Fan1 and Fan3 + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" +#include "chip.h" + + +/* Register addresses */ +// Choose between AMD and Intel +#define HWM_AMD_TSI_ADDR 0x08 +#define HWM_AMD_TSI_CONTROL_REG 0x0A + +// Set temp sensors type +#define TEMP_SENS_TYPE_REG 0x6B + +// FAN prog sel +#define HWM_FAN3_CONTROL 0x9A +#define HWM_FAN_SEL 0x94 +#define HWM_FAN_MODE 0x96 +#define HWM_FAN2_TEMP_MAP_SEL 0xBF + +// Fan 2 - 4 Boundries +#define HWM_FAN2_BOUND1 0xB6 +#define HWM_FAN2_BOUND2 0xB7 +#define HWM_FAN2_BOUND3 0xB8 +#define HWM_FAN2_BOUND4 0xB9 +// Fan 2 - 5 Segment speeds +#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA +#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB +#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC +#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD +#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE + + +void f81866d_hwm_init(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + const struct superio_fintek_f81866d_config *reg = dev->chip_info; + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + /* Use AMD TSI */ + pnp_write_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr); + pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control); + + /* Set temp1 sensor to thermistor */ + pnp_write_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type); + + /* Select FAN Type */ + pnp_write_index(port, HWM_FAN_SEL, reg->hwm_fan_select); + + /* Select FAN Mode*/ + pnp_write_index(port, HWM_FAN_MODE, reg->hwm_fan_mode); + + /* Set Boundries */ + pnp_write_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1); + pnp_write_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2); + pnp_write_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3); + pnp_write_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4); + + /* Set Speed */ + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed); + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed); + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed); + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed); + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed); + + /* Set Fan control freq */ + pnp_write_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control); + pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h new file mode 100644 index 0000000..acd7532 --- /dev/null +++ b/src/superio/fintek/f81866d/fintek_internal.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_FINTEK_F81866D_INTERNAL_H +#define SUPERIO_FINTEK_F81866D_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f81866d_hwm_init(struct device *dev); + +#endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */ diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c new file mode 100644 index 0000000..a2245a0 --- /dev/null +++ b/src/superio/fintek/f81866d/superio.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f81866d.h" +#include "fintek_internal.h" + +static void f81866d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need extra code for serial, wdt etc. */ + case F81866D_KBC: + pc_keyboard_init(); + break; + case F81866D_HWM: + // Fixing temp sensor read out and init Fan control + f81866d_hwm_init(dev); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81866d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F81866D_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81866D_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, }, + { &ops, F81866D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81866D_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + { &ops, F81866D_GPIO, PNP_IRQ0, }, + { &ops, F81866D_PME, }, + { &ops, F81866D_WDT, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81866d_ops = { + CHIP_NAME("Fintek F81866AD-I Super I/O") + .enable_dev = enable_dev +};

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Patch set updated for coreboot: ff4a925 Add TCPA table.
by Vladimir Serbinenko 26 May '15

26 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10274 -gerrit commit ff4a925710f6229a5fba54e6c419481faf94213e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 20 19:52:01 2015 +0200 Add TCPA table. This allows SeaBIOS to fill it as necessarry. This is the last step to make BitLocker work. Change-Id: I35858cd31a90c799ee1a240547c4b4a80fa13dd8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 69 ++++++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 7 ++++ src/include/cbmem.h | 1 + 3 files changed, 77 insertions(+) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index b2e0df3..60f0617 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -249,6 +249,65 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) header->checksum = acpi_checksum((void *)mcfg, header->length); } +#if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static void *get_tcpa_log(u32 *size) +{ + const struct cbmem_entry *ce; + const u32 tcpa_default_log_len = 0x10000; + void *lasa; + ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); + if (ce) { + lasa = cbmem_entry_start(ce); + *size = cbmem_entry_size(ce); + printk(BIOS_DEBUG, "TCPA log found at %p\n", lasa); + return lasa; + } + lasa = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_default_log_len); + if (!lasa) { + printk(BIOS_ERR, "TCPA log creation failed\n"); + return NULL; + } + + printk(BIOS_DEBUG, "TCPA log created at %p\n", lasa); + memset (lasa, 0, tcpa_default_log_len); + + *size = tcpa_default_log_len; + return lasa; +} + +static void acpi_create_tcpa(acpi_tcpa_t *tcpa) +{ + acpi_header_t *header = &(tcpa->header); + u32 tcpa_log_len; + void *lasa; + + memset((void *)tcpa, 0, sizeof(acpi_tcpa_t)); + + lasa = get_tcpa_log(&tcpa_log_len); + if (!lasa) { + return; + } + + /* Fill out header fields. */ + memcpy(header->signature, "TCPA", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_tcpa_t); + header->revision = 2; + + tcpa->platform_class = 0; + tcpa->laml = tcpa_log_len; + tcpa->lasa = (u32) lasa; + + /* Calculate checksum. */ + header->checksum = acpi_checksum((void *)tcpa, header->length); +} + +#endif + #if !IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) /* * This can be overridden by platform ACPI setup code, if it calls @@ -710,6 +769,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *dsdt; acpi_mcfg_t *mcfg; + acpi_tcpa_t *tcpa; acpi_madt_t *madt; struct device *dev; unsigned long fw; @@ -808,6 +868,15 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, mcfg); } + printk(BIOS_DEBUG, "ACPI: * TCPA\n"); + tcpa = (acpi_tcpa_t *) current; + acpi_create_tcpa(tcpa); + if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { + current += tcpa->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, tcpa); + } + printk(BIOS_DEBUG, "ACPI: * MADT\n"); madt = (acpi_madt_t *) current; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 067a26a..891b711 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -129,6 +129,13 @@ typedef struct acpi_mcfg { u8 reserved[8]; } __attribute__ ((packed)) acpi_mcfg_t; +typedef struct acpi_tcpa { + struct acpi_table_header header; + u16 platform_class; + u32 laml; + u64 lasa; +} __attribute__ ((packed)) acpi_tcpa_t; + typedef struct acpi_mcfg_mmconfig { u32 base_address; u32 base_reserved; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 20cc174..b56a51b 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -86,6 +86,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 +#define CBMEM_ID_TCPA_LOG 0x54435041 #ifndef __ASSEMBLER__ #include <stddef.h>

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Patch merged into coreboot/master: 49d3066 arm64: Add weak implementation of soc_get_bl31_plat_params
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit 49d30668b628cb68c61a7b2512628263752360c3 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 20 11:03:50 2015 -0700 arm64: Add weak implementation of soc_get_bl31_plat_params This function is required to be implemented by SoC only if some platform specific parameters are to be passed in from the early bootloader to bl31 component. BUG=chrome-os-partner:40414 BRANCH=None TEST=Compiles successfully. Change-Id: I6e76a0b6735267971e12aa72a987e8d83f5ad102 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6ab8bc12ffc2ee5bf69cef68bae852dcbf7ccb98 Original-Change-Id: If55aaee8d18a8045a5d842145c0e2c97a37a8bca Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272377 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See http://review.coreboot.org/10308 for details. -gerrit

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Patch merged into coreboot/master: b9215ab arm64: Remove PLAT= variable initialization based on Kconfig variable
by gerrit＠coreboot.org 26 May '15

26 May '15

the following patch was just integrated into master: commit b9215ab8c84d817fb51c68ee3df839321b21d2c2 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 20 11:31:08 2015 -0700 arm64: Remove PLAT= variable initialization based on Kconfig variable Each SoC should have a BL31_MAKEARGS += ... defining all the make arguments required for bl31 component compilation. BUG=chrome-os-partner:40414 BRANCH=None TEST=Compiles successfully and boots into bl31. Change-Id: I20383ab61d012f7294d969f196044a5f1c07dfc1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 72bd297994248a9d96acc6f21d06bb6ff0d5292c Original-Change-Id: I1ddd5c38e9214021d857d9d586310e23fa4114e0 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272430 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10309 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See http://review.coreboot.org/10309 for details. -gerrit

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coreboot-gerrit May 2015