coreboot-gerrit May 2015

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Patch set updated for coreboot: 48cce3f SuperIO: Add support for Fintek F81866D
by Fabian Kunkel 27 May '15

27 May '15

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10287 -gerrit commit 48cce3f9dda2be764331aa74b73a3648972a7dbd Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Mon May 25 17:04:28 2015 +0200 SuperIO: Add support for Fintek F81866D This patch adds support for the Fintek F81866D, which is very similar to the F81865. The F81866 adds some Fancontrol and correct temp sensor read out. Change-Id: Id2fc1119b37142f8101f71908e394ee69c45041d Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/superio/fintek/Kconfig | 4 + src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f81866d/Makefile.inc | 24 +++++ src/superio/fintek/f81866d/f81866d.h | 45 ++++++++ src/superio/fintek/f81866d/f81866d_hwm.c | 124 +++++++++++++++++++++++ src/superio/fintek/f81866d/f81866d_temp_sensor.c | 47 +++++++++ src/superio/fintek/f81866d/fintek_internal.h | 31 ++++++ src/superio/fintek/f81866d/superio.c | 89 ++++++++++++++++ 8 files changed, 365 insertions(+) diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index 2a7438b..5403e0a 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -54,3 +54,7 @@ config SUPERIO_FINTEK_F81216H config SUPERIO_FINTEK_F81865F bool select SUPERIO_FINTEK_COMMON_ROMSTAGE + +config SUPERIO_FINTEK_F81866D + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE \ No newline at end of file diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 60a7a04..40abb8a 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -28,3 +28,4 @@ subdirs-y += f71872 subdirs-y += f71889 subdirs-y += f81216h subdirs-y += f81865f +subdirs-y += f81866d diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc new file mode 100644 index 0000000..dd69894 --- /dev/null +++ b/src/superio/fintek/f81866d/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_temp_sensor.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c diff --git a/src/superio/fintek/f81866d/f81866d.h b/src/superio/fintek/f81866d/f81866d.h new file mode 100644 index 0000000..055bb9e --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* + * Datasheet: + * - Name: F81866D/A-I + */ + +#ifndef SUPERIO_FINTEK_F81866_H +#define SUPERIO_FINTEK_F81866_H + +/* Logical Device Numbers (LDN) */ +#define F81866D_FDC 0x00 /* Floppy */ +#define F81866D_SP1 0x10 /* UART1 */ +#define F81866D_SP2 0x11 /* UART2 */ +#define F81866D_SP3 0x12 /* UART3 */ +#define F81866D_SP4 0x13 /* UART4 */ +#define F81866D_SP5 0x14 /* UART3 */ +#define F81866D_SP6 0x15 /* UART4 */ +#define F81866D_PP 0x03 /* Parallel Port */ +#define F81866D_HWM 0x04 /* Hardware Monitor */ +#define F81866D_KBC 0x05 /* Keyboard/Mouse */ +#define F81866D_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81866D_WDT 0x07 /* Watchdog */ +#define F81866D_PME 0x0a /* Power Management Events (PME) */ + +#endif /* SUPERIO_FINTEK_F81866_H */ diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c new file mode 100644 index 0000000..073b371 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Setup only for Fan2 + * Todo: Add support for Fan1 and Fan3 + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" + + +// Set to AMD +#define HWM_AMD_TSI_ADDR 0x08 +#define HWM_AMD_TSI_CONTROL_REG 0x0A + +// Set temp sensors type +#define TEMP_SENS_TYPE_REG 0x6B + +// FAN prog sel +#define HWM_FAN3_CONTROL 0x9A +#define HWM_FAN_SEL 0x94 +#define HWM_FAN_MODE 0x96 +#define HWM_FAN_FAST_FILTER 0x97 + +// Fan expected speed +#define HWM_FAN2_EX_SPEED1 0xB2 +#define HWM_FAN2_EX_SPEED2 0xB3 + +// 4 Boundries +#define HWM_FAN2_BOUND1 0xB6 +#define HWM_FAN2_BOUND2 0xB7 +#define HWM_FAN2_BOUND3 0xB8 +#define HWM_FAN2_BOUND4 0xB9 + +// 5 Segment Speeds +#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA +#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB +#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC +#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD +#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE + +// FAN1 Temp Mapping +#define HWM_FAN2_TEMP_MAP_SEL 0xBF + +/* Defines freq. for fan control */ +#define PWM_220HZ_FAN3_CONTROL 0x20 +#define PWM_5KHZ_FAN3_CONTROL 0x20 +#define PWM_11KHZ_FAN3_CONTROL 0x00 +#define PWM_23KHZ_FAN3_CONTROL 0x00 + +#define PWM_220HZ_FAN2_MAP_SEL 0x3D +#define PWM_5KHZ_FAN2_MAP_SEL 0x1D +#define PWM_11KHZ_FAN2_MAP_SEL 0x3D +#define PWM_23KHZ_FAN2_MAP_SEL 0x1D + + +void f81866d_hwm_init(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + /* Use AMD TSI */ + pnp_write_index(port, HWM_AMD_TSI_ADDR, 0x98); + pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, 0x02); + + // Set temp1 sensor to thermistor + pnp_write_index(port, TEMP_SENS_TYPE_REG, 0x04); + + /* Select FAN Type */ + pnp_write_index(port, HWM_FAN_SEL, 0xC0); // 0xC0 set FAN2 to PWM + + /* Select FAN Mode*/ + pnp_write_index(port, HWM_FAN_MODE, 0xD5); // 0xD5 sets FAN1-3 to Auto RPM mode + + pnp_write_index(port, HWM_FAN_FAST_FILTER, 0x02); // Faster fan + + /* Set Boundries */ + pnp_write_index(port, HWM_FAN2_BOUND1, 0x3C); //60°C + pnp_write_index(port, HWM_FAN2_BOUND2, 0x32); //50°C + pnp_write_index(port, HWM_FAN2_BOUND3, 0x28); //40°C + pnp_write_index(port, HWM_FAN2_BOUND4, 0x1E); //30°C + + /* Set Speed */ + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, 0xFF); // 100% + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, 0xD9); // 85% + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, 0xB2); // 70% + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, 0x99); // 60% + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, 0x80); // 50% + + /* Set temp follows */ + pnp_write_index(port, HWM_FAN3_CONTROL, PWM_220HZ_FAN3_CONTROL); + pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, PWM_220HZ_FAN2_MAP_SEL); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/f81866d_temp_sensor.c b/src/superio/fintek/f81866d/f81866d_temp_sensor.c new file mode 100644 index 0000000..aaddd45 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_temp_sensor.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include "fintek_internal.h" + +#define TEMP_SENS_TYPE_REG 0x6B + +void f81866d_temp_sensor(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + // Set temp1 sensor correct to thermistor + pnp_write_index(port, TEMP_SENS_TYPE_REG, 0x04); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h new file mode 100644 index 0000000..c198421 --- /dev/null +++ b/src/superio/fintek/f81866d/fintek_internal.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef SUPERIO_FINTEK_F81866D_INTERNAL_H +#define SUPERIO_FINTEK_F81866D_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f81866d_temp_sensor(struct device *dev); +void f81866d_hwm_init(struct device *dev); + +#endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */ diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c new file mode 100644 index 0000000..d12d241 --- /dev/null +++ b/src/superio/fintek/f81866d/superio.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f81866d.h" +#include "fintek_internal.h" + +static void f81866d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need extra code for serial, wdt etc. */ + case F81866D_KBC: + pc_keyboard_init(); + break; + case F81866D_HWM: + + #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + // Fixing temp sensor readout according data sheet + f81866d_temp_sensor(dev); + #else + // Fixing temp sensor read out and init Fan control + f81866d_hwm_init(dev); + #endif + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81866d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F81866D_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81866D_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F81866D_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, }, + { &ops, F81866D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F81866D_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + { &ops, F81866D_GPIO, PNP_IRQ0, }, + { &ops, F81866D_PME, }, + { &ops, F81866D_WDT, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81866d_ops = { + CHIP_NAME("Fintek F81866D Super I/O") + .enable_dev = enable_dev +};

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Patch set updated for coreboot: 901f013 HyperTransport: Use subordinate property to track chain enumeration
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8688 -gerrit commit 901f0138ac556cfb6605177c2306d9b14caf22aa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 12 05:56:22 2015 +0200 HyperTransport: Use subordinate property to track chain enumeration For amdfam10, (ht_c_index > 3) never evaluates true as the code already has a return for this case above. Change-Id: Ie90941671e1b2b4f42e2b1b0641ca59334fcf0f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/hypertransport.c | 4 ++-- src/northbridge/amd/agesa/family10/northbridge.c | 11 ++++++++--- src/northbridge/amd/agesa/family15/northbridge.c | 14 ++++++++++---- src/northbridge/amd/amdfam10/northbridge.c | 23 ++++++++++++----------- src/northbridge/amd/amdk8/northbridge.c | 20 ++++++++++++++------ 5 files changed, 46 insertions(+), 26 deletions(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 1a2e7ff..84b1aa7 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -501,8 +501,8 @@ static unsigned int hypertransport_scan_chain_x(struct bus *bus, ht_unitid_base, offset_unitid); /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, max); - return max; + bus->subordinate = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, bus->secondary); + return bus->subordinate; } unsigned int ht_scan_bridge(struct device *dev, unsigned int max) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 6d0b1b7..9f2555f 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -554,13 +554,14 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; device_t io_hub = NULL; u32 next_unitid = 0xff; + unsigned int max = dev->bus->subordinate; nodeid = amdfam10_nodeid(dev); if (nodeid == 0) { @@ -576,7 +577,9 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) } } - return max; + dev->bus->subordinate = max; + + return unused; } static struct device_operations northbridge_operations = { @@ -913,7 +916,9 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) } for (link = dev->link_list; link; link = link->next) { - max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + link->secondary = dev->bus->subordinate; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, link->secondary); + dev->bus->subordinate = link->subordinate; } /* Tune the hypertransport transaction for best performance. diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index b2d8abd..a4f78f1 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -459,12 +459,14 @@ static void nb_set_resources(device_t dev) } } -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(device_t dev, unsigned unused) { unsigned nodeid; struct bus *link; device_t io_hub = NULL; u32 next_unitid = 0x18; + unsigned int max = dev->bus->subordinate; + nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { for (link = dev->link_list; link; link = link->next) { @@ -479,7 +481,10 @@ static unsigned scan_chains(device_t dev, unsigned max) } } } - return max; + + dev->bus->subordinate = max; + + return unused; } @@ -948,8 +953,9 @@ static void domain_set_resources(device_t dev) /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) { - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); - return max; + struct bus *link = dev->link_list; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); + return link->subordinate; } static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a2124f0..c3473d8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -263,16 +263,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, max); + link->subordinate = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, link->secondary); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - if(ht_c_index>3) { // clear the extend reg - clear_config_map_reg(nodeid, link->link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes); - } - - link->subordinate = max; set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); sysconf.ht_c_num++; @@ -286,15 +281,16 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool sysconf.hcdn_reg[ht_c_index] = temp; } - store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); - return max; + store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); + return link->subordinate; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; + unsigned int max = dev->bus->subordinate; nodeid = amdfam10_nodeid(dev); @@ -312,7 +308,10 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } - return max; + + dev->bus->subordinate = max; + + return unused; } @@ -924,7 +923,9 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) } for(link = dev->link_list; link; link = link->next) { - max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + link->secondary = dev->bus->subordinate; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, link->secondary); + dev->bus->subordinate = link->subordinate; } /* Tune the hypertransport transaction for best performance. diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 29cc5ed..6b06f52 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -213,12 +213,11 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, max); + link->subordinate = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, link->secondary); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - link->subordinate = max; busses = (busses & 0xff00ffff) | ((unsigned int) (link->subordinate) << 16); pci_write_config32(dev, link->cap + 0x14, busses); @@ -239,14 +238,15 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ sysconf.hcdn_reg[index] = temp; } - return max; + return link->subordinate; } -static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static unsigned amdk8_scan_chains(device_t dev, unsigned unused) { unsigned nodeid; struct bus *link; unsigned sblink = 0; + unsigned int max = dev->bus->subordinate; nodeid = amdk8_nodeid(dev); if (nodeid == 0) @@ -266,7 +266,10 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } - return max; + + dev->bus->subordinate = max; + + return unused; } @@ -1096,11 +1099,16 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) { u32 reg; int i; + struct bus *link = dev->link_list; + /* Unmap all of the HT chains */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); + + link->secondary = dev->bus->subordinate; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); + dev->bus->subordinate = link->subordinate; /* Tune the hypertransport transaction for best performance. * Including enabling relaxed ordering if it is safe.

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Patch set updated for coreboot: 49d8b42 mainboard/bap: Add support for BAP ODE E20XX
by Fabian Kunkel 27 May '15

27 May '15

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10288 -gerrit commit 49d8b427bbaa165c8c27b10bb8e2a94f8da859e9 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Mon May 25 17:08:17 2015 +0200 mainboard/bap: Add support for BAP ODE E20XX Adding new board based on AMD Kabini. Most of the code is copied from gizmosphere/gizmo2 Board is developed by BAP - Bruhnspace Advanced Projects: http://www.unibap.com/ (Site is under construction) Special on this board is: -Soldered down memory -SuperIO Fintek F81866D Known bugs: -S3 doesnt work -Serial ports only works for the first boot. Needs power cut. Tested with: -SeaBios as Payload -Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1 -Windows 8 64Bit Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/mainboard/bap/Kconfig | 24 ++- src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex | 283 ++++++++++++++++++++++++++ src/mainboard/bap/ode_e20XX/Kconfig | 1 + src/mainboard/bap/ode_e20XX/Makefile.inc | 2 +- src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c | 26 +-- src/mainboard/bap/ode_e20XX/acpi/superio.asl | 34 +++- src/mainboard/bap/ode_e20XX/devicetree.cb | 67 +++++- src/mainboard/bap/ode_e20XX/romstage.c | 15 +- 8 files changed, 421 insertions(+), 31 deletions(-) diff --git a/src/mainboard/bap/Kconfig b/src/mainboard/bap/Kconfig index 17b85bf..d72f131 100644 --- a/src/mainboard/bap/Kconfig +++ b/src/mainboard/bap/Kconfig @@ -1,13 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## if VENDOR_BAP choice prompt "Mainboard model" -source "src/mainboard/bap/*/Kconfig.name" +config BOARD_ODE_E20XX + bool "ODE_E20XX" endchoice -source "src/mainboard/bap/*/Kconfig" +source "src/mainboard/bap/ode_e20XX/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex new file mode 100644 index 0000000..e2558ba --- /dev/null +++ b/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex @@ -0,0 +1,283 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects +## (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +# BAP ODE E20XX has 2GB ram soldered down on the Q7 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 1 = 128 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 125 +92 + +# 1 SPD Revision - +# 0x10 = Revision 1.0 +12 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0b = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SO-DIMM +# bits[7:4]: reserved +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bit7 : reserved +04 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 2 = 14 Row Address Bits +# bits[7:6]: reserved +19 + +# 6 Module Nominal Voltage, VDD +# bit0 : 0 = 1.5 V operable +# bit1 : 0 = NOT 1.35 V operable +# bit2 : 0 = NOT 1.25 V operable +# bits[7:3]: reserved +00 + +# 7 Module Organization +# bits[2:0]: 2 = 16 bits +# bits[5:3]: 0 = 1 Rank +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus Width +# bits[2:0]: 3 = Primary bus width is 64 bits +# bits[4:3]: 0 = 0 bits (no bus width extension) +# bits[7:5]: reserved +08 + +# 9 Fine Timebase (FTB) Dividend / Divisor +# bits[3:0]: 0x02 divisor +# bits[7:4]: 0x05 dividend +# 5/2 = 2.5ps +52 + +# 10 Medium Timebase (MTB) Dividend +# 11 Medium Timebase (MTB) Divisor +# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz +01 08 + +# 12 SDRAM Minimum Cycle Time (tCKmin) +# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock) +0C + +# 13 Reserved +00 + +# 14 CAS Latencies Supported, Least Significant Byte +# 15 CAS Latencies Supported, Most Significant Byte +# Cas Latencies of 11 - 5 are supported +7E 00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 = tWR of 15ns - All DDR3 speed grades +78 + +# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C = 7.5ns +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x6E = 13.75ns - DDR3-1600K +69 + +# 21 Upper Nibbles for tRAS and tRC +# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) +# bits[7:4]: tRC most significant nibble = 1 (see byte 23) +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB +# 0x118 = 35ns - DDR3-1600 (see byte 21) +20 + +# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB +# 0x186 = 48.75ns - DDR3-1600K +89 + +# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB +# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB +# 0x500 = 160ns - for 2 Gigabit chips +20 08 + +# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) +# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins +3C + +# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) +# 0x3c = 7.5ns - All DDR3 SDRAM speed bins +3C + +# 28 Upper Nibble for tFAWmin +# 29 Minimum Four Activate Window Delay Time (tFAWmin) +# 0x0140 = 40ns - DDR3-1600, 2 KB page size +01 68 + +# 30 SDRAM Optional Feature +# bit0 : 1= RZQ/6 supported +# bit1 : 1 = RZQ/7 supported +# bits[6:2]: reserved +# bit7 : 1 = DLL Off mode supported +83 + +# 31 SDRAM Thermal and Refresh Options +# bit0 : 1 = Temp up to 95c supported +# bit1 : 0 = 85-95c uses 2x refresh rate +# bit2 : 1 = Auto Self Refresh supported +# bit3 : 0 = no on die thermal sensor +# bits[6:4]: reserved +# bit7 : 0 = partial self refresh supported +01 + +# 32 Module Thermal Sensor +# 0 = Thermal sensor not incorporated onto this assembly +00 + +# 33 SDRAM Device Type +# bits[1:0]: 0 = Signal Loading not specified +# bits[3:2]: reserved +# bits[6:4]: 0 = Die count not specified +# bit7 : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) +# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) +# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) +# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) +# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) +00 00 00 00 00 + +# 39 - 59 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60 Raw Card Extension, Module Nominal Height +# bits[4:0]: 0 = <= 15mm tall +# bits[7:5]: 0 = raw card revision 0-3 +0f + +# 61 Module Maximum Thickness +# bits[3:0]: 0 = thickness front <= 1mm +# bits[7:4]: 0 = thinkness back <= 1mm +11 + +# 62 Reference Raw Card Used +# bits[4:0]: 0 = Reference Raw card A used +# bits[6:5]: 0 = revision 0 +# bit7 : 0 = Reference raw cards A through AL +22 + +# 63 Address Mapping from Edge Connector to DRAM +# bit0 : 0 = standard mapping (not mirrored) +# bits[7:1]: reserved +00 + +# 64 - 116 (reserved) +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code +# 0x0001 = AMD +80 AD + +# 119 Module ID: Module Manufacturing Location - oem specified +# 120 Module ID: Module Manufacture Year in BCD +# 0x13 = 2013 +01 00 + +# 121 Module ID: Module Manufacture week +# 0x12 = 12th week +00 + +# 122 - 125: Module Serial Number +00 00 00 00 + +# 126 - 127: Cyclical Redundancy Code +D4 51 + +# Coreboot is only interested in the first 128 values +#128 - 135 +48 4d 54 34 32 35 53 36 + +#136 - 143 +4d 46 52 36 43 2d 48 39 + +#144 - 151 +20 20 4e 30 80 ad 00 00 + +#152 - 159 +00 00 00 00 00 00 00 00 + +#160 - 167 +00 00 00 00 00 00 00 00 + +#168 - 175 +00 00 00 00 00 00 00 00 + +#176 - 183 +00 00 00 00 00 00 00 00 + +#184 - 191 +00 00 00 00 00 00 00 00 + +#192 - 199 +00 00 00 00 00 00 00 00 + +#200 - 207 +00 00 00 00 00 00 00 00 + +#208 - 215 +00 00 00 00 00 00 00 00 + +#216 - 223 +00 00 00 00 00 00 00 00 + +#224 - 231 +00 00 00 00 00 00 00 00 + +#232 - 239 +00 00 00 00 00 00 00 00 + +#240 - 247 +00 00 00 00 00 00 00 00 + +#248 - 255 +00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 94ad97b..15face5 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA + select SUPERIO_FINTEK_F81866D select SPD_CACHE config MAINBOARD_DIR diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc index 6bbb85a..13523dd 100644 --- a/src/mainboard/bap/ode_e20XX/Makefile.inc +++ b/src/mainboard/bap/ode_e20XX/Makefile.inc @@ -30,7 +30,7 @@ ramstage-y += PlatformGnbPcie.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Micron_MT41J128M16JT +SPD_SOURCES = BAP_Q7 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c index 66bebc2..8a49af5 100644 --- a/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c +++ b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c @@ -32,20 +32,20 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x01, 0) + AspmL0sL1, 0x01, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x02, 0) + AspmL0sL1, 0x02, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -55,7 +55,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x03, 0) + AspmL0sL1, 0x03, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -65,32 +65,32 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x04, 0) + AspmL0sL1, 0x04, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { - DESCRIPTOR_TERMINATE_LIST, + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x05, 0) + AspmL0sL1, 0x05, 0) } }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - /* DP0 to HDMI0/DP */ + /* DP0 to LVDS*/ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - /* DP1 to high-speed edge connector */ + /* DP1 to HDMI */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) }, }; diff --git a/src/mainboard/bap/ode_e20XX/acpi/superio.asl b/src/mainboard/bap/ode_e20XX/acpi/superio.asl index 97304f9..1c5b3cd 100644 --- a/src/mainboard/bap/ode_e20XX/acpi/superio.asl +++ b/src/mainboard/bap/ode_e20XX/acpi/superio.asl @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,4 +19,34 @@ * Foundation, Inc. */ -/* No Super I/O device or functionality yet */ +/* SuperIO support for Windows */ + +Device (UAR1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {4} + }) +} + +Device (UAR2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3} + }) + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3} + }) +} diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb index 34c2fd4..93f5e73 100644 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -9,7 +9,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -32,11 +32,11 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # PCIe GFX Bridge - device pci 2.2 on end # PCIe GPP mini PCIe - device pci 2.3 on end # PCIe LAN - device pci 2.4 on end # PCIe x2 to high speed edge connector - device pci 2.5 on end # PCIe x2 to high speed edge connector + device pci 2.1 on end # x4 PCIe Slot + device pci 2.2 on end # PCIe Q7 Realtek GBit LAN + device pci 2.3 on end # PCIe CB Realtek GBit LAN + device pci 2.4 on end # PCIe BAP FPGA + device pci 2.5 on end # PCIe BAP FPGA (unused, for 050T) end #chip northbridge/amd/agesa/family16kb chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus @@ -48,7 +48,60 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 13.2 on end # USB device pci 14.0 on end # SM device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81866d + register "hwm_amd_tsi_addr" = "0x98" # Set to AMD + register "hwm_amd_tsi_control" = "0x02" # Set to AMD + register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM + register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode + register "hwm_fan3_control" = "0x00" # Fan control 23kHz + register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz + register "hwm_fan2_bound1" = "0x3C" # 60°C + register "hwm_fan2_bound2" = "0x32" # 50°C + register "hwm_fan2_bound3" = "0x28" # 40°C + register "hwm_fan2_bound4" = "0x1E" # 30°C + register "hwm_fan2_seg1_speed" = "0xFF" # 100% + register "hwm_fan2_seg2_speed" = "0xD9" # 85% + register "hwm_fan2_seg3_speed" = "0xB2" # 70% + register "hwm_fan2_seg4_speed" = "0x99" # 60% + register "hwm_fan2_seg5_speed" = "0x80" # 50% + register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # Hardware Monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.7 on end # WDT + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 off # COM3 + end + device pnp 4e.13 off # COM4 + end + device pnp 4e.14 off # COM5 + end + device pnp 4e.15 off # COM6 + end + end # f81866d + end #LPC device pci 14.7 on end # SD end #chip southbridge/amd/hudson diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index 4cfca8e..62b9d1c 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,20 +37,18 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <cpu/amd/agesa/s3_resume.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> #include "cbmem.h" +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); + // All cores: set pstate 7 (800 MHz) early to save power + __writemsr (0xc0010062, 7); amd_initmmio(); @@ -62,6 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); post_code(0x31); + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); console_init(); }

1 0

Patch set updated for coreboot: 3d9a7e5 PCI subsystem: Drop parameter max from scan_bus
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8539 -gerrit commit 3d9a7e5cfdd49098b061a85693324aaea3f2b451 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Mar 18 13:09:47 2015 +0200 PCI subsystem: Drop parameter max from scan_bus Change-Id: Ib33d3363c8d42fa54ac07c11a7ab2bc7ee4ae8bf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/hypertransport.c | 9 +++------ src/device/pci_device.c | 24 ++++++++++-------------- src/device/pciexp_device.c | 7 +++---- src/include/device/pci.h | 9 ++++++--- src/include/device/pciexp.h | 5 +++-- src/include/device/pcix.h | 2 -- src/northbridge/amd/agesa/family10/northbridge.c | 6 ++++-- src/northbridge/amd/agesa/family15/northbridge.c | 6 ++++-- src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- src/northbridge/amd/amdk8/northbridge.c | 4 ++-- src/southbridge/amd/amd8131/bridge.c | 12 +++++------- src/southbridge/amd/amd8132/bridge.c | 13 +++++-------- 12 files changed, 47 insertions(+), 54 deletions(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 84b1aa7..799038c 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -488,11 +488,9 @@ end_of_chain: * @param bus TODO * @param min_devfn TODO * @param max_devfn TODO - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate busses. */ -static unsigned int hypertransport_scan_chain_x(struct bus *bus, - unsigned int min_devfn, unsigned int max_devfn, unsigned int max) +static void hypertransport_scan_chain_x(struct bus *bus, + unsigned int min_devfn, unsigned int max_devfn) { unsigned int ht_unitid_base[4]; unsigned int offset_unitid = 1; @@ -501,8 +499,7 @@ static unsigned int hypertransport_scan_chain_x(struct bus *bus, ht_unitid_base, offset_unitid); /* Now that nothing is overlapping it is safe to scan the children. */ - bus->subordinate = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, bus->secondary); - return bus->subordinate; + pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); } unsigned int ht_scan_bridge(struct device *dev, unsigned int max) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index fe03d61..188f101 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1074,17 +1074,12 @@ unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev) * Determine the existence of devices and bridges on a PCI bus. If there are * bridges on the bus, recursively scan the buses behind the bridges. * - * This function is the default scan_bus() method for the root device - * 'dev_root'. - * * @param bus Pointer to the bus structure. * @param min_devfn Minimum devfn to look at in the scan, usually 0x00. * @param max_devfn Maximum devfn to look at in the scan, usually 0xff. - * @param max Current bus number. - * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, - unsigned max_devfn, unsigned int max) +void pci_scan_bus(struct bus *bus, unsigned min_devfn, + unsigned max_devfn) { unsigned int devfn; struct device *old_devices; @@ -1149,17 +1144,19 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, * For all children that implement scan_bus() (i.e. bridges) * scan the bus behind that child. */ + unsigned int max = bus->secondary; + for (child = bus->children; child; child = child->sibling) max = scan_bus(child, max); + bus->subordinate = max; + /* * We've scanned the bus and so we know all about what's on the other * side of any bridges that may be on this bus plus any devices. * Return how far we've got finding sub-buses. */ - printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max); post_code(0x55); - return max; } typedef enum { @@ -1228,10 +1225,9 @@ static void pci_bridge_route(struct bus *link, scan_state state) * @return The maximum bus number found, after scanning all subordinate buses. */ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, - unsigned int (*do_scan_bus) (struct bus * bus, + void (*do_scan_bus) (struct bus * bus, unsigned min_devfn, - unsigned max_devfn, - unsigned int max)) + unsigned max_devfn)) { struct bus *bus; @@ -1251,7 +1247,7 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, pci_bridge_route(bus, PCI_ROUTE_SCAN); - bus->subordinate = do_scan_bus(bus, 0x00, 0xff, bus->secondary); + do_scan_bus(bus, 0x00, 0xff); pci_bridge_route(bus, PCI_ROUTE_FINAL); @@ -1287,7 +1283,7 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) unsigned int pci_domain_scan_bus(device_t dev, unsigned int unused) { struct bus *link = dev->link_list; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); return unused; } diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f6127b2..5311397 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -416,12 +416,12 @@ static void pciexp_tune_dev(device_t dev) #endif } -unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max) +void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn) { device_t child; - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); for (child = bus->children; child; child = child->sibling) { if ((child->path.pci.devfn < min_devfn) || @@ -430,7 +430,6 @@ unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, } pciexp_tune_dev(child); } - return max; } unsigned int pciexp_scan_bridge(device_t dev, unsigned int max) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 141d2e8..f1dcd03 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -70,11 +70,14 @@ void pci_dev_enable_resources(device_t dev); void pci_bus_enable_resources(device_t dev); void pci_bus_reset(struct bus *bus); device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); + unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, - unsigned int (*do_scan_bus)(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max)); + void (*do_scan_bus)(struct bus *bus, + unsigned min_devfn, unsigned max_devfn)); unsigned int pci_scan_bridge(device_t bus, unsigned int max); -unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); + +void pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn); + uint8_t pci_moving_config8(struct device *dev, unsigned reg); uint16_t pci_moving_config16(struct device *dev, unsigned reg); uint32_t pci_moving_config32(struct device *dev, unsigned reg); diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 1146557..b600228 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -9,8 +9,9 @@ enum aspm_type { PCIE_ASPM_BOTH = 3, }; -unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max); +void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn); + unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 4ffab5b..75be7aa 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,8 +2,6 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pcix_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max); unsigned int pcix_scan_bridge(device_t dev, unsigned int max); const char *pcix_speed(u16 sstatus); diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index bb2f1d8..6ba6770 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -565,6 +565,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) nodeid = amdfam10_nodeid(dev); if (nodeid == 0) { + ASSERT(dev->bus->secondary == 0); for (link = dev->link_list; link; link = link->next) { if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[3] */ io_hub = link->children; @@ -572,9 +573,10 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); } /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); } } + max = dev->bus->subordinate; } dev->bus->subordinate = max; @@ -917,7 +919,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) for (link = dev->link_list; link; link = link->next) { link->secondary = dev->bus->subordinate; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff); dev->bus->subordinate = link->subordinate; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 093d0c0..e480eba 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -469,6 +469,7 @@ static unsigned scan_chains(device_t dev, unsigned unused) nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { + ASSERT(dev->bus->secondary == 0); for (link = dev->link_list; link; link = link->next) { //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ @@ -477,9 +478,10 @@ static unsigned scan_chains(device_t dev, unsigned unused) die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); } /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); } } + max = dev->bus->subordinate; } dev->bus->subordinate = max; @@ -954,7 +956,7 @@ static void domain_set_resources(device_t dev) static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int unused) { struct bus *link = dev->link_list; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); return unused; } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3e2d0f5..511d72e 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -263,7 +263,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); /* Now that nothing is overlapping it is safe to scan the children. */ - link->subordinate = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, link->secondary); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value @@ -924,7 +924,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) for(link = dev->link_list; link; link = link->next) { link->secondary = dev->bus->subordinate; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff); dev->bus->subordinate = link->subordinate; } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index f4177ba..0d3a6c5 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -213,7 +213,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); /* Now that nothing is overlapping it is safe to scan the children. */ - link->subordinate = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, link->secondary); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value @@ -1107,7 +1107,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 unused) } link->secondary = dev->bus->subordinate; - link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); + pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); dev->bus->subordinate = link->subordinate; /* Tune the hypertransport transaction for best performance. diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index e638fae..cb76980 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -192,16 +192,15 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) pci_write_config16(dev, cap + PCI_X_CMD, cmd); } } -static unsigned int amd8131_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max) +static void amd8131_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn) { struct amd8131_bus_info info; struct bus *pbus; unsigned pos; - /* Find the children on the bus */ - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); /* Find the revision of the 8131 */ info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION); @@ -243,13 +242,13 @@ static unsigned int amd8131_scan_bus(struct bus *bus, pcix_misc &= ~(0x1f << 16); pci_write_config32(bus->dev, 0x40, pcix_misc); - return max; + return; } /* If we are in conventional PCI mode nothing more is necessary. */ if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { - return max; + return; } @@ -264,7 +263,6 @@ static unsigned int amd8131_scan_bus(struct bus *bus, bus_path(pbus)); pbus->disable_relaxed_ordering = 1; } - return max; } static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max) diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 2684e7c..48d7c51 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -138,15 +138,14 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) } -static unsigned int amd8132_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max) +static void amd8132_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn) { struct amd8132_bus_info info; unsigned pos; - /* Find the children on the bus */ - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); /* Find the revision of the 8132 */ info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION); @@ -181,20 +180,18 @@ static unsigned int amd8132_scan_bus(struct bus *bus, pcix_misc &= ~(0x1f << 16); pci_write_config32(bus->dev, 0x40, pcix_misc); - return max; + return; } #endif /* If we are in conventional PCI mode nothing more is necessary. */ if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { - return max; + return; } /* Tune the devices on the bus */ amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info); - - return max; } static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max)

1 0

Patch set updated for coreboot: 565c3e3 PCI subsystem: Refactor PCI bridge register control
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8536 -gerrit commit 565c3e3ff203844118f81e820cd009b3d707a33a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 06:58:26 2015 +0200 PCI subsystem: Refactor PCI bridge register control Change-Id: I1766c92abe7a74326c49df74ba38930a502fcb5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 76 +++++++++++++++++++++++++++++---------------- src/include/device/device.h | 1 + 2 files changed, 51 insertions(+), 26 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index e43d4e5..7ac560b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1162,6 +1162,53 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, return max; } +typedef enum { + PCI_ROUTE_CLOSE, + PCI_ROUTE_SCAN, + PCI_ROUTE_FINAL, +} scan_state; + +static void pci_bridge_route(struct bus *link, scan_state state) +{ + struct device *dev = link->dev; + struct bus *parent = dev->bus; + u32 reg, buses = 0; + + if (state == PCI_ROUTE_CLOSE) { + buses |= 0xfeff << 8; + } else if (state == PCI_ROUTE_SCAN) { + buses |= ((u32) link->secondary & 0xff) << 8; + buses |= ((u32) link->subordinate & 0xff) << 16; + } else if (state == PCI_ROUTE_FINAL) { + buses |= parent->secondary & 0xff; + buses |= ((u32) link->secondary & 0xff) << 8; + buses |= ((u32) link->subordinate & 0xff) << 16; + } + + if (state == PCI_ROUTE_SCAN) { + /* Clear all status bits and turn off memory, I/O and master enables. */ + link->bridge_cmd = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, 0x0000); + pci_write_config16(dev, PCI_STATUS, 0xffff); + } + + /* + * Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is not + * correctly configured. + */ + + reg = pci_read_config32(dev, PCI_PRIMARY_BUS); + reg &= 0xff000000; + reg |= buses; + pci_write_config32(dev, PCI_PRIMARY_BUS, reg); + + if (state == PCI_ROUTE_FINAL) { + pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd); + } +} + + /** * Scan a PCI bridge and the buses behind the bridge. * @@ -1182,8 +1229,6 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, unsigned int max)) { struct bus *bus; - u32 buses; - u16 cr; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev)); @@ -1207,27 +1252,7 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, bus->secondary = ++max; bus->subordinate = 0xff; - /* Clear all status bits and turn off memory, I/O and master enables. */ - cr = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, 0x0000); - pci_write_config16(dev, PCI_STATUS, 0xffff); - - /* - * Read the existing primary/secondary/subordinate bus - * number configuration. - */ - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - - /* - * Configure the bus numbers for this bridge: the configuration - * transactions will not be propagated by the bridge if it is not - * correctly configured. - */ - buses &= 0xff000000; - buses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(bus->secondary) << 8) | - ((unsigned int)(bus->subordinate) << 16)); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); + pci_bridge_route(bus, PCI_ROUTE_SCAN); /* Now we can scan all subordinate buses (those behind the bridge). */ max = do_scan_bus(bus, 0x00, 0xff, max); @@ -1237,9 +1262,8 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, * bus number to its real value. */ bus->subordinate = max; - buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - pci_write_config16(dev, PCI_COMMAND, cr); + + pci_bridge_route(bus, PCI_ROUTE_FINAL); printk(BIOS_SPEW, "%s returns max %d\n", __func__, max); return max; diff --git a/src/include/device/device.h b/src/include/device/device.h index d9fc663..aec1af5 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -81,6 +81,7 @@ struct bus { ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ + uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */

1 0

Patch set updated for coreboot: a2c04b7 PCI subsystem: Use subordinate property to track bus enumeration
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8537 -gerrit commit a2c04b7e56cefca7028d2a0bc92acf76f6e78ebe Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 06:58:26 2015 +0200 PCI subsystem: Use subordinate property to track bus enumeration Parameter max is the cumulative number of PCI buses scanned on the system so far. Use the property subordinate from the parent PCI bridge device to keep track of the first available bus number instead of passing that on the stack. Change-Id: I1a884c98d50fa4f1eb2752e10b778aea8a7b090a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 29 +++++++++-------------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7ac560b..fe03d61 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1174,11 +1174,16 @@ static void pci_bridge_route(struct bus *link, scan_state state) struct bus *parent = dev->bus; u32 reg, buses = 0; + if (state == PCI_ROUTE_SCAN) { + link->secondary = parent->subordinate + 1; + link->subordinate = link->secondary; + } + if (state == PCI_ROUTE_CLOSE) { buses |= 0xfeff << 8; } else if (state == PCI_ROUTE_SCAN) { buses |= ((u32) link->secondary & 0xff) << 8; - buses |= ((u32) link->subordinate & 0xff) << 16; + buses |= 0xff << 16; /* MAX PCI_BUS number here */ } else if (state == PCI_ROUTE_FINAL) { buses |= parent->secondary & 0xff; buses |= ((u32) link->secondary & 0xff) << 8; @@ -1205,10 +1210,10 @@ static void pci_bridge_route(struct bus *link, scan_state state) if (state == PCI_ROUTE_FINAL) { pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd); + parent->subordinate = link->subordinate; } } - /** * Scan a PCI bridge and the buses behind the bridge. * @@ -1244,29 +1249,13 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, bus = dev->link_list; - /* - * Set up the primary, secondary and subordinate bus numbers. We have - * no idea how many buses are behind this bridge yet, so we set the - * subordinate bus number to 0xff for the moment. - */ - bus->secondary = ++max; - bus->subordinate = 0xff; - pci_bridge_route(bus, PCI_ROUTE_SCAN); - /* Now we can scan all subordinate buses (those behind the bridge). */ - max = do_scan_bus(bus, 0x00, 0xff, max); - - /* - * We know the number of buses behind this bridge. Set the subordinate - * bus number to its real value. - */ - bus->subordinate = max; + bus->subordinate = do_scan_bus(bus, 0x00, 0xff, bus->secondary); pci_bridge_route(bus, PCI_ROUTE_FINAL); - printk(BIOS_SPEW, "%s returns max %d\n", __func__, max); - return max; + return bus->subordinate; } /**

1 0

Patch set updated for coreboot: 673345d devicetree: Rename unused parameter max in domain_scan_bus()
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8855 -gerrit commit 673345dd48977f79497913f0933950d679a2e73a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 19 15:26:52 2015 +0200 devicetree: Rename unused parameter max in domain_scan_bus() For the PCI root node, input parameter max==0 and output value max is not relevant for operation. Change-Id: I23adab24aa957c4d51d703098a9a40ed660b4e6c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 7 ++++--- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++-- src/northbridge/amd/agesa/family15/northbridge.c | 4 ++-- src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- src/northbridge/amd/amdk8/northbridge.c | 4 ++-- 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4651258..e43d4e5 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1271,10 +1271,11 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) * @param max The highest bus number assigned up to now. * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +unsigned int pci_domain_scan_bus(device_t dev, unsigned int unused) { - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); - return max; + struct bus *link = dev->link_list; + link->subordinate = pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff, link->secondary); + return unused; } /** diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index c9e4200..bb2f1d8 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -905,7 +905,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) { u32 reg; int i; @@ -942,7 +942,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; + return unused; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5a08f23..093d0c0 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -951,11 +951,11 @@ static void domain_set_resources(device_t dev) } /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int unused) { struct bus *link = dev->link_list; link->subordinate = pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff, link->secondary); - return link->subordinate; + return unused; } static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 68b0a80..3e2d0f5 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -912,7 +912,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) { u32 reg; int i; @@ -949,7 +949,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; + return unused; } #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 18f7459..f4177ba 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1095,7 +1095,7 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 max) +static u32 amdk8_domain_scan_bus(device_t dev, u32 unused) { u32 reg; int i; @@ -1131,7 +1131,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; + return unused; } static struct device_operations pci_domain_ops = {

1 0

Patch set updated for coreboot: 7e4c46a devicetree: Single scan_bridges()
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8540 -gerrit commit 7e4c46a59a482a82ee36b6ef704346748911f67a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 20 21:28:31 2015 +0200 devicetree: Single scan_bridges() Change-Id: Ifd277992a69a4182e2fac92aaf746abe4fec2a1b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 21 +++++++++++++++++---- src/device/pci_device.c | 7 +------ src/device/root_device.c | 12 ++---------- src/include/device/device.h | 2 +- 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 35bb6e2..a8900a6 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -916,15 +916,15 @@ int reset_bus(struct bus *bus) * @param max Current bus number. * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int scan_bus(struct device *busdev, unsigned int max) +static unsigned int scan_bus(struct device *busdev, unsigned int max) { unsigned int new_max; int do_scan_bus; - if (!busdev || !busdev->enabled || !busdev->ops || - !busdev->ops->scan_bus) { + if (!busdev->enabled) return max; - } + + printk(BIOS_SPEW, "%s scanning...\n", dev_path(busdev)); post_log_path(busdev); @@ -945,6 +945,19 @@ unsigned int scan_bus(struct device *busdev, unsigned int max) return new_max; } +void scan_bridges(struct bus *bus) +{ + struct device *child; + unsigned int max = bus->secondary; + + for (child = bus->children; child; child = child->sibling) { + if (!child->ops || !child->ops->scan_bus) + continue; + max = scan_bus(child, max); + } + bus->subordinate = max; +} + /** * Determine the existence of devices and extend the device tree. * diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 188f101..07b1993 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1083,7 +1083,6 @@ void pci_scan_bus(struct bus *bus, unsigned min_devfn, { unsigned int devfn; struct device *old_devices; - struct device *child; printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary); @@ -1144,12 +1143,8 @@ void pci_scan_bus(struct bus *bus, unsigned min_devfn, * For all children that implement scan_bus() (i.e. bridges) * scan the bus behind that child. */ - unsigned int max = bus->secondary; - for (child = bus->children; child; child = child->sibling) - max = scan_bus(child, max); - - bus->subordinate = max; + scan_bridges(bus); /* * We've scanned the bus and so we know all about what's on the other diff --git a/src/device/root_device.c b/src/device/root_device.c index d4ad034..4eae12a 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -126,22 +126,14 @@ unsigned int scan_smbus(device_t bus, unsigned int passthru) */ static unsigned int root_dev_scan_bus(device_t bus, unsigned int passthru) { - device_t child; struct bus *link; - unsigned int max = 0; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); scan_static_bus(bus, 0); - for (link = bus->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - if (!child->ops || !child->ops->scan_bus) - continue; - printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); - max = scan_bus(child, max); - } - } + for (link = bus->link_list; link; link = link->next) + scan_bridges(link); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); diff --git a/src/include/device/device.h b/src/include/device/device.h index aec1af5..84a17d0 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -172,7 +172,7 @@ void dev_finalize_chips(void); /* Generic device helper functions */ int reset_bus(struct bus *bus); -unsigned int scan_bus(struct device *bus, unsigned int _max); +void scan_bridges(struct bus *bus); void assign_resources(struct bus *bus); const char *dev_name(device_t dev); const char *dev_path(device_t dev);

1 0

Patch set updated for coreboot: 49a5810 devicetree: Change scan_bus() prototype in device ops
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8541 -gerrit commit 49a58102109e59f5b95d12c9b99a3021aac0ada8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 19 21:04:23 2015 +0200 devicetree: Change scan_bus() prototype in device ops The input/output value max is no longer used for tracking the bus enumeration sequence, everything is handled in the context of devicetree bus objects. Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 16 +++++---------- src/device/hypertransport.c | 4 ++-- src/device/pci_device.c | 17 ++++----------- src/device/pciexp_device.c | 4 ++-- src/device/pcix_device.c | 6 ++---- src/device/root_device.c | 24 ++++++---------------- src/include/device/device.h | 8 ++++---- src/include/device/hypertransport.h | 3 ++- src/include/device/pci.h | 4 ++-- src/include/device/pciexp.h | 2 +- src/include/device/pcix.h | 3 ++- src/mainboard/emulation/qemu-i440fx/northbridge.c | 5 ++--- src/northbridge/amd/agesa/family10/northbridge.c | 10 +++------ src/northbridge/amd/agesa/family14/northbridge.c | 3 +-- src/northbridge/amd/agesa/family15/northbridge.c | 10 +++------ src/northbridge/amd/agesa/family15rl/northbridge.c | 3 +-- src/northbridge/amd/agesa/family15tn/northbridge.c | 3 +-- src/northbridge/amd/agesa/family16kb/northbridge.c | 3 +-- src/northbridge/amd/amdfam10/northbridge.c | 10 +++------ src/northbridge/amd/amdk8/northbridge.c | 10 +++------ src/northbridge/amd/pi/00630F01/northbridge.c | 3 +-- src/northbridge/amd/pi/00730F01/northbridge.c | 3 +-- src/northbridge/intel/i3100/pciexp_porta.c | 5 +++-- src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 5 +++-- src/southbridge/amd/amd8131/bridge.c | 4 ++-- src/southbridge/amd/amd8132/bridge.c | 4 ++-- src/southbridge/amd/cs5536/cs5536.c | 4 ++-- src/southbridge/intel/bd82x6x/pcie.c | 7 ++----- src/southbridge/intel/i3100/pciexp_portb.c | 5 +++-- src/southbridge/intel/i82801ix/pcie.c | 7 ++----- 30 files changed, 71 insertions(+), 124 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index a8900a6..6bdeae1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -913,16 +913,13 @@ int reset_bus(struct bus *bus) * required, reset the bus and scan it again. * * @param busdev Pointer to the bus device. - * @param max Current bus number. - * @return The maximum bus number found, after scanning all subordinate buses. */ -static unsigned int scan_bus(struct device *busdev, unsigned int max) +static void scan_bus(struct device *busdev) { - unsigned int new_max; int do_scan_bus; if (!busdev->enabled) - return max; + return; printk(BIOS_SPEW, "%s scanning...\n", dev_path(busdev)); @@ -931,7 +928,7 @@ static unsigned int scan_bus(struct device *busdev, unsigned int max) do_scan_bus = 1; while (do_scan_bus) { struct bus *link; - new_max = busdev->ops->scan_bus(busdev, max); + busdev->ops->scan_bus(busdev); do_scan_bus = 0; for (link = busdev->link_list; link; link = link->next) { if (link->reset_needed) { @@ -942,20 +939,17 @@ static unsigned int scan_bus(struct device *busdev, unsigned int max) } } } - return new_max; } void scan_bridges(struct bus *bus) { struct device *child; - unsigned int max = bus->secondary; for (child = bus->children; child; child = child->sibling) { if (!child->ops || !child->ops->scan_bus) continue; - max = scan_bus(child, max); + scan_bus(child); } - bus->subordinate = max; } /** @@ -999,7 +993,7 @@ void dev_enumerate(void) printk(BIOS_ERR, "dev_root missing scan_bus operation"); return; } - scan_bus(root, 0); + scan_bus(root); post_log_clear(); printk(BIOS_INFO, "done\n"); } diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 799038c..584ac78 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -502,9 +502,9 @@ static void hypertransport_scan_chain_x(struct bus *bus, pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); } -unsigned int ht_scan_bridge(struct device *dev, unsigned int max) +void ht_scan_bridge(struct device *dev) { - return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x); + do_pci_scan_bridge(dev, hypertransport_scan_chain_x); } /** Default device operations for hypertransport bridges */ diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 07b1993..6332209 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1215,11 +1215,9 @@ static void pci_bridge_route(struct bus *link, scan_state state) * This function is the default scan_bus() method for PCI bridge devices. * * @param dev Pointer to the bridge device. - * @param max The highest bus number assigned up to now. * @param do_scan_bus TODO - * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, +void do_pci_scan_bridge(struct device *dev, void (*do_scan_bus) (struct bus * bus, unsigned min_devfn, unsigned max_devfn)) @@ -1245,8 +1243,6 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, do_scan_bus(bus, 0x00, 0xff); pci_bridge_route(bus, PCI_ROUTE_FINAL); - - return bus->subordinate; } /** @@ -1258,12 +1254,10 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, * This function is the default scan_bus() method for PCI bridge devices. * * @param dev Pointer to the bridge device. - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int pci_scan_bridge(struct device *dev, unsigned int max) +void pci_scan_bridge(struct device *dev) { - return do_pci_scan_bridge(dev, max, pci_scan_bus); + do_pci_scan_bridge(dev, pci_scan_bus); } /** @@ -1272,14 +1266,11 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) * This function is the default scan_bus() method for PCI domains. * * @param dev Pointer to the domain. - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_domain_scan_bus(device_t dev, unsigned int unused) +void pci_domain_scan_bus(device_t dev) { struct bus *link = dev->link_list; pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); - return unused; } /** diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 5311397..ee24456 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -432,9 +432,9 @@ void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, } } -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max) +void pciexp_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, pciexp_scan_bus); + do_pci_scan_bridge(dev, pciexp_scan_bus); } /** Default device operations for PCI Express bridges */ diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index cfa2f91..7ed64df 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -112,12 +112,12 @@ const char *pcix_speed(u16 sstatus) return result; } -unsigned int pcix_scan_bridge(device_t dev, unsigned int max) +void pcix_scan_bridge(device_t dev) { unsigned int pos; u16 sstatus; - max = do_pci_scan_bridge(dev, max, pci_scan_bus); + do_pci_scan_bridge(dev, pci_scan_bus); /* Find the PCI-X capability. */ pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); @@ -129,8 +129,6 @@ unsigned int pcix_scan_bridge(device_t dev, unsigned int max) /* Print the PCI-X bus speed. */ printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary, pcix_speed(sstatus)); - - return max; } /** Default device operations for PCI-X bridges */ diff --git a/src/device/root_device.c b/src/device/root_device.c index 4eae12a..0185275 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -45,11 +45,9 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_ * file under some static bus in order to be enumerated at run time. * * @param bus Pointer to the device to which the static buses are attached to. - * @param max Maximum bus number currently used before scanning. - * @return The largest bus number used. */ -static unsigned int scan_static_bus(device_t bus, unsigned int passthru) +static void scan_static_bus(device_t bus) { device_t child; struct bus *link; @@ -67,22 +65,18 @@ static unsigned int scan_static_bus(device_t bus, unsigned int passthru) child->enabled ? "enabled" : "disabled"); } } - - return passthru; } -unsigned int scan_lpc_bus(device_t bus, unsigned int passthru) +void scan_lpc_bus(device_t bus) { printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus, 0); + scan_static_bus(bus); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - - return passthru; } -unsigned int scan_smbus(device_t bus, unsigned int passthru) +void scan_smbus(device_t bus) { device_t child; struct bus *link; @@ -111,8 +105,6 @@ unsigned int scan_smbus(device_t bus, unsigned int passthru) } printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - - return passthru; } /** @@ -121,23 +113,19 @@ unsigned int scan_smbus(device_t bus, unsigned int passthru) * This function is the default scan_bus() method of the root device. * * @param root The root device structure. - * @param max The current bus number scanned so far, usually 0x00. - * @return The largest bus number used. */ -static unsigned int root_dev_scan_bus(device_t bus, unsigned int passthru) +static void root_dev_scan_bus(device_t bus) { struct bus *link; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus, 0); + scan_static_bus(bus); for (link = bus->link_list; link; link = link->next) scan_bridges(link); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - - return passthru; } static void root_dev_reset(struct bus *bus) diff --git a/src/include/device/device.h b/src/include/device/device.h index 84a17d0..9c53f95 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -46,7 +46,7 @@ struct device_operations { void (*enable_resources)(device_t dev); void (*init)(device_t dev); void (*final)(device_t dev); - unsigned int (*scan_bus)(device_t bus, unsigned int _max); + void (*scan_bus)(device_t bus); void (*enable)(device_t dev); void (*disable)(device_t dev); void (*set_link)(device_t dev, unsigned int link); @@ -224,13 +224,13 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); -unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); +void pci_domain_scan_bus(struct device *dev); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); -unsigned int scan_smbus(device_t bus, unsigned int _max); -unsigned int scan_lpc_bus(device_t bus, unsigned int _max); +void scan_smbus(device_t bus); +void scan_lpc_bus(device_t bus); /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index 03e327d..22e0ac4 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -5,7 +5,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned *ht_unit_base, unsigned offset_unitid); -unsigned int ht_scan_bridge(struct device *dev, unsigned int max); +void ht_scan_bridge(struct device *dev); + extern struct device_operations default_ht_ops_bus; #define HT_IO_HOST_ALIGN 4096 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f1dcd03..2a76ba9 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -71,11 +71,11 @@ void pci_bus_enable_resources(device_t dev); void pci_bus_reset(struct bus *bus); device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); -unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, +void do_pci_scan_bridge(device_t bus, void (*do_scan_bus)(struct bus *bus, unsigned min_devfn, unsigned max_devfn)); -unsigned int pci_scan_bridge(device_t bus, unsigned int max); +void pci_scan_bridge(device_t bus); void pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn); uint8_t pci_moving_config8(struct device *dev, unsigned reg); diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index b600228..f3df1a5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -12,7 +12,7 @@ enum aspm_type { void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); +void pciexp_scan_bridge(device_t dev); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 75be7aa..024c548 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,7 +2,8 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pcix_scan_bridge(device_t dev, unsigned int max); +void pcix_scan_bridge(device_t dev); + const char *pcix_speed(u16 sstatus); extern struct device_operations default_pcix_ops_bus; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 1967c8b..26cbda5 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -241,14 +241,14 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static unsigned int cpu_bus_scan(device_t bus, unsigned int passthru) +static void cpu_bus_scan(device_t bus) { int max_cpus = fw_cfg_max_cpus(); device_t cpu; int i; if (max_cpus < 0) - return 0; + return; /* * TODO: This only handles the simple "qemu -smp $nr" case @@ -261,7 +261,6 @@ static unsigned int cpu_bus_scan(device_t bus, unsigned int passthru) if (cpu) set_cpu_topology(cpu, 1, 0, i, 0); } - return max_cpus; } static struct device_operations cpu_bus_ops = { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 6ba6770..0fe1910 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -554,7 +554,7 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) +static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; @@ -580,8 +580,6 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) } dev->bus->subordinate = max; - - return unused; } static struct device_operations northbridge_operations = { @@ -907,7 +905,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) +static void amdfam10_domain_scan_bus(device_t dev) { u32 reg; int i; @@ -944,7 +942,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return unused; } @@ -1012,7 +1009,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1188,7 +1185,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 426ec74..32b74f6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -765,7 +765,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static u32 cpu_bus_scan(struct device *dev, u32 passthru) +static void cpu_bus_scan(struct device *dev) { struct bus *cpu_bus = dev->link_list; device_t cpu; @@ -784,7 +784,6 @@ static u32 cpu_bus_scan(struct device *dev, u32 passthru) if (cpu) amd_cpu_topology(cpu, 0, apic_id); } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index e480eba..94e16ac 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -459,7 +459,7 @@ static void nb_set_resources(device_t dev) } } -static unsigned scan_chains(device_t dev, unsigned unused) +static void scan_chains(device_t dev) { unsigned nodeid; struct bus *link; @@ -485,8 +485,6 @@ static unsigned scan_chains(device_t dev, unsigned unused) } dev->bus->subordinate = max; - - return unused; } @@ -953,11 +951,10 @@ static void domain_set_resources(device_t dev) } /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int unused) +static void f15_pci_domain_scan_bus(device_t dev) { struct bus *link = dev->link_list; pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); - return unused; } static struct device_operations pci_domain_ops = { @@ -1011,7 +1008,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1187,7 +1184,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d322fdc..0a1e7d3 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -992,7 +992,7 @@ static void add_more_links(struct device *dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1166,7 +1166,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(struct device *dev) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 08287dc..37b6a8e 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -991,7 +991,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1165,7 +1165,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 7c603c0..9bbc279 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -1008,7 +1008,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1182,7 +1182,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 511d72e..c9ec8cf 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -285,7 +285,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool return link->subordinate; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) +static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; @@ -310,8 +310,6 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned unused) } dev->bus->subordinate = max; - - return unused; } @@ -912,7 +910,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) +static void amdfam10_domain_scan_bus(device_t dev) { u32 reg; int i; @@ -949,7 +947,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 unused) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return unused; } #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) @@ -1214,7 +1211,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1383,7 +1380,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 0d3a6c5..902066c 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -241,7 +241,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ return link->subordinate; } -static unsigned amdk8_scan_chains(device_t dev, unsigned unused) +static void amdk8_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; @@ -268,8 +268,6 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned unused) } dev->bus->subordinate = max; - - return unused; } @@ -1095,7 +1093,7 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 unused) +static void amdk8_domain_scan_bus(device_t dev) { u32 reg; int i; @@ -1131,7 +1129,6 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 unused) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return unused; } static struct device_operations pci_domain_ops = { @@ -1180,7 +1177,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1319,7 +1316,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index e0fc11e..60a1d49 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -985,7 +985,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1176,7 +1176,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 71099d9..8e340ce 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1001,7 +1001,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 passthru) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1187,7 +1187,6 @@ static u32 cpu_bus_scan(device_t dev, u32 passthru) amd_cpu_topology(cpu, i, j); } //j } - return passthru; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c index b37e3cf..a4be7a6 100644 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ b/src/northbridge/intel/i3100/pciexp_porta.c @@ -45,7 +45,7 @@ static void pcie_init(struct device *dev) } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -62,7 +62,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index 31cd29f..f7e3a6a 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -67,7 +67,7 @@ static void pcie_bus_enable_resources(struct device *dev) } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -84,7 +84,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index cb76980..1587268 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -265,9 +265,9 @@ static void amd8131_scan_bus(struct bus *bus, } } -static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max) +static void amd8131_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, amd8131_scan_bus); + do_pci_scan_bridge(dev, amd8131_scan_bus); } diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 48d7c51..027a085 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -194,9 +194,9 @@ static void amd8132_scan_bus(struct bus *bus, amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info); } -static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max) +static void amd8132_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, amd8132_scan_bus); + do_pci_scan_bridge(dev, amd8132_scan_bus); } diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index cece16d..67eabb0 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -688,10 +688,10 @@ static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, }; -static unsigned int scan_lpc_smbus(device_t dev, unsigned int max) +static void scan_lpc_smbus(device_t dev) { /* FIXME. Do we have mixed LPC/SMBus device node here. */ - return scan_smbus(dev, max); + scan_smbus(dev); } static struct device_operations southbridge_ops = { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 42a8578..1b8ac76 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -273,13 +273,12 @@ static void pch_pcie_enable(device_t dev) pch_pcie_pm_early(dev); } -static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) +static void pch_pciexp_scan_bridge(device_t dev) { - unsigned int ret; struct southbridge_intel_bd82x6x_config *config = dev->chip_info; /* Normal PCIe Scan */ - ret = pciexp_scan_bridge(dev, max); + pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); @@ -287,8 +286,6 @@ static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) /* Late Power Management init after bridge device enumeration */ pch_pcie_pm_late(dev); - - return ret; } static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c index 815c081..41e921c 100644 --- a/src/southbridge/intel/i3100/pciexp_portb.c +++ b/src/southbridge/intel/i3100/pciexp_portb.c @@ -39,7 +39,7 @@ static void pcie_init(struct device *dev) { } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -56,7 +56,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index 58c0e19..5858176 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -110,19 +110,16 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) +static void pch_pciexp_scan_bridge(device_t dev) { - unsigned int ret; struct southbridge_intel_i82801ix_config *config = dev->chip_info; /* Normal PCIe Scan */ - ret = pciexp_scan_bridge(dev, max); + pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); } - - return ret; } static struct pci_operations pci_ops = {

1 0

Patch set updated for coreboot: 1d82a82 devicetree: Discriminate device ops scan_bus()
by Kyösti Mälkki 27 May '15

27 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8534 -gerrit commit 1d82a828e8ef0002df78af599d6191f096a8a22d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 26 20:47:47 2015 +0200 devicetree: Discriminate device ops scan_bus() Use of scan_static_bus() and tree traversals is somewhat convoluted. Start cleaning this up by assigning each path type with separate static scan_bus() function. For ME, SMBus and LPC paths a bus cannot expose bridges, as those would add to the number of encountered PCI buses. Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/root_device.c | 84 ++++++++++++++++++------- src/drivers/i2c/i2cmux/i2cmux.c | 7 +-- src/drivers/i2c/i2cmux2/i2cmux2.c | 7 +-- src/include/device/device.h | 3 +- src/mainboard/lippert/frontrunner/devicetree.cb | 6 +- src/northbridge/via/cx700/lpc.c | 2 +- src/northbridge/via/vx800/lpc.c | 2 +- src/northbridge/via/vx900/lpc.c | 2 +- src/northbridge/via/vx900/traf_ctrl.c | 5 +- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/broadwell/smbus.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 2 +- src/southbridge/amd/agesa/hudson/lpc.c | 2 +- src/southbridge/amd/agesa/hudson/sm.c | 2 +- src/southbridge/amd/amd8111/acpi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 2 +- src/southbridge/amd/amd8111/smbus.c | 2 +- src/southbridge/amd/amd8111/usb.c | 2 - src/southbridge/amd/cimx/sb700/late.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/cimx/sb900/late.c | 2 +- src/southbridge/amd/cs5535/cs5535.c | 1 - src/southbridge/amd/cs5536/cs5536.c | 9 ++- src/southbridge/amd/pi/hudson/lpc.c | 2 +- src/southbridge/amd/pi/hudson/sm.c | 2 +- src/southbridge/amd/sb600/lpc.c | 2 +- src/southbridge/amd/sb600/sm.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/sm.c | 2 +- src/southbridge/amd/sb800/lpc.c | 2 +- src/southbridge/amd/sb800/sm.c | 2 +- src/southbridge/broadcom/bcm5785/lpc.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 1 - src/southbridge/intel/bd82x6x/me_8.x.c | 1 - src/southbridge/intel/bd82x6x/smbus.c | 2 +- src/southbridge/intel/esb6300/lpc.c | 2 +- src/southbridge/intel/esb6300/smbus.c | 2 +- src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- src/southbridge/intel/fsp_bd82x6x/me.c | 1 - src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 1 - src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- src/southbridge/intel/fsp_rangeley/smbus.c | 2 +- src/southbridge/intel/i3100/lpc.c | 2 +- src/southbridge/intel/i3100/smbus.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 2 +- src/southbridge/intel/i82371eb/smbus.c | 2 +- src/southbridge/intel/i82801ax/lpc.c | 2 +- src/southbridge/intel/i82801ax/smbus.c | 2 +- src/southbridge/intel/i82801bx/lpc.c | 2 +- src/southbridge/intel/i82801bx/smbus.c | 2 +- src/southbridge/intel/i82801cx/lpc.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 2 +- src/southbridge/intel/i82801ex/lpc.c | 2 +- src/southbridge/intel/i82801ex/smbus.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801gx/smbus.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801ix/smbus.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/ibexpeak/me.c | 1 - src/southbridge/intel/ibexpeak/smbus.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- src/southbridge/intel/lynxpoint/smbus.c | 2 +- src/southbridge/intel/sch/lpc.c | 2 +- src/southbridge/intel/sch/smbus.c | 2 +- src/southbridge/nvidia/ck804/lpc.c | 2 +- src/southbridge/nvidia/ck804/smbus.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 2 +- src/southbridge/rdc/r8610/r8610.c | 1 - src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 6 +- src/superio/smsc/lpc47b397/superio.c | 1 - 77 files changed, 140 insertions(+), 117 deletions(-) diff --git a/src/device/root_device.c b/src/device/root_device.c index 1ec6f7f..0575b56 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -44,51 +44,69 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_ * debug device. Those virtual devices have to be listed in the config * file under some static bus in order to be enumerated at run time. * - * This function is the default scan_bus() method for the root device and - * LPC bridges. - * * @param bus Pointer to the device to which the static buses are attached to. * @param max Maximum bus number currently used before scanning. * @return The largest bus number used. */ -static int smbus_max = 0; -unsigned int scan_static_bus(device_t bus, unsigned int max) + +static unsigned int scan_static_bus(device_t bus, unsigned int max) { device_t child; struct bus *link; - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - for (link = bus->link_list; link; link = link->next) { - /* For SMBus bus enumerate. */ - child = link->children; - - if (child && child->path.type == DEVICE_PATH_I2C) - link->secondary = ++smbus_max; - for (child = link->children; child; child = child->sibling) { + if (child->chip_ops && child->chip_ops->enable_dev) child->chip_ops->enable_dev(child); if (child->ops && child->ops->enable) child->ops->enable(child); - if (child->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(child->bus->dev), - child->bus->link_num); - } printk(BIOS_DEBUG, "%s %s\n", dev_path(child), child->enabled ? "enabled" : "disabled"); } } + return max; +} + +unsigned int scan_lpc_bus(device_t bus, unsigned int max) +{ + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); + + max = scan_static_bus(bus, max); + + printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); + + return max; +} + +unsigned int scan_smbus(device_t bus, unsigned int max) +{ + device_t child; + struct bus *link; + static int smbus_max = 0; + + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); + for (link = bus->link_list; link; link = link->next) { + + link->secondary = ++smbus_max; + for (child = link->children; child; child = child->sibling) { - if (!child->ops || !child->ops->scan_bus) - continue; - printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); - max = scan_bus(child, max); + + if (child->chip_ops && child->chip_ops->enable_dev) + child->chip_ops->enable_dev(child); + + if (child->ops && child->ops->enable) + child->ops->enable(child); + + printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(child->bus->dev), + child->bus->link_num); + + printk(BIOS_DEBUG, "%s %s\n", dev_path(child), + child->enabled ? "enabled" : "disabled"); } } @@ -106,9 +124,27 @@ unsigned int scan_static_bus(device_t bus, unsigned int max) * @param max The current bus number scanned so far, usually 0x00. * @return The largest bus number used. */ -static unsigned int root_dev_scan_bus(device_t root, unsigned int max) +static unsigned int root_dev_scan_bus(device_t bus, unsigned int max) { - return scan_static_bus(root, max); + device_t child; + struct bus *link; + + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); + + max = scan_static_bus(bus, max); + + for (link = bus->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { + if (!child->ops || !child->ops->scan_bus) + continue; + printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); + max = scan_bus(child, max); + } + } + + printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); + + return max; } static void root_dev_reset(struct bus *bus) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index 1091653..ef5ab3a 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -1,10 +1,5 @@ -#include <console/console.h> #include <device/device.h> #include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/x86/msr.h> static void i2cmux_set_link(struct device *dev, unsigned int link) { @@ -21,7 +16,7 @@ static struct device_operations i2cmux_operations = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .set_link = i2cmux_set_link, }; diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index fe48e76..4d1241a 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -1,10 +1,5 @@ -#include <console/console.h> #include <device/device.h> #include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/x86/msr.h> static void i2cmux2_set_link(struct device *dev, unsigned int link) { @@ -20,7 +15,7 @@ static struct device_operations i2cmux2_operations = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .set_link = i2cmux2_set_link, }; diff --git a/src/include/device/device.h b/src/include/device/device.h index 0acebb8..d9fc663 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -224,11 +224,12 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); -unsigned int scan_static_bus(device_t bus, unsigned int _max); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); +unsigned int scan_smbus(device_t bus, unsigned int _max); +unsigned int scan_lpc_bus(device_t bus, unsigned int _max); /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index 78d099a..239f1f9 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -6,10 +6,10 @@ chip northbridge/amd/gx2 end device domain 0 on - device pci 0.0 on end + device pci 0.0 on chip southbridge/amd/cs5535 - register "setupflash" = "0" - device pci 12.0 on + register "setupflash" = "0" + device pci 12.0 on end device pci 12.1 off end # SMI device pci 12.2 on end # IDE device pci 12.3 off end # Audio diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 91a9930..483f19e 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -297,7 +297,7 @@ static struct device_operations cx700_lpc_ops = { .set_resources = cx700_set_resources, .enable_resources = cx700_enable_resources, .init = cx700_lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 00955b0..be39acd 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -362,7 +362,7 @@ static struct device_operations vx800_lpc_ops = { .set_resources = vx800_set_resources, .enable_resources = pci_dev_enable_resources, .init = southbridge_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 61a8a7b..f6c4c6a 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -192,7 +192,7 @@ static struct device_operations vx900_lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index fb15193..011bb41 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -134,8 +134,9 @@ static struct device_operations traf_ctrl_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_traf_ctr_init, - /* Need this here, or the IOAPIC driver won't be called */ - .scan_bus = scan_static_bus, + /* Need this here, or the IOAPIC driver won't be called. + * FIXME: Technically not a LPC bus. */ + .scan_bus = scan_lpc_bus, }; static const struct pci_driver traf_ctrl_driver __pci_driver = { diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 365ac3d..26e0156 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -546,7 +546,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 0acfe78..13c975f 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -643,7 +643,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = &lpc_init, - .scan_bus = &scan_static_bus, + .scan_bus = &scan_lpc_bus, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index e0f9b8a..5660a41 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -94,7 +94,7 @@ static struct device_operations smbus_ops = { .read_resources = &smbus_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_static_bus, + .scan_bus = &scan_smbus, .init = &pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &broadwell_pci_ops, diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 44127ee..ac80478 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -607,7 +607,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index f3a525c..65cb955 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -333,7 +333,7 @@ static struct device_operations lpc_ops = { #endif .enable_resources = hudson_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index fd8e6ad..09fbf8b 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -163,7 +163,7 @@ static struct device_operations smbus_ops = { .set_resources = hudson_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 6d0ce26..396b7c4 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -226,7 +226,7 @@ static struct device_operations acpi_ops = { .set_resources = pci_dev_set_resources, .enable_resources = acpi_enable_resources, .init = acpi_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, /* We don't need amd8111_enable, chip ops takes care of it. * It could be useful if these devices were not * enabled by default. diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 2ded0cb..47b9ae7 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -151,7 +151,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = amd8111_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c index 0a0c58d..def1377 100644 --- a/src/southbridge/amd/amd8111/smbus.c +++ b/src/southbridge/amd/amd8111/smbus.c @@ -28,7 +28,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = amd8111_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c index 13dccf4..feb7793 100644 --- a/src/southbridge/amd/amd8111/usb.c +++ b/src/southbridge/amd/amd8111/usb.c @@ -25,8 +25,6 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, -// .enable = amd8111_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 4254a5c..cd36fac 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -111,7 +111,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 79c2203..0ada673 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -161,7 +161,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 7249ec5..fbff7df 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -132,7 +132,7 @@ static struct device_operations lpc_ops = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index e66a1e2..70b8386 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -94,7 +94,6 @@ static struct device_operations southbridge_ops = { .enable_resources = pci_dev_enable_resources, .init = southbridge_init, .enable = southbridge_enable, - .scan_bus = scan_static_bus, }; static const struct pci_driver cs5535_pci_driver __pci_driver = { diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 0db8195..cece16d 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -688,13 +688,18 @@ static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, }; +static unsigned int scan_lpc_smbus(device_t dev, unsigned int max) +{ + /* FIXME. Do we have mixed LPC/SMBus device node here. */ + return scan_smbus(dev, max); +} + static struct device_operations southbridge_ops = { .read_resources = cs5536_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = southbridge_init, -// .enable = southbridge_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_smbus, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 840ff7a..b813d12 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -340,7 +340,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index fd8e6ad..09fbf8b 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -163,7 +163,7 @@ static struct device_operations smbus_ops = { .set_resources = hudson_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 62c88de..2fb9e22 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -242,7 +242,7 @@ static struct device_operations lpc_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, /* .enable = sb600_enable, */ .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c index 0254f83..40fde47 100644 --- a/src/southbridge/amd/sb600/sm.c +++ b/src/southbridge/amd/sb600/sm.c @@ -361,7 +361,7 @@ static struct device_operations smbus_ops = { .set_resources = sb600_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, /* .enable = sb600_enable, */ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index be3c4d6..94d8dcb 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -287,7 +287,7 @@ static struct device_operations lpc_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 2a88a80..f544c88 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -452,7 +452,7 @@ static struct device_operations smbus_ops = { .set_resources = sb700_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 5a40a8d..0cd5b32 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -254,7 +254,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index b34cfbd..1523c60 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -343,7 +343,7 @@ static struct device_operations smbus_ops = { .set_resources = sb800_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index 28e8a8f..ef70df6 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -135,7 +135,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = bcm5785_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = bcm5785_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index bddb090..3390b0d 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -154,7 +154,7 @@ static struct device_operations sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sb_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, // .enable = bcm5785_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 19b4757..192de74 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -619,7 +619,7 @@ static struct device_operations vortex_sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = 0, .ops_pci = 0, }; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0ecd389..5e249ca 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -855,7 +855,7 @@ static struct device_operations device_ops = { .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index ed25e44..ab3d475 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -760,7 +760,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 75e517f..6bd26c4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -763,7 +763,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 94546a7..0198841 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -151,7 +151,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index 22bb150..e1718bb 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -362,7 +362,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = esb6300_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = esb6300_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/esb6300/smbus.c b/src/southbridge/intel/esb6300/smbus.c index 92cb288..2c026b8 100644 --- a/src/southbridge/intel/esb6300/smbus.c +++ b/src/southbridge/intel/esb6300/smbus.c @@ -35,7 +35,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = esb6300_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e707afa..d9dd38c 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -796,7 +796,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index ab6ae09..8f65da3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -759,7 +759,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 5e7b661..292dbba 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -762,7 +762,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 3aee7ed..22de62d 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -463,7 +463,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .enable = soc_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c index 8368afe..7864b1e 100644 --- a/src/southbridge/intel/fsp_rangeley/smbus.c +++ b/src/southbridge/intel/fsp_rangeley/smbus.c @@ -87,7 +87,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, }; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index b29180c..aef855f 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -457,7 +457,7 @@ static struct device_operations lpc_ops = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i3100_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c index 445b668..2feb00f 100644 --- a/src/southbridge/intel/i3100/smbus.c +++ b/src/southbridge/intel/i3100/smbus.c @@ -74,7 +74,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i3100_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 1945fae..024604b 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -145,7 +145,7 @@ static const struct device_operations isa_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = isa_init, - .scan_bus = scan_static_bus, /* TODO: Needed? */ + .scan_bus = scan_lpc_bus, /* TODO: Needed? */ .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 82647e1..3817357 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -121,7 +121,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = pwrmgt_enable, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 4bd69d6..e960551 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -286,7 +286,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801ax_enable, }; diff --git a/src/southbridge/intel/i82801ax/smbus.c b/src/southbridge/intel/i82801ax/smbus.c index cbe9e4a..76a78d1 100644 --- a/src/southbridge/intel/i82801ax/smbus.c +++ b/src/southbridge/intel/i82801ax/smbus.c @@ -48,7 +48,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801ax_enable, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index edadf40..7247cdc 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -304,7 +304,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801bx_enable, }; diff --git a/src/southbridge/intel/i82801bx/smbus.c b/src/southbridge/intel/i82801bx/smbus.c index 8feb75b..836c256 100644 --- a/src/southbridge/intel/i82801bx/smbus.c +++ b/src/southbridge/intel/i82801bx/smbus.c @@ -48,7 +48,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801bx_enable, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index 22671c3..a348c95 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -230,7 +230,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = 0, }; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 9f2a23f..29a457a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -336,7 +336,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 0a2f6e3..630484a 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -369,7 +369,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = i82801ex_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801ex_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c index fe49e11..75ea119 100644 --- a/src/southbridge/intel/i82801ex/smbus.c +++ b/src/southbridge/intel/i82801ex/smbus.c @@ -35,7 +35,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801ex_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ccaabba..9480c80 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -644,7 +644,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801gx_enable, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 585d16c..e556d72 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -258,7 +258,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801gx_enable, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index de936a3..309b161 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -576,7 +576,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index 635cb19..9ae267d 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -101,7 +101,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index c33f9d9..724814d 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -843,7 +843,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index e68bb01..96e16e3 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -634,7 +634,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 085aec0..2bb4cbf 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -108,7 +108,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b2a522..15a79f8 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -828,7 +828,7 @@ static struct device_operations device_ops = { .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index ae16a92..b7c8503 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -155,7 +155,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index f06c149..d8bd5f4 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -216,7 +216,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/sch/smbus.c b/src/southbridge/intel/sch/smbus.c index d208fcc..c3bff67 100644 --- a/src/southbridge/intel/sch/smbus.c +++ b/src/southbridge/intel/sch/smbus.c @@ -65,7 +65,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, }; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index c6f8c24..406b4f2 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -329,7 +329,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &ck804_pci_ops, }; diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index f5fa1d5..2803df0 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -96,7 +96,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &ck804_pci_ops, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index d9c6211..d3399f3 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -261,7 +261,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 91d5830..2a56069 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -127,7 +127,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = mcp55_sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/rdc/r8610/r8610.c b/src/southbridge/rdc/r8610/r8610.c index 338a133..328f3be 100644 --- a/src/southbridge/rdc/r8610/r8610.c +++ b/src/southbridge/rdc/r8610/r8610.c @@ -105,7 +105,6 @@ static struct device_operations r8610_sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, - .scan_bus = scan_static_bus, .enable = 0, .ops_pci = 0, }; diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 9194420..e5eaa06 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -259,7 +259,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = sis966_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = sis966_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index ebaaa04..f7f2dbe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -657,7 +657,7 @@ static const struct device_operations vt8237r_lpc_ops_s = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237s_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; @@ -666,7 +666,7 @@ static const struct device_operations vt8237r_lpc_ops_r = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237r_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; @@ -675,7 +675,7 @@ static const struct device_operations vt8237r_lpc_ops_a = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237a_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 8c7d70f..a9a8092 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -134,7 +134,6 @@ static struct device_operations ops_hwm = { .enable_resources = lpc47b397_pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b397_init, - .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, .ops_pnp_mode = &pnp_conf_mode_55_aa, };

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coreboot-gerrit May 2015