coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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1299 discussions

New patch to review for coreboot: d569655 h8: Add missing include of types.h
by Vladimir Serbinenko 27 May '15

27 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10330 -gerrit commit d56965578350bcdc9c534ab22ef7db1f50a764d8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 27 09:57:35 2015 +0200 h8: Add missing include of types.h h8.h uses u8 without including types.h. Change-Id: I7e46f6b8ca92ed23af93597fe2f08add464eb176 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/h8.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index ab56b7d..33139dc 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -20,6 +20,8 @@ #ifndef EC_LENOVO_H8_H #define EC_LENOVO_H8_H +#include <types.h> + void h8_trackpoint_enable(int on); void h8_wlan_enable(int on); void h8_set_audio_mute(int on);

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New patch to review for coreboot: 078c187 intel: Remove pstate_coord_type.
by Vladimir Serbinenko 27 May '15

27 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10329 -gerrit commit 078c187eab60676418c33515c4ca1c53d517d0ba Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 27 21:07:09 2015 +0200 intel: Remove pstate_coord_type. Not used anywhere. Change-Id: I9bab092d285aaebdf9283ba08e23197f9785b3a6 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/chip.h | 2 -- src/cpu/intel/fsp_model_406dx/chip.h | 2 -- src/cpu/intel/haswell/chip.h | 2 -- src/cpu/intel/model_2065x/chip.h | 2 -- src/cpu/intel/model_206ax/chip.h | 2 -- src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 1 - src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb | 1 - src/mainboard/google/butterfly/devicetree.cb | 3 --- src/mainboard/google/link/devicetree.cb | 3 --- src/mainboard/google/parrot/devicetree.cb | 3 --- src/mainboard/google/stout/devicetree.cb | 3 --- src/mainboard/kontron/ktqm77/devicetree.cb | 3 --- src/mainboard/lenovo/t420s/devicetree.cb | 3 --- src/mainboard/lenovo/t430s/devicetree.cb | 3 --- src/mainboard/lenovo/t520/devicetree.cb | 3 --- src/mainboard/lenovo/t530/devicetree.cb | 3 --- src/mainboard/lenovo/x220/devicetree.cb | 3 --- src/mainboard/lenovo/x230/devicetree.cb | 3 --- src/mainboard/samsung/lumpy/devicetree.cb | 3 --- 19 files changed, 48 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/chip.h b/src/cpu/intel/fsp_model_206ax/chip.h index 3041c53..759a74c 100644 --- a/src/cpu/intel/fsp_model_206ax/chip.h +++ b/src/cpu/intel/fsp_model_206ax/chip.h @@ -23,8 +23,6 @@ struct cpu_intel_fsp_model_206ax_config { u8 disable_acpi; /* Do not generate CPU ACPI tables */ - u8 pstate_coord_type; /* Processor Coordination Type */ - int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ int c3_battery; /* ACPI C3 on Battery Power */ diff --git a/src/cpu/intel/fsp_model_406dx/chip.h b/src/cpu/intel/fsp_model_406dx/chip.h index 155c00c..a59e403 100644 --- a/src/cpu/intel/fsp_model_406dx/chip.h +++ b/src/cpu/intel/fsp_model_406dx/chip.h @@ -24,8 +24,6 @@ #define SPEEDSTEP_APIC_MAGIC 0xACAC struct cpu_intel_fsp_model_406dx_config { - u8 pstate_coord_type; /* Processor Coordination Type */ - int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ int c3_battery; /* ACPI C3 on Battery Power */ diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 92823a6..89d168d 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -25,8 +25,6 @@ extern struct chip_operations cpu_intel_haswell_ops; struct cpu_intel_haswell_config { u8 disable_acpi; /* Do not generate CPU ACPI tables */ - u8 pstate_coord_type; /* Processor Coordination Type */ - int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ int c3_battery; /* ACPI C3 on Battery Power */ diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h index f677611..550d478 100644 --- a/src/cpu/intel/model_2065x/chip.h +++ b/src/cpu/intel/model_2065x/chip.h @@ -23,8 +23,6 @@ struct cpu_intel_model_2065x_config { u8 disable_acpi; /* Do not generate CPU ACPI tables */ - u8 pstate_coord_type; /* Processor Coordination Type */ - int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ int c3_battery; /* ACPI C3 on Battery Power */ diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 10bca53..c690d52 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -23,8 +23,6 @@ struct cpu_intel_model_206ax_config { u8 disable_acpi; /* Do not generate CPU ACPI tables */ - u8 pstate_coord_type; /* Processor Coordination Type */ - int c1_battery; /* ACPI C1 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */ int c3_battery; /* ACPI C3 on Battery Power */ diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 3c7641a..a3b8675 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -4,7 +4,6 @@ chip northbridge/intel/sandybridge device lapic 0 on end end chip cpu/intel/model_206ax - register "pstate_coord_type" = "0xfe" register "c1_acpower" = "1" register "c2_acpower" = "3" register "c3_acpower" = "5" diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb index 1c08359..10db86b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb @@ -4,7 +4,6 @@ chip northbridge/intel/sandybridge device lapic 0 on end end chip cpu/intel/model_206ax - register "pstate_coord_type" = "0xfe" register "c1_acpower" = "1" register "c2_acpower" = "3" register "c3_acpower" = "5" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 90925b9..26baf41 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -22,9 +22,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 5333dfc..380f1c5 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -23,9 +23,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index a4baafd..54fd51b 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -23,9 +23,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 4ac89f6..68e53a8 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -19,9 +19,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "tcc_offset" = "5" # TCC of 95C register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 855fd5c..396450b 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -8,9 +8,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" # TODO: This is never read. - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "0" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 7fd6a53..0776fa1 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -25,9 +25,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index af3de6c..5d5c73f 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -25,9 +25,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index bf575d8..7642a8f 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -25,9 +25,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index d59524b..3550ede 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -25,9 +25,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 6eb3b15..75dae99 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -25,9 +25,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index c8274e2..cc51b1a 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -25,9 +25,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 0372614..a3733b5 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -19,9 +19,6 @@ chip northbridge/intel/sandybridge # Magic APIC ID to locate this chip device lapic 0xACAC off end - # Coordinate with HW_ALL - register "pstate_coord_type" = "0xfe" - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)

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New patch to review for coreboot: 1bfc7ac board-status: Don't consider Kconfig.name a valid mainboard.
by Vladimir Serbinenko 27 May '15

27 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10328 -gerrit commit 1bfc7ac6ed6740a071be56f7a89f3b65f21b70ab Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 27 18:53:12 2015 +0200 board-status: Don't consider Kconfig.name a valid mainboard. Change-Id: Ibc06b17f48f72d5f9931437ffce020023ece2445 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 3e80d44..f1a6bd5 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -144,7 +144,7 @@ EOF for vendor_board_dir in "$COREBOOT_DIR"/src/mainboard/*/* ; do board="$(basename "$vendor_board_dir")" vendor="$(basename "$(dirname "$vendor_board_dir")")" - if [ "$board" = Kconfig ]; then + if [ "$board" = Kconfig ] || [ "$board" = Kconfig.name ]; then continue fi

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New patch to review for coreboot: 43bba8e tpm: Add dummy _DSM to make Bitlocker happy.
by Vladimir Serbinenko 27 May '15

27 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10323 -gerrit commit 43bba8e7c70a7016658490da6bfe19ae0882242f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri May 22 08:01:37 2015 +0200 tpm: Add dummy _DSM to make Bitlocker happy. Change-Id: Ieb6f70f5b2863336bd6143b2dfbb1d67c4c26109 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/pc80/tpm/acpi/tpm.asl | 84 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl index 0562f2a..c55a165 100644 --- a/src/drivers/pc80/tpm/acpi/tpm.asl +++ b/src/drivers/pc80/tpm/acpi/tpm.asl @@ -101,4 +101,88 @@ Device (TPM) Return (RBUF) } } + + /* Dummy _DSM to make Bitlocker work. */ + Method (_DSM, 4, Serialized) + { + /* Physical presence interface. Just a dummy. */ + If (LEqual (Arg0, ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653"))) + { + If (LEqual (Arg2, 0)) + { + /* Functions 1-8. */ + Return (Buffer (2) { 0xFF, 0x01 }) + } + + /* Interface version: 1.2 */ + If (LEqual (Arg2, 1)) + { + Return ("1.2") + } + + /* Submit operations: drop on the floor and return success. */ + If (LEqual (Arg2, 2)) + { + Return (0x00) + } + + /* Pending operation: none. */ + If (LEqual (Arg2, 3)) + { + Return (Package (2) { 0, 0 }) + } + + /* Pre-OS transition method: reboot. */ + If (LEqual (Arg2, 4)) + { + Return (2) + } + + /* Operation response: no operation executed. */ + If (LEqual (Arg2, 5)) + { + Return (Package (3) { 0, 0, 0 }) + } + + /* Set preffered user language: deprecated and must return 3 aka "not implemented". */ + If (LEqual (Arg2, 6)) + { + Return (3) + } + + /* Submit operations: deny. */ + If (LEqual (Arg2, 7)) + { + Return (3) + } + + /* All actions are forbidden. */ + If (LEqual (Arg2, 8)) + { + Return (1) + } + + Return (1) + } + + /* Memory clearing on boot: just a dummy. */ + If (LEqual (Arg0, ToUUID("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + If (LEqual (Arg2, 0)) + { + /* Function 1. */ + Return (Buffer (1) { 3 }) + } + + /* Just return success. */ + If (LEqual (Arg2, 1)) + { + Return (0) + } + + Return (1) + } + + Return (Buffer (1) { 0 }) + } }

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Patch set updated for coreboot: c256f84 Add TCPA table.
by Vladimir Serbinenko 27 May '15

27 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10274 -gerrit commit c256f845558eab72a8bcc32d4ed92cea6f61466c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 20 19:52:01 2015 +0200 Add TCPA table. This allows SeaBIOS to fill it as necessarry. This is needed to make BitLocker work. Change-Id: I35858cd31a90c799ee1a240547c4b4a80fa13dd8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 65 ++++++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 7 +++++ src/include/cbmem.h | 1 + 3 files changed, 73 insertions(+) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 48260fc..a7a638f 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -250,6 +250,61 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg) header->checksum = acpi_checksum((void *)mcfg, header->length); } +static void *get_tcpa_log(u32 *size) +{ + const struct cbmem_entry *ce; + const u32 tcpa_default_log_len = 0x10000; + void *lasa; + ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); + if (ce) { + lasa = cbmem_entry_start(ce); + *size = cbmem_entry_size(ce); + printk(BIOS_DEBUG, "TCPA log found at %p\n", lasa); + return lasa; + } + lasa = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_default_log_len); + if (!lasa) { + printk(BIOS_ERR, "TCPA log creation failed\n"); + return NULL; + } + + printk(BIOS_DEBUG, "TCPA log created at %p\n", lasa); + memset (lasa, 0, tcpa_default_log_len); + + *size = tcpa_default_log_len; + return lasa; +} + +static void acpi_create_tcpa(acpi_tcpa_t *tcpa) +{ + acpi_header_t *header = &(tcpa->header); + u32 tcpa_log_len; + void *lasa; + + memset((void *)tcpa, 0, sizeof(acpi_tcpa_t)); + + lasa = get_tcpa_log(&tcpa_log_len); + if (!lasa) { + return; + } + + /* Fill out header fields. */ + memcpy(header->signature, "TCPA", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_tcpa_t); + header->revision = 2; + + tcpa->platform_class = 0; + tcpa->laml = tcpa_log_len; + tcpa->lasa = (u32) lasa; + + /* Calculate checksum. */ + header->checksum = acpi_checksum((void *)tcpa, header->length); +} + void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); @@ -688,6 +743,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *ssdt; acpi_header_t *dsdt; acpi_mcfg_t *mcfg; + acpi_tcpa_t *tcpa; acpi_madt_t *madt; struct device *dev; unsigned long fw; @@ -805,6 +861,15 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, mcfg); } + printk(BIOS_DEBUG, "ACPI: * TCPA\n"); + tcpa = (acpi_tcpa_t *) current; + acpi_create_tcpa(tcpa); + if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { + current += tcpa->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, tcpa); + } + printk(BIOS_DEBUG, "ACPI: * MADT\n"); madt = (acpi_madt_t *) current; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 245599f..10db820 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -129,6 +129,13 @@ typedef struct acpi_mcfg { u8 reserved[8]; } __attribute__ ((packed)) acpi_mcfg_t; +typedef struct acpi_tcpa { + struct acpi_table_header header; + u16 platform_class; + u32 laml; + u64 lasa; +} __attribute__ ((packed)) acpi_tcpa_t; + typedef struct acpi_mcfg_mmconfig { u32 base_address; u32 base_reserved; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5fd67af..afee873 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -79,6 +79,7 @@ #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 +#define CBMEM_ID_TCPA_LOG 0x54435041 #ifndef __ASSEMBLER__ #include <stddef.h>

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Patch merged into coreboot/master: ce58a4e Deactivate TPM
by gerrit＠coreboot.org 27 May '15

27 May '15

the following patch was just integrated into master: commit ce58a4e0021eb1b1bb6ab26bdb3bbbff26a5ad83 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:46:57 2015 +0200 Deactivate TPM Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10270 for details. -gerrit

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Patch set updated for coreboot: 1209362 Deactivate TPM
by Vladimir Serbinenko 27 May '15

27 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10270 -gerrit commit 120936208fdfdf34a41ae0c8d4e2b0e1654e0fff Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:46:57 2015 +0200 Deactivate TPM Just not exporting TPM isn't good enough as it can still be accessed. You need to send it a deactivate command. Change-Id: I3eb84660949c2d1e2b492d541e01d4ba78037630 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/pc80/tpm/Kconfig | 7 +++++++ src/drivers/pc80/tpm/acpi/tpm.asl | 10 +++++----- src/drivers/pc80/tpm/romstage.c | 19 +++++++++++++++++++ 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index fc9270b..1483871 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -37,3 +37,10 @@ config SKIP_TPM_STARTUP_ON_NORMAL_BOOT depends on LPC_TPM help Skip TPM init on normal boot. Useful if payload does TPM init. + +config TPM_DEACTIVATE + bool "Deactivate TPM" + default n + depends on LPC_TPM + help + Deactivate TPM by issuing deactivate command. diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl index 30b14ce..0562f2a 100644 --- a/src/drivers/pc80/tpm/acpi/tpm.asl +++ b/src/drivers/pc80/tpm/acpi/tpm.asl @@ -27,11 +27,11 @@ Device (TPM) Method (_STA, 0) { - If (CONFIG_LPC_TPM) { - Return (0xf) - } Else { - Return (0x0) - } +#if CONFIG_LPC_TPM && !CONFIG_TPM_DEACTIVATE + Return (0xf) +#else + Return (0x0) +#endif } Name (IBUF, ResourceTemplate () diff --git a/src/drivers/pc80/tpm/romstage.c b/src/drivers/pc80/tpm/romstage.c index 5e29e3a..96760e2 100644 --- a/src/drivers/pc80/tpm/romstage.c +++ b/src/drivers/pc80/tpm/romstage.c @@ -51,6 +51,12 @@ static const struct { }; static const struct { + u8 buffer[12]; +} tpm_deactivate_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x3 } +}; + +static const struct { u8 buffer[10]; } tpm_continueselftest_cmd = { { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } @@ -181,6 +187,19 @@ void init_tpm(int s3resume) u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + if (CONFIG_TPM_DEACTIVATE) { + printk(BIOS_SPEW, "TPM: Deactivate\n"); + result = TlclSendReceive(tpm_deactivate_cmd.buffer, + response, sizeof(response)); + if (result == TPM_SUCCESS) { + printk(BIOS_SPEW, "TPM: OK.\n"); + return; + } + + printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); + return; + } + /* Doing TPM startup when we're not coming in on the S3 resume path * saves us roughly 20ms in boot time only. This does not seem to * be worth an API change to vboot_reference-firmware right now, so

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Patch merged into coreboot/master: a93c014 x201: Add TPM declaration.
by gerrit＠coreboot.org 27 May '15

27 May '15

the following patch was just integrated into master: commit a93c0143ac79f937f774b99e4afedee6a20eb5d3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu May 21 09:28:14 2015 +0200 x201: Add TPM declaration. This allows to deactivate TPM on X201. Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10278 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> See http://review.coreboot.org/10278 for details. -gerrit

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Patch merged into coreboot/master: 61273d4 x230: Add TPM declaration.
by gerrit＠coreboot.org 27 May '15

27 May '15

the following patch was just integrated into master: commit 61273d46197b724598b6a579951a03321a2789c9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 13 17:47:58 2015 +0200 x230: Add TPM declaration. This allows to deactivate TPM on X230. Change-Id: I73d4272da62335ec3766ce4814d5b46538b190fe Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10273 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> See http://review.coreboot.org/10273 for details. -gerrit

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Patch merged into coreboot/master: ed54cc7 sandybridge native: Add call to TPM code.
by gerrit＠coreboot.org 27 May '15

27 May '15

the following patch was just integrated into master: commit ed54cc707b77385af69c1854d64447078a0ddc9a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 10:31:35 2015 +0200 sandybridge native: Add call to TPM code. This allows to deactivate TPM on boards using native sandy/ivy init. Change-Id: I9455179c7b51097a3a9554c16a407365fbc65e6f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10272 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> See http://review.coreboot.org/10272 for details. -gerrit

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