coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 58b7524 DO NOT MERGE: Cyan configuration file
by Leroy P Leahy 28 May '15

28 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10319 -gerrit commit 58b752486ba005048d92c68681ffbc67f07f692a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue May 26 15:27:44 2015 -0700 DO NOT MERGE: Cyan configuration file Add .config file to build for cyan BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: Ic3a3a08f4d86ab1199f22418f2956f6a4b5de0fd Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- .config | 64 ++++++++++++++++++++++++++++++++++++++++------------------------ 1 file changed, 40 insertions(+), 24 deletions(-) diff --git a/.config b/.config index be10bc1..fc5afab 100644 --- a/.config +++ b/.config @@ -66,12 +66,12 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set -# CONFIG_VENDOR_GOOGLE is not set +CONFIG_VENDOR_GOOGLE=y # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set -CONFIG_VENDOR_INTEL=y +# CONFIG_VENDOR_INTEL is not set # CONFIG_VENDOR_IWAVE is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set @@ -104,9 +104,9 @@ CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_WINENT is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y -CONFIG_MAINBOARD_DIR="intel/strago" -CONFIG_MAINBOARD_PART_NUMBER="Strago" -CONFIG_MAINBOARD_VENDOR="Intel" +CONFIG_MAINBOARD_DIR="google/cyan" +CONFIG_MAINBOARD_PART_NUMBER="Cyan" +CONFIG_MAINBOARD_VENDOR="Google" CONFIG_MAX_CPUS=4 CONFIG_VGA_BIOS_ID="8086,22b0" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set @@ -126,22 +126,42 @@ CONFIG_UART_FOR_CONSOLE=0 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y +# CONFIG_BOARD_GOOGLE_BOLT is not set +# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set +# CONFIG_BOARD_GOOGLE_COSMOS is not set +CONFIG_BOARD_GOOGLE_CYAN=y +# CONFIG_BOARD_GOOGLE_DAISY is not set +# CONFIG_BOARD_GOOGLE_FALCO is not set +# CONFIG_BOARD_GOOGLE_LINK is not set +# CONFIG_BOARD_GOOGLE_NYAN_BIG is not set +# CONFIG_BOARD_GOOGLE_NYAN_BLAZE is not set +# CONFIG_BOARD_GOOGLE_NYAN is not set +# CONFIG_BOARD_GOOGLE_PANTHER is not set +# CONFIG_BOARD_GOOGLE_PARROT is not set +# CONFIG_BOARD_GOOGLE_PEACH_PIT is not set +# CONFIG_BOARD_GOOGLE_PEPPY is not set +# CONFIG_BOARD_GOOGLE_PURIN is not set +# CONFIG_BOARD_GOOGLE_RAMBI is not set +# CONFIG_BOARD_GOOGLE_RUSH is not set +# CONFIG_BOARD_GOOGLE_RUSH_RYU is not set +# CONFIG_BOARD_GOOGLE_SAMUS is not set +# CONFIG_BOARD_GOOGLE_SLIPPY is not set +# CONFIG_BOARD_GOOGLE_STORM is not set +# CONFIG_BOARD_GOOGLE_STOUT is not set +# CONFIG_BOARD_GOOGLE_URARA is not set +# CONFIG_BOARD_GOOGLE_VEYRON_BRAIN is not set +# CONFIG_BOARD_GOOGLE_VEYRON_DANGER is not set +# CONFIG_BOARD_GOOGLE_VEYRON_JERRY is not set +# CONFIG_BOARD_GOOGLE_VEYRON_MIGHTY is not set +# CONFIG_BOARD_GOOGLE_VEYRON_PINKY is not set +# CONFIG_BOARD_GOOGLE_VEYRON_RIALTO is not set +# CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY is not set CONFIG_BOOT_MEDIA_SPI_BUS=0 +# CONFIG_DISPLAY_SPD_DATA is not set +# CONFIG_DYNAMIC_VNN_SUPPORT is not set +CONFIG_VBOOT_RAMSTAGE_INDEX=0x2 +CONFIG_VBOOT_REFCODE_INDEX=0x3 CONFIG_TTYS0_LCS=3 -# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set -# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set -# CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set -# CONFIG_BOARD_INTEL_COUGAR_CANYON2 is not set -# CONFIG_BOARD_INTEL_D810E2CB is not set -# CONFIG_BOARD_INTEL_D945GCLF is not set -# CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set -# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set -# CONFIG_BOARD_INTEL_MINNOWMAX is not set -# CONFIG_BOARD_INTEL_MOHONPEAK is not set -# CONFIG_BOARD_INTEL_MTARVON is not set -CONFIG_BOARD_INTEL_STRAGO=y -# CONFIG_BOARD_INTEL_TRUXTON is not set -# CONFIG_BOARD_INTEL_WTM2 is not set # CONFIG_LOCK_MANAGEMENT_ENGINE is not set CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x100000 CONFIG_FSP_FILE="3rdparty/mainboard/$(MAINBOARDDIR)/fsp/BSWFSP.fd" @@ -150,10 +170,6 @@ CONFIG_VIRTUAL_ROM_SIZE=0x800000 CONFIG_POST_IO=y CONFIG_POST_DEVICE=y CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y -# CONFIG_DISPLAY_SPD_DATA is not set -# CONFIG_DYNAMIC_VNN_SUPPORT is not set -CONFIG_VBOOT_RAMSTAGE_INDEX=0x2 -CONFIG_VBOOT_REFCODE_INDEX=0x3 CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_MAINBOARD_VERSION="1.0" @@ -496,7 +512,7 @@ CONFIG_HAVE_ACPI_TABLES=y # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Strago" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Cyan" # # Payload

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Patch set updated for coreboot: 0ed13fe mainboard/google/cyan: Cyan board support
by Leroy P Leahy 28 May '15

28 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10182 -gerrit commit 0ed13feee654571451837f3bd77288f3b65a87ac Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 11 17:24:31 2015 -0700 mainboard/google/cyan: Cyan board support Add initial files for the cyan board. BRANCH=none BUG=None Test=Build and run on cyan Change-Id: I935839be033c25e197e78fbee306104b4162a99a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/google/cyan/Kconfig | 62 +++++ src/mainboard/google/cyan/Kconfig.name | 2 + src/mainboard/google/cyan/Makefile.inc | 33 +++ src/mainboard/google/cyan/acpi/chromeos.asl | 37 +++ src/mainboard/google/cyan/acpi/dptf.asl | 93 +++++++ src/mainboard/google/cyan/acpi/ec.asl | 25 ++ src/mainboard/google/cyan/acpi/mainboard.asl | 266 +++++++++++++++++++++ src/mainboard/google/cyan/acpi/superio.asl | 34 +++ src/mainboard/google/cyan/acpi_tables.c | 69 ++++++ src/mainboard/google/cyan/chromeos.c | 142 +++++++++++ src/mainboard/google/cyan/cmos.layout | 140 +++++++++++ src/mainboard/google/cyan/com_init.c | 48 ++++ src/mainboard/google/cyan/devicetree.cb | 139 +++++++++++ src/mainboard/google/cyan/dsdt.asl | 58 +++++ src/mainboard/google/cyan/ec.c | 55 +++++ src/mainboard/google/cyan/ec.h | 69 ++++++ src/mainboard/google/cyan/fadt.c | 51 ++++ src/mainboard/google/cyan/gpio.c | 266 +++++++++++++++++++++ src/mainboard/google/cyan/irqroute.c | 23 ++ src/mainboard/google/cyan/irqroute.h | 64 +++++ src/mainboard/google/cyan/mainboard.c | 27 +++ src/mainboard/google/cyan/onboard.h | 81 +++++++ src/mainboard/google/cyan/ramstage.c | 26 ++ src/mainboard/google/cyan/romstage.c | 48 ++++ src/mainboard/google/cyan/smihandler.c | 166 +++++++++++++ src/mainboard/google/cyan/spd/Makefile.inc | 42 ++++ .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 +++ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 +++ src/mainboard/google/cyan/spd/spd.c | 115 +++++++++ src/mainboard/google/cyan/w25q64.c | 75 ++++++ 31 files changed, 2352 insertions(+) diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig new file mode 100644 index 0000000..dd4543c --- /dev/null +++ b/src/mainboard/google/cyan/Kconfig @@ -0,0 +1,62 @@ +if BOARD_GOOGLE_CYAN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ALWAYS_LOAD_OPROM + select BOARD_ROMSIZE_KB_8192 +# select ENABLE_BUILTIN_COM1 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_BRASWELL + select VIRTUAL_DEV_SWITCH + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory configuration data. + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory SPD data. + +config DYNAMIC_VNN_SUPPORT + bool "Enables support for Dynamic VNN" + default n + +config MAINBOARD_DIR + string + default google/cyan + +config MAINBOARD_PART_NUMBER + string + default "Cyan" + +config MAINBOARD_VENDOR + string + default "Google" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +if !CONFIG_GOP_SUPPORT +config VGA_BIOS_FILE + string + default "3rdparty/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT + default "3rdparty/mainboard/intel/strago/vgabios.bin" if !C0_DISP_SUPPORT + +config VGA_BIOS_ID + string + default "8086,22b1" if C0_DISP_SUPPORT + default "8086,22b0" if !C0_DISP_SUPPORT +endif + +endif # BOARD_GOOGLE_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name new file mode 100644 index 0000000..a4562d3 --- /dev/null +++ b/src/mainboard/google/cyan/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_CYAN + bool "Cyan" diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc new file mode 100755 index 0000000..f1b501f --- /dev/null +++ b/src/mainboard/google/cyan/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += spd + +romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += irqroute.c +ramstage-y += ramstage.c +ramstage-y += w25q64.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl new file mode 100644 index 0000000..04edefa --- /dev/null +++ b/src/mainboard/google/cyan/acpi/chromeos.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: We need to encode gpios within the 3 separate banks + * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded + * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. + */ + +Name(OIPG, Package() { + /* No physical recovery button */ + Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, + Package () { 0x0003, 1, 0x2006, "Braswell" }, +}) diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl new file mode 100755 index 0000000..67bdbb4 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/braswell/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl new file mode 100644 index 0000000..5736c27 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/cyan/ec.h> + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl new file mode 100755 index 0000000..831453d --- /dev/null +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <mainboard/google/cyan/onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + +Scope (\_SB.I2C1) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen ") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x10, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { CYAN_TOUCH_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.I2C2) +{ + /* Maxim Audio Codec */ + Device (MAXM) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } + Device (TISW) /* TI Switch driver I2C */ + { + Name (_ADR, 0) + Name (_HID, TI_SWITCH_HID) + Name (_CID, TI_SWITCH_CID) + Name (_DDN, TI_SWITCH_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { CYAN_JACK_TI_GPIO_INDEX } + + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + } +} + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C5", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C6", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_TRACKPAD_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX } + }) +} + +Scope (\_SB.GPNC) +{ + Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_SCI_GPIO_INDEX } + }) + Return (RBUF) + } + + Method (_E0F, 0, NotSerialized) // _Exx: Edge-Triggered GPE + { + } +} diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl new file mode 100755 index 0000000..018fdb0 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/cyan/ec.h> +#include <mainboard/google/cyan/onboard.h> + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Override default IRQ settings */ +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\ + BOARD_I8042_IRQ} + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c new file mode 100755 index 0000000..3c2a7ba --- /dev/null +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <string.h> +#include <types.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 1; + + /* Enable DPTF */ + gnvs->dpte = 1; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c new file mode 100644 index 0000000..07de630 --- /dev/null +++ b/src/mainboard/google/cyan/chromeos.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#endif +#include <soc/gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ +#define WP_STATUS_PAD 36 + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static int get_lid_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + return !!(ec_switches & EC_SWITCH_LID_OPEN); +#else + /* Default to force open. */ + return 1; +#endif +} + +static void fill_lb_gpio(struct lb_gpio *gpio, int port, int polarity, + const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = port; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + recovery_mode_enabled()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif /* ENV_RAMSTAGE */ + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + u32 ec_events; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +#else + return 0; +#endif +} + +int clear_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + const uint32_t kb_rec_mask = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + /* Unconditionally clear the EC recovery request. */ + return google_chromeec_clear_events_b(kb_rec_mask); +#else + return 0; +#endif +} + +int get_write_protect_state(void) +{ + /* + * The vboot loader queries this function in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. The + * hardware defaults to an input but there is a 20K pulldown. Externally + * there is a 10K pullup. Disable the internal pull in romstage so that + * there isn't any ambiguity in the reading. + */ +#if ENV_ROMSTAGE + ssus_disable_internal_pull(WP_STATUS_PAD); +#endif + + /* WP is enabled when the pin is reading high. */ + return ssus_get_gpio(WP_STATUS_PAD); +} diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout new file mode 100644 index 0000000..18bf4ce --- /dev/null +++ b/src/mainboard/google/cyan/cmos.layout @@ -0,0 +1,140 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c new file mode 100644 index 0000000..b07b205 --- /dev/null +++ b/src/mainboard/google/cyan/com_init.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void mainboard_pre_console_init(struct romstage_params *params) +{ + uint32_t reg; + uint32_t *pad_config_reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* + * Set up the pads to select the UART function for Cyan + * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Set Mode 2 for UART0_RXD + * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD + */ + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); + + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); +} diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb new file mode 100755 index 0000000..490e8ef --- /dev/null +++ b/src/mainboard/google/cyan/devicetree.cb @@ -0,0 +1,139 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "1" + register "PcdEnableAzalia" = "1" + register "PcdEnableSata" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "1" + register "PcdEnableI2C3" = "1" + register "PcdEnableI2C4" = "1" + register "PcdEnableI2C5" = "1" + register "PcdEnableI2C6" = "1" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "SVID_CONFIG3" + register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdPciClkSsc" = "1" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 on end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 on end # 8086 22c3 - I2C Port 3 + device pci 18.4 on end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 on end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 on end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 on end # 8086 2290 - SPI 2 + device pci 1e.7 on end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl new file mode 100755 index 0000000..9f1db24 --- /dev/null +++ b/src/mainboard/google/cyan/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, /* DSDT revision: ACPI v5.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/braswell/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/braswell/acpi/globalnvs.asl> + + #include <soc/intel/braswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* #include <soc/intel/braswell/acpi/northcluster.asl> */ + #include <soc/intel/braswell/acpi/southcluster.asl> + #include <soc/intel/braswell/acpi/dptf/cpu.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/braswell/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c new file mode 100755 index 0000000..e233408 --- /dev/null +++ b/src/mainboard/google/cyan/ec.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" +#include <vendorcode/google/chromeos/chromeos.h> +#include <types.h> + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Restore SCI event mask on resume. */ + if (acpi_slp_type == 3) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + /* Clear wake events, these are enabled on entry to sleep */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + google_chromeec_set_wake_mask(0); +#endif + + post_code(0xf1); +} diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h new file mode 100755 index 0000000..7e70d48 --- /dev/null +++ b/src/mainboard/google/cyan/ec.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +/* GPIO_S0_000 is EC_SCI#, but it is bit 16 in GPE_STS */ +#define EC_SCI_GPI 16 +/* GPIO_S5_07 is EC_SMI#, but it is bit 19 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 19 + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c new file mode 100644 index 0000000..45a680a --- /dev/null +++ b/src/mainboard/google/cyan/fadt.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c new file mode 100644 index 0000000..09b31a2 --- /dev/null +++ b/src/mainboard/google/cyan/gpio.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERTB */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + Native_M5, /* 00 GPIO_DFX0 */ + Native_M5, /* 01 GPIO_DFX3 */ + Native_M1, /* 02 GPIO_DFX7 */ + Native_M5, /* 03 GPIO_DFX1 */ + Native_M1, /* 04 GPIO_DFX5 */ + Native_M1, /* 05 GPIO_DFX4 */ + GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), + /* 06 GPIO_DFX8 */ + Native_M5, /* 07 GPIO_DFX2 */ + Native_M8, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + GPIO_NC, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/cyan/irqroute.c b/src/mainboard/google/cyan/irqroute.c new file mode 100644 index 0000000..83207d9 --- /dev/null +++ b/src/mainboard/google/cyan/irqroute.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/google/cyan/irqroute.h b/src/mainboard/google/cyan/irqroute.h new file mode 100644 index 0000000..5353d42 --- /dev/null +++ b/src/mainboard/google/cyan/irqroute.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +#define TPAD_IRQ_OFFSET 0 +#define TOUCH_IRQ_OFFSET 1 +#define I8042_IRQ_OFFSET 2 +#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +#define TPAD_IRQ_GPIO 55 +#define TOUCH_IRQ_GPIO 72 +#define I8042_IRQ_GPIO 101 +#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c new file mode 100755 index 0000000..f155a04 --- /dev/null +++ b/src/mainboard/google/cyan/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootstate.h> +#include <device/device.h> +#include <soc/gpio.h> + +struct chip_operations mainboard_ops = { +}; diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h new file mode 100755 index 0000000..00ff28e --- /dev/null +++ b/src/mainboard/google/cyan/onboard.h @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include "irqroute.h" + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* + * gpio based irq for kbd, 17th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 18 + */ +/* ToDO: change kbd irq to gpio bank index */ +#define CYAN_KBD_IRQ 182 + + +/* SCI: Gpio index in N bank */ +#define CYAN_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define CYAN_TRACKPAD_GPIO_INDEX 18 +/* Touch: Gpio index in SW bank */ +#define CYAN_TOUCH_GPIO_INDEX 76 +/* TI Audio: Gpio index in SW bank */ +#define CYAN_JACK_TI_GPIO_INDEX 34 +/* MAXIM Audio: Gpio index in SE bank */ +#define CYAN_JACK_MAXIM_GPIO_INDEX 77 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ + +#define BOARD_I8042_IRQ CYAN_KBD_IRQ +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "193C9890" +#define AUDIO_CODEC_CID "193C9890" +#define AUDIO_CODEC_DDN "Maxim 98090 Codec " +#define AUDIO_CODEC_I2C_ADDR 0x10 + +#define TI_SWITCH_HID "104C227E" +#define TI_SWITCH_CID "104C227E" +#define TI_SWITCH_DDN "TI SWITCH " +#define TI_SWITCH_I2C_ADDR 0x3B +#endif diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c new file mode 100644 index 0000000..80df958 --- /dev/null +++ b/src/mainboard/google/cyan/ramstage.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(UPD_DATA_REGION *upd_ptr) +{ + if (IS_ENABLED(CONFIG_DYNAMIC_VNN_SUPPORT)) + upd_ptr->ChvSvidConfig = SVID_CONFIG1; +} diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c new file mode 100755 index 0000000..a6d7e36 --- /dev/null +++ b/src/mainboard/google/cyan/romstage.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data *ps = rp->pei_data; + + mainboard_fill_spd_data(ps); + + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +} + +void mainboard_memory_init_params( + struct romstage_params *params, + UPD_DATA_REGION *upd_ptr) +{ + /* Update SPD data */ + upd_ptr->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + upd_ptr->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + upd_ptr->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c new file mode 100644 index 0000000..5af0421 --- /dev/null +++ b/src/mainboard/google/cyan/smihandler.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#include <elog.h> +#include <soc/nvs.h> +#include <soc/pm.h> + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +static uint8_t mainboard_smi_ec(void) +{ + uint8_t cmd = google_chromeec_get_event(); + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt; + +#if IS_ENABLED(CONFIG_ELOG_GSMI) + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); + outl(pm1_cnt, pmbase + PM1_CNT); + break; + } + + return cmd; +} +#endif + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +#endif +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); +#endif + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case 5: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); +#endif + break; + } + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0) + ; +#endif +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); +#endif + break; + case APM_CNT_ACPI_DISABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); +#endif + break; + } + return 0; +} diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc new file mode 100644 index 0000000..4b4bff6 --- /dev/null +++ b/src/mainboard/google/cyan/spd/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex new file mode 100644 index 0000000..ff4fd29 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 ff ab +48 4d 54 34 32 35 53 36 +41 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex new file mode 100644 index 0000000..fdd1a43 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex @@ -0,0 +1,32 @@ +92 13 0B 03 04 19 02 02 +03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 +00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 +43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex new file mode 100644 index 0000000..e0b0ac5 --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 +88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 +34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c new file mode 100644 index 0000000..01f4dd7 --- /dev/null +++ b/src/mainboard/google/cyan/spd/spd.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> + +#define SPD_SIZE 256 +#define SATA_GP3_PAD_CFG0 0x5828 +#define I2C3_SCL_PAD_CFG0 0x5438 +#define MF_PLT_CLK1_PAD_CFG0 0x4410 +#define I2C3_SDA_PAD_CFG0 0x5420 + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ +static const uint32_t dual_channel_config = (1 << 0); + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; + ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) + << 2; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; + + /* + * There are only 2 SPDs supported on Cyan Board: + * Samsung 4G:0000 & Hynix 2G:0011 + */ + + /* + * RAMID0 on the first boot does not read the correct value,so checking + * bit 1 is enough as WA + */ + if (ram_id > 0) + ram_id = 3; + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + + if (ram_id >= total_spds) + return NULL; + + /* Single channel configs */ + if (dual_channel_config & (1 << ram_id)) + *dual = 1; + + return &spd_file_content[SPD_SIZE * ram_id]; +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + struct cbfs_file *spd_file; + void *spd_content; + int dual_channel = 0; + + /* Find the SPD data in CBFS. */ + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), + ntohl(spd_file->len) / SPD_SIZE, + &dual_channel); + if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_SIZE); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + ps->spd_data_ch0 = spd_content; + ps->spd_ch0_config = 1; + if (dual_channel) { + ps->spd_data_ch1 = spd_content; + ps->spd_ch1_config = 1; + } else { + ps->spd_ch1_config = 2; + } + } +} diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c new file mode 100644 index 0000000..4399d88 --- /dev/null +++ b/src/mainboard/google/cyan/w25q64.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/spi.h> +#include <string.h> + +/* + * SPI lockdown configuration W25Q64FW. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +}

1 0

Patch set updated for coreboot: 8670191 device_ops: add device_t argument to acpi_inject_dsdt_generator
by Alexander Couzens 28 May '15

28 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9597 -gerrit commit 86701919e921bc32bf803f6bbf464c78b9bdc8a1 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Apr 12 21:49:46 2015 +0200 device_ops: add device_t argument to acpi_inject_dsdt_generator `device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I3fc8e0339fa46fe92cc39f7afa896ffd38c26c8d Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/arch/x86/boot/acpi.c | 2 +- src/include/device/device.h | 2 +- src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mainboard.h | 2 +- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/fsp_baytrail/acpi.c | 2 +- src/soc/intel/fsp_baytrail/baytrail/acpi.h | 3 ++- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- src/southbridge/intel/sch/lpc.c | 2 +- 16 files changed, 17 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 48260fc..3fb3e7f 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -754,7 +754,7 @@ unsigned long write_acpi_tables(unsigned long start) acpigen_set_current((char *) current); for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_inject_dsdt_generator) { - dev->ops->acpi_inject_dsdt_generator(); + dev->ops->acpi_inject_dsdt_generator(dev); } current = (unsigned long) acpigen_get_current(); memcpy((char *)current, diff --git a/src/include/device/device.h b/src/include/device/device.h index 0acebb8..d221b2c 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -58,7 +58,7 @@ struct device_operations { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt_generator)(void); - void (*acpi_inject_dsdt_generator)(void); + void (*acpi_inject_dsdt_generator)(device_t dev); #endif const struct pci_operations *ops_pci; const struct smbus_bus_operations *ops_smbus_bus; diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index c6f7dc1..dbb3229 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -91,7 +91,7 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -void mainboard_inject_dsdt(void) +void mainboard_inject_dsdt(device_t device) { global_vars_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, GLOBAL_VARS_SIZE); diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.h b/src/mainboard/siemens/sitemp_g1p1/mainboard.h index 7f80ca8..33d0a5e 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.h +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.h @@ -1 +1 @@ -void mainboard_inject_dsdt(void); +void mainboard_inject_dsdt(device_t device); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 365ac3d..f53a43a 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -513,7 +513,7 @@ void southcluster_enable_dev(device_t dev) } } -static void southcluster_inject_dsdt(void) +static void southcluster_inject_dsdt(device_t device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 0acfe78..db22b53 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -611,7 +611,7 @@ static void pch_lpc_read_resources(device_t dev) memset(gnvs, 0, sizeof(global_nvs_t)); } -static void southcluster_inject_dsdt(void) +static void southcluster_inject_dsdt(device_t device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 1a0c0ce..2825773 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -596,7 +596,7 @@ unsigned long southcluster_write_acpi_tables(unsigned long current, return current; } -void southcluster_inject_dsdt(void) +void southcluster_inject_dsdt(device_t device) { global_nvs_t *gnvs; diff --git a/src/soc/intel/fsp_baytrail/baytrail/acpi.h b/src/soc/intel/fsp_baytrail/baytrail/acpi.h index 6798f45..1e60508 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/acpi.h +++ b/src/soc/intel/fsp_baytrail/baytrail/acpi.h @@ -23,6 +23,7 @@ #include <arch/acpi.h> #include <baytrail/nvs.h> +#include <device/device.h> void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); @@ -31,6 +32,6 @@ unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); unsigned long southcluster_write_acpi_tables(unsigned long current, struct acpi_rsdp *rsdp); -void southcluster_inject_dsdt(void); +void southcluster_inject_dsdt(device_t device); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0ecd389..e768ed9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -669,7 +669,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(void) +static void southbridge_inject_dsdt(device_t dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); void *opregion; diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index e707afa..bcbaaa8 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -631,7 +631,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(void) +static void southbridge_inject_dsdt(device_t dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); void *opregion; diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 3aee7ed..a0ea24c 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -431,7 +431,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(void) +static void southbridge_inject_dsdt(device_t dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ccaabba..822ee7e 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -612,7 +612,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(void) +static void southbridge_inject_dsdt(device_t dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index de936a3..cffbae0 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -539,7 +539,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(void) +static void southbridge_inject_dsdt(device_t dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index c33f9d9..cf45897 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -662,7 +662,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(void) +static void southbridge_inject_dsdt(device_t dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); void *opregion; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6b2a522..c31624a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -743,7 +743,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(void) +static void southbridge_inject_dsdt(device_t dev) { global_nvs_t *gnvs; diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index f06c149..09ff6a6 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -188,7 +188,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(void) +static void southbridge_inject_dsdt(device_t dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));

1 0

Patch set updated for coreboot: 5c70d41 device_ops: add device_t argument to acpi_fill_ssdt_generator
by Alexander Couzens 28 May '15

28 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9598 -gerrit commit 5c70d41ac5fe482afc31fa6b26aa2dd3653f3a73 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Apr 12 22:18:55 2015 +0200 device_ops: add device_t argument to acpi_fill_ssdt_generator `device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/arch/x86/boot/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 3 ++- src/cpu/intel/fsp_model_206ax/acpi.c | 2 +- src/cpu/intel/fsp_model_406dx/acpi.c | 2 +- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/include/device/device.h | 2 +- src/mainboard/lenovo/x200/mainboard.c | 2 +- src/mainboard/lenovo/x201/mainboard.c | 2 +- src/mainboard/lenovo/x60/mainboard.c | 2 +- src/mainboard/tyan/s2891/mainboard.c | 2 +- src/mainboard/tyan/s2892/mainboard.c | 2 +- src/mainboard/tyan/s2895/mainboard.c | 2 +- src/mainboard/winent/mb6047/mainboard.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdfam10/amdfam10.h | 2 +- src/northbridge/amd/amdk8/acpi.c | 2 +- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/intel/fsp_rangeley/acpi.c | 4 ++-- src/northbridge/intel/fsp_rangeley/northbridge.h | 8 +++++++- src/soc/intel/baytrail/acpi.c | 2 +- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/fsp_baytrail/acpi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 2 +- src/southbridge/amd/sb600/lpc.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82371eb/acpi_tables.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 4 ++-- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/nvidia/ck804/lpc.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 2 +- src/southbridge/via/k8t890/traf_ctrl.c | 2 +- 44 files changed, 53 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 3fb3e7f..391cc15 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -270,7 +270,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { - dev->ops->acpi_fill_ssdt_generator(); + dev->ops->acpi_fill_ssdt_generator(dev); } current = (unsigned long) acpigen_get_current(); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 245599f..27fce31 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -29,6 +29,7 @@ #include <stdint.h> #include <rules.h> +#include <device/device.h> #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ @@ -532,7 +533,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(void); +void generate_cpu_entries(device_t device); #endif void acpi_create_mcfg(acpi_mcfg_t *mcfg); diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index 95c90fb..272f486 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -302,7 +302,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index ba778b6..abc35ad 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -263,7 +263,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index b8aad14..c072075 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -307,7 +307,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 1e4bb03..da8ba4e 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -299,7 +299,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 47c958a..94cc6de 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -302,7 +302,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 6c7178e..1c3cb9d 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -117,7 +117,7 @@ static void gen_pstate_entries(const sst_table_t *const pstates, /** * @brief Generate ACPI entries for Speedstep for each cpu */ -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = determine_total_number_of_cores(); diff --git a/src/include/device/device.h b/src/include/device/device.h index d221b2c..1a36220 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -57,7 +57,7 @@ struct device_operations { #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); - void (*acpi_fill_ssdt_generator)(void); + void (*acpi_fill_ssdt_generator)(device_t dev); void (*acpi_inject_dsdt_generator)(device_t dev); #endif const struct pci_operations *ops_pci; diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 518b51a..8b5a70e 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -32,7 +32,7 @@ #include <ec/lenovo/h8/h8.h> #include "drivers/lenovo/lenovo.h" -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 85c27b2..7bc529a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -91,7 +91,7 @@ static void mainboard_init(device_t dev) pc_keyboard_init(); } -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index fbab0f1..b137aaa 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -99,7 +99,7 @@ static void mainboard_init(device_t dev) } } -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); } diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index 604df51..e62b95e 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -8,7 +8,7 @@ extern u16 pm_base; -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/winent/mb6047/mainboard.c +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 935e137..ee291a5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -811,7 +811,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 355a458..9329749 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -794,7 +794,7 @@ static void cpu_bus_init(device_t dev) /* North Bridge Structures */ -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index b2d8abd..c070693 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -501,7 +501,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 1f11f1d..d00406b 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c39ebd1..2525289 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d1b06ec..6c815c2 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index dee2087..734ebb6 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -196,7 +196,7 @@ void update_ssdtx(void *ssdtx, int i) } -void northbridge_acpi_write_vars(void) +void northbridge_acpi_write_vars(device_t device) { /* * If more than one physical CPU is installed, northbridge_acpi_write_vars() diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 0bbdbd3..9213ed1 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1076,6 +1076,6 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); -void northbridge_acpi_write_vars(void); +void northbridge_acpi_write_vars(device_t device); #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index d407d7e..1bb1d83 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -277,7 +277,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { acpigen_pop_len(); } -void k8acpi_write_vars(void) +void k8acpi_write_vars(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index a9c2ded..4d822e4 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -21,7 +21,7 @@ #define AMDK8_ACPI_H #include <arch/acpigen.h> -void k8acpi_write_vars(void); +void k8acpi_write_vars(device_t device); unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); #endif diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 15892c6..b94970b 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -471,7 +471,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index c44c189..60b7174 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -465,7 +465,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index 6b6a703..c726155 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -65,7 +65,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -void northbridge_acpi_fill_ssdt_generator(void) +void northbridge_acpi_fill_ssdt_generator(device_t device) { u32 bmbound; char pscope[] = "\\_SB.PCI0"; @@ -74,5 +74,5 @@ void northbridge_acpi_fill_ssdt_generator(void) acpigen_write_scope(pscope); acpigen_write_name_dword("BMBD", bmbound); acpigen_pop_len(); - generate_cpu_entries(); + generate_cpu_entries(device); } diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index d7f4ebd..dc4676b 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -27,6 +27,9 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ +#include <rules.h> +#include <device/device.h> + /* Device 0:0.0 PCI configuration space (Host Bridge) */ /* SideBand B-UNIT */ @@ -72,7 +75,10 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); -void northbridge_acpi_fill_ssdt_generator(void); + +#if ENV_RAMSTAGE +void northbridge_acpi_fill_ssdt_generator(device_t device); +#endif #endif /* #ifndef __ASSEMBLER__ */ #endif /* #ifndef __ACPI__ */ diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index dd8833d..e3444b6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -447,7 +447,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int core; int pcontrol_blk = get_pmbase(), plen = 6; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 67220c5..34a576d 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -537,7 +537,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 2825773..9b0d148 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -513,7 +513,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int core; int pcontrol_blk = get_pmbase(), plen = 6; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 2ded0cb..5bb59b9 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -128,7 +128,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { #if CONFIG_SET_FIDVID amd_generate_powernow(pm_base + 0x10, 6, 1); acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 62c88de..ae36b4b 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -223,7 +223,7 @@ static void sb600_lpc_enable_resources(device_t dev) extern u16 pm_base; -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(pm_base + 8, 6, 1); } diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index be3c4d6..0ebd103 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -267,7 +267,7 @@ static void sb700_lpc_enable_resources(device_t dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e768ed9..4203c91 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -834,7 +834,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index c919205..fa3029c 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -45,7 +45,7 @@ static int determine_total_number_of_cores(void) return count; } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; int numcpus = determine_total_number_of_cores(); diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 1945fae..ee256e6 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -129,10 +129,10 @@ static void sb_read_resources(struct device *dev) } #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - generate_cpu_entries(); + generate_cpu_entries(device); } #endif diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index cffbae0..810f5e0 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -556,7 +556,7 @@ static void southbridge_inject_dsdt(device_t dev) } } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index cf45897..60face4 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -822,7 +822,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index c6f8c24..5419c17 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -313,7 +313,7 @@ static void ck804_lpc_enable_resources(device_t dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index d9c6211..a1c9600 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -283,7 +283,7 @@ static const struct pci_driver lpc_driver __pci_driver = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index b4620da..75dc353 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -127,7 +127,7 @@ static void traf_ctrl_enable_k8t890(struct device *dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t dev) { amd_generate_powernow(0, 0, 0); acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); }

1 0

Patch set updated for coreboot: 256930c device_ops: add device_t argument to write_acpi_tables
by Alexander Couzens 28 May '15

28 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9599 -gerrit commit 256930c38a5752cba3593bd90057e0fccafeac36 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Apr 12 22:28:37 2015 +0200 device_ops: add device_t argument to write_acpi_tables `device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I1ba4bfa0ac36a09a82b108249158c80c50f9f5fd Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/arch/x86/boot/acpi.c | 4 ++-- src/arch/x86/include/arch/acpi.h | 2 +- src/include/device/device.h | 2 +- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 2 +- src/mainboard/amd/serengeti_cheetah/mainboard.h | 2 +- src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c | 3 ++- src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h | 2 +- src/mainboard/emulation/qemu-i440fx/acpi.h | 2 +- src/mainboard/getac/p470/acpi_tables.c | 4 +++- src/mainboard/getac/p470/mainboard.h | 3 ++- src/mainboard/iwill/dk8_htx/acpi_tables.c | 4 +++- src/mainboard/iwill/dk8_htx/mainboard.h | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 3 ++- src/northbridge/amd/agesa/family14/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15rl/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15tn/northbridge.c | 3 ++- src/northbridge/amd/agesa/family16kb/northbridge.c | 3 ++- src/northbridge/amd/amdfam10/acpi.c | 5 +++-- src/northbridge/amd/amdfam10/amdfam10.h | 3 ++- src/northbridge/amd/amdk8/acpi.c | 5 ++++- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 3 ++- src/northbridge/amd/pi/00730F01/northbridge.c | 3 ++- src/northbridge/intel/gm45/acpi.c | 4 +++- src/northbridge/intel/gm45/gm45.h | 8 +++++++- src/soc/intel/fsp_baytrail/acpi.c | 5 +++-- src/soc/intel/fsp_baytrail/baytrail/acpi.h | 3 ++- src/southbridge/intel/lynxpoint/lpc.c | 4 +++- 29 files changed, 63 insertions(+), 32 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 391cc15..9cb51ef 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -453,7 +453,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } -unsigned long acpi_write_hpet(unsigned long current, acpi_rsdp_t *rsdp) +unsigned long acpi_write_hpet(device_t device, unsigned long current, acpi_rsdp_t *rsdp) { acpi_hpet_t *hpet; @@ -819,7 +819,7 @@ unsigned long write_acpi_tables(unsigned long start) for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->write_acpi_tables) { - current = dev->ops->write_acpi_tables(current, rsdp); + current = dev->ops->write_acpi_tables(dev, current, rsdp); ALIGN_CURRENT; } } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 27fce31..f1fbde8 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -530,7 +530,7 @@ void acpi_create_slit(acpi_slit_t *slit, #if ENV_RAMSTAGE void acpi_create_hpet(acpi_hpet_t *hpet); -unsigned long acpi_write_hpet(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(device_t device); diff --git a/src/include/device/device.h b/src/include/device/device.h index 1a36220..9cc7f30 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -56,7 +56,7 @@ struct device_operations { void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); + unsigned long (*write_acpi_tables)(device_t dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt_generator)(device_t dev); void (*acpi_inject_dsdt_generator)(device_t dev); #endif diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 168793e..e0fe77d 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -122,7 +122,7 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ssdtx; diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.h b/src/mainboard/amd/serengeti_cheetah/mainboard.h index 80d8f2a..fc2dcaf 100644 --- a/src/mainboard/amd/serengeti_cheetah/mainboard.h +++ b/src/mainboard/amd/serengeti_cheetah/mainboard.h @@ -1 +1 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 8c24528..7a0b79e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -131,7 +131,8 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long current, +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_header_t *ssdtx; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h index 8f17804..b152b04 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h @@ -1,2 +1,2 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/mainboard/emulation/qemu-i440fx/acpi.h b/src/mainboard/emulation/qemu-i440fx/acpi.h index c0d4e6e..f2ffdeb 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi.h +++ b/src/mainboard/emulation/qemu-i440fx/acpi.h @@ -1 +1 @@ -unsigned long northbridge_write_acpi_tables(unsigned long start); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start); diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index bc805dc..698af09 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -118,7 +118,9 @@ unsigned long acpi_fill_madt(unsigned long current) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ecdt; diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h index 45d961b..56f5455 100644 --- a/src/mainboard/getac/p470/mainboard.h +++ b/src/mainboard/getac/p470/mainboard.h @@ -1,4 +1,5 @@ struct acpi_rsdp; -unsigned long mainboard_write_acpi_tables(unsigned long start, +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, struct acpi_rsdp *rsdp); diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index e1c5c80..e724557 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -129,7 +129,9 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ssdtx; diff --git a/src/mainboard/iwill/dk8_htx/mainboard.h b/src/mainboard/iwill/dk8_htx/mainboard.h index 80d8f2a..fc2dcaf 100644 --- a/src/mainboard/iwill/dk8_htx/mainboard.h +++ b/src/mainboard/iwill/dk8_htx/mainboard.h @@ -1 +1 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index ee291a5..ec1f493 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -832,7 +832,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 9329749..964fe9d 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -833,7 +833,8 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c070693..38f670c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -522,7 +522,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d00406b..a54054a 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2525289..fec901b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 6c815c2..4373a99 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 734ebb6..4b86e96 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -330,8 +330,9 @@ void northbridge_acpi_write_vars(device_t device) acpigen_pop_len(); } -unsigned long northbridge_write_acpi_tables(unsigned long current, - struct acpi_rsdp *rsdp) +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) { acpi_srat_t *srat; acpi_slit_t *slit; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 9213ed1..9461385 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1074,7 +1074,8 @@ BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(unsigned long start, +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, struct acpi_rsdp *rsdp); void northbridge_acpi_write_vars(device_t device); diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 1bb1d83..10228cf 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -204,7 +204,10 @@ static unsigned long acpi_fill_slit(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long northbridge_write_acpi_tables( + device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_srat_t *srat; diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index 4d822e4..b874dd4 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -22,6 +22,6 @@ #include <arch/acpigen.h> void k8acpi_write_vars(device_t device); -unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); #endif diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index b94970b..12b51b0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -492,7 +492,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 60b7174..7f2b6c9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -486,7 +486,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index a1cfdb5..daa5aed 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -109,7 +109,9 @@ static unsigned long acpi_fill_dmar(unsigned long current) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, + struct acpi_rsdp *rsdp) { unsigned long current; #if CONFIG_IOMMU diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index db3db00..cb946fc 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -25,6 +25,7 @@ #ifndef __ACPI__ +#include <rules.h> #include <stdint.h> typedef enum { @@ -435,8 +436,13 @@ u32 decode_igd_gtt_size(u32 gsm); void init_iommu(void); +#if ENV_RAMSTAGE +#include <device/device.h> + struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif + +#endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 9b0d148..ed607b3 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -569,12 +569,13 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long southcluster_write_acpi_tables(unsigned long current, +unsigned long southcluster_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp) { acpi_header_t *ssdt2; - current = acpi_write_hpet(current, rsdp); + current = acpi_write_hpet(device, current, rsdp); ALIGN_CURRENT; ssdt2 = (acpi_header_t *)current; diff --git a/src/soc/intel/fsp_baytrail/baytrail/acpi.h b/src/soc/intel/fsp_baytrail/baytrail/acpi.h index 1e60508..0cd978d 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/acpi.h +++ b/src/soc/intel/fsp_baytrail/baytrail/acpi.h @@ -30,7 +30,8 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -unsigned long southcluster_write_acpi_tables(unsigned long current, +unsigned long southcluster_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(device_t device); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c31624a..6c5ce96 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -780,7 +780,9 @@ static void southbridge_inject_dsdt(device_t dev) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +static unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long start, + struct acpi_rsdp *rsdp) { unsigned long current; acpi_hpet_t *hpet;

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Patch set updated for coreboot: 7ac6317 acpi/sata: add generic sata ssdt port generator
by Alexander Couzens 27 May '15

27 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9708 -gerrit commit 7ac631732a2adde0d990ba09967335a0bbd84dfb Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:03:26 2015 +0200 acpi/sata: add generic sata ssdt port generator generate_sata_ssdt_ports() generates ports based on sata enable map Change-Id: Ie68e19c93f093d6c61634c4adfde484b88f28a77 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- Makefile.inc | 2 +- src/Kconfig | 2 ++ src/acpi/Kconfig | 6 +++++ src/acpi/Makefile.inc | 1 + src/acpi/sata.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/acpi/sata.h | 3 +++ 6 files changed, 74 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 0c688f7..03b4489 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,7 +52,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/console src/device +subdirs-y := src/lib src/console src/device src/acpi subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode diff --git a/src/Kconfig b/src/Kconfig index 26e1194..fffe7a3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -329,6 +329,8 @@ config RAM_CODE_SUPPORT endmenu +source "src/acpi/Kconfig" + source "src/mainboard/Kconfig" source "src/arch/*/Kconfig" diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig new file mode 100644 index 0000000..e025f99 --- /dev/null +++ b/src/acpi/Kconfig @@ -0,0 +1,6 @@ + +config ACPI_SATA_GENERATOR + bool + default n + help + Use acpi sata port generator. diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc new file mode 100644 index 0000000..53ac679 --- /dev/null +++ b/src/acpi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_ACPI_SATA_GENERATOR) += sata.c diff --git a/src/acpi/sata.c b/src/acpi/sata.c new file mode 100644 index 0000000..b488574 --- /dev/null +++ b/src/acpi/sata.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "sata.h" + +#include <arch/acpi.h> +#include <arch/acpigen.h> + +/* e.g. + * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); + * generates: + * Scope (\_SB.PCI0.SATA) + * { + * Device (PRT0) + * { + * Name (_ADR, 0x0000FFFF) // _ADR: Address + * } + * + * Device (PRT1) + * { + * Name (_ADR, 0x0001FFFF) // _ADR: Address + * } + * } + */ +void generate_sata_ssdt_ports(const char *scope, uint8_t enable_map) +{ + int i; + int bit; + char port_name[4] = "PRT0"; + + acpigen_write_scope(scope); + + /* generate a device for every enabled port */ + for (i = 0; i < 8; i++) { + bit = 1 << i; + if (!(bit & enable_map)) + continue; + + port_name[3] = '0' + i; + acpigen_write_device(port_name); + + acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000); + acpigen_pop_len(); /* close PRT%d */ + } + + acpigen_pop_len(); /* close scope */ +} diff --git a/src/acpi/sata.h b/src/acpi/sata.h new file mode 100644 index 0000000..b7f17b2 --- /dev/null +++ b/src/acpi/sata.h @@ -0,0 +1,3 @@ +#include <stdint.h> + +void generate_sata_ssdt_ports(const char *scope, uint8_t enable_map);

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Patch set updated for coreboot: 31dce15 southbridge/bd82x6x: use new ssdt sata port generator
by Alexander Couzens 27 May '15

27 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709 -gerrit commit 31dce15b0790c0f861623e09d113902acace092d Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:00:21 2015 +0200 southbridge/bd82x6x: use new ssdt sata port generator Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 ----------------------------- src/southbridge/intel/bd82x6x/sata.c | 8 +++++ 3 files changed, 9 insertions(+), 52 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 6190879..3a68fec 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl index fb685a3..00d3010 100644 --- a/src/southbridge/intel/bd82x6x/acpi/sata.asl +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -26,56 +26,4 @@ Device (SATA) { Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } } diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 1cdc5e2..18e5a08 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -247,6 +248,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -255,6 +261,8 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator + = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, .scan_bus = 0,

1 0

Patch set updated for coreboot: 9e0d80d southbridge/ibexpeak: use new ssdt sata port generator
by Alexander Couzens 27 May '15

27 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9710 -gerrit commit 9e0d80dfcc99367e9515b485144f46771773610f Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:23:00 2015 +0200 southbridge/ibexpeak: use new ssdt sata port generator Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/sata.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index ccd16bf..f31f83c 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select HAVE_USBDEBUG_OPTIONS select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 29d9240..be2b961 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -26,6 +26,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -249,6 +250,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -259,6 +265,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, + .acpi_fill_ssdt_generator = sata_fill_ssdt, .scan_bus = 0, .ops_pci = &sata_pci_ops, };

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Patch set updated for coreboot: c207714 device_ops: add device_t argument to acpi_fill_ssdt_generator
by Alexander Couzens 27 May '15

27 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9598 -gerrit commit c20771411e5360df370fb228d993c5e6fa90ea06 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Apr 12 22:18:55 2015 +0200 device_ops: add device_t argument to acpi_fill_ssdt_generator `device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/arch/x86/boot/acpi.c | 2 +- src/arch/x86/include/arch/acpi.h | 3 ++- src/cpu/intel/fsp_model_206ax/acpi.c | 2 +- src/cpu/intel/fsp_model_406dx/acpi.c | 2 +- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/include/device/device.h | 2 +- src/mainboard/lenovo/x200/mainboard.c | 2 +- src/mainboard/lenovo/x201/mainboard.c | 2 +- src/mainboard/lenovo/x60/mainboard.c | 2 +- src/mainboard/tyan/s2891/mainboard.c | 2 +- src/mainboard/tyan/s2892/mainboard.c | 2 +- src/mainboard/tyan/s2895/mainboard.c | 2 +- src/mainboard/winent/mb6047/mainboard.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdfam10/amdfam10.h | 2 +- src/northbridge/amd/amdk8/acpi.c | 2 +- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 2 +- src/northbridge/amd/pi/00730F01/northbridge.c | 2 +- src/northbridge/intel/fsp_rangeley/acpi.c | 4 ++-- src/northbridge/intel/fsp_rangeley/northbridge.h | 8 +++++++- src/soc/intel/baytrail/acpi.c | 2 +- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/fsp_baytrail/acpi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 2 +- src/southbridge/amd/sb600/lpc.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/i82371eb/acpi_tables.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 4 ++-- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/nvidia/ck804/lpc.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 2 +- src/southbridge/via/k8t890/traf_ctrl.c | 2 +- 44 files changed, 53 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 3fb3e7f..391cc15 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -270,7 +270,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { - dev->ops->acpi_fill_ssdt_generator(); + dev->ops->acpi_fill_ssdt_generator(dev); } current = (unsigned long) acpigen_get_current(); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 245599f..27fce31 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -29,6 +29,7 @@ #include <stdint.h> #include <rules.h> +#include <device/device.h> #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ @@ -532,7 +533,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(void); +void generate_cpu_entries(device_t device); #endif void acpi_create_mcfg(acpi_mcfg_t *mcfg); diff --git a/src/cpu/intel/fsp_model_206ax/acpi.c b/src/cpu/intel/fsp_model_206ax/acpi.c index 95c90fb..272f486 100644 --- a/src/cpu/intel/fsp_model_206ax/acpi.c +++ b/src/cpu/intel/fsp_model_206ax/acpi.c @@ -302,7 +302,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index ba778b6..abc35ad 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -263,7 +263,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index b8aad14..c072075 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -307,7 +307,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 1e4bb03..da8ba4e 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -299,7 +299,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 47c958a..94cc6de 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -302,7 +302,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 6c7178e..1c3cb9d 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -117,7 +117,7 @@ static void gen_pstate_entries(const sst_table_t *const pstates, /** * @brief Generate ACPI entries for Speedstep for each cpu */ -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; int totalcores = determine_total_number_of_cores(); diff --git a/src/include/device/device.h b/src/include/device/device.h index d221b2c..1a36220 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -57,7 +57,7 @@ struct device_operations { #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); - void (*acpi_fill_ssdt_generator)(void); + void (*acpi_fill_ssdt_generator)(device_t dev); void (*acpi_inject_dsdt_generator)(device_t dev); #endif const struct pci_operations *ops_pci; diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 518b51a..8b5a70e 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -32,7 +32,7 @@ #include <ec/lenovo/h8/h8.h> #include "drivers/lenovo/lenovo.h" -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 85c27b2..7bc529a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -91,7 +91,7 @@ static void mainboard_init(device_t dev) pc_keyboard_init(); } -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index fbab0f1..b137aaa 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -99,7 +99,7 @@ static void mainboard_init(device_t dev) } } -static void fill_ssdt(void) +static void fill_ssdt(device_t device) { drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); } diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index 604df51..e62b95e 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -8,7 +8,7 @@ extern u16 pm_base; -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c index 9a8dd90..10d99a2 100644 --- a/src/mainboard/winent/mb6047/mainboard.c +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -6,7 +6,7 @@ #include <arch/acpigen.h> #include <cpu/amd/amdk8_sysconf.h> -static void mainboard_acpi_fill_ssdt_generator(void) { +static void mainboard_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 935e137..ee291a5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -811,7 +811,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 355a458..9329749 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -794,7 +794,7 @@ static void cpu_bus_init(device_t dev) /* North Bridge Structures */ -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index b2d8abd..c070693 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -501,7 +501,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 1f11f1d..d00406b 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c39ebd1..2525289 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d1b06ec..6c815c2 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -477,7 +477,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index dee2087..734ebb6 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -196,7 +196,7 @@ void update_ssdtx(void *ssdtx, int i) } -void northbridge_acpi_write_vars(void) +void northbridge_acpi_write_vars(device_t device) { /* * If more than one physical CPU is installed, northbridge_acpi_write_vars() diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 0bbdbd3..9213ed1 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1076,6 +1076,6 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); -void northbridge_acpi_write_vars(void); +void northbridge_acpi_write_vars(device_t device); #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index d407d7e..1bb1d83 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -277,7 +277,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { acpigen_pop_len(); } -void k8acpi_write_vars(void) +void k8acpi_write_vars(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index a9c2ded..4d822e4 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -21,7 +21,7 @@ #define AMDK8_ACPI_H #include <arch/acpigen.h> -void k8acpi_write_vars(void); +void k8acpi_write_vars(device_t device); unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); #endif diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 15892c6..b94970b 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -471,7 +471,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index c44c189..60b7174 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -465,7 +465,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(void) +static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; char pscope[] = "\\_SB.PCI0"; diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index 6b6a703..c726155 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -65,7 +65,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -void northbridge_acpi_fill_ssdt_generator(void) +void northbridge_acpi_fill_ssdt_generator(device_t device) { u32 bmbound; char pscope[] = "\\_SB.PCI0"; @@ -74,5 +74,5 @@ void northbridge_acpi_fill_ssdt_generator(void) acpigen_write_scope(pscope); acpigen_write_name_dword("BMBD", bmbound); acpigen_pop_len(); - generate_cpu_entries(); + generate_cpu_entries(device); } diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index d7f4ebd..dc4676b 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -27,6 +27,9 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ +#include <rules.h> +#include <device/device.h> + /* Device 0:0.0 PCI configuration space (Host Bridge) */ /* SideBand B-UNIT */ @@ -72,7 +75,10 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); -void northbridge_acpi_fill_ssdt_generator(void); + +#if ENV_RAMSTAGE +void northbridge_acpi_fill_ssdt_generator(device_t device); +#endif #endif /* #ifndef __ASSEMBLER__ */ #endif /* #ifndef __ACPI__ */ diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index dd8833d..e3444b6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -447,7 +447,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int core; int pcontrol_blk = get_pmbase(), plen = 6; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 67220c5..34a576d 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -537,7 +537,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; int totalcores = dev_count_cpu(); diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 2825773..9b0d148 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -513,7 +513,7 @@ static void generate_P_state_entries(int core, int cores_per_package) acpigen_pop_len(); } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int core; int pcontrol_blk = get_pmbase(), plen = 6; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 2ded0cb..5bb59b9 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -128,7 +128,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { #if CONFIG_SET_FIDVID amd_generate_powernow(pm_base + 0x10, 6, 1); acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 62c88de..ae36b4b 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -223,7 +223,7 @@ static void sb600_lpc_enable_resources(device_t dev) extern u16 pm_base; -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(pm_base + 8, 6, 1); } diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index be3c4d6..0ebd103 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -267,7 +267,7 @@ static void sb700_lpc_enable_resources(device_t dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e768ed9..4203c91 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -834,7 +834,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index c919205..fa3029c 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -45,7 +45,7 @@ static int determine_total_number_of_cores(void) return count; } -void generate_cpu_entries(void) +void generate_cpu_entries(device_t device) { int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; int numcpus = determine_total_number_of_cores(); diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 1945fae..ee256e6 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -129,10 +129,10 @@ static void sb_read_resources(struct device *dev) } #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - generate_cpu_entries(); + generate_cpu_entries(device); } #endif diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index cffbae0..810f5e0 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -556,7 +556,7 @@ static void southbridge_inject_dsdt(device_t dev) } } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index cf45897..60face4 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -822,7 +822,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static void southbridge_fill_ssdt(void) +static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index c6f8c24..5419c17 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -313,7 +313,7 @@ static void ck804_lpc_enable_resources(device_t dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index d9c6211..a1c9600 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -283,7 +283,7 @@ static const struct pci_driver lpc_driver __pci_driver = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) +static void southbridge_acpi_fill_ssdt_generator(device_t device) { amd_generate_powernow(0, 0, 0); } diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index b4620da..75dc353 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -127,7 +127,7 @@ static void traf_ctrl_enable_k8t890(struct device *dev) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(void) { +static void southbridge_acpi_fill_ssdt_generator(device_t dev) { amd_generate_powernow(0, 0, 0); acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); }

1 0

Patch set updated for coreboot: 78eb492 device_ops: add device_t argument to write_acpi_tables
by Alexander Couzens 27 May '15

27 May '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9599 -gerrit commit 78eb4926106aad0eb9ce42e50b75db0d27467f1d Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Apr 12 22:28:37 2015 +0200 device_ops: add device_t argument to write_acpi_tables `device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I1ba4bfa0ac36a09a82b108249158c80c50f9f5fd Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/arch/x86/boot/acpi.c | 4 ++-- src/arch/x86/include/arch/acpi.h | 2 +- src/include/device/device.h | 2 +- src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 2 +- src/mainboard/amd/serengeti_cheetah/mainboard.h | 2 +- src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c | 3 ++- src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h | 2 +- src/mainboard/emulation/qemu-i440fx/acpi.h | 2 +- src/mainboard/getac/p470/acpi_tables.c | 4 +++- src/mainboard/getac/p470/mainboard.h | 3 ++- src/mainboard/iwill/dk8_htx/acpi_tables.c | 4 +++- src/mainboard/iwill/dk8_htx/mainboard.h | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 3 ++- src/northbridge/amd/agesa/family14/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15rl/northbridge.c | 3 ++- src/northbridge/amd/agesa/family15tn/northbridge.c | 3 ++- src/northbridge/amd/agesa/family16kb/northbridge.c | 3 ++- src/northbridge/amd/amdfam10/acpi.c | 5 +++-- src/northbridge/amd/amdfam10/amdfam10.h | 3 ++- src/northbridge/amd/amdk8/acpi.c | 5 ++++- src/northbridge/amd/amdk8/acpi.h | 2 +- src/northbridge/amd/pi/00630F01/northbridge.c | 3 ++- src/northbridge/amd/pi/00730F01/northbridge.c | 3 ++- src/northbridge/intel/gm45/acpi.c | 4 +++- src/northbridge/intel/gm45/gm45.h | 8 +++++++- src/soc/intel/fsp_baytrail/acpi.c | 5 +++-- src/soc/intel/fsp_baytrail/baytrail/acpi.h | 3 ++- src/southbridge/intel/lynxpoint/lpc.c | 4 +++- 29 files changed, 63 insertions(+), 32 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 391cc15..9cb51ef 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -453,7 +453,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } -unsigned long acpi_write_hpet(unsigned long current, acpi_rsdp_t *rsdp) +unsigned long acpi_write_hpet(device_t device, unsigned long current, acpi_rsdp_t *rsdp) { acpi_hpet_t *hpet; @@ -819,7 +819,7 @@ unsigned long write_acpi_tables(unsigned long start) for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->write_acpi_tables) { - current = dev->ops->write_acpi_tables(current, rsdp); + current = dev->ops->write_acpi_tables(dev, current, rsdp); ALIGN_CURRENT; } } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 27fce31..f1fbde8 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -530,7 +530,7 @@ void acpi_create_slit(acpi_slit_t *slit, #if ENV_RAMSTAGE void acpi_create_hpet(acpi_hpet_t *hpet); -unsigned long acpi_write_hpet(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp); /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(device_t device); diff --git a/src/include/device/device.h b/src/include/device/device.h index 1a36220..9cc7f30 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -56,7 +56,7 @@ struct device_operations { void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t); #endif #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - unsigned long (*write_acpi_tables)(unsigned long start, struct acpi_rsdp *rsdp); + unsigned long (*write_acpi_tables)(device_t dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt_generator)(device_t dev); void (*acpi_inject_dsdt_generator)(device_t dev); #endif diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 168793e..e0fe77d 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -122,7 +122,7 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ssdtx; diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.h b/src/mainboard/amd/serengeti_cheetah/mainboard.h index 80d8f2a..fc2dcaf 100644 --- a/src/mainboard/amd/serengeti_cheetah/mainboard.h +++ b/src/mainboard/amd/serengeti_cheetah/mainboard.h @@ -1 +1 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 8c24528..7a0b79e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -131,7 +131,8 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long current, +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_header_t *ssdtx; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h index 8f17804..b152b04 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h @@ -1,2 +1,2 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/mainboard/emulation/qemu-i440fx/acpi.h b/src/mainboard/emulation/qemu-i440fx/acpi.h index c0d4e6e..f2ffdeb 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi.h +++ b/src/mainboard/emulation/qemu-i440fx/acpi.h @@ -1 +1 @@ -unsigned long northbridge_write_acpi_tables(unsigned long start); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start); diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index bc805dc..698af09 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -118,7 +118,9 @@ unsigned long acpi_fill_madt(unsigned long current) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ecdt; diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h index 45d961b..56f5455 100644 --- a/src/mainboard/getac/p470/mainboard.h +++ b/src/mainboard/getac/p470/mainboard.h @@ -1,4 +1,5 @@ struct acpi_rsdp; -unsigned long mainboard_write_acpi_tables(unsigned long start, +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, struct acpi_rsdp *rsdp); diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index e1c5c80..e724557 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -129,7 +129,9 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_header_t *ssdtx; diff --git a/src/mainboard/iwill/dk8_htx/mainboard.h b/src/mainboard/iwill/dk8_htx/mainboard.h index 80d8f2a..fc2dcaf 100644 --- a/src/mainboard/iwill/dk8_htx/mainboard.h +++ b/src/mainboard/iwill/dk8_htx/mainboard.h @@ -1 +1 @@ -unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index ee291a5..ec1f493 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -832,7 +832,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 9329749..964fe9d 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -833,7 +833,8 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c070693..38f670c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -522,7 +522,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d00406b..a54054a 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2525289..fec901b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 6c815c2..4373a99 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -498,7 +498,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 734ebb6..4b86e96 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -330,8 +330,9 @@ void northbridge_acpi_write_vars(device_t device) acpigen_pop_len(); } -unsigned long northbridge_write_acpi_tables(unsigned long current, - struct acpi_rsdp *rsdp) +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) { acpi_srat_t *srat; acpi_slit_t *slit; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 9213ed1..9461385 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1074,7 +1074,8 @@ BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(unsigned long start, +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, struct acpi_rsdp *rsdp); void northbridge_acpi_write_vars(device_t device); diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 1bb1d83..10228cf 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -204,7 +204,10 @@ static unsigned long acpi_fill_slit(unsigned long current) return current; } -unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp) +unsigned long northbridge_write_acpi_tables( + device_t device, + unsigned long start, + acpi_rsdp_t *rsdp) { unsigned long current; acpi_srat_t *srat; diff --git a/src/northbridge/amd/amdk8/acpi.h b/src/northbridge/amd/amdk8/acpi.h index 4d822e4..b874dd4 100644 --- a/src/northbridge/amd/amdk8/acpi.h +++ b/src/northbridge/amd/amdk8/acpi.h @@ -22,6 +22,6 @@ #include <arch/acpigen.h> void k8acpi_write_vars(device_t device); -unsigned long northbridge_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); #endif diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index b94970b..12b51b0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -492,7 +492,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 60b7174..7f2b6c9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -486,7 +486,8 @@ static void northbridge_fill_ssdt_generator(device_t device) acpigen_pop_len(); } -static unsigned long agesa_write_acpi_tables(unsigned long current, +static unsigned long agesa_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) { acpi_srat_t *srat; diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index a1cfdb5..daa5aed 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -109,7 +109,9 @@ static unsigned long acpi_fill_dmar(unsigned long current) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, + struct acpi_rsdp *rsdp) { unsigned long current; #if CONFIG_IOMMU diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index db3db00..cb946fc 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -25,6 +25,7 @@ #ifndef __ACPI__ +#include <rules.h> #include <stdint.h> typedef enum { @@ -435,8 +436,13 @@ u32 decode_igd_gtt_size(u32 gsm); void init_iommu(void); +#if ENV_RAMSTAGE +#include <device/device.h> + struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); #endif + +#endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 9b0d148..ed607b3 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -569,12 +569,13 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) #define ALIGN_CURRENT current = (ALIGN(current, 16)) -unsigned long southcluster_write_acpi_tables(unsigned long current, +unsigned long southcluster_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp) { acpi_header_t *ssdt2; - current = acpi_write_hpet(current, rsdp); + current = acpi_write_hpet(device, current, rsdp); ALIGN_CURRENT; ssdt2 = (acpi_header_t *)current; diff --git a/src/soc/intel/fsp_baytrail/baytrail/acpi.h b/src/soc/intel/fsp_baytrail/baytrail/acpi.h index aa76088..7250aa6 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/acpi.h +++ b/src/soc/intel/fsp_baytrail/baytrail/acpi.h @@ -29,7 +29,8 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -unsigned long southcluster_write_acpi_tables(unsigned long current, +unsigned long southcluster_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(device_t device); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c31624a..6c5ce96 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -780,7 +780,9 @@ static void southbridge_inject_dsdt(device_t dev) } #define ALIGN_CURRENT current = (ALIGN(current, 16)) -static unsigned long southbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp) +static unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long start, + struct acpi_rsdp *rsdp) { unsigned long current; acpi_hpet_t *hpet;

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coreboot-gerrit May 2015