coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

1 participants
1299 discussions

Patch set updated for coreboot: 410ca72 northbridge/intel/pineview: Add minimal Pineview northbridge.
by Damien Zammit 04 May '15

04 May '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10073 -gerrit commit 410ca722d0a3b9c9828c28bf7ccf083687b61043 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun May 3 21:34:38 2015 +1000 northbridge/intel/pineview: Add minimal Pineview northbridge. Based on i945. Tested on Intel D510MO mainboard. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/pineview/Kconfig | 73 +++++++++++++++ src/northbridge/intel/pineview/Makefile.inc | 31 ++++++ src/northbridge/intel/pineview/acpi.c | 76 +++++++++++++++ src/northbridge/intel/pineview/bootblock.c | 22 +++++ src/northbridge/intel/pineview/pineview.h | 140 ++++++++++++++++++++++++++++ src/northbridge/intel/pineview/ram_calc.c | 62 ++++++++++++ src/northbridge/intel/pineview/udelay.c | 82 ++++++++++++++++ 7 files changed, 486 insertions(+) diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig new file mode 100644 index 0000000..4d6dcc2 --- /dev/null +++ b/src/northbridge/intel/pineview/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_PINEVIEW + bool + +if NORTHBRIDGE_INTEL_PINEVIEW + +config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + #select HAVE_DEBUG_RAM_SETUP + select LAPIC_MONOTONIC_TIMER + select VGA + select PER_DEVICE_ACPI_TABLES + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/pineview/bootblock.c" + +config VGA_BIOS_ID + string + default "8086,a001" + +config CHANNEL_XOR_RANDOMIZATION + bool + default n + +config OVERRIDE_CLOCK_DISABLE + bool + default n + help + Usually system firmware turns off system memory clock + signals to unused SO-DIMM slots to reduce EMI and power + consumption. + However, some boards do not like unused clock signals to + be disabled. + +config MAXIMUM_SUPPORTED_FREQUENCY + int + default 0 + help + If non-zero, this designates the maximum DDR frequency + the board supports, despite what the chipset should be + capable of. + +config CHECK_SLFRCS_ON_RESUME + def_bool n + help + On some boards it may be neccessary to hard reset early + during resume from S3 if the SLFRCS register indicates that + a memory channel is not guaranteed to be in self-refresh. + On other boards the check always creates a false positive, + effectively making it impossible to resume. + +endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc new file mode 100644 index 0000000..657da33 --- /dev/null +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -0,0 +1,31 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += ram_calc.c +#ramstage-y += northbridge.c +#ramstage-y += gma.c +ramstage-y += acpi.c + +romstage-y += ram_calc.c +#romstage-y += raminit.c +#romstage-y += early_init.c +#romstage-y += errata.c +#romstage-y += debug.c + +smm-y += udelay.c diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c new file mode 100644 index 0000000..ae5fc37 --- /dev/null +++ b/src/northbridge/intel/pineview/acpi.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cbmem.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> +#include "pineview.h" + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 pciexbar_reg; + int max_buses; + + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + if (!dev) + return current; + + pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & (1 << 0))) + return current; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + max_buses = 256; + break; + case 1: // 128M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + max_buses = 128; + break; + case 2: // 64M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + max_buses = 64; + break; + default: // RSVD + return current; + } + + if (!pciexbar) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, max_buses - 1); + + return current; +} diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c new file mode 100644 index 0000000..d524f83 --- /dev/null +++ b/src/northbridge/intel/pineview/bootblock.c @@ -0,0 +1,22 @@ +#include <arch/io.h> +#include "pineview.h" + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h new file mode 100644 index 0000000..ff7129d --- /dev/null +++ b/src/northbridge/intel/pineview/pineview.h @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H +#define NORTHBRIDGE_INTEL_PINEVIEW_H + +/* Northbridge BARs */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#include "../../../southbridge/intel/i82801gx/i82801gx.h" + +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ + +/* Display defines for the interrupt 15h handler */ +#define INT15_5F35_CL_DISPLAY_DEFAULT 0 +#define INT15_5F35_CL_DISPLAY_CRT (1 << 0) +#define INT15_5F35_CL_DISPLAY_TV (1 << 1) +#define INT15_5F35_CL_DISPLAY_EFP (1 << 2) +#define INT15_5F35_CL_DISPLAY_LCD (1 << 3) +#define INT15_5F35_CL_DISPLAY_CRT2 (1 << 4) +#define INT15_5F35_CL_DISPLAY_TV2 (1 << 5) +#define INT15_5F35_CL_DISPLAY_EFP2 (1 << 6) +#define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7) + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + +#define GGC 0x52 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) +#define DEVEN_D2F0 (1 << 3) +#define DEVEN_D2F1 (1 << 4) + +#ifndef BOARD_DEVEN +#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) +#endif /* BOARD_DEVEN */ + +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 + +#define LAC 0x97 /* Legacy Access Control */ +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAM 0x9e /* Extended System Management RAM Control */ + +#define TOM 0xa0 +#define TOUUD 0xa2 +#define GBSM 0xa4 +#define BGSM 0xa8 +#define TSEGMB 0xac +#define TOLUD 0xb0 /* Top of Low Used Memory */ +#define ERRSTS 0xc8 +#define ERRCMD 0xca +#define SMICMD 0xcc +#define SCICMD 0xce +#define CGDIS 0xd8 +#define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0 0xe0 +#define DEV0T 0xf0 +#define MSLCK 0xf4 +#define MID0 0xf8 +#define DEBUP0 0xfc + +/* Device 0:1.0 PCI configuration space (PCI Express) */ + +#define BCTRL1 0x3e /* 16bit */ +#define PEGSTS 0x214 /* 32bit */ + + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define GMADR 0x18 +#define GTTADR 0x1c +#define BSM 0x5c +#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ + + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +/* + * EPBAR - Egress Port Root Complex Register Block + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +/* provided by mainboard code */ +void setup_ich7_gpios(void); + +#endif /* __ACPI__ */ + +#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */ diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c new file mode 100644 index 0000000..6f19c1e --- /dev/null +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "pineview.h" + +static unsigned long find_ramtop(void) +{ + u32 tom; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), BSM); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x100000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x200000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x800000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long) tom; +} + +void *cbmem_top(void) +{ + return (void *) find_ramtop(); +} diff --git a/src/northbridge/intel/pineview/udelay.c b/src/northbridge/intel/pineview/udelay.c new file mode 100644 index 0000000..60ca9fb --- /dev/null +++ b/src/northbridge/intel/pineview/udelay.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> + +/** + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; /* ticks per us */ + + msr = rdmsr(MSR_FSB_FREQ); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + + multiply_to_tsc(&tscd, us, d); + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}

1 0

New patch to review for coreboot: 905fd74 DO NOT MERGE: towiki-for-users branch: Also generate user targetted page.
by Denis Carikli 03 May '15

03 May '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10086 -gerrit commit 905fd743482e39e144343ccc0924181a2cbd4ee3 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 3 21:44:22 2015 +0200 DO NOT MERGE: towiki-for-users branch: Also generate user targetted page. The goal of this branch is to produce a page for users who are looking which board to buy. For instance a user won't buy a board based on which superIO it has, so we can ommit that information. Also the user will need to know how much blob-free is the board. That can also be generated from Kconfig. Change-Id: Ieebe5d77ad299da196c82647c34486993ef4a7d2 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>

1 0

New patch to review for coreboot: 82f01bd DO NOT MERGE: to-wiki.sh: Add some northbridge_nice
by Denis Carikli 03 May '15

03 May '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10085 -gerrit commit 82f01bde24c7abdbbbede243e1b409fff2b2932f Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 3 15:47:08 2015 +0200 DO NOT MERGE: to-wiki.sh: Add some northbridge_nice Only some intels are added subtypes not handled correctly yet. Change-Id: I5d63cdf5620f6fbe3a394fdde9cd5cc3625db54d Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- util/board_status/to-wiki/towiki.sh | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index efb3c1f..0fb5e00 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -212,7 +212,22 @@ EOF vendor_board_dir="$COREBOOT_DIR"/src/mainboard/"$venboard"; northbridge="$(sed -n "/^[[:space:]]*select NORTHBRIDGE_/ s,^[[:space:]]*select NORTHBRIDGE_,,p" "$vendor_board_dir/Kconfig")" - northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel,g;')" + northbridge_subtype_nice="" + + case "$northbridge" in + INTEL_SUBTYPE_I945GC|INTEL_SUBTYPE_I945GM) + northbridge_subtype_nice="$(echo "$northbridge"|sed 's,INTEL_SUBTYPE_,Intel ,g')";; + INTEL_NEHALEM) + northbridge_nice="Intel Nehalem (1st Gen)";; + INTEL_SANDYBRIDGE|INTEL_SANDYBRIDGE_NATIVE) + northbridge_nice="Intel Sandybridge (2nd Gen)";; + INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE|INTEL_IVYBRIDGE_NATIVE) + northbridge_nice="Intel Ivybridge (3rd Gen)";; + INTEL_HASWELL) + northbridge_nice="Intel Haswell (4th Gen)";; + *) + northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel,g;')";; + esac cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY")" case "$cpu" in @@ -304,14 +319,9 @@ EOF ;; INTEL_SOCKET_RPGA989) case $northbridge in - INTEL_HASWELL) - cpu_nice="Intel 4th Gen (Haswell) Core i3/i5/i7" - socket_nice="Socket RPGA989";; - INTEL_IVYBRIDGE_NATIVE|INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE) - cpu_nice="Intel 3rd Gen (Ivybridge) Core i3/i5/i7" - socket_nice="Socket RPGA989";; - INTEL_SANDYBRIDGE) - cpu_nice="Intel 2nd Gen (Sandybridge) Core i3/i5/i7" + INTEL_HASWELL|INTEL_IVYBRIDGE_NATIVE|INTEL_IVYBRIDGE| \ + INTEL_FSP_IVYBRIDGE|INTEL_SANDYBRIDGE) + cpu_nice="Core i3/i5/i7" socket_nice="Socket RPGA989";; *) cpu_nice="$northbridge" @@ -397,8 +407,11 @@ EOF else echo "| style=\"background:lime\" | [[#$vendor/$board|$lastgood]]" fi - - echo "| $northbridge_nice" + if ! [ -z "$northbridge_subtype_nice" ]; then + echo "| $northbridge_subtype_nice" + else + echo "| $northbridge_nice" + fi echo "|" echo "* $cpu_nice" echo "* $socket_nice"

1 0

New patch to review for coreboot: 4056a21 DO NOT MERGE: to-wiki.sh: Make it more user friendly
by Denis Carikli 03 May '15

03 May '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10084 -gerrit commit 4056a21b001c2f9708c3cedcc264b9f619b8edb5 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 3 15:04:19 2015 +0200 DO NOT MERGE: to-wiki.sh: Make it more user friendly Change-Id: I280d8182421866fe3dd75b3e91e86c45088ca706 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- util/board_status/to-wiki/foreword.wiki | 25 ------------------------- util/board_status/to-wiki/towiki.sh | 2 +- 2 files changed, 1 insertion(+), 26 deletions(-) diff --git a/util/board_status/to-wiki/foreword.wiki b/util/board_status/to-wiki/foreword.wiki index be05c8c..e69de29 100644 --- a/util/board_status/to-wiki/foreword.wiki +++ b/util/board_status/to-wiki/foreword.wiki @@ -1,25 +0,0 @@ -= coreboot status by mainboard = - -* This list contains reports of successful coreboot execution, ordered by date. It's shows which boards can actually run with current coreboot versions. - -* Using the precise commit id and config.txt, it's possible to reproduce working coreboot builds (assuming no compiler bugs). - -* By sorting it by date, we encourage developers and users to keep ports current and well-tested. - -* Status data comes from the [http://review.coreboot.org/gitweb?p=board-status.git board status repository]. - -* The coreboot tree [http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=util/board_status… contains a tool] to generate and push suitable data -as well as the scripts that present the data in wiki format. - -* Board info is automatically generated from Kconfig and board_info.txt files. All boards present in the tree will appear here with varying amount of details. - -* An account on review.coreboot.org is required for sending data. - -* Sometimes the same board is sold under different names, we've tried to list all known names but some names might be missing. - -* Some boards have been removed for various reasons, may be brought back if someone works on them. Consult [[Graveyard]] for details. - -* If the board is not found in the corebootv4's source code, there might be some form of support that is not ready yet for inclusion in coreboot, usually people willing to send their patches to coreboot goes trough [http://review.coreboot.org gerrit], so looking there could find some code for boards that are not yet merged. -* some vendors have their own coreboot trees/fork, like for instance: -** [http://git.xivo.fr/?p=official/xioh/coreboot.git;a=summary xivo's tree] -** [http://git.chromium.org/gitweb/?p=chromiumos/third_party/coreboot.git;a=sum… chrome/chromium's tree] diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index faa6b99..efb3c1f 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -39,7 +39,7 @@ while read line; do done cat <<EOF -== Motherboards supported in coreboot == +== Compatible mainboards == {| border="0" style="font-size: smaller" |- bgcolor="#6699ff"

1 0

New patch to review for coreboot: 341fc3c DO NOT MERGE: to-wiki.sh: Unify flash information
by Denis Carikli 03 May '15

03 May '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10083 -gerrit commit 341fc3cdca48273e51166e88b41e3a23466903d0 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 3 14:28:26 2015 +0200 DO NOT MERGE: to-wiki.sh: Unify flash information Change-Id: Id14ccb89665ea5b43639af9db3afd0a242972fbb Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- util/board_status/to-wiki/towiki.sh | 49 +++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index d41ac5b..faa6b99 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -50,10 +50,9 @@ cat <<EOF ! align="left" | * CPU * Socket -! align="left" | ROM 1 -! align="left" | P 2 -! align="left" | S 3 -! align="left" | F 4 +! align="left" | +* Flash chip +* Flashrom support EOF for category in desktop server laptop half mini settop "eval" sbc emulation misc unclass; do @@ -403,37 +402,39 @@ EOF echo "|" echo "* $cpu_nice" echo "* $socket_nice" - if [ "$rom_package" = "" ]; then - echo "| ?" + + if [ "$flashrom_support" = "y" ]; then + echo "| style=\"background:lime\" |" + elif [ "$flashrom_support" = "n" ]; then + echo "| style=\"background:red\" |" + elif [ "$flashrom_support" = "coreboot-only" ]; then + echo "| style=\"background:yellow\" |" else - echo "| $rom_package" + echo "|" fi - if [ "$rom_protocol" = "" ]; then - echo "| ?" - else - echo "| $rom_protocol" + + if [ "$rom_package" != "" ]; then + echo "$rom_package" + fi + if [ "$rom_protocol" != "" ]; then + echo "$rom_protocol" fi if [ "$rom_socketed" = "y" ]; then - echo "| style=\"background:lime\" | Y" + echo "removable" elif [ "$rom_socketed" = "n" ]; then - echo "| style=\"background:red\" | N" - elif [ "$flashrom_support" = "variable" ]; then - echo "| ...7" - elif [ "$rom_socketed" = "" ]; then - echo "| ?" - else - echo "| $rom_socketed" + echo "soldered" fi + if [ "$flashrom_support" = "y" ]; then - echo "| style=\"background:lime\" | Y" + echo "Supported" elif [ "$flashrom_support" = "n" ]; then - echo "| style=\"background:red\" | N" + echo "Not supported" elif [ "$flashrom_support" = "coreboot-only" ]; then - echo "| style=\"background:yellow\" | ...6" + echo "Only from coreboot" elif [ "$flashrom_support" = "" ]; then - echo "| ?" + echo "?" else - echo "| $flashrom_support" + echo "$flashrom_support" fi echo done

1 0

New patch to review for coreboot: 7418ce3 DO NOT MERGE: to-wiki.sh: Unify CPU and socket
by Denis Carikli 03 May '15

03 May '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10082 -gerrit commit 7418ce36863ecdb9873d8ecb9963ea6af5d857c5 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 3 14:16:56 2015 +0200 DO NOT MERGE: to-wiki.sh: Unify CPU and socket Change-Id: I9ab34ceeb1f8cef5bf35183c0d168c568e9cd493 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- util/board_status/to-wiki/towiki.sh | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index db6e64c..d41ac5b 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -47,8 +47,9 @@ cat <<EOF ! align="left" | Mainboard ! align="left" | Latest known good ! align="left" | Northbridge -! align="left" | CPU -! align="left" | Socket +! align="left" | +* CPU +* Socket ! align="left" | ROM 1 ! align="left" | P 2 ! align="left" | S 3 @@ -399,8 +400,9 @@ EOF fi echo "| $northbridge_nice" - echo "| $cpu_nice" - echo "| $socket_nice" + echo "|" + echo "* $cpu_nice" + echo "* $socket_nice" if [ "$rom_package" = "" ]; then echo "| ?" else

1 0

New patch to review for coreboot: f90ccde DO NOT MERGE: to-wiki.sh: Remove vendor cooperation score
by Denis Carikli 03 May '15

03 May '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10081 -gerrit commit f90ccded8bfd1e862238e4ffed572fe74a6ddd43 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 3 14:10:30 2015 +0200 DO NOT MERGE: to-wiki.sh: Remove vendor cooperation score Change-Id: Ice0a759de4e4ffb5e4ad2d5e3d52ef62b89d301a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- util/board_status/to-wiki/towiki.sh | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index d1f4881..db6e64c 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -53,7 +53,6 @@ cat <<EOF ! align="left" | P 2 ! align="left" | S 3 ! align="left" | F 4 -! align="left" | VCS5 EOF for category in desktop server laptop half mini settop "eval" sbc emulation misc unclass; do @@ -170,8 +169,6 @@ EOF rom_protocol="$(sed -n "/^[[:space:]]*ROM protocol:/ s,^[[:space:]]*ROM protocol:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" rom_socketed="$(sed -n "/^[[:space:]]*ROM socketed:/ s,^[[:space:]]*ROM socketed:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" flashrom_support="$(sed -n "/^[[:space:]]*Flashrom support:/ s,^[[:space:]]*Flashrom support:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" - vendor_cooperation_score="$(sed -n "/^[[:space:]]*Vendor cooperation score:/ s,^[[:space:]]*Vendor cooperation score:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" - vendor_cooperation_page="$(sed -n "/^[[:space:]]*Vendor cooperation page:/ s,^[[:space:]]*Vendor cooperation page:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" board_url="$(sed -n "/^[[:space:]]*Board URL:/ s,^[[:space:]]*Board URL:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" clone_of="$(sed -n "/^[[:space:]]*Clone of:/ s,^[[:space:]]*Clone of:[[:space:]]*,,p" "$vendor_board_dir/board_info.txt")" else @@ -181,8 +178,6 @@ EOF rom_protocol= rom_socketed= flashrom_support= - vendor_cooperation_score= - vendor_cooperation_page= board_url= clone_of= fi @@ -438,18 +433,6 @@ EOF else echo "| $flashrom_support" fi - if [ "$vendor_cooperation_score" = "4" ]; then - echo -n "| style=\"background:lime\"" - elif [ "$vendor_cooperatio_scoren" = "3" ]; then - echo -n "| style=\"background:yellow\"" - fi - if [ "$vendor_cooperation_page" != "" ]; then - echo "| [[$vendor_cooperation_page|$vendor_cooperation_score]]" - elif [ "$vendor_cooperation_score" = "" ]; then - echo "| —" - else - echo "| $vendor_cooperation_score" - fi echo done done @@ -461,7 +444,6 @@ cat <<EOF 2 ROM chip protocol/type (parallel flash, LPC, FWH, SPI). 3 ROM chip socketed (Y/N)? 4 Board supported by [http://www.flashrom.org flashrom] (Y/N)? -5 Vendor Cooperation Score. 6 [http://www.flashrom.org flashrom] does not work when the vendor BIOS is booted, but it does work when the machine is booted with coreboot. 7 Some boards have ROM sockets, others are soldered.

1 0

New patch to review for coreboot: 3478d45 DO NOT MERGE: to-wiki.sh: Remove northbridge and superio information
by Denis Carikli 03 May '15

03 May '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10080 -gerrit commit 3478d45803d75c9c675787bd89887d486ad80ee3 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 3 14:05:03 2015 +0200 DO NOT MERGE: to-wiki.sh: Remove northbridge and superio information This information is usefull for the developers, not for potential users. Change-Id: I03787a3ba602477ebf8e10997e61823f1d31dc63 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- util/board_status/to-wiki/towiki.sh | 8 -------- 1 file changed, 8 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 338e895..d1f4881 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -47,8 +47,6 @@ cat <<EOF ! align="left" | Mainboard ! align="left" | Latest known good ! align="left" | Northbridge -! align="left" | Southbridge -! align="left" | Super I/O ! align="left" | CPU ! align="left" | Socket ! align="left" | ROM 1 @@ -221,10 +219,6 @@ EOF northbridge="$(sed -n "/^[[:space:]]*select NORTHBRIDGE_/ s,^[[:space:]]*select NORTHBRIDGE_,,p" "$vendor_board_dir/Kconfig")" northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel,g;')" - southbridge="$(sed -n "/[[:space:]]*select SOUTHBRIDGE_/ s,[[:space:]]*select SOUTHBRIDGE_$[^ ]*$.*$,\1,p" "$vendor_board_dir/Kconfig"|grep -v SKIP_ISA_DMA_INIT)" - southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel,g')" - superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" - superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond,g;s,ITE,ITE,g;s,SMSC,SMSC,g')" cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY")" case "$cpu" in ALLWINNER_A10) @@ -410,8 +404,6 @@ EOF fi echo "| $northbridge_nice" - echo "| $southbridge_nice" - echo "| $superio_nice" echo "| $cpu_nice" echo "| $socket_nice" if [ "$rom_package" = "" ]; then

1 0

New patch to review for coreboot: 3027fbd DO NOT MERGE: to-wiki.sh: remove useless ™ and ®
by Denis Carikli 03 May '15

03 May '15

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10079 -gerrit commit 3027fbd7a305fdc352a2de5f77791de298a35ac9 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun May 3 14:01:27 2015 +0200 DO NOT MERGE: to-wiki.sh: remove useless ™ and ® This is to shorten the names: The table is already big. Change-Id: I78bc0c7e8419da62baf92264ef4294435512e3cd Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- util/board_status/to-wiki/towiki.sh | 72 ++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 3e80d44..338e895 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -219,65 +219,65 @@ EOF vendor_board_dir="$COREBOOT_DIR"/src/mainboard/"$venboard"; northbridge="$(sed -n "/^[[:space:]]*select NORTHBRIDGE_/ s,^[[:space:]]*select NORTHBRIDGE_,,p" "$vendor_board_dir/Kconfig")" - northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel®,g;')" + northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel,g;')" southbridge="$(sed -n "/[[:space:]]*select SOUTHBRIDGE_/ s,[[:space:]]*select SOUTHBRIDGE_$[^ ]*$.*$,\1,p" "$vendor_board_dir/Kconfig"|grep -v SKIP_ISA_DMA_INIT)" - southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" + southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" - superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g')" + superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond,g;s,ITE,ITE,g;s,SMSC,SMSC,g')" cpu="$(sed -n "/ select CPU_/ s, select CPU_,,p" "$vendor_board_dir/Kconfig"|grep -v "AMD_AGESA_FAMILY")" case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" socket_nice="?";; AMD_GEODE_*) - cpu_nice="AMD Geode™ ${cpu#AMD_GEODE_}"; + cpu_nice="AMD Geode ${cpu#AMD_GEODE_}"; socket_nice="—";; AMD_SOCKET_754) - cpu_nice="AMD Sempron™ / Athlon™ 64 / Turion™ 64"; + cpu_nice="AMD Sempron / Athlon 64 / Turion 64"; socket_nice="Socket 754";; AMD_SOCKET_ASB2) - cpu_nice="AMD Turion™ II Neo/Athlon™ II Neo"; + cpu_nice="AMD Turion II Neo/Athlon II Neo"; socket_nice="ASB2 (BGA812)";; AMD_SOCKET_S1G1) - cpu_nice="AMD Turion™ / X2 Sempron™"; + cpu_nice="AMD Turion / X2 Sempron"; socket_nice="Socket S1G1";; AMD_SOCKET_G34) - cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; + cpu_nice="AMD Opteron Magny-Cours/Interlagos"; socket_nice="Socket G34";; AMD_SOCKET_C32|AMD_SOCKET_C32_NON_AGESA) - cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; + cpu_nice="AMD Opteron Magny-Cours/Interlagos"; socket_nice="Socket C32";; AMD_SOCKET_AM2) cpu_nice="?"; socket_nice="Socket AM2" ;; AMD_SOCKET_AM3) - cpu_nice="AMD Athlon™ 64 / FX / X2"; + cpu_nice="AMD Athlon 64 / FX / X2"; socket_nice="Socket AM3" ;; AMD_SOCKET_AM2R2) - cpu_nice="AMD Athlon™ 64 / X2 / FX, Sempron™"; + cpu_nice="AMD Athlon 64 / X2 / FX, Sempron"; socket_nice="Socket AM2+" ;; AMD_SOCKET_F) - cpu_nice="AMD Opteron™"; + cpu_nice="AMD Opteron"; socket_nice="Socket F" ;; AMD_SOCKET_F_1207) - cpu_nice="AMD Opteron™"; + cpu_nice="AMD Opteron"; socket_nice="Socket F 1207" ;; AMD_SOCKET_940) - cpu_nice="AMD Opteron™"; + cpu_nice="AMD Opteron"; socket_nice="Socket 940" ;; AMD_SOCKET_939) - cpu_nice="AMD Athlon™ 64 / FX / X2"; + cpu_nice="AMD Athlon 64 / FX / X2"; socket_nice="Socket 939" ;; AMD_SC520) - cpu_nice="AMD Élan™SC520"; + cpu_nice="AMD ÉlanSC520"; socket_nice="—";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; @@ -295,34 +295,34 @@ EOF cpu_nice="TI AM335X"; socket_nice="?";; INTEL_SLOT_1) - cpu_nice="Intel® Pentium® II/III, Celeron®"; + cpu_nice="Intel Pentium II/III, Celeron"; socket_nice="Slot 1";; INTEL_SOCKET_MPGA604) - cpu_nice="Intel® Xeon®"; + cpu_nice="Intel Xeon"; socket_nice="Socket 604";; INTEL_SOCKET_MFCPGA478) - cpu_nice="Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M"; + cpu_nice="Intel Core 2 Duo Mobile, Core Duo/Solo, Celeron M"; socket_nice="Socket mPGA478";; INTEL_SOCKET_LGA771) - cpu_nice="Intel Xeon™ 5000 series"; + cpu_nice="Intel Xeon 5000 series"; socket_nice="Socket LGA771";; INTEL_SOCKET_PGA370) - cpu_nice="Intel® Pentium® III-800, Celeron®" + cpu_nice="Intel Pentium III-800, Celeron" socket_nice="Socket 370";; INTEL_SOCKET_MPGA479M) - cpu_nice="Intel® Mobile Celeron" + cpu_nice="Intel Mobile Celeron" socket_nice="Socket 479" ;; INTEL_SOCKET_RPGA989) case $northbridge in INTEL_HASWELL) - cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7" + cpu_nice="Intel 4th Gen (Haswell) Core i3/i5/i7" socket_nice="Socket RPGA989";; INTEL_IVYBRIDGE_NATIVE|INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE) - cpu_nice="Intel® 3rd Gen (Ivybridge) Core i3/i5/i7" + cpu_nice="Intel 3rd Gen (Ivybridge) Core i3/i5/i7" socket_nice="Socket RPGA989";; INTEL_SANDYBRIDGE) - cpu_nice="Intel® 2nd Gen (Sandybridge) Core i3/i5/i7" + cpu_nice="Intel 2nd Gen (Sandybridge) Core i3/i5/i7" socket_nice="Socket RPGA989";; *) cpu_nice="$northbridge" @@ -330,39 +330,39 @@ EOF esac ;; INTEL_SOCKET_441) - cpu_nice="Intel® Atom™ 230"; + cpu_nice="Intel Atom 230"; socket_nice="Socket 441";; INTEL_SOCKET_BGA956) case $northbridge in INTEL_GM45) - cpu_nice="Intel® Core 2 Duo (Penryn)" + cpu_nice="Intel Core 2 Duo (Penryn)" socket_nice="Socket P";; *) - cpu_nice="Intel® Pentium® M"; + cpu_nice="Intel Pentium M"; socket_nice="BGA956";; esac ;; INTEL_SOCKET_FC_PGA370) - cpu_nice="Intel® Pentium® III / Celeron®"; + cpu_nice="Intel Pentium III / Celeron"; socket_nice="Socket 370" ;; INTEL_EP80579) - cpu_nice="Intel® EP80579"; - socket_nice="Intel® EP80579" + cpu_nice="Intel EP80579"; + socket_nice="Intel EP80579" ;; INTEL_SOCKET_MFCBGA479) - cpu_nice="Intel® Mobile Celeron" + cpu_nice="Intel Mobile Celeron" socket_nice="Socket 479";; VIA_C3) - cpu_nice="VIA C3™"; + cpu_nice="VIA C3"; socket_nice="?" ;; VIA_C7) - cpu_nice="VIA C7™"; + cpu_nice="VIA C7"; socket_nice="?" ;; VIA_NANO) - cpu_nice="VIA Nano™"; + cpu_nice="VIA Nano"; socket_nice="?" ;; QEMU_X86) @@ -372,7 +372,7 @@ EOF "") case $northbridge in INTEL_NEHALEM) - cpu_nice="Intel® 1st Gen (Nehalem) Core i3/i5/i7" + cpu_nice="Intel 1st Gen (Nehalem) Core i3/i5/i7" socket_nice="?";; RDC_R8610) cpu_nice="RDC 8610"

1 0

Patch set updated for coreboot: c328ebc [Do not Merge] try to add i945G based board
by HAOUAS Elyes 03 May '15

03 May '15

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9971 -gerrit commit c328ebcfb5454c7a5cc62c7a6a8b9ea642ae2e5f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Apr 23 12:10:17 2015 +0200 [Do not Merge] try to add i945G based board here is the serial log: https://www.dropbox.com/home?preview=log.+03052015.txt "No Preamble found (neither high nor low)." Change-Id: I97401a39a958a17f2f9120539362e3fa7819a742 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/nec/945g-m4/Kconfig | 42 +++++ src/mainboard/nec/945g-m4/Kconfig.name | 2 + src/mainboard/nec/945g-m4/acpi/ec.asl | 1 + src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl | 83 +++++++++ src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 ++++++++++++ src/mainboard/nec/945g-m4/acpi/platform.asl | 90 ++++++++++ src/mainboard/nec/945g-m4/acpi/superio.asl | 92 ++++++++++ src/mainboard/nec/945g-m4/acpi/thermal.asl | 94 +++++++++++ src/mainboard/nec/945g-m4/acpi/video.asl | 43 +++++ src/mainboard/nec/945g-m4/acpi_tables.c | 77 +++++++++ src/mainboard/nec/945g-m4/board_info.txt | 7 + src/mainboard/nec/945g-m4/cmos.layout | 194 +++++++++++++++++++++ src/mainboard/nec/945g-m4/devicetree.cb | 116 +++++++++++++ src/mainboard/nec/945g-m4/dsdt.asl | 44 +++++ src/mainboard/nec/945g-m4/hda_verb.c | 5 + src/mainboard/nec/945g-m4/irq_tables.c | 61 +++++++ src/mainboard/nec/945g-m4/mainboard.c | 94 +++++++++++ src/mainboard/nec/945g-m4/mptable.c | 106 ++++++++++++ src/mainboard/nec/945g-m4/romstage.c | 205 +++++++++++++++++++++++ src/mainboard/nec/945g-m4/smihandler.c | 49 ++++++ src/mainboard/nec/945g-m4/superio_hwm.c | 161 ++++++++++++++++++ src/mainboard/nec/945g-m4/superio_hwm.h | 25 +++ src/northbridge/intel/i945/early_init.c | 5 +- src/northbridge/intel/i945/gma.c | 14 +- src/northbridge/intel/i945/raminit.c | 91 +++++++--- 25 files changed, 1771 insertions(+), 33 deletions(-) diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig new file mode 100644 index 0000000..791a8f9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig @@ -0,0 +1,42 @@ +if BOARD_NEC_945G_M4 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627EHG + select HAVE_ACPI_TABLES + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + +config MAINBOARD_DIR + string + default nec/945g-m4 + +config MAINBOARD_PART_NUMBER + string + default "945G-M4" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 4 + +#config VGA_BIOS_FILE +# string +# default "amipci_01.20" +endif # BOARD_NEC_945G_M4 diff --git a/src/mainboard/nec/945g-m4/Kconfig.name b/src/mainboard/nec/945g-m4/Kconfig.name new file mode 100644 index 0000000..46571f0 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_NEC_945G_M4 + bool "945G-M" diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl new file mode 100644 index 0000000..8f20f9d --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ec.asl @@ -0,0 +1 @@ +//to make the compiler happy diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..fb57b5e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for i945G */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 10 }, + Package() { 0x0001ffff, 1, 0, 11 }, + Package() { 0x0001ffff, 2, 0, 12 }, + Package() { 0x0001ffff, 3, 0, 13 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 10 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 10 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 10 }, + Package() { 0x001cffff, 1, 0, 11 }, + Package() { 0x001cffff, 2, 0, 12 }, + Package() { 0x001cffff, 3, 0, 13 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 17 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 13 }, + Package() { 0x001dffff, 3, 0, 12 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 11 }, + Package() { 0x001effff, 1, 0, 24 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 12 }, + Package() { 0x001fffff, 1, 0, 13 }, + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..c108d3f --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16}, + + Package() { 0x0001ffff, 0, 0, 20}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 22}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + Package() { 0x0002ffff, 2, 0, 23}, + Package() { 0x0002ffff, 3, 0, 20}, + + Package() { 0x0003ffff, 0, 0, 22}, + Package() { 0x0003ffff, 1, 0, 23}, + Package() { 0x0003ffff, 2, 0, 20}, + Package() { 0x0003ffff, 3, 0, 21}, + + Package() { 0x0004ffff, 0, 0, 23}, + Package() { 0x0004ffff, 1, 0, 20}, + Package() { 0x0004ffff, 2, 0, 21}, + Package() { 0x0004ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 19}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 17}, + Package() { 0x0005ffff, 3, 0, 16}, + + Package() { 0x0006ffff, 0, 0, 18}, + Package() { 0x0006ffff, 1, 0, 17}, + Package() { 0x0006ffff, 2, 0, 16}, + Package() { 0x0006ffff, 3, 0, 19}, + + Package() { 0x0009ffff, 0, 0, 21}, + Package() { 0x0009ffff, 1, 0, 22}, + Package() { 0x0009ffff, 2, 0, 23}, + Package() { 0x0009ffff, 3, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl new file mode 100644 index 0000000..6770348 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/platform.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl new file mode 100644 index 0000000..997a33a --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/superio.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_DDN, "COM1") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_DDN, "COM2") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl new file mode 100644 index 0000000..d1774d4 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x64) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Method (_AC1, 0, Serialized) + // { + // Return (0xf5c) + // } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (Add (0x0aac, 0x50)) // FIXME + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (0xaaf) // FIXME + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Return (0xaac) // FIXME + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU1, \_PR.CPU2}) + } + Return (Package() {\_PR.CPU1}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c new file mode 100644 index 0000000..dba2953 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi_tables.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> + +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt new file mode 100644 index 0000000..8c6f8c8 --- /dev/null +++ b/src/mainboard/nec/945g-m4/board_info.txt @@ -0,0 +1,7 @@ +Board name:945G-M4 (Rev: B) +Category: µATX 24.4 cm x 24.4 cm Form Factor +Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=d… +ROM package: PLCC +ROM protocol: FWH +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout new file mode 100644 index 0000000..b3e8c4e --- /dev/null +++ b/src/mainboard/nec/945g-m4/cmos.layout @@ -0,0 +1,194 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 40 r 0 unused + +# coreboot config options: mainboard specific options +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature + +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 + +#971 13 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# Fan Cruise Control +8 0 Disabled +8 1 Speed +#8 2 Thermal +# Fan Speed (Rotations per Minute) +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 +# +# Temperature (�C/�F) +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb new file mode 100644 index 0000000..550195d --- /dev/null +++ b/src/mainboard/nec/945g-m4/devicetree.cb @@ -0,0 +1,116 @@ +chip northbridge/intel/i945 + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + end + device domain 0 on + device pci 00.0 on end # 82945G/GZ/P/PL Memory Controller Hub [8086:2770] + device pci 02.0 on end # 82945G/GZ Integrated Graphics Controller [8086:2772] + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8a" + register "pirqb_routing" = "0x85" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x87" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" + + device pci 1c.0 on end # PCI Express Gigabit Ethernet Controller [10ec:8168] + device pci 1d.0 on end # NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] + device pci 1d.1 on end # NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9] + device pci 1d.2 on end # NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca] + device pci 1d.3 on end # NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb] + device pci 1d.7 on end # NM10/ICH7 Family USB2 EHCI Controller [8086:27cc] + device pci 1e.0 on end # 82801 PCI Bridge [8086:244e] + device pci 1e.2 on end # 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de] + device pci 1f.0 on # 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] + + chip superio/winbond/w83627ehg # Super I/O Winbond + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.5 on # Keyboard + end + + device pnp 2e.106 on # Serial flash interface + io 0x60 = 0x100 + end + + device pnp 2e.007 on # GPIO 1 + end + + device pnp 2e.107 off # Game port + io 0x60 = 0x201 + end + + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + + device pnp 2e.307 on # GPIO 6 + end + + device pnp 2e.8 off # WDTO#, PLED + end + + device pnp 2e.009 on # GPIO 2 + end + + device pnp 2e.109 on # GPIO 3 + end + + device pnp 2e.209 on # GPIO 4 + end + + device pnp 2e.309 on # GPIO 5 + end + + device pnp 2e.a on # ACPI + end + + device pnp 2e.b on # Hardware monitor + io 0x60 = 0xa10 + irq 0x70 = 0 + end + + end # Winbond + end # LPC + + device pci 1f.1 on end # 82801G (ICH7 Family) IDE Controller [8086:27df] + device pci 1f.2 on end # NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0] + device pci 1f.3 on end # NM10/ICH7 Family SMBus Controller [8086:27da] + end # i82801gx + end # domain 0 +end diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl new file mode 100644 index 0000000..05a93d3 --- /dev/null +++ b/src/mainboard/nec/945g-m4/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + //#include "acpi/platform.asl" + + // General Purpose Events + //#include "acpi/gpe.asl" + + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/nec/945g-m4/hda_verb.c b/src/mainboard/nec/945g-m4/hda_verb.c new file mode 100644 index 0000000..aaa0a93 --- /dev/null +++ b/src/mainboard/nec/945g-m4/hda_verb.c @@ -0,0 +1,5 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; +const u32 pc_beep_verbs[0] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c new file mode 100644 index 0000000..4b050fe --- /dev/null +++ b/src/mainboard/nec/945g-m4/irq_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 14, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0}, + {0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0}, + {0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0}, + {0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0}, + {0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0}, + {0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c new file mode 100644 index 0000000..d872d95 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mainboard.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include "superio_hwm.h" + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + // M.x86.R_AX = 0x015f; // Supported but failed + X86_AX = 0x005f; // Success + X86_CL = 3; // Display ID + break; + default: + /* Interrupt was not handled */ + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif +/* Audio Setup */ + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + // Default VERB is fine on this mainboard. + cim_verb_data = NULL; + cim_verb_data_size = 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +// hwm_setup(); /* commented while debugging */ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c new file mode 100644 index 0000000..7276028 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mptable.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#define INTA 0x00 +#define INTB 0x01 +#define INTC 0x02 +#define INTD 0x03 +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LOCAL_APIC_ADDR); + smp_write_processors(mc); + /* Bus: Bus ID Type */ + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 2, "PCI "); + my_smp_write_bus(mc, 3, "PCI "); + my_smp_write_bus(mc, 4, "ISA "); + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 0x1, 0x20, VIO_APIC_VADDR); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13); + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); +/* mptable_lintsrc(mc, isa_bus); */ + /* Compute the checksums */ + return mptable_finalize(mc); +} +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 1); + return (unsigned long)smp_write_config_table(v); +} +/*MP Config Extended Table Entries: +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x600000000000 + address range: 0x148000000000 +Extended Table HOSED! +*/ diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c new file mode 100644 index 0000000..adcccbe --- /dev/null +++ b/src/mainboard/nec/945g-m4/romstage.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/romstage.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <halt.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void setup_ich7_gpios(void) +{ + + printk(BIOS_DEBUG, "GPIOS..."); + /* General Registers */ + outl(0x1f9fffc3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffffbf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x0000af03, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000000f7, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(LPC_DEV, 0x64, 0xd0); + // LPC I/O decode range + pci_write_config16(LPC_DEV, 0x80, 0x0010); + // LPC Interface Enables + pci_write_config16(LPC_DEV, 0x82, 0x340f); + // GEN1_DEC. LPC interface generic decode Rang1 + pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); + // GEN2_DEC. LPC interface generic decode Rang2 + pci_write_config32(LPC_DEV, 0x88, 0x00fc4701); + +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(RC) |= (1 << 2);// to check if we need to enable it once again on RAM init + RCBA32(D31IP) = 0x42210; + RCBA32(D30IP) = 0x2100; + RCBA32(D29IP) = 0x10004321; + RCBA32(D28IP) = 0x214321; + RCBA32(D27IP) = 1; + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x0146; + RCBA32(D29IR) = 0x0237; + RCBA32(D28IR) = 0x3201; + RCBA32(D27IR) = 0x0146; + reg32 = RCBA32(0x020c); + reg32 &= 0x7fc0c0c0; + reg32 |= 0x10804; + RCBA32(0x020c)= reg32; + reg32 = RCBA32(RPC + 4); + reg32 &= 0xebffffff; + reg32 |= 0x28000000; + RCBA32(RPC + 4) = reg32; + RCBA32(0x214) = 0x10030549; + RCBA32(0x218) = 0x00020504; + RCBA32(0x220 /*BCR*/) = 0xffffffc5; + reg32 = RCBA32(0x2024 /*CIR6*/); + reg32 &= 0xffffff; + reg32 |= 0xd000000; + RCBA32(0x2024 /*CIR6*/) = reg32; + RCBA32(0x1ac) |= 2; + reg32 = RCBA32(0x200 /*CIR4*/); + reg32 &= 0xc1d0e0c8; + reg32 |= 0x1102008; + RCBA32(0x200 /*CIR4*/) = reg32; + RCBA16(0x208c) |= 0xf0000; + RCBA16(0x20ac) |= 0xf0000; + RCBA16(0x20cc) |= 0xf0000; + RCBA16(0x20ec) |= 0xf0000; + reg8 = RCBA8(0x3430 /*CIR8*/); + reg8 &= 0xfc; + reg8 |= 1; + RCBA8(0x3430 /*CIR8*/) = reg8; + RCBA32(GCS) |= (1 << 2); + RCBA32(0x0088 /*CIR1*/) |= 0x0011d000; + RCBA16(0x01fc /*CIR3*/) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + + reg32 = RCBA32(0x3410 /*GCS*/); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + RCBA32(FD /*0x3418*/) |= (1 << 0); + RCBA32(0x3418/*FD*/) |= (1 << 0); + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + RCBA32(HPTC /*0x3404*/) = 0x80; + //reg32 = RCBA32(0x2034 /*CIR7*/); + //reg32 &= ~(0x0f << 16); + //reg32 |= (5 << 16); + //RCBA32(0x2034 /*CIR7*/) = reg32; +} + +void main(unsigned long bist) +{ + int s3resume = 0; +device_t dev; + if (bist == 0) + enable_lapic(); + + ich7_enable_lpc(); + /* Set up the console */ +// winbond_enable_serial(SERIAL_DEV,CONFIG_TTYS0_BASE); + + dev=PNP_DEV(0x2e, W83627EHG_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + console_init(); + + report_bist_failure(bist); + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + halt(); + } + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + + i945_early_initialization(); + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(s3resume ? 2 : 0, NULL); + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + /* Chipset Errata! */ +sdram_dump_mchbar_registers(); + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); +sdram_dump_mchbar_registers(); +} diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c new file mode 100644 index 0000000..d1f4f7b --- /dev/null +++ b/src/mainboard/nec/945g-m4/smihandler.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801gx/nvs.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c new file mode 100644 index 0000000..622f8e8 --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <arch/io.h> +#include <pc80/mc146818rtc.h> + +#include "superio_hwm.h" + +/* Hardware Monitor */ + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +#define HWM_BASE 0x290 + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, HWM_BASE + 0x05); // Index port + outb(value, HWM_BASE + 0x06); // Data port +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x2e, bank); +} + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h new file mode 100644 index 0000000..346b97c --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +void hwm_setup(void); + +#endif /* SUPERIO_HWM_H */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ea92ce1..f529919 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -810,7 +810,7 @@ static void i945_setup_root_complex_topology(void) printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); /* Egress Port Root Topology */ - +if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) != 0x2770){ reg32 = EPBAR32(EPESD); reg32 &= 0xff00ffff; reg32 |= (1 << 16); @@ -821,7 +821,7 @@ static void i945_setup_root_complex_topology(void) EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); - +} /* DMI Port Root Topology */ reg32 = DMIBAR32(DMILE1D); @@ -922,6 +922,7 @@ static void i945_prepare_resume(int s3resume) void i945_late_initialization(int s3resume) { + //if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) != 0x2770) i945_setup_egress_port(); ich7_setup_root_complex_topology(); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e5f2d35..4f3cdf2 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -519,23 +519,27 @@ static struct device_operations gma_func1_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { +static const unsigned short i945_gma_func0_ids[] = { 0x2772, - 0x2776, 0x27a2, - 0x27a6, 0x27ae, 0 }; +static const unsigned short i945_gma_func1_ids[] = { + 0x2776, + 0x27a6, + 0 +}; + static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func1_ids, }; diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index bd6e0c9..defadbd 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -113,11 +113,13 @@ static int memclk(void) #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM offset++; #endif +if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) + offset = 0; switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { case 1: return 400; case 2: return 533; case 3: return 667; - default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset); + default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", MCHBAR32(CLKCFG));// >> 4) & 7) - offset); } return -1; } @@ -211,15 +213,16 @@ static int sdram_capabilities_enhanced_addressing_xor(void) return (!reg8); } -static int sdram_capabilities_two_dimms_per_channel(void) -{ - u8 reg8; - - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */ - reg8 &= (1 << 0); +//static int sdram_capabilities_two_dimms_per_channel(void) +//{ +// u8 reg8; +//if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) +// return (1); /* this board support 2 dimms per channel */ +// reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */ +// reg8 &= (1 << 0); +// return (reg8 != 0); - return (reg8 != 0); -} +//} // TODO check if we ever need this function #if 0 @@ -384,8 +387,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) continue; /* Two DIMMs per channel not supported, but odd DIMM number? */ - if (!sdram_capabilities_two_dimms_per_channel() && (i& 1)) - continue; +// if (!sdram_capabilities_two_dimms_per_channel() && (i & 1)) +// continue; printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); @@ -1260,8 +1263,20 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ switch (sysinfo->memory_frequency) { case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */ + case 533: + if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + chan0dll = 0x24242424; chan1dll=0x24242424; + }else{ + chan0dll = 0x22222222; chan1dll=0x22222222; + } + break; /* 533MHz */ + case 667: + if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + chan0dll = 0x25252525; chan1dll=0x25252525; + }else{ + chan0dll = 0x11111111; chan1dll=0x11111111; + } + break; /* 667MHz */ } for (i=0; i < 4; i++) { @@ -1306,6 +1321,11 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Initializing System Memory IO... \n"); /* Enable Data Half Clock Pushout */ +if ((pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770)||(pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2778)){ + MCHBAR8(C0HCTC) = 1; + MCHBAR8(C1HCTC) = 1; + +}else{ reg8 = MCHBAR8(C0HCTC); reg8 &= ~0x1f; reg8 |= ( 1 << 0); @@ -1315,7 +1335,7 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo) reg8 &= ~0x1f; reg8 |= ( 1 << 0); MCHBAR8(C1HCTC) = reg8; - +} MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) ); MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0); @@ -1748,13 +1768,13 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) }; reg32 = MCHBAR32(C0DRC0); - reg32 |= (1 << 2); /* Burst Length 8 */ reg32 &= ~( (1 << 13) | (1 << 12) ); + reg32 |= (1 << 2); /* Burst Length 8 */ MCHBAR32(C0DRC0) = reg32; reg32 = MCHBAR32(C1DRC0); - reg32 |= (1 << 2); /* Burst Length 8 */ reg32 &= ~( (1 << 13) | (1 << 12) ); + reg32 |= (1 << 2); /* Burst Length 8 */ MCHBAR32(C1DRC0) = reg32; if (!sysinfo->dual_channel && sysinfo->dimm[1] != @@ -2265,7 +2285,7 @@ static void sdram_program_clock_crossing(void) 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020180, 0x00000008, /* DDR667 FSB800 */ + 0x04020130, 0x00000008, /* DDR667 FSB800 */ 0x00020904, 0x00000000, /* DDR400 FSB1066 */ 0x02010804, 0x00000000, /* DDR533 FSB1066 */ @@ -2326,18 +2346,32 @@ static void sdram_pre_jedec_initialization(void) u32 reg32; reg32 = MCHBAR32(WCC); - reg32 &= 0x113ff3ff; - reg32 |= (4 << 29) | (3 << 25) | (1 << 10); - MCHBAR32(WCC) = reg32; + if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) + { + reg32 &= 0xf3fff7ff; + reg32 |= (1 << 25) | (3 << 22) | (1 << 10); + MCHBAR32(WCC) = reg32; + MCHBAR32(MMARB0) |= (3 << 7)|(3 << 8); + MCHBAR32(MMARB1) |= (1 << 18)|(3 << 12); + if (pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4) & 0x2000 && pci_read_config32(PCI_DEV(0, 0x00,0), 0x54) & 8) + { + MCHBAR32(MMARB1) &= ~(7 << 8); + } + MCHBAR32(MMARB1 +4) |= (3 << 12); + } else { + reg32 &= 0x113ff3ff; + reg32 |= (4 << 29) | (3 << 25) | (1 << 10); - MCHBAR32(SMVREFC) |= (1 << 6); + MCHBAR32(WCC) = reg32; - MCHBAR32(MMARB0) &= ~(3 << 17); - MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16); + MCHBAR32(SMVREFC) |= (1 << 6); - MCHBAR32(MMARB1) &= ~(7 << 8); - MCHBAR32(MMARB1) |= (3 << 8); + MCHBAR32(MMARB0) &= ~(3 << 17); + MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16); + MCHBAR32(MMARB1) &= ~(7 << 8); + MCHBAR32(MMARB1) |= (3 << 8); + } /* Adaptive Idle Timer Control */ MCHBAR32(C0AIT) = 0x000006c4; MCHBAR32(C0AIT+4) = 0x871a066d; @@ -2617,6 +2651,11 @@ static void sdram_power_management(struct sys_info *sysinfo) reg8 |= (1 << 2); pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); +if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) { + MCHBAR16(MIPMC4) |= 0x6000; + MCHBAR16(MIPMC5) |= 0x6000; + MCHBAR16(MIPMC6) |= 0x6000; +}else{ #ifdef C2_SELF_REFRESH_DISABLE if (integrated_graphics) { @@ -2641,7 +2680,7 @@ static void sdram_power_management(struct sys_info *sysinfo) } #endif - +} reg32 = MCHBAR32(PMCFG); reg32 &= ~(3 << 17); reg32 |= (2 << 17);

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2015