coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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1299 discussions

New patch to review for coreboot: df2e2de veyron_danger: Turn on backlight enable before VCC_LCD
by Patrick Georgi 04 May '15

04 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10089 -gerrit commit df2e2deddeb7e5e79e5b3ea33a47dc4dd39cc4f8 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Apr 22 15:05:18 2015 -0700 veyron_danger: Turn on backlight enable before VCC_LCD On current Danger boards, VCC_LCD is gated by BL_EN. Thus we need to enable BL_EN in order to power on the display so that we can read the EDID and set things up. Later board revisions may change this ordering, but for now it doesn't seem to be causing a significant issues (no noticable "snow" or other corruption using Pepto display). BUG=none BRANCH=none TEST=booted on Danger, saw dev mode screen come up Change-Id: I70aab8c1f6da2d0fce310d59073026eef0f67821 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1a918824e747600a2f3a88602320f4f563ce17b7 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Iaf17cc4682bd3c46f62cba789e3ecf8d5a474362 Original-Reviewed-on: https://chromium-review.googlesource.com/266913 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_danger/board.h | 1 + src/mainboard/google/veyron_danger/mainboard.c | 13 ++++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_danger/board.h b/src/mainboard/google/veyron_danger/board.h index 10bcf45..a2f4000 100644 --- a/src/mainboard/google/veyron_danger/board.h +++ b/src/mainboard/google/veyron_danger/board.h @@ -25,6 +25,7 @@ #define GPIO_BACKLIGHT GPIO(7, A, 3) #define GPIO_RESET GPIO(0, B, 5) +#define GPIO_LCDC_BL GPIO(7, A, 7) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/veyron_danger/mainboard.c b/src/mainboard/google/veyron_danger/mainboard.c index b664d55..9bb5cb1 100644 --- a/src/mainboard/google/veyron_danger/mainboard.c +++ b/src/mainboard/google/veyron_danger/mainboard.c @@ -93,6 +93,17 @@ static void configure_vop(void) /* lcdc(vop) iodomain select 1.8V */ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0)); + /* + * BL_EN gates VCC_LCD. This might be changed in future revisions + * of the board so that the display can be stablized before we + * turn on the backlight. + * + * To minimize display corruption, turn off LCDC_BL before + * powering on the backlight. + */ + gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */ + gpio_output(GPIO_LCDC_BL, 0); + rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */ rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */ rk808_configure_switch(1, 1); /* VCC33_LCD */ @@ -135,5 +146,5 @@ void lb_board(struct lb_header *header) void mainboard_power_on_backlight(void) { - gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */ + gpio_output(GPIO_LCDC_BL, 1); }

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New patch to review for coreboot: b6e9982 veyron: Initialize EC interrupt GPIO and add them to coreboot tables
by Patrick Georgi 04 May '15

04 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10088 -gerrit commit b6e9982d909ee634e869e4b713a331b6627254ba Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Apr 24 17:30:36 2015 -0700 veyron: Initialize EC interrupt GPIO and add them to coreboot tables This patch initializes the GPIO for the Chrome EC interrupt line on Veyron boards and passes its description through the coreboot table, so that payloads with keyboard support can use it to detect pending key presses. BRANCH=none BUG=chrome-os-partner:39514 TEST=Booted Jerry, confirmed that it could still detect keypresses. Confirmed that EC log does not show a huge amount of MKBP polls. Change-Id: I4de35ef411c3acc02282ebf8e764785a1e7bf6f1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8ad95d667ef3af3fb217e3c370468dc1d6ec36c9 Original-Change-Id: I8b426621af088460929cfff0a4b46618e2a86725 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/267344 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> --- src/mainboard/google/veyron_jerry/chromeos.c | 10 ++++++++++ src/mainboard/google/veyron_mighty/chromeos.c | 10 ++++++++++ src/mainboard/google/veyron_pinky/chromeos.c | 10 ++++++++++ src/mainboard/google/veyron_speedy/chromeos.c | 10 ++++++++++ 4 files changed, 40 insertions(+) diff --git a/src/mainboard/google/veyron_jerry/chromeos.c b/src/mainboard/google/veyron_jerry/chromeos.c index d509a01..e0f816c 100644 --- a/src/mainboard/google/veyron_jerry/chromeos.c +++ b/src/mainboard/google/veyron_jerry/chromeos.c @@ -32,6 +32,7 @@ #define GPIO_POWER GPIO(0, A, 5) #define GPIO_RECOVERY GPIO(0, B, 1) #define GPIO_ECINRW GPIO(0, A, 7) +#define GPIO_ECIRQ GPIO(7, A, 7) void setup_chromeos_gpios(void) { @@ -39,6 +40,7 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_LID); gpio_input(GPIO_POWER); gpio_input_pullup(GPIO_RECOVERY); + gpio_input(GPIO_ECIRQ); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -92,6 +94,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); count++; + /* EC interrupt: GPIO active high */ + gpios->gpios[count].port = GPIO_ECIRQ.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "EC interrupt", + GPIO_MAX_NAME_LENGTH); + count++; + /* Reset: GPIO active high (output) */ gpios->gpios[count].port = GPIO_RESET.raw; gpios->gpios[count].polarity = ACTIVE_HIGH; diff --git a/src/mainboard/google/veyron_mighty/chromeos.c b/src/mainboard/google/veyron_mighty/chromeos.c index d509a01..e0f816c 100644 --- a/src/mainboard/google/veyron_mighty/chromeos.c +++ b/src/mainboard/google/veyron_mighty/chromeos.c @@ -32,6 +32,7 @@ #define GPIO_POWER GPIO(0, A, 5) #define GPIO_RECOVERY GPIO(0, B, 1) #define GPIO_ECINRW GPIO(0, A, 7) +#define GPIO_ECIRQ GPIO(7, A, 7) void setup_chromeos_gpios(void) { @@ -39,6 +40,7 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_LID); gpio_input(GPIO_POWER); gpio_input_pullup(GPIO_RECOVERY); + gpio_input(GPIO_ECIRQ); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -92,6 +94,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); count++; + /* EC interrupt: GPIO active high */ + gpios->gpios[count].port = GPIO_ECIRQ.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "EC interrupt", + GPIO_MAX_NAME_LENGTH); + count++; + /* Reset: GPIO active high (output) */ gpios->gpios[count].port = GPIO_RESET.raw; gpios->gpios[count].polarity = ACTIVE_HIGH; diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c index dd781aa..b64bae0 100644 --- a/src/mainboard/google/veyron_pinky/chromeos.c +++ b/src/mainboard/google/veyron_pinky/chromeos.c @@ -32,6 +32,7 @@ #define GPIO_POWER GPIO(0, A, 5) #define GPIO_RECOVERY GPIO(0, B, 1) #define GPIO_ECINRW GPIO(0, A, 7) +#define GPIO_ECIRQ GPIO(7, A, 7) void setup_chromeos_gpios(void) { @@ -39,6 +40,7 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_LID); gpio_input(GPIO_POWER); gpio_input_pullup(GPIO_RECOVERY); + gpio_input(GPIO_ECIRQ); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -93,6 +95,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); count++; + /* EC interrupt: GPIO active high */ + gpios->gpios[count].port = GPIO_ECIRQ.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "EC interrupt", + GPIO_MAX_NAME_LENGTH); + count++; + /* Reset: GPIO active high (output) */ gpios->gpios[count].port = GPIO_RESET.raw; gpios->gpios[count].polarity = ACTIVE_HIGH; diff --git a/src/mainboard/google/veyron_speedy/chromeos.c b/src/mainboard/google/veyron_speedy/chromeos.c index d509a01..e0f816c 100644 --- a/src/mainboard/google/veyron_speedy/chromeos.c +++ b/src/mainboard/google/veyron_speedy/chromeos.c @@ -32,6 +32,7 @@ #define GPIO_POWER GPIO(0, A, 5) #define GPIO_RECOVERY GPIO(0, B, 1) #define GPIO_ECINRW GPIO(0, A, 7) +#define GPIO_ECIRQ GPIO(7, A, 7) void setup_chromeos_gpios(void) { @@ -39,6 +40,7 @@ void setup_chromeos_gpios(void) gpio_input_pullup(GPIO_LID); gpio_input(GPIO_POWER); gpio_input_pullup(GPIO_RECOVERY); + gpio_input(GPIO_ECIRQ); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -92,6 +94,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); count++; + /* EC interrupt: GPIO active high */ + gpios->gpios[count].port = GPIO_ECIRQ.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "EC interrupt", + GPIO_MAX_NAME_LENGTH); + count++; + /* Reset: GPIO active high (output) */ gpios->gpios[count].port = GPIO_RESET.raw; gpios->gpios[count].polarity = ACTIVE_HIGH;

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Patch merged into coreboot/master: 99cc1aa Mediawiki editing warning
by gerrit＠coreboot.org 04 May '15

04 May '15

the following patch was just integrated into master: commit 99cc1aacc68e6458e2465842c3afe4d684970d1b Author: David Englund <public(a)beloved.name> Date: Sat Mar 14 19:41:09 2015 +0100 Mediawiki editing warning The file have been updated to warn wiki users to edit the page as it is generated by a bot. Change-Id: I5802ff8c7986c0fd93adf58e2353df81de9c2b75 Signed-off-by: David Englund <public(a)beloved.name> Reviewed-on: http://review.coreboot.org/8682 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8682 for details. -gerrit

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Patch set updated for coreboot: cea404e Mediawiki editing warning
by Patrick Georgi 04 May '15

04 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8682 -gerrit commit cea404e9a8cbe6c97c8dd2e383c4f90818aac4a8 Author: David Englund <public(a)beloved.name> Date: Sat Mar 14 19:41:09 2015 +0100 Mediawiki editing warning The file have been updated to warn wiki users to edit the page as it is generated by a bot. Change-Id: I5802ff8c7986c0fd93adf58e2353df81de9c2b75 Signed-off-by: David Englund <public(a)beloved.name> --- util/board_status/to-wiki/foreword.wiki | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/board_status/to-wiki/foreword.wiki b/util/board_status/to-wiki/foreword.wiki index be05c8c..925646f 100644 --- a/util/board_status/to-wiki/foreword.wiki +++ b/util/board_status/to-wiki/foreword.wiki @@ -1,3 +1,6 @@ +This page was automatically generated. Please do not edit, any edits will be overwritten by an +automatic utility. + = coreboot status by mainboard = * This list contains reports of successful coreboot execution, ordered by date. It's shows which boards can actually run with current coreboot versions.

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Patch merged into coreboot/master: e9b7e25 util/xcompile/xcompile: Allow to override `HOSTCC` variable
by gerrit＠coreboot.org 04 May '15

04 May '15

the following patch was just integrated into master: commit e9b7e25708db1eb234c87def87a8e4e9b5c03b28 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Apr 9 18:15:09 2015 +0200 util/xcompile/xcompile: Allow to override `HOSTCC` variable Currently `xcompile` generates `.xcompile` with the following at the top. # platform agnostic and host tools IASL:=iasl HOSTCC:=gcc The assignment `:=` doesn’t allow to override the variable. So use `?=` instead so the host compiler can be passed to coreboot. HOSTCC=gcc-5 make Note, that this is just a hack, as the existence of `gcc` is checked beforehand. Change-Id: Iebf3e43eb7eaffa7cf0efe97710d9feb3fe2a989 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/9457 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9457 for details. -gerrit

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Patch merged into coreboot/master: 939dc84 crossgcc: Re-download the archive if it is incomplete
by gerrit＠coreboot.org 04 May '15

04 May '15

the following patch was just integrated into master: commit 939dc8492ae80858575db3e808baf18f5ab651a0 Author: zbao <fishbaozi(a)gmail.com> Date: Thu Apr 30 04:44:07 2015 +0800 crossgcc: Re-download the archive if it is incomplete If the buildgcc is interrupt by Ctrl-C, probably part of an archive is downloaded. If we run buildgcc again, the incomplete archive would be considered as cached file and skipped. We check file hashes to see if the file is complete. If test is failed, we need to delete the partially-downloaded file and download it again. sha1sum is quite different among the distributions. Only Linux, Cygwin, Darwin have been tested. Once new archive is deployed, a new checksum would be created, which should be uploaded along with the script buildgcc. Change-Id: Ibb1aa25a0374f774e1e643fe5e698de7bf7cc418 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/4511 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/4511 for details. -gerrit

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Patch set updated for coreboot: 07dc67f drivers/spi/stmicro: Rename N25Q256A to N25Q256
by Patrick Georgi 04 May '15

04 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10078 -gerrit commit 07dc67f7092f32486881347bd35839cc125e189d Author: David Imhoff <dimhoff_devel(a)xs4all.nl> Date: Sun May 3 16:57:38 2015 +0200 drivers/spi/stmicro: Rename N25Q256A to N25Q256 The 'A' indicates the production process(64 nm). All other chips from the same family leave this out. TEST=Build and booted on Minnowboard Max Change-Id: I21e6c01de5d547bbc2252e679a001948e7ab752c Signed-off-by: David Imhoff <dimhoff_devel(a)xs4all.nl> --- src/drivers/spi/stmicro.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index ab21f8f..37907f6 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -57,7 +57,7 @@ #define STM_ID_M25P64 0x2017 #define STM_ID_M25P80 0x2014 #define STM_ID_M25P128 0x2018 -#define STM_ID_N25Q256A 0xba19 +#define STM_ID_N25Q256 0xba19 #define STM_ID_N25Q064 0xbb17 #define STM_ID_N25Q128 0xbb18 @@ -164,12 +164,12 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { .name = "N25Q128", }, { - .device_id = STM_ID_N25Q256A, + .device_id = STM_ID_N25Q256, .op_erase = CMD_M25PXX_SSE, .page_size = 256, .pages_per_sector = 16, .nr_sectors = 8192, - .name = "N25Q256A", + .name = "N25Q256", }, };

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Patch merged into coreboot/master: 6548ae9 cbfstool/Makefile*: Use `LDFLAGS` instead of `LINKFLAGS`
by gerrit＠coreboot.org 04 May '15

04 May '15

the following patch was just integrated into master: commit 6548ae9f99beba89f3dcf5c7b0c86c75d5c0ab5c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 3 09:35:32 2015 +0200 cbfstool/Makefile*: Use `LDFLAGS` instead of `LINKFLAGS` Commit 0e53931f (cbfstool: Clean up in preparation for adding new files) split out the flags and introduced the variable `LINKFLAGS`. Rename it to `LDFLAGS` which is more commonly used. Change-Id: Ib6299f8ef5cf30dbe05bfae36f30ae4371f0a738 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10064 Tested-by: build bot (Jenkins) Reviewed-by: Sol Boucher <solb(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10064 for details. -gerrit

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New patch to review for coreboot: 51ff374 make: improve building out of tree
by Vadim Bendebury 04 May '15

04 May '15

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10087 -gerrit commit 51ff374d534fe61d3668b4ccaddaae8f7d5d861f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun Apr 26 18:39:37 2015 -0700 make: improve building out of tree When trying to build out of tree and specifying a relative path to a directory somewhere above the source code root, make fails as follows: $ make obj=../build/peppy ... No rule to make target `<full_path_to>/build/peppy/mainboard/google/peppy/static.c', needed by `<full_path_to>/build/peppy/mainboard/google/peppy/static.romstage.o'. Stop Invoking make using the full path to the build directory works fine: $ make obj=<full_path_to>/build/peppy With the suggested change make proceeds much further with either way of specifying build directory location. It succeeds if obj= is specified as the full path, but still fails to build if it is specified as a relative path. The failure is different though - for some reason linker complaints about multiple definitions of certain names. That other failure will have to be investigated separately, this patch allows the build to go much further and should be merged on its own merits. Change-Id: I583a18d9bb52d2cfba818fb47931c6ccbc615256 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 6403977..46a93f8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -339,7 +339,8 @@ $(BIMGTOOL): $(top)/util/bimgtool/bimgtool.c ####################################################################### # needed objects that every mainboard uses # Creation of these is architecture and mainboard independent -$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig +$(abspath $(obj)/mainboard/$(MAINBOARDDIR)/static.c): \ + $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR)

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Patch set updated for coreboot: 7412790 mainboard/intel/d510mo: Add Intel D510MO mainboard
by Damien Zammit 04 May '15

04 May '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10074 -gerrit commit 7412790f87988716b9c8a54be69eed2bc01f5272 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon May 4 10:41:21 2015 +1000 mainboard/intel/d510mo: Add Intel D510MO mainboard Board currently has no raminit, (but uses Pineview minimal northbridge). Board boots to UART console. Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/Kconfig | 57 ++++++++++++++ src/mainboard/intel/d510mo/Kconfig.name | 2 + src/mainboard/intel/d510mo/acpi/ec.asl | 49 ++++++++++++ src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl | 82 +++++++++++++++++++ src/mainboard/intel/d510mo/acpi/mainboard.asl | 34 ++++++++ src/mainboard/intel/d510mo/acpi/superio.asl | 45 +++++++++++ src/mainboard/intel/d510mo/acpi_tables.c | 66 ++++++++++++++++ src/mainboard/intel/d510mo/board_info.txt | 5 ++ src/mainboard/intel/d510mo/devicetree.cb | 77 ++++++++++++++++++ src/mainboard/intel/d510mo/dsdt.asl | 55 +++++++++++++ src/mainboard/intel/d510mo/hda_verb.c | 7 ++ src/mainboard/intel/d510mo/romstage.c | 95 +++++++++++++++++++++++ 12 files changed, 574 insertions(+) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig new file mode 100644 index 0000000..aed13db --- /dev/null +++ b/src/mainboard/intel/d510mo/Kconfig @@ -0,0 +1,57 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +if BOARD_INTEL_D510MO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_ATOM_D5XX + select CPU_MICROCODE_CBFS_NONE + select NORTHBRIDGE_INTEL_PINEVIEW + #select NORTHBRIDGE_INTEL_SUBTYPE_I945GM + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627THG + #select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES + select BROKEN_CAR_MIGRATE + #select USE_WATCHDOG_ON_BOOT + #select UDELAY_TSC + select EARLY_CBMEM_INIT + select BOARD_ROMSIZE_KB_1024 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 + +config MAINBOARD_DIR + string + default intel/d510mo + +config MAINBOARD_PART_NUMBER + string + default "D510MO" + +config IRQ_SLOT_COUNT + int + default 7 + +endif # BOARD_INTEL_D510MO diff --git a/src/mainboard/intel/d510mo/Kconfig.name b/src/mainboard/intel/d510mo/Kconfig.name new file mode 100644 index 0000000..2df0dca --- /dev/null +++ b/src/mainboard/intel/d510mo/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_D510MO + bool "D510MO" diff --git a/src/mainboard/intel/d510mo/acpi/ec.asl b/src/mainboard/intel/d510mo/acpi/ec.asl new file mode 100644 index 0000000..31c7001 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/ec.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..74c1ca0 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 21}, + Package() { 0x0000ffff, 1, 0, 22}, + Package() { 0x0000ffff, 2, 0, 23}, + Package() { 0x0000ffff, 3, 0, 20}, + + Package() { 0x0001ffff, 0, 0, 22}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 20}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 18}, + Package() { 0x0002ffff, 1, 0, 19}, + Package() { 0x0002ffff, 2, 0, 17}, + Package() { 0x0002ffff, 3, 0, 16}, + + Package() { 0x0003ffff, 0, 0, 19}, + Package() { 0x0003ffff, 1, 0, 18}, + Package() { 0x0003ffff, 2, 0, 21}, + Package() { 0x0003ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 17}, + Package() { 0x0005ffff, 1, 0, 20}, + Package() { 0x0005ffff, 2, 0, 22}, + Package() { 0x0005ffff, 3, 0, 21}, + + Package() { 0x0008ffff, 0, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/intel/d510mo/acpi/mainboard.asl b/src/mainboard/intel/d510mo/acpi/mainboard.asl new file mode 100644 index 0000000..73189be --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/mainboard.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} diff --git a/src/mainboard/intel/d510mo/acpi/superio.asl b/src/mainboard/intel/d510mo/acpi/superio.asl new file mode 100644 index 0000000..d615242 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/superio.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c new file mode 100644 index 0000000..35c23a5 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi_tables.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <arch/ioapic.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/intel/d510mo/board_info.txt b/src/mainboard/intel/d510mo/board_info.txt new file mode 100644 index 0000000..192798a --- /dev/null +++ b/src/mainboard/intel/d510mo/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb new file mode 100644 index 0000000..7fca8b4 --- /dev/null +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +chip northbridge/intel/pineview # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/model_106cx # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # Integrated graphics controller + chip southbridge/intel/i82801gx # Southbridge + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 off end # Floppy + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 4e.a on end # ACPI + device pnp 4e.b on # HWM + io 0x60 = 0x290 + end + end + end + device pci 1f.1 off end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl new file mode 100644 index 0000000..b6a1b8d --- /dev/null +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + //#include "acpi/platform.asl" + + // global NVS and variables + //#include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + //#include <southbridge/intel/i82801gx/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + //#include "acpi/mainboard.asl" + + // Thermal Zone + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + //#include <northbridge/intel/pineview/acpi/i945.asl> + //#include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + //#include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c new file mode 100644 index 0000000..072a306 --- /dev/null +++ b/src/mainboard/intel/d510mo/hda_verb.c @@ -0,0 +1,7 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c new file mode 100644 index 0000000..1a52405 --- /dev/null +++ b/src/mainboard/intel/d510mo/romstage.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "northbridge/intel/pineview/pineview.h" +#include "cpu/x86/bist.h" +#include <superio/winbond/w83627thg/w83627thg.h> +#include <superio/winbond/common/winbond.h> +#include <lib.h> + +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +/* Early mainboard specific GPIO setup. */ +static void mb_gpio_init(void) +{ + device_t dev; + + /* Southbridge GPIOs. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000fe, DEFAULT_GPIOBASE + 0x30); + outl(0x0000007e, DEFAULT_GPIOBASE + 0x34); + outl(0x000300f3, DEFAULT_GPIOBASE + 0x38); +} + +static void nm10_enable_lpc(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c); +} + +void main(unsigned long bist) +{ + /* + const u8 spd_addrmap[4] = { 0x50, 0x51 }; + */ + + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; + + /* Set southbridge and Super I/O GPIOs. */ + mb_gpio_init(); + + nm10_enable_lpc(); + winbond_enable_serial(SERIAL_DEV, 0x3f8); + console_init(); + + report_bist_failure(bist); + enable_smbus(); + die("Waiting here\n"); + + /* + i945_early_initialization(); + sdram_initialize(0, spd_addrmap); + */ +}

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coreboot-gerrit May 2015