coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

1 participants
1299 discussions

New patch to review for coreboot: 9b1f840 vboot2: Fix compiler flags dropped during verstage/libverstage split
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10098 -gerrit commit 9b1f840e9a726d34bb65161c052ecd7cacd5b102 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot2: Fix compiler flags dropped during verstage/libverstage split verstage still needs to be built with its flags. Change-Id: I125e4be283d3838fc7ce6587bf9996731540d517 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index 29115de..def43ad 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -18,6 +18,7 @@ ## libverstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ +verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ bootblock-y += ../vboot_common.c verstage-y += ../vboot_common.c

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New patch to review for coreboot: d52363f nvidia/tegra132: Fix vboot2 memory layout
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10097 -gerrit commit d52363f5f31b5c6ffc319309c6888ba8b4328ef6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 nvidia/tegra132: Fix vboot2 memory layout bootblock et al were listed twice, which shouldn't happen. Change-Id: I3e6077d70e064ebe74bd4e5e3156f87d548c2fcb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 2fdc38f..18a86e6 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -36,11 +36,9 @@ SECTIONS PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) - BOOTBLOCK(0x40019000, 20K) - VERSTAGE(0x4001E000, 60K) - BOOTBLOCK(0x40019000, 22K) - VERSTAGE(0x4001E800, 58K) - ROMSTAGE(0x4002D000, 76K) + BOOTBLOCK(0x40019000, 24K) + VERSTAGE(0x4001f000, 60K) + ROMSTAGE(0x4002e000, 72K) SRAM_END(0x40040000) DRAM_START(0x80000000)

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New patch to review for coreboot: 74970c8 console: rename do_vtxprintf to do_printk_va_list and use it
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10096 -gerrit commit 74970c8197face6b76d07229b4fc4134b56634b6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 console: rename do_vtxprintf to do_printk_va_list and use it The name is more consistent with what we have elsewhere, and the callsite didn't build at all (with vboot enabled) Change-Id: I3576f3b8f737d360f68b67b6ce1683199948776d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/console/printk.c | 4 +++- src/include/console/console.h | 4 ++-- src/vendorcode/google/chromeos/vboot2/verstage.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index 10a7da2..aab7ff5 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -54,8 +54,10 @@ int do_printk(int msg_level, const char *fmt, ...) } #if IS_ENABLED (CONFIG_CHROMEOS) -void do_vtxprintf(const char *fmt, va_list args) +void do_printk_va_list(int msg_level, const char *fmt, va_list args) { + if (!console_log_level(msg_level)) + return; vtxprintf(wrap_putchar, fmt, args, NULL); console_tx_flush(); } diff --git a/src/include/console/console.h b/src/include/console/console.h index b0971e5..ad93a9a 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -80,9 +80,9 @@ static inline void do_putchar(unsigned char byte) {} /* FIXME: Collision of varargs with AMD headers without guard. */ #include <console/vtxprintf.h> #if __CONSOLE_ENABLE__ -void do_vtxprintf(const char *fmt, va_list args); +void do_printk_va_list(int msg_level, const char *fmt, va_list args); #else -static inline void do_vtxprintf(const char *fmt, va_list args) {}; +static inline void do_printk_va_list(int l, const char *fmt, va_list args) {} #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c index c62c102..019208d 100644 --- a/src/vendorcode/google/chromeos/vboot2/verstage.c +++ b/src/vendorcode/google/chromeos/vboot2/verstage.c @@ -45,7 +45,7 @@ void vb2ex_printf(const char *func, const char *fmt, ...) printk(BIOS_INFO, "VB2:%s() ", func); va_start(args, fmt); - vprintk(BIOS_INFO, fmt, args); + do_printk_va_list(BIOS_INFO, fmt, args); va_end(args); return;

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New patch to review for coreboot: 82263df vboot: Remove vboot_get_payload()
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10095 -gerrit commit 82263dfc277e0355b17871c2bb4b17e61eb32ea6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot: Remove vboot_get_payload() It's not used at all. Change-Id: I97bf02a9277f6ca348443c6886f77b4dfc70da78 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/vendorcode/google/chromeos/chromeos.h | 2 -- src/vendorcode/google/chromeos/vboot_common.c | 35 --------------------------- 2 files changed, 37 deletions(-) diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 3e427b9..57ab640 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -65,10 +65,8 @@ struct romstage_handoff; #if CONFIG_VBOOT_VERIFY_FIRMWARE /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); -void *vboot_get_payload(int *len); #else /* CONFIG_VBOOT_VERIFY_FIRMWARE */ static inline void vboot_verify_firmware(struct romstage_handoff *h) {} -static inline void *vboot_get_payload(int *len) { return NULL; } static inline int vboot_get_handoff_info(void **addr, uint32_t *size) { return -1; diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c index 68aa314..d3a939c 100644 --- a/src/vendorcode/google/chromeos/vboot_common.c +++ b/src/vendorcode/google/chromeos/vboot_common.c @@ -94,41 +94,6 @@ struct vboot_components *vboot_locate_components(struct vboot_region *region) return vbc; } -void *vboot_get_payload(int *len) -{ - struct vboot_handoff *vboot_handoff; - struct firmware_component *fwc; - - if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) - return NULL; /* Let CBFS figure it out. */ - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - - if (vboot_handoff == NULL) - return NULL; - - if (CONFIG_VBOOT_BOOT_LOADER_INDEX >= MAX_PARSED_FW_COMPONENTS) { - printk(BIOS_ERR, "Invalid boot loader index: %d\n", - CONFIG_VBOOT_BOOT_LOADER_INDEX); - return NULL; - } - - fwc = &vboot_handoff->components[CONFIG_VBOOT_BOOT_LOADER_INDEX]; - - /* If payload size is zero fall back to cbfs path. */ - if (fwc->size == 0) - return NULL; - - if (len != NULL) - *len = fwc->size; - - printk(BIOS_DEBUG, "Booting 0x%x byte verified payload at 0x%08x.\n", - fwc->size, fwc->address); - - /* This will leak a mapping. */ - return vboot_get_region(fwc->address, fwc->size, NULL); -} - void vboot_reboot(void) { if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))

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New patch to review for coreboot: 4c2b179 vboot: remove uses of vboot2_verify_firmware()
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10094 -gerrit commit 4c2b179befa59179c1f82b8d0a543f418791fdc5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot: remove uses of vboot2_verify_firmware() The vboot mechanism will be implemented within the program loader subsystem to make it transparent to mainboards and chipsets. Change-Id: Icd0bdcba06cdc30591f9b25068b3fa3a112e58fb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/nyan_blaze/romstage.c | 7 ------- src/mainboard/google/veyron_brain/romstage.c | 6 ------ src/mainboard/google/veyron_danger/romstage.c | 6 ------ src/mainboard/google/veyron_jerry/romstage.c | 6 ------ src/mainboard/google/veyron_mighty/romstage.c | 6 ------ src/mainboard/google/veyron_pinky/romstage.c | 6 ------ src/mainboard/google/veyron_rialto/romstage.c | 6 ------ src/mainboard/google/veyron_speedy/romstage.c | 6 ------ src/soc/broadcom/cygnus/verstage.c | 12 ++---------- src/soc/marvell/bg4cd/bootblock.c | 3 ++- src/soc/nvidia/tegra124/verstage.c | 9 ++------- src/soc/nvidia/tegra132/verstage.c | 8 ++------ 12 files changed, 8 insertions(+), 73 deletions(-) diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 12b2ffb..e56683d 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -95,13 +95,6 @@ static void __attribute__((noinline)) romstage(void) early_mainboard_init(); -#if CONFIG_VBOOT_VERIFY_FIRMWARE - entry = vboot2_load_ramstage(); -#else - early_mainboard_init(); - vboot_verify_firmware(romstage_handoff_find_or_add()); -#endif - run_ramstage(); } diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 4156401..0be99ce 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -117,11 +117,5 @@ void main(void) timestamp_add_now(TS_END_ROMSTAGE); #endif -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) - void *entry = vboot2_load_ramstage(); - if (entry != NULL) - stage_exit(entry); -#endif - run_ramstage(); } diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 9be13fe..d1dfb84 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -127,11 +127,5 @@ void main(void) timestamp_add_now(TS_END_ROMSTAGE); #endif -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) - void *entry = vboot2_load_ramstage(); - if (entry != NULL) - stage_exit(entry); -#endif - run_ramstage(); } diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index e8f54de..0ff4585 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -126,11 +126,5 @@ void main(void) timestamp_add_now(TS_END_ROMSTAGE); #endif -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) - void *entry = vboot2_load_ramstage(); - if (entry != NULL) - stage_exit(entry); -#endif - run_ramstage(); } diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index e8f54de..0ff4585 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -126,11 +126,5 @@ void main(void) timestamp_add_now(TS_END_ROMSTAGE); #endif -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) - void *entry = vboot2_load_ramstage(); - if (entry != NULL) - stage_exit(entry); -#endif - run_ramstage(); } diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 3e88564..742522e 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -134,11 +134,5 @@ void main(void) timestamp_add_now(TS_END_ROMSTAGE); #endif -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) - void *entry = vboot2_load_ramstage(); - if (entry != NULL) - stage_exit(entry); -#endif - run_ramstage(); } diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 9be13fe..d1dfb84 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -127,11 +127,5 @@ void main(void) timestamp_add_now(TS_END_ROMSTAGE); #endif -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) - void *entry = vboot2_load_ramstage(); - if (entry != NULL) - stage_exit(entry); -#endif - run_ramstage(); } diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index 9be13fe..d1dfb84 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -127,11 +127,5 @@ void main(void) timestamp_add_now(TS_END_ROMSTAGE); #endif -#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) - void *entry = vboot2_load_ramstage(); - if (entry != NULL) - stage_exit(entry); -#endif - run_ramstage(); } diff --git a/src/soc/broadcom/cygnus/verstage.c b/src/soc/broadcom/cygnus/verstage.c index b5ec27f..6b166cb 100644 --- a/src/soc/broadcom/cygnus/verstage.c +++ b/src/soc/broadcom/cygnus/verstage.c @@ -19,10 +19,8 @@ #include <arch/cache.h> #include <arch/exception.h> -#include <arch/hlt.h> -#include <arch/stages.h> #include <console/console.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <program_loading.h> void main(void) { @@ -30,11 +28,5 @@ void main(void) console_init(); exception_init(); - - entry = vboot2_verify_firmware(); - - if (entry != (void *)-1) - stage_exit(entry); - - hlt(); + run_romstage(); } diff --git a/src/soc/marvell/bg4cd/bootblock.c b/src/soc/marvell/bg4cd/bootblock.c index 4913a1c..b4de972 100644 --- a/src/soc/marvell/bg4cd/bootblock.c +++ b/src/soc/marvell/bg4cd/bootblock.c @@ -18,10 +18,11 @@ */ #include <console/console.h> +#include <program_loading.h> #include <vendorcode/google/chromeos/chromeos.h> void main(void) { console_init(); - vboot2_verify_firmware(); + run_romstage(); } diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 2d7a953..6b259bf 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -22,11 +22,11 @@ #include <arch/hlt.h> #include <arch/stages.h> #include <console/console.h> +#include <program_loading.h> #include <soc/cache.h> #include <soc/early_configs.h> #include <stdlib.h> #include <symbols.h> -#include <vendorcode/google/chromeos/chromeos.h> static void enable_cache(void) { @@ -51,14 +51,9 @@ static void soc_init(void) static void verstage(void) { - void *entry; - soc_init(); early_mainboard_init(); - - entry = vboot2_verify_firmware(); - if (entry != (void *)-1) - stage_exit(entry); + run_romstage(); } void main(void) diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c index e629eed..baf7fb7 100644 --- a/src/soc/nvidia/tegra132/verstage.c +++ b/src/soc/nvidia/tegra132/verstage.c @@ -23,7 +23,7 @@ #include <arch/stages.h> #include <console/console.h> #include <soc/verstage.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <program_loading.h> void __attribute__((weak)) verstage_mainboard_init(void) { @@ -32,15 +32,11 @@ void __attribute__((weak)) verstage_mainboard_init(void) static void verstage(void) { - void *entry; - console_init(); exception_init(); verstage_mainboard_init(); - entry = vboot2_verify_firmware(); - if (entry != (void *)-1) - stage_exit(entry); + run_romstage(); } void main(void)

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Patch set updated for coreboot: 95289e0 vboot checkopoint
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10059 -gerrit commit 95289e073b665ac285ffd04c277a87b682123654 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot checkopoint Change-Id: I2a43c8a2f8f0626a7635150aa3efc44329a477d9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/Makefile.inc | 9 +- src/arch/arm64/Makefile.inc | 5 +- src/arch/arm64/cpu.c | 6 + src/include/cbfs.h | 2 + src/include/program_loading.h | 1 + src/lib/Makefile.inc | 2 + src/lib/cbfs.c | 2 +- src/lib/cbfs_core.h | 2 + src/lib/loaders/Makefile.inc | 1 + src/lib/loaders/load_and_run_payload.c | 4 +- src/lib/loaders/load_and_run_ramstage.c | 7 +- src/lib/loaders/load_and_run_romstage.c | 7 + src/lib/timestamp.c | 31 ++- src/vendorcode/google/chromeos/chromeos.c | 19 +- src/vendorcode/google/chromeos/vboot2/Kconfig | 8 +- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 22 +- src/vendorcode/google/chromeos/vboot2/common.c | 33 --- src/vendorcode/google/chromeos/vboot2/misc.h | 3 +- .../google/chromeos/vboot2/vboot_handoff.c | 53 ++--- .../google/chromeos/vboot2/vboot_loader.c | 243 +++++++++++++++++++++ src/vendorcode/google/chromeos/vboot2/verstub.c | 107 --------- 21 files changed, 361 insertions(+), 206 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index c05b33e..6e52def 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -61,9 +61,9 @@ bootblock-y += memmove.S bootblock-y += div0.c bootblock-y += clock.c -$(objcbfs)/bootblock.debug: $$(bootblock-objs) $$(VERSTAGE_LIB) +$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(objgenerated)/libverstage.a @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) $(objgenerated)/libverstage.a --end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -73,10 +73,11 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group +verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c verstage-y += memset.S diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 3791ae7..095457e 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -84,11 +84,12 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM64 ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(libverstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(verstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(libverstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c verstage-y += ../../lib/memset.c diff --git a/src/arch/arm64/cpu.c b/src/arch/arm64/cpu.c index cd8dd38..7965577 100644 --- a/src/arch/arm64/cpu.c +++ b/src/arch/arm64/cpu.c @@ -22,6 +22,7 @@ #include <arch/lib_helpers.h> #include <cpu/cpu.h> #include <console/console.h> +#include <smp/node.h> #include "cpu-internal.h" struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; @@ -218,3 +219,8 @@ void arch_cpu_wait_for_action(void) action_queue_complete(q, orig); } } + +int boot_cpu(void) +{ + return cpu_is_bsp(); +} diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 05ce2f7..1d7917c 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -60,6 +60,8 @@ void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset); /* Load a stage from a prog structure. Returns < 0 on error. 0 on success. */ struct prog; int cbfs_load_prog_stage(struct cbfs_media *media, struct prog *prog); +int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, + struct prog *prog, ssize_t offset); /* Simple buffer for streaming media. */ struct cbfs_simple_buffer { diff --git a/src/include/program_loading.h b/src/include/program_loading.h index ca80b0e..5fc0fd6 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -39,6 +39,7 @@ struct buffer_area { }; enum prog_type { + PROG_VERSTAGE, PROG_ROMSTAGE, PROG_RAMSTAGE, PROG_PAYLOAD, diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 82dd5c5..b50e3aa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -33,6 +33,8 @@ bootblock-y += memcmp.c verstage-y += prog_ops.c verstage-y += delay.c verstage-y += cbfs.c +verstage-y += cbfs_core.c +verstage-y += halt.c verstage-y += memcmp.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 88a292f..8239f07 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -74,7 +74,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -static int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, +int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, struct prog *prog, ssize_t offset) { struct cbfs_stage stage; diff --git a/src/lib/cbfs_core.h b/src/lib/cbfs_core.h index c301c33..f9aeaa8 100644 --- a/src/lib/cbfs_core.h +++ b/src/lib/cbfs_core.h @@ -15,6 +15,8 @@ # define CBFS_MINI_BUILD #elif defined(__BOOTBLOCK__) /* No LZMA in boot block. */ +#elif defined(__VERSTAGE__) + /* No LZMA in verstage. */ #elif defined(__PRE_RAM__) && !CONFIG_COMPRESS_RAMSTAGE /* No LZMA in romstage if ramstage is not compressed. */ #else diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc index fbc7f87..6b22801 100644 --- a/src/lib/loaders/Makefile.inc +++ b/src/lib/loaders/Makefile.inc @@ -23,3 +23,4 @@ romstage-y += cbfs_ramstage_loader.c romstage-y += load_and_run_ramstage.c ramstage-y += cbfs_payload_loader.c ramstage-y += load_and_run_payload.c +verstage-y += load_and_run_romstage.c diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 7a08097..4928e0c 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -27,12 +27,12 @@ #include <symbols.h> #include <timestamp.h> -extern const struct prog_loader_ops vboot_payload_loader; +extern const struct prog_loader_ops vboot_loader; extern const struct prog_loader_ops cbfs_payload_loader; static const struct prog_loader_ops *payload_ops[] = { #if CONFIG_VBOOT_VERIFY_FIRMWARE - &vboot_payload_loader, + &vboot_loader, #endif &cbfs_payload_loader, }; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index fddea4d..af8667a 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -23,17 +23,20 @@ #include <cbfs.h> #include <program_loading.h> #include <romstage_handoff.h> +#include <rules.h> #include <stage_cache.h> #include <timestamp.h> extern const struct prog_loader_ops cbfs_ramstage_loader; -extern const struct prog_loader_ops vboot_ramstage_loader; +extern const struct prog_loader_ops vboot_loader; static const struct prog_loader_ops *loaders[] = { #if CONFIG_VBOOT_VERIFY_FIRMWARE - &vboot_ramstage_loader, + &vboot_loader, #endif +#if !ENV_VERSTAGE &cbfs_ramstage_loader, +#endif }; void __attribute__((weak)) stage_cache_add(int stage_id, struct prog *stage) {} diff --git a/src/lib/loaders/load_and_run_romstage.c b/src/lib/loaders/load_and_run_romstage.c index b54bfc7..25a75bd 100644 --- a/src/lib/loaders/load_and_run_romstage.c +++ b/src/lib/loaders/load_and_run_romstage.c @@ -24,12 +24,19 @@ #include <cbfs.h> #include <halt.h> #include <program_loading.h> +#include <rules.h> #include <timestamp.h> extern const struct prog_loader_ops cbfs_romstage_loader; +extern const struct prog_loader_ops vboot_loader; static const struct prog_loader_ops *loaders[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_loader, +#endif +#if !ENV_VERSTAGE &cbfs_romstage_loader, +#endif }; void run_romstage(void) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 5846781..0c9c884 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -21,8 +21,10 @@ #include <stdint.h> #include <console/console.h> #include <cbmem.h> +#include <timer.h> #include <timestamp.h> #include <arch/early_variables.h> +#include <rules.h> #include <smp/node.h> #define MAX_TIMESTAMPS 60 @@ -52,12 +54,24 @@ static void timestamp_real_init(uint64_t base) car_set_var(ts_table_p, tst); } +/* Determine if one should proceed into timestamp code. This is for protecting + * systems that have multiple processors running in romstage -- namely AMD + * based x86 platforms. */ +static int timestamp_should_run(void) +{ + /* Only check boot_cpu() in other stages than ramstage on x86. */ + if ((!ENV_RAMSTAGE && IS_ENABLED(CONFIG_ARCH_X86)) && !boot_cpu()) + return 0; + + return 1; +} + void timestamp_add(enum timestamp_id id, uint64_t ts_time) { struct timestamp_entry *tse; struct timestamp_table *ts_table = NULL; - if (!boot_cpu()) + if (!timestamp_should_run()) return; ts_table = car_get_var(ts_table_p); @@ -121,7 +135,7 @@ static void timestamp_do_sync(void) void timestamp_init(uint64_t base) { - if (!boot_cpu()) + if (!timestamp_should_run()) return; #ifdef __PRE_RAM__ @@ -145,7 +159,7 @@ void timestamp_init(uint64_t base) void timestamp_reinit(void) { - if (!boot_cpu()) + if (!timestamp_should_run()) return; #ifdef __PRE_RAM__ @@ -160,3 +174,14 @@ void timestamp_reinit(void) /* Call timestamp_reinit at CAR migration time. */ CAR_MIGRATE(timestamp_reinit) + +/* Provide default timestamp implementation using monotonic timer. */ +uint64_t __attribute__((weak)) timestamp_get(void) +{ + struct mono_time t1, t2; + + mono_time_set_usecs(&t1, 0); + timer_monotonic_get(&t2); + + return mono_time_diff_microseconds(&t1, &t2); +} diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index fb72673..1e49bd1 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "vboot_handoff.h" -int vboot_skip_display_init(void) +static int vboot_handoff_flag(uint32_t flag) { struct vboot_handoff *vbho; @@ -35,7 +35,22 @@ int vboot_skip_display_init(void) if (vbho == NULL) return 0; - return !(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DISPLAY); + return !!(vbho->init_params.out_flags & flag); +} + +int vboot_skip_display_init(void) +{ + return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY); +} + +int vboot_enable_developer(void) +{ + return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER); +} + +int vboot_enable_recovery(void) +{ + return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY); } int __attribute__((weak)) clear_recovery_mode_switch(void) diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index 8396113..bb6c1ad 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -17,14 +17,14 @@ ## config VBOOT_STARTS_IN_BOOTBLOCK - bool + bool "Vboot starts verifying in bootblock" default n depends on VBOOT_VERIFY_FIRMWARE help Firmware verification happens during or at the end of bootblock. config VBOOT_STARTS_IN_ROMSTAGE - bool + bool "Vboot starts verifying in romstage" default n depends on VBOOT_VERIFY_FIRMWARE && !VBOOT_STARTS_IN_BOOTBLOCK help @@ -51,12 +51,12 @@ config VBOOT_DISABLE_DEV_ON_RECOVERY handy on embedded devices with limited input capabilities. config SEPARATE_VERSTAGE - bool + bool "Vboot verification is built into a separate stage" default n depends on VBOOT_VERIFY_FIRMWARE config RETURN_FROM_VERSTAGE - bool + bool "The separate verification stage returns to its caller" default n depends on SEPARATE_VERSTAGE help diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index def43ad..bc0ab6b 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -20,13 +20,16 @@ libverstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ +bootblock-y += vboot_loader.c +romstage-y += vboot_loader.c +ramstage-y += vboot_loader.c +verstage-y += vboot_loader.c + bootblock-y += ../vboot_common.c verstage-y += ../vboot_common.c romstage-y += ../vboot_common.c ramstage-y += ../vboot_common.c -bootblock-y += verstub.c -libverstage-y += verstub.c bootblock-y += common.c libverstage-y += verstage.c verstage-y += common.c @@ -37,9 +40,20 @@ libverstage-y += antirollback.c endif romstage-y += vboot_handoff.c common.c +ramstage-y += common.c + verstage-y += verstage.ld -VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) +ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y)) +else +ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y) +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-bootblock-y)) +else +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-romstage-y)) +endif +endif # CONFIG_SEPARATE_VERSTAGE + VB2_LIB = $(obj)/external/vboot_reference/vboot_fw20.a VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CPPFLAGS_verstage))) VBOOT_CFLAGS += $(libverstage-c-ccopts) @@ -64,7 +78,7 @@ fallback/verstage-file = $(objcbfs)/verstage.elf fallback/verstage-type = stage fallback/verstage-compression = none else -ifeq ($(VBOOT_STARTS_IN_BOOTBLOCK),y) +ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y) bootblock-srcs += $(objgenerated)/libverstage.a else romstage-srcs += $(objgenerated)/libverstage.a diff --git a/src/vendorcode/google/chromeos/vboot2/common.c b/src/vendorcode/google/chromeos/vboot2/common.c index d70a108..beffebe 100644 --- a/src/vendorcode/google/chromeos/vboot2/common.c +++ b/src/vendorcode/google/chromeos/vboot2/common.c @@ -25,39 +25,6 @@ #include "../vboot_handoff.h" #include "misc.h" -void *vboot_load_stage(int stage_index, - struct vboot_region *fw_main, - struct vboot_components *fw_info) -{ - struct cbfs_media default_media, *media = &default_media; - uintptr_t fc_addr; - uint32_t fc_size; - void *entry; - - if (stage_index >= fw_info->num_components) { - printk(BIOS_INFO, "invalid stage index\n"); - return NULL; - } - - fc_addr = fw_main->offset_addr + fw_info->entries[stage_index].offset; - fc_size = fw_info->entries[stage_index].size; - if (fc_size == 0 || - fc_addr + fc_size > fw_main->offset_addr + fw_main->size) { - printk(BIOS_INFO, "invalid stage address or size\n"); - return NULL; - } - - init_default_cbfs_media(media); - - /* we're making cbfs access offset outside of the region managed by - * cbfs. this works because cbfs_load_stage_by_offset does not check - * the offset. */ - entry = cbfs_load_stage_by_offset(media, fc_addr); - if (entry == (void *)-1) - entry = NULL; - return entry; -} - struct vb2_working_data * const vboot_get_working_data(void) { return (struct vb2_working_data *)_vboot2_work; diff --git a/src/vendorcode/google/chromeos/vboot2/misc.h b/src/vendorcode/google/chromeos/vboot2/misc.h index 7425082..d942d56 100644 --- a/src/vendorcode/google/chromeos/vboot2/misc.h +++ b/src/vendorcode/google/chromeos/vboot2/misc.h @@ -22,8 +22,7 @@ #include "../vboot_common.h" -void *vboot2_verify_firmware(void); -void *vboot2_load_ramstage(void); +void vboot_fill_handoff(void); void verstage_main(void); void *vboot_load_stage(int stage_index, struct vboot_region *fw_main, diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c index b84e47e..16261b4 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c @@ -36,30 +36,6 @@ #include "../vboot_handoff.h" #include "misc.h" -static void *load_ramstage(struct vboot_handoff *vboot_handoff, - struct vboot_region *fw_main) -{ - struct vboot_components *fw_info; - void *ret; - int i; - - fw_info = vboot_locate_components(fw_main); - if (fw_info == NULL) - die("failed to locate firmware components\n"); - - /* these offset & size are used to load a rw boot loader */ - for (i = 0; i < fw_info->num_components; i++) { - vboot_handoff->components[i].address = - fw_main->offset_addr + fw_info->entries[i].offset; - vboot_handoff->components[i].size = fw_info->entries[i].size; - } - - timestamp_add_now(TS_START_COPYRAM); - ret = vboot_load_stage(CONFIG_VBOOT_RAMSTAGE_INDEX, fw_main, fw_info); - timestamp_add_now(TS_END_COPYRAM); - return ret; -} - /** * Sets vboot_handoff based on the information in vb2_shared_data * @@ -146,14 +122,13 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, vb_sd->recovery_reason = vb2_sd->recovery_reason; } -/** - * Load ramstage and return the entry point - */ -void *vboot2_load_ramstage(void) +void vboot_fill_handoff(void) { + int i; struct vboot_handoff *vh; struct vb2_shared_data *sd; struct vboot_region fw_main; + struct vboot_components *fw_info; struct vb2_working_data *wd = vboot_get_working_data(); sd = vboot_get_work_buffer(wd); @@ -172,17 +147,15 @@ void *vboot2_load_ramstage(void) /* needed until we finish transtion to vboot2 for kernel verification */ fill_vboot_handoff(vh, sd); - if (vboot_is_readonly_path(wd)) - /* we're on recovery path. continue to ro-ramstage. */ - return NULL; - - if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) { - return cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/ramstage"); - } else { - printk(BIOS_INFO, "loading ramstage from Slot %c\n", - sd->fw_slot ? 'B' : 'A'); - vb2_get_selected_region(wd, &fw_main); - return load_ramstage(vh, &fw_main); + vb2_get_selected_region(wd, &fw_main); + fw_info = vboot_locate_components(&fw_main); + if (fw_info == NULL) + die("failed to locate firmware components\n"); + + /* these offset & size are used to load a rw boot loader */ + for (i = 0; i < fw_info->num_components; i++) { + vh->components[i].address = + fw_main.offset_addr + fw_info->entries[i].offset; + vh->components[i].size = fw_info->entries[i].size; } } diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c new file mode 100644 index 0000000..c731abb --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <program_loading.h> +#include <rules.h> +#include <string.h> +#include "misc.h" +#include "../symbols.h" + +/* The stage loading code is compiled and entered from mutilple stages. The + * helper functions below attempt to provde more clarity on when certain + * code should be called. */ + +static int verification_should_run(void) +{ + if (ENV_VERSTAGE && IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) + return 1; + + if (!IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) { + if (ENV_ROMSTAGE && + IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) + return 1; + if (ENV_BOOTBLOCK && + IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + return 1; + } + + return 0; +} + +static int verstage_should_load(void) +{ + if (!IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) + return 0; + + if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) + return 1; + + if (ENV_BOOTBLOCK && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + return 1; + + return 0; +} + +static void init_vb2_working_data(void) +{ + struct vb2_working_data *wd; + + wd = vboot_get_working_data(); + memset(wd, 0, _vboot2_work_size); + /* + * vboot prefers 16-byte alignment. This takes away 16 bytes + * from the VBOOT2_WORK region, but the vboot devs said that's okay. + */ + wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); + wd->buffer_size = _vboot2_work_size - wd->buffer_offset; +} + +static int vboot_loader_active(struct prog *prog) +{ + struct vb2_working_data *wd; + int run_verification; + + run_verification = verification_should_run(); + + if (run_verification) { + init_vb2_working_data(); + verstage_main(); + } else if (verstage_should_load()) { + struct prog verstage = { + .type = PROG_VERSTAGE, + .name = CONFIG_CBFS_PREFIX "/verstage", + }; + + /* load verstage from RO */ + if (cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, &verstage)) + die("failed to load verstage"); + + /* verify and select a slot */ + prog_run(&verstage); + + /* This is not actually possible to hit this condition at + * runtime, but this provides a hint to the compiler for dead + * code elimination below. */ + if (!IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) + return 0; + } + + wd = vboot_get_working_data(); + + if (vboot_is_slot_selected(wd)) { + if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES) && + run_verification) { + /* RW A or B */ + struct vboot_region fw_main; + + vb2_get_selected_region(wd, &fw_main); + cbfs_set_header_offset(fw_main.offset_addr); + } + return 1; + } + + return 0; +} + +static uintptr_t vboot_fw_region(int fw_index, struct vboot_region *fw_main, + struct vboot_components *fw_info, size_t *size) +{ + uintptr_t fc_addr; + uint32_t fc_size; + + if (fw_index >= fw_info->num_components) { + printk(BIOS_INFO, "invalid stage index: %d\n", fw_index); + return 0; + } + + fc_addr = fw_main->offset_addr + fw_info->entries[fw_index].offset; + fc_size = fw_info->entries[fw_index].size; + if (fc_size == 0 || + fc_addr + fc_size > fw_main->offset_addr + fw_main->size) { + printk(BIOS_INFO, "invalid stage address or size\n"); + return 0; + } + + *size = fc_addr; + return fc_addr; +} + +/* This function is only called when vboot_loader_active() returns 1. That + * means we are taking vboot paths. */ +static int vboot_prepare(struct prog *prog) +{ + struct vb2_working_data *wd; + struct vboot_region fw_main; + struct vboot_components *fw_info; + + /* Code size optimization. We'd never actually get called under the + * followin cirumstances because verstage was loaded and ran -- never + * returning. */ + if (verstage_should_load() && !IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) + return 0; + + /* In the multi cbfs case the cbfs offset pointer has already been + * updated after firmware verification. */ + if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) { + if (!ENV_RAMSTAGE && + cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, prog) != 0) + return -1; + + /* Need to load payload. */ + if (ENV_RAMSTAGE) { + void *payload; + size_t size; + + payload = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + prog->name, + CBFS_TYPE_PAYLOAD, + &size); + + if (payload == NULL) + die("Couldn't load payload\n"); + + prog_set_area(prog, payload, size); + } + return 0; + } + + wd = vboot_get_working_data(); + vb2_get_selected_region(wd, &fw_main); + fw_info = vboot_locate_components(&fw_main); + if (fw_info == NULL) + die("failed to locate firmware components\n"); + + /* Load payload in ramstage. */ + if (ENV_RAMSTAGE) { + uintptr_t payload; + void *payload_ptr; + size_t size; + + payload = vboot_fw_region(CONFIG_VBOOT_BOOT_LOADER_INDEX, + &fw_main, fw_info, &size); + + if (payload == 0) + die("Couldn't load payload."); + + payload_ptr = vboot_get_region(payload, size, NULL); + + if (payload_ptr == NULL) + die("Couldn't load payload."); + + prog_set_area(prog, payload_ptr, size); + } else { + uintptr_t stage; + size_t size; + int stage_index = 0; + + if (prog->type == PROG_ROMSTAGE) + stage_index = CONFIG_VBOOT_ROMSTAGE_INDEX; + else if (prog->type == PROG_RAMSTAGE) + stage_index = CONFIG_VBOOT_RAMSTAGE_INDEX; + else + die("Invalid program type for vboot."); + + stage = vboot_fw_region(stage_index, &fw_main, fw_info, &size); + + if (stage == 0) + die("Vboot stage load failed."); + + if (cbfs_load_prog_stage_by_offset(CBFS_DEFAULT_MEDIA, + prog, stage) < 0) + die("Vboot couldn't load stage"); + } + + /* Fill in vboot handoff structure before moving to ramstage. */ + if (ENV_ROMSTAGE) + vboot_fill_handoff(); + + return 0; +} + +const struct prog_loader_ops vboot_loader = { + .name = "VBOOT", + .is_loader_active = vboot_loader_active, + .prepare = vboot_prepare, +}; diff --git a/src/vendorcode/google/chromeos/vboot2/verstub.c b/src/vendorcode/google/chromeos/vboot2/verstub.c deleted file mode 100644 index c4319ba..0000000 --- a/src/vendorcode/google/chromeos/vboot2/verstub.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/stages.h> -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <timestamp.h> -#include "../chromeos.h" -#include "../symbols.h" -#include "misc.h" - -static struct vb2_working_data *init_vb2_working_data(void) -{ - struct vb2_working_data *wd; - - wd = vboot_get_working_data(); - memset(wd, 0, _vboot2_work_size); - /* - * vboot prefers 16-byte alignment. This takes away 16 bytes - * from the VBOOT2_WORK region, but the vboot devs said that's okay. - */ - wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); - wd->buffer_size = _vboot2_work_size - wd->buffer_offset; - - return wd; -} - -/** - * Verify a slot and jump to the next stage - * - * This could be either part of the (1) bootblock or the (2) verstage, depending - * on CONFIG_RETURN_FROM_VERSTAGE. - * - * 1) It jumps to the verstage and comes back, then, loads the romstage over the - * verstage space and exits to it. (note the cbfs cache is trashed on return - * from the verstage.) - * - * 2) We're already in the verstage. Verify firmware, then load the romstage and - * exits to it. - */ -void *vboot2_verify_firmware(void) -{ - void *entry; - struct vb2_working_data *wd; - - wd = init_vb2_working_data(); - - if (IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) { - /* load verstage from RO */ - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/verstage"); - if (entry == (void *)-1) - die("failed to load verstage"); - - /* verify and select a slot */ - stage_exit(entry); - } else { - verstage_main(); - } - - /* jump to the selected slot */ - timestamp_add_now(TS_START_COPYROM); - entry = (void *)-1; - if (vboot_is_slot_selected(wd)) { - /* RW A or B */ - struct vboot_region fw_main; - - vb2_get_selected_region(wd, &fw_main); - - if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) { - cbfs_set_header_offset(fw_main.offset_addr); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/romstage"); - } else { - struct vboot_components *fw_info; - fw_info = vboot_locate_components(&fw_main); - if (fw_info == NULL) - die("failed to locate firmware components\n"); - entry = vboot_load_stage(CONFIG_VBOOT_ROMSTAGE_INDEX, - &fw_main, fw_info); - } - } else if (vboot_is_readonly_path(wd)) { - /* RO */ - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/romstage"); - } - timestamp_add_now(TS_END_COPYROM); - - return entry; -}

1 0

New patch to review for coreboot: 7371f0b chromeos: Fix build for the region-based CBFS/FMAP APIs
by Sol Boucher 05 May '15

05 May '15

Sol Boucher (solb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10093 -gerrit commit 7371f0b3449d61837cda2ff3ab3ad31d0dbee565 Author: Sol Boucher <solb(a)chromium.org> Date: Mon May 4 21:46:03 2015 -0700 chromeos: Fix build for the region-based CBFS/FMAP APIs This restores the ability to build with CONFIG_CHROMEOS enabled, which was broken by the introduction of the new region-based CBFS and FMAP APIs. Note that this does not touch vboot integration, and that builds still fail when CONFIG_VBOOT_VERIFY_FIRMWARE and friends are enabled. Building panther from this commit using the config file from the Chromium OS project[1] (but modified with CONFIG_VBOOT_VERIFY_FIRMWARE=n, CONFIG_BUILD_WITH_FAKE_IFD=n, and CONFIG_HAVE_ME_BIN=y) results in firmware that successfully gets as far as loading depthcharge. [1] https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/… Change-Id: I198e2f639a3584deb2b464cf3c237f69d93c1c5f Signed-off-by: Sol Boucher <solb(a)chromium.org> --- src/drivers/elog/elog.c | 33 +----- src/lib/Makefile.inc | 4 +- src/mainboard/google/butterfly/mainboard.c | 16 +-- src/mainboard/google/panther/lan.c | 10 +- src/northbridge/intel/haswell/mrccache.c | 18 +-- src/northbridge/intel/sandybridge/mrccache.c | 18 +-- src/soc/intel/common/mrc_cache.c | 21 ++-- src/vendorcode/google/chromeos/Makefile.inc | 4 - src/vendorcode/google/chromeos/cros_vpd.c | 38 ++++--- src/vendorcode/google/chromeos/fmap.c | 157 --------------------------- src/vendorcode/google/chromeos/fmap.h | 46 -------- 11 files changed, 76 insertions(+), 289 deletions(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index d7751c2..e5a99a6 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -26,6 +26,7 @@ #include <pc80/mc146818rtc.h> #endif #include <bcd.h> +#include <fmap.h> #include <rtc.h> #include <smbios.h> #include <spi-generic.h> @@ -35,8 +36,6 @@ #include <elog.h> #include "elog_internal.h" -#include <vendorcode/google/chromeos/fmap.h> - #if !IS_ENABLED(CONFIG_CHROMEOS) && CONFIG_ELOG_FLASH_BASE == 0 #error "CONFIG_ELOG_FLASH_BASE is invalid" #endif @@ -86,26 +85,6 @@ static inline u32 get_rom_size(void) } /* - * Convert a memory mapped flash address into a flash offset - */ -static inline u32 elog_flash_address_to_offset(u8 *address) -{ -#if CONFIG_ARCH_X86 - /* For x86, assume address is memory-mapped near 4GB */ - u32 rom_size; - - if (!elog_spi) - return 0; - - rom_size = get_rom_size(); - - return (u32)address - ((u32)~0UL - rom_size + 1); -#else - return (u32)(uintptr_t)address; -#endif -} - -/* * Pointer to an event log header in the event data area */ static inline struct event_header* @@ -517,16 +496,16 @@ static void elog_find_flash(void) { elog_debug("elog_find_flash()\n"); + // TODO: Eliminate the base Kconfig option and always read from FMAP. #if CONFIG_CHROMEOS /* Find the ELOG base and size in FMAP */ - u8 *flash_base_ptr; - int fmap_size = find_fmap_entry("RW_ELOG", (void **)&flash_base_ptr); - if (fmap_size < 0) { + struct region section; + if (fmap_locate_area("RW_ELOG", &section) < 0) { printk(BIOS_WARNING, "ELOG: Unable to find RW_ELOG in FMAP\n"); flash_base = total_size = 0; } else { - flash_base = elog_flash_address_to_offset(flash_base_ptr); - total_size = MIN(fmap_size, CONFIG_ELOG_AREA_SIZE); + flash_base = section.offset; + total_size = MIN(section.size, CONFIG_ELOG_AREA_SIZE); } #else flash_base = CONFIG_ELOG_FLASH_BASE; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1c69c95..34b31c7 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -140,7 +140,9 @@ ramstage-y += mem_pool.c romstage-y += region.c ramstage-y += region.c -smm-y += cbfs.c memcmp.c +smm-y += cbfs.c +smm-y += fmap.c +smm-y += memcmp.c smm-y += region.c smm-y += mem_pool.c smm-$(CONFIG_COMPILER_GCC) += gcc.c diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 5420f72..65debe7 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cbfs.h> +#include <fmap.h> #include <types.h> #include <string.h> #include <device/device.h> @@ -36,11 +38,6 @@ #include <smbios.h> #include <device/pci.h> #include <ec/quanta/ene_kb3940q/ec.h> -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/fmap.h> -#else -#include <cbfs.h> -#endif static unsigned int search(char *p, char *a, unsigned int lengthp, unsigned int lengtha) @@ -201,9 +198,12 @@ static void mainboard_init(device_t dev) u16 io_base = 0; struct device *ethernet_dev = NULL; #if CONFIG_CHROMEOS - char **vpd_region_ptr = NULL; - search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); - search_address = (unsigned long)(*vpd_region_ptr); + struct region_device region; + if (fmap_locate_area_as_rdev("RO_VPD", &region) >= 0) { + search_address = (unsigned long)rdev_mmap(&region, 0, + region.region.size); + search_length = region.region.size; + } #else void *vpd_file = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, &search_length); diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 22da881..8500d90 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -18,6 +18,7 @@ */ #include <cbfs.h> +#include <fmap.h> #include <string.h> #include <types.h> #include <arch/io.h> @@ -25,7 +26,6 @@ #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <vendorcode/google/chromeos/fmap.h> #include "onboard.h" static unsigned int search(char *p, u8 *a, unsigned int lengthp, @@ -118,14 +118,18 @@ static void program_mac_address(u16 io_base) u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ #if CONFIG_CHROMEOS - search_length = find_fmap_entry("RO_VPD", &search_address); + struct region_device region; + if (fmap_locate_area_as_rdev("RO_VPD", &region) >= 0) { + search_address = rdev_mmap(&region, 0, region.region.size); + search_length = region.region.size; + } #else search_address = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, &search_length); #endif if (search_length <= 0) - printk(BIOS_ERR, "LAN: find_fmap_entry returned -1.\n"); + printk(BIOS_ERR, "LAN: Unable to find saved MAC address!\n"); else get_mac_address(&high_dword, &low_dword, search_address, search_length); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index d6522a0..15845f8 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -22,6 +22,7 @@ #include <bootstate.h> #include <console/console.h> #include <cbfs.h> +#include <fmap.h> #include <ip_checksum.h> #include <device/device.h> #include <cbmem.h> @@ -30,7 +31,6 @@ #include <spi-generic.h> #include <spi_flash.h> #if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/fmap.h> #endif /* convert a pointer to flash area into the offset inside the flash */ @@ -58,16 +58,18 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); } -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { + // TODO: Eliminate the CBFS access/write and always read from FMAP. #if CONFIG_CHROMEOS - return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); + struct region_device region; + if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &region) < 0) { + *mrc_region_ptr = NULL; + return 0; + } + *mrc_region_ptr = (struct mrc_data_container *)rdev_mmap(&region, 0, + region.region.size); + return region.region.size; #else size_t region_size; *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 6b02c21..60e4b25 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -22,6 +22,7 @@ #include <bootstate.h> #include <console/console.h> #include <cbfs.h> +#include <fmap.h> #include <ip_checksum.h> #include <device/device.h> #include <cbmem.h> @@ -30,7 +31,6 @@ #include <spi-generic.h> #include <spi_flash.h> #if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/fmap.h> #endif /* convert a pointer to flash area into the offset inside the flash */ @@ -58,16 +58,18 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); } -/* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make - * this more flexible, there are two of options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - Use CBFS - */ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { + // TODO: Eliminate the CBFS access/write and always read from FMAP. #if CONFIG_CHROMEOS - return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); + struct region_device region; + if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &region) < 0) { + *mrc_region_ptr = NULL; + return 0; + } + *mrc_region_ptr = (struct mrc_data_container *)rdev_mmap(&region, 0, + region.region.size); + return region.region.size; #else size_t region_size; *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index f854046..3155fae 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -20,9 +20,9 @@ #include <string.h> #include <console/console.h> #include <cbmem.h> +#include <fmap.h> #include <ip_checksum.h> #if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/fmap.h> #endif #include "mrc_cache.h" @@ -37,18 +37,19 @@ struct mrc_data_region { }; /* common code */ -static int mrc_cache_get_region(struct mrc_data_region *region) +static int mrc_cache_get_region(struct mrc_data_region *data_region) { + // TODO: Eliminate the CBFS access/write and always read from FMAP. #if CONFIG_CHROMEOS - int ret; - ret = find_fmap_entry("RW_MRC_CACHE", &region->base); - if (ret >= 0) { - region->size = ret; - return 0; - } + struct region_device region; + if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &region) < 0) + return -1; + data_region->base = rdev_mmap(&region, 0, region.region.size); + data_region->size = region.region.size; + return 0; #endif - region->base = (void *)CONFIG_MRC_SETTINGS_CACHE_BASE; - region->size = CONFIG_MRC_SETTINGS_CACHE_SIZE; + data_region->base = (void *)CONFIG_MRC_SETTINGS_CACHE_BASE; + data_region->size = CONFIG_MRC_SETTINGS_CACHE_SIZE; return 0; } diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 0c66985..87bbc82 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -35,11 +35,7 @@ ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c -verstage-y += fmap.c -romstage-y += fmap.c -ramstage-y += fmap.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c -smm-y += fmap.c romstage-y += vpd_decode.c cros_vpd.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c ifeq ($(CONFIG_ARCH_X86)$(CONFIG_ARCH_MIPS),) diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index c0e4830..bd28e30 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -7,11 +7,11 @@ #include <console/console.h> #include <cbfs.h> +#include <fmap.h> #include <stdlib.h> #include <string.h> #include "cros_vpd.h" -#include "fmap.h" #include "lib_vpd.h" #include "vpd_tables.h" @@ -30,14 +30,14 @@ struct vpd_gets_arg { static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) { MAYBE_STATIC int cached = 0; + MAYBE_STATIC uint8_t *mapped_address = NULL; MAYBE_STATIC uint8_t *cached_address = NULL; MAYBE_STATIC int32_t cached_size = 0; MAYBE_STATIC int result = -1; struct google_vpd_info info; int32_t base; - const struct fmap_area *area; - struct cbfs_media media; + struct region_device region; if (cached) { *vpd_address = cached_address; @@ -46,32 +46,36 @@ static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) } cached = 1; - area = find_fmap_area(fmap_find(), "RO_VPD"); - if (!area) { + if (fmap_locate_area_as_rdev("RO_VPD", &region) < 0) { printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", __func__); return result; } - if (area->size <= GOOGLE_VPD_2_0_OFFSET + sizeof(info)) { + if (region.region.size <= GOOGLE_VPD_2_0_OFFSET + sizeof(info)) { printk(BIOS_ERR, "%s: Too small (%d) for Google VPD 2.0.\n", - __func__, area->size); + __func__, region.region.size); return result; } - base = area->offset + GOOGLE_VPD_2_0_OFFSET; - cached_size = area->size - GOOGLE_VPD_2_0_OFFSET; - init_default_cbfs_media(&media); - media.open(&media); + base = GOOGLE_VPD_2_0_OFFSET; + cached_size = region.region.size - GOOGLE_VPD_2_0_OFFSET; + mapped_address = rdev_mmap(&region, base, cached_size); + if (!mapped_address) { + printk(BIOS_ERR, "%s: Couldn't map Google VPD from flash offset %#x.\n", + __func__, region.region.offset); + return result; + } /* Try if we can find a google_vpd_info, otherwise read whole VPD. */ - if (media.read(&media, &info, base, sizeof(info)) == sizeof(info) && - memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) - == 0 && cached_size >= info.size + sizeof(info)) { - base += sizeof(info); + cached_address = mapped_address; + memcpy(&info, cached_address, sizeof(info)); + if (memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) + == 0 && cached_size >= info.size + sizeof(info) && + sizeof(info) + info.size <= cached_size) { + cached_address += sizeof(info); cached_size = info.size; } + rdev_munmap(&region, mapped_address); - cached_address = media.map(&media, base, cached_size); - media.close(&media); if (cached_address) { *vpd_address = cached_address; *vpd_size = cached_size; diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c deleted file mode 100644 index 21d439e..0000000 --- a/src/vendorcode/google/chromeos/fmap.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <stddef.h> -#include <string.h> -#include <console/console.h> -#include <cbfs.h> -#include "fmap.h" - -static int is_fmap_signature_valid(const struct fmap *fmap) -{ - const char reversed_sig[] = FMAP_REVERSED_SIGNATURE; - const char *p2 = reversed_sig + sizeof(FMAP_REVERSED_SIGNATURE) - 2; - const char *p1 = (char *)fmap; - - while (p2 >= reversed_sig) - if (*p1++ != *p2--) { - printk(BIOS_ERR, "No FMAP found at %p.\n", fmap); - return 1; - } - - printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %p.\n", - fmap->name, fmap->ver_major, fmap->ver_minor, fmap); - printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n", - (unsigned long long)fmap->base, fmap->size, fmap->nareas); - - return 0; -} - -/* Find FMAP data structure in ROM. - * See http://code.google.com/p/flashmap/ for more information on FMAP. - */ -const struct fmap *fmap_find(void) -{ - /* FIXME: Get rid of the hard codes. The "easy" way would be to - * do a binary search, but since ROM accesses are slow, we don't - * want to spend a lot of time looking for the FMAP. An elegant - * solution would be to store a pointer to the FMAP in the CBFS - * master header; that would require some more changes to cbfstool - * and possibly cros_bundle_firmware. - */ - const struct fmap *fmap; - struct cbfs_media media; - size_t size; - - if (init_default_cbfs_media(&media)) { - printk(BIOS_ERR, "failed to init default cbfs media\n"); - return NULL; - } - - media.open(&media); - fmap = media.map(&media, CONFIG_FLASHMAP_OFFSET, sizeof(*fmap)); - - if (fmap == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - printk(BIOS_ERR, "failed to map FMAP header\n"); - media.close(&media); - return NULL; - } - - if (is_fmap_signature_valid(fmap)) { - media.unmap(&media, fmap); - media.close(&media); - return NULL; - } - - size = sizeof(*fmap) + sizeof(struct fmap_area) * fmap->nareas; - media.unmap(&media, fmap); - fmap = media.map(&media, CONFIG_FLASHMAP_OFFSET, size); - - if (fmap == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - printk(BIOS_ERR, "failed to map FMAP (size=%zu)\n", size); - media.unmap(&media, fmap); - media.close(&media); - return NULL; - } - - media.close(&media); - return fmap; -} - -const struct fmap_area *find_fmap_area(const struct fmap *fmap, - const char name[]) -{ - const struct fmap_area *area = NULL; - - if (fmap) { - int i; - for (i = 0; i < fmap->nareas; i++) { - if (!strcmp((const char *)fmap->areas[i].name, name)) { - area = &fmap->areas[i]; - break; - } - } - } - - if (area) { - printk(BIOS_DEBUG, "FMAP: area %s found\n", name); - printk(BIOS_DEBUG, "FMAP: offset: %x\n", area->offset); - printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", area->size); - } else { - printk(BIOS_DEBUG, "FMAP: area %s not found\n", name); - } - - return area; -} - -int find_fmap_entry(const char name[], void **pointer) -{ - MAYBE_STATIC const struct fmap *fmap = NULL; - const struct fmap_area *area; - void *base = NULL; - - if (!fmap) - fmap = fmap_find(); - - area = find_fmap_area(fmap, name); - - if (!area) - return -1; - - /* Right now cros_bundle_firmware does not write a valid - * base address into the FMAP. Hence, if base is 0, assume - * 4GB-8MB as base address. - */ - if (fmap->base) { - base = (void *)(unsigned long)fmap->base; - printk(BIOS_DEBUG, "FMAP: %s base at %p\n", name, base); - } else { -#if CONFIG_ARCH_X86 - base = (void *)(0 - CONFIG_ROM_SIZE); - printk(BIOS_WARNING, "FMAP: No valid base address, using" - " 0x%p\n", base); -#endif - } - - *pointer = (void*) ((uintptr_t)base + area->offset); - printk(BIOS_DEBUG, "FMAP: %s at %p (offset %x)\n", - name, *pointer, area->offset); - return area->size; -} diff --git a/src/vendorcode/google/chromeos/fmap.h b/src/vendorcode/google/chromeos/fmap.h deleted file mode 100644 index fc84f15..0000000 --- a/src/vendorcode/google/chromeos/fmap.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2010, Google Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google Inc. nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - */ - -#ifndef FLASHMAP_LIB_FMAP_H__ -#define FLASHMAP_LIB_FMAP_H__ - -#include <fmap_serialized.h> - -/* coreboot specific function prototypes */ -const struct fmap *fmap_find(void); -const struct fmap_area *find_fmap_area(const struct fmap *fmap, - const char name[]); -int find_fmap_entry(const char name[], void **pointer); -#endif /* FLASHMAP_LIB_FMAP_H__*/

1 0

Patch merged into coreboot/master: 8ccdeae haswell: Link stage_cache_external_region into ramstage, too
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 8ccdeaeb207031eea3881511acfaf3e949678f74 Author: Sol Boucher <solb(a)chromium.org> Date: Thu Apr 30 18:02:08 2015 -0700 haswell: Link stage_cache_external_region into ramstage, too When CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is set, this function is now linked into the ramstage as well as the romstage, since the former makes calls to it in panther builds. With this commit, it's possible to build panther using the config file from the Chromium OS project[1] if you supply the appropriate Intel descriptor and ME binary blobs and manually set CONFIG_VBOOT_VERIFY_FIRMWARE=n, CONFIG_BUILD_WITH_FAKE_IFD=n, and CONFIG_HAVE_ME_BIN=y. The resulting image is at least able to load a payload, although I only tested with depthcharge, which immediately complained, "vboot handoff pointer is NULL" and gave up the ghost. [1] https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/… Change-Id: Id3bb510fa60129a4d36a0117dc33e7aa62d6c742 Signed-off-by: Sol Boucher <solb(a)chromium.org> Reviewed-on: http://review.coreboot.org/10046 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10046 for details. -gerrit

1 0

Patch set updated for coreboot: e7d80bf amd/pi: Move AGESA cbfs access into the wrapper
by Marc Jones 05 May '15

05 May '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10058 -gerrit commit e7d80bfdf980223b970824f47cd03f4b914382c2 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 1 14:57:50 2015 -0600 amd/pi: Move AGESA cbfs access into the wrapper The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- 3rdparty | 2 +- src/northbridge/amd/pi/agesawrapper.c | 25 +++++++++++++++++++++++++ src/northbridge/amd/pi/agesawrapper.h | 6 ++++++ src/vendorcode/amd/pi/00630F01/Makefile.inc | 1 + src/vendorcode/amd/pi/00730F01/Makefile.inc | 1 + 5 files changed, 34 insertions(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index 892a697..98bafbe 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit 892a6976ba8c7d14e1aaa518d4d02923d51b22c3 +Subproject commit 98bafbe3730e42e00d111037c2e378e0da085bd8 diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index efdfdbd..79e3895 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -18,6 +18,7 @@ */ #include <AGESA.h> +#include <cbfs.h> #include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> @@ -589,3 +590,27 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) return Status; } + +const void *agesawrapper_locate_module (const CHAR8 name[8]) +{ + struct cbfs_media media; + struct cbfs_file* file; + const void* agesa; + const AMD_IMAGE_HEADER* image; + const AMD_MODULE_HEADER* module; + size_t file_size; + + if (init_default_cbfs_media(&media)) + return NULL; + file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME); + if (!file) + return NULL; + agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME, + ntohl(file->type), &file_size); + if (!agesa) + return NULL; + image = LibAmdLocateImage(agesa, agesa + ntohl(file->len) - 1, 4096, name); + module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset; + + return module; +} diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index adcc755..b77e04c 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -24,6 +24,11 @@ #include "Porting.h" #include "AGESA.h" +/* TODO: Add a kconfig option to name the AGESA ROM file in CBFS */ +#ifndef CONFIG_CBFS_AGESA_NAME +#define CONFIG_CBFS_AGESA_NAME "AGESA" +#endif + enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ @@ -55,5 +60,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void); VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); VOID amd_initcpuio(void); VOID amd_initmmio(void); +const void *agesawrapper_locate_module (const CHAR8 name[8]); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/vendorcode/amd/pi/00630F01/Makefile.inc b/src/vendorcode/amd/pi/00630F01/Makefile.inc index 7908378..6141763 100644 --- a/src/vendorcode/amd/pi/00630F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00630F01/Makefile.inc @@ -48,6 +48,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include diff --git a/src/vendorcode/amd/pi/00730F01/Makefile.inc b/src/vendorcode/amd/pi/00730F01/Makefile.inc index a302e33..d6ba93c 100644 --- a/src/vendorcode/amd/pi/00730F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00730F01/Makefile.inc @@ -47,6 +47,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include

1 0

Patch set updated for coreboot: eb0ca6e PCI subsystem: Drop PCI_64BIT_PREF_MEM option
by Kyösti Mälkki 05 May '15

05 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8705 -gerrit commit eb0ca6e574315f5cfe5dfd6f9cec3c2ca67bd68a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Mar 17 06:42:54 2015 +0200 PCI subsystem: Drop PCI_64BIT_PREF_MEM option No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 5 -- src/device/device.c | 35 ++------- src/mainboard/asus/kfsn4-dre/Kconfig | 4 -- src/mainboard/asus/m2n-e/Kconfig | 4 -- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 4 -- src/mainboard/gigabyte/m57sli/Kconfig | 4 -- src/mainboard/msi/ms7260/Kconfig | 4 -- src/mainboard/msi/ms9282/Kconfig | 4 -- src/mainboard/nvidia/l1_2pvv/Kconfig | 4 -- src/mainboard/tyan/s2912/Kconfig | 4 -- src/mainboard/tyan/s2912_fam10/Kconfig | 4 -- src/northbridge/amd/agesa/family10/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family12/northbridge.c | 81 +-------------------- src/northbridge/amd/agesa/family14/northbridge.c | 82 ---------------------- src/northbridge/amd/agesa/family15/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family15rl/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 77 -------------------- src/northbridge/amd/agesa/family16kb/northbridge.c | 77 -------------------- src/northbridge/amd/amdfam10/northbridge.c | 76 -------------------- src/northbridge/amd/amdk8/northbridge.c | 68 ------------------ src/northbridge/amd/pi/00630F01/northbridge.c | 77 +------------------- src/northbridge/amd/pi/00730F01/northbridge.c | 78 -------------------- 22 files changed, 8 insertions(+), 915 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 8ddb58c..beb29fb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -205,11 +205,6 @@ config PCI bool default n -config PCI_64BIT_PREF_MEM - bool - depends on PCI - default n - config HYPERTRANSPORT_PLUGIN_SUPPORT bool depends on PCI diff --git a/src/device/device.c b/src/device/device.c index 35bb6e2..c0efa1f 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -611,19 +611,14 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, } } -#if CONFIG_PCI_64BIT_PREF_MEM -#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM) -#else #define MEM_MASK (IORESOURCE_MEM) -#endif - #define IO_MASK (IORESOURCE_IO) #define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM) #define MEM_TYPE (IORESOURCE_MEM) #define IO_TYPE (IORESOURCE_IO) struct constraints { - struct resource pref, io, mem; + struct resource io, mem; }; static void constrain_resources(struct device *dev, struct constraints* limits) @@ -644,10 +639,8 @@ static void constrain_resources(struct device *dev, struct constraints* limits) continue; } - /* PREFETCH, MEM, or I/O - skip any others. */ - if ((res->flags & MEM_MASK) == PREF_TYPE) - lim = &limits->pref; - else if ((res->flags & MEM_MASK) == MEM_TYPE) + /* MEM, or I/O - skip any others. */ + if ((res->flags & MEM_MASK) == MEM_TYPE) lim = &limits->mem; else if ((res->flags & IO_MASK) == IO_TYPE) lim = &limits->io; @@ -696,8 +689,6 @@ static void avoid_fixed_resources(struct device *dev) printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); /* Initialize constraints to maximum size. */ - limits.pref.base = 0; - limits.pref.limit = 0xffffffffffffffffULL; limits.io.base = 0; limits.io.limit = 0xffffffffffffffffULL; limits.mem.base = 0; @@ -709,9 +700,7 @@ static void avoid_fixed_resources(struct device *dev) continue; printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, dev_path(dev), res->index, res->limit); - if ((res->flags & MEM_MASK) == PREF_TYPE && - (res->limit < limits.pref.limit)) - limits.pref.limit = res->limit; + if ((res->flags & MEM_MASK) == MEM_TYPE && (res->limit < limits.mem.limit)) limits.mem.limit = res->limit; @@ -730,10 +719,8 @@ static void avoid_fixed_resources(struct device *dev) if ((res->flags & IORESOURCE_FIXED)) continue; - /* PREFETCH, MEM, or I/O - skip any others. */ - if ((res->flags & MEM_MASK) == PREF_TYPE) - lim = &limits.pref; - else if ((res->flags & MEM_MASK) == MEM_TYPE) + /* MEM, or I/O - skip any others. */ + if ((res->flags & MEM_MASK) == MEM_TYPE) lim = &limits.mem; else if ((res->flags & IO_MASK) == IO_TYPE) lim = &limits.io; @@ -1038,11 +1025,6 @@ void dev_configure(void) for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; - if (res->flags & IORESOURCE_PREFETCH) { - compute_resources(child->link_list, - res, MEM_MASK, PREF_TYPE); - continue; - } if (res->flags & IORESOURCE_MEM) { compute_resources(child->link_list, res, MEM_MASK, MEM_TYPE); @@ -1070,11 +1052,6 @@ void dev_configure(void) for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; - if (res->flags & IORESOURCE_PREFETCH) { - allocate_resources(child->link_list, - res, MEM_MASK, PREF_TYPE); - continue; - } if (res->flags & IORESOURCE_MEM) { allocate_resources(child->link_list, res, MEM_MASK, MEM_TYPE); diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 47fccda..558f758 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -56,10 +56,6 @@ config HW_MEM_HOLE_SIZEK hex default 0x100000 -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 12 diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 7292bf3..c86de2d 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -65,10 +65,6 @@ config MAINBOARD_PART_NUMBER string default "M2N-E" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..660ac1c 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -45,10 +45,6 @@ config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..3132d37 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -49,10 +49,6 @@ config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..60ea9ea 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -47,10 +47,6 @@ config MAINBOARD_PART_NUMBER string default "MS-7260" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 2 diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..e88f36f 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -41,10 +41,6 @@ config MAINBOARD_PART_NUMBER string default "MS-9282" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..7694492 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -51,10 +51,6 @@ config MAINBOARD_PART_NUMBER string default "l1_2pvv" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..8b59eb5 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -46,10 +46,6 @@ config MAINBOARD_PART_NUMBER string default "S2912" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 4 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 1dd74ca..1e0d4d0 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -43,10 +43,6 @@ config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" -config PCI_64BIT_PREF_MEM - bool - default n - config MAX_CPUS int default 12 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index cd36192..3a18452 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -635,29 +635,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void amdfam10_domain_enable_resources(device_t dev) @@ -737,10 +715,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -751,57 +725,6 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 9d078ed..5328cec 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -509,9 +509,6 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM -//- pci_domain_read_resources(dev); - struct resource *resource; /* Initialize the system-wide I/O space constraints. */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -526,27 +523,7 @@ static void domain_read_resources(device_t dev) resource->limit = 0xdfffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -#else - struct bus *link; - struct resource *resource; - for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -556,10 +533,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -570,58 +543,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - -printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); - for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for(res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4017944..f00c405 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -498,29 +498,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for (link = dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0 | (link->link_num << 2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1 | (link->link_num << 2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2 | (link->link_num << 2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void setup_uma_memory(void) @@ -553,10 +531,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -567,62 +541,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1 | (link->link_num << 2)); - mem2 = find_resource(dev, 2 | (link->link_num << 2)); - - printk(BIOS_DEBUG, - "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - (u32) (mem1->base), (u32) (mem1->limit), - (u32) (mem1->size), u32) (mem1->align)); - printk(BIOS_DEBUG, - "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - (u32) (mem2->base), (u32) (mem2->limit), - (u32) (mem2->size), (u32) (mem2->align)); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) - || ((mem1->limit > 0xffffffff) - && (mem2->limit > 0xffffffff))) { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, - "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, - "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 593579e..49e6783 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -668,30 +668,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -792,10 +769,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -806,56 +779,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 223a0a0..abd281c 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -663,30 +663,7 @@ static void domain_read_resources(struct device *dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(struct device *dev) @@ -787,10 +764,6 @@ static void setup_uma_memory(void) static void domain_set_resources(struct device *dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -801,56 +774,6 @@ static void domain_set_resources(struct device *dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index a18da68..29bcb2a 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -661,30 +661,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -785,10 +762,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -799,56 +772,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d0638ca..8de76f6 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -677,30 +677,7 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -803,10 +780,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -817,56 +790,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f857b72..1822bad 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -634,29 +634,8 @@ static void amdfam10_domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); -#else - struct bus *link; - struct resource *resource; - for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif #if CONFIG_MMCONF_SUPPORT struct resource *res = new_resource(dev, 0xc0010058); res->base = CONFIG_MMCONF_BASE_ADDRESS; @@ -752,10 +731,6 @@ static void setup_uma_memory(void) static void amdfam10_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; int i, idx; @@ -765,57 +740,6 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for(res = dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { pci_tolm = my_find_pci_tolm(link, pci_tolm); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a17aa65..b42b6bf 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -667,13 +667,6 @@ static void amdk8_domain_read_resources(device_t dev) } pci_domain_read_resources(dev); - -#if CONFIG_PCI_64BIT_PREF_MEM - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 2); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; -#endif } static void my_tolm_test(void *gp, struct device *dev, struct resource *new) @@ -904,10 +897,6 @@ static void setup_uma_memory(void) static void amdk8_domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -917,63 +906,6 @@ static void amdk8_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if 0 - /* Place the IO devices somewhere safe */ - io = find_resource(dev, 0); - io->base = DEVICE_IO_START; -#endif -#if CONFIG_PCI_64BIT_PREF_MEM - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1); - mem2 = find_resource(dev, 2); - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - for(res = dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = my_find_pci_tolm(dev->link_list); // FIXME handle interleaved nodes. If you fix this here, please fix diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f8b3246..e5fa0cb 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -654,29 +654,8 @@ static void domain_read_resources(device_t dev) /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - if (!IS_ENABLED(CONFIG_PCI_64BIT_PREF_MEM)) pci_domain_read_resources(dev); - else { - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } - } + } static void domain_enable_resources(device_t dev) @@ -780,10 +759,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -794,56 +769,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b10da3d..d33f021 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -663,31 +663,7 @@ static void domain_read_resources(device_t dev) } /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ - -#if !CONFIG_PCI_64BIT_PREF_MEM pci_domain_read_resources(dev); - -#else - struct bus *link; - struct resource *resource; - for (link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - } -#endif } static void domain_enable_resources(device_t dev) @@ -796,10 +772,6 @@ static void setup_uma_memory(void) static void domain_set_resources(device_t dev) { -#if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; - struct resource *res; -#endif unsigned long mmio_basek; u32 pci_tolm; u64 ramtop = 0; @@ -810,56 +782,6 @@ static void domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif -#if CONFIG_PCI_64BIT_PREF_MEM - - for (link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - } - - for (res = &dev->resource_list; res; res = res->next) - { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); - } -#endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link);

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coreboot-gerrit May 2015