coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

1 participants
1299 discussions

Patch merged into coreboot/master: 32bc18e nvidia/tegra132: Fix vboot2 memory layout
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 32bc18ef9772d006bea014d3e871e7353a438d55 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 nvidia/tegra132: Fix vboot2 memory layout bootblock et al were listed twice, which shouldn't happen. Change-Id: I3e6077d70e064ebe74bd4e5e3156f87d548c2fcb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10097 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10097 for details. -gerrit

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Patch merged into coreboot/master: 8fb36c0 console: rename do_vtxprintf to do_printk_va_list and use it
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 8fb36c07ac4eb34da61894bba260ab57c4b7f9db Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 console: rename do_vtxprintf to do_printk_va_list and use it The name is more consistent with what we have elsewhere, and the callsite didn't build at all (with vboot enabled) Change-Id: I3576f3b8f737d360f68b67b6ce1683199948776d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10096 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10096 for details. -gerrit

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Patch merged into coreboot/master: ed98eee vboot: Remove vboot_get_payload()
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit ed98eeea8451f7f9a320525e73fb448371adb34f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot: Remove vboot_get_payload() It's not used at all. Change-Id: I97bf02a9277f6ca348443c6886f77b4dfc70da78 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10095 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10095 for details. -gerrit

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Patch merged into coreboot/master: 0946a1b vboot: remove uses of vboot2_verify_firmware()
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 0946a1bb21594d274fd21df7a9e40f3d90b0ba84 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot: remove uses of vboot2_verify_firmware() The vboot mechanism will be implemented within the program loader subsystem to make it transparent to mainboards and chipsets. Change-Id: Icd0bdcba06cdc30591f9b25068b3fa3a112e58fb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10094 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10094 for details. -gerrit

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Patch set updated for coreboot: 8ce99cd amd/pi: Move AGESA cbfs access into the wrapper
by Marc Jones 05 May '15

05 May '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10058 -gerrit commit 8ce99cdb77b5b6f7235c9cfb056feb7254b2be4c Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 1 14:57:50 2015 -0600 amd/pi: Move AGESA cbfs access into the wrapper The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- 3rdparty | 2 +- src/northbridge/amd/pi/agesawrapper.c | 25 +++++++++++++++++++++++++ src/northbridge/amd/pi/agesawrapper.h | 6 ++++++ src/vendorcode/amd/pi/00630F01/Makefile.inc | 1 + src/vendorcode/amd/pi/00730F01/Makefile.inc | 1 + 5 files changed, 34 insertions(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index 892a697..98bafbe 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit 892a6976ba8c7d14e1aaa518d4d02923d51b22c3 +Subproject commit 98bafbe3730e42e00d111037c2e378e0da085bd8 diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index efdfdbd..79e3895 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -18,6 +18,7 @@ */ #include <AGESA.h> +#include <cbfs.h> #include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> @@ -589,3 +590,27 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) return Status; } + +const void *agesawrapper_locate_module (const CHAR8 name[8]) +{ + struct cbfs_media media; + struct cbfs_file* file; + const void* agesa; + const AMD_IMAGE_HEADER* image; + const AMD_MODULE_HEADER* module; + size_t file_size; + + if (init_default_cbfs_media(&media)) + return NULL; + file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME); + if (!file) + return NULL; + agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME, + ntohl(file->type), &file_size); + if (!agesa) + return NULL; + image = LibAmdLocateImage(agesa, agesa + ntohl(file->len) - 1, 4096, name); + module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset; + + return module; +} diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index adcc755..b77e04c 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -24,6 +24,11 @@ #include "Porting.h" #include "AGESA.h" +/* TODO: Add a kconfig option to name the AGESA ROM file in CBFS */ +#ifndef CONFIG_CBFS_AGESA_NAME +#define CONFIG_CBFS_AGESA_NAME "AGESA" +#endif + enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ @@ -55,5 +60,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void); VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); VOID amd_initcpuio(void); VOID amd_initmmio(void); +const void *agesawrapper_locate_module (const CHAR8 name[8]); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/vendorcode/amd/pi/00630F01/Makefile.inc b/src/vendorcode/amd/pi/00630F01/Makefile.inc index 7908378..6141763 100644 --- a/src/vendorcode/amd/pi/00630F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00630F01/Makefile.inc @@ -48,6 +48,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include diff --git a/src/vendorcode/amd/pi/00730F01/Makefile.inc b/src/vendorcode/amd/pi/00730F01/Makefile.inc index a302e33..d6ba93c 100644 --- a/src/vendorcode/amd/pi/00730F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00730F01/Makefile.inc @@ -47,6 +47,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include

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Patch set updated for coreboot: 41b03f0 amd/pi/hudson: Add AMD Avalon binaries to CBFS
by WANG Siyuan 05 May '15

05 May '15

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9416 -gerrit commit 41b03f0139dead450fc6e86f6f0a8784ce0f5ff6 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed Apr 8 18:51:15 2015 +0800 amd/pi/hudson: Add AMD Avalon binaries to CBFS trustlets.bin and Trustlet.tkn.cert are binaries for the AMD PSP and are necessary for AGESA binary PI operation. AGESA.bin (3rdparty Change-Id: I7c413c) will hang without these files. AMD Olive Hill Plus successfully boots with this change. This change depends on the binaries added to the 3rdparty repository in <If81c2285269> : amd/avalon: Add PSP firmware. Change-Id: I03c612fc49ddc77777a70cc7a1a8d297b9786bc8 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> --- src/southbridge/amd/pi/hudson/Makefile.inc | 32 +++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c66d541..de172fb 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -207,10 +207,22 @@ SMUFWM_POS=$(call int-align, \ $(call int-add,$(PSPNVRAM_POS) $(PSPNVRAM_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUFWM_SIZE=$(call file-size,$(CONFIG_SMUFWM_FILE)) +## 12 +CONFIG_TRUSTLET_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +TRUSTLET_POS=$(call int-align, \ + $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +TRUSTLET_SIZE=$(call file-size,$(CONFIG_TRUSTLET_FILE)) +## 13 +CONFIG_TRUSTLET_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +TRUSTLET_KEY_POS=$(call int-align, \ + $(call int-add,$(TRUSTLET_POS) $(TRUSTLET_SIZE) $(CBFS_HEADER_SIZE)), \ + $(CBFS_HEADER_SIZE)) +TRUSTLET_KEY_SIZE=$(call file-size,$(CONFIG_TRUSTLET_KEY_FILE)) CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin SMUSCS_POS=$(call int-align, \ - $(call int-add,$(SMUFWM_POS) $(SMUFWM_SIZE) $(CBFS_HEADER_SIZE)), \ + $(call int-add,$(TRUSTLET_KEY_POS) $(TRUSTLET_KEY_SIZE) $(CBFS_HEADER_SIZE)), \ $(CBFS_HEADER_SIZE)) SMUSCS_SIZE=$(call file-size,$(CONFIG_SMUSCS_FILE)) @@ -241,6 +253,12 @@ $(obj)/coreboot_psp_directory.bin: $(obj)/config.h $(FLETCHER) $(RTM_FILE) for fwm in 4 $(PSPNVRAM_SIZE) $(PSPNVRAM_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp + for fwm in 12 $(TRUSTLET_SIZE) $(TRUSTLET_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp + for fwm in 13 $(TRUSTLET_KEY_SIZE) $(TRUSTLET_KEY_POS) 0; do \ + echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ + done >> $(a)_tail.tmp for fwm in 95 $(SMUSCS_SIZE) $(SMUSCS_POS) 0; do \ echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ done >> $(a)_tail.tmp @@ -300,6 +318,18 @@ apu/smufwm-file := $(CONFIG_SMUFWM_FILE) apu/smufwm-position := $(SMUFWM_POS) apu/smufwm-type := raw +#12 +cbfs-files-y += apu/trustlet +apu/trustlet-file := $(CONFIG_TRUSTLET_FILE) +apu/trustlet-position := $(TRUSTLET_POS) +apu/trustlet-type := raw + +#13 +cbfs-files-y += apu/trustlet_key +apu/trustlet_key-file := $(CONFIG_TRUSTLET_KEY_FILE) +apu/trustlet_key-position := $(TRUSTLET_KEY_POS) +apu/trustlet_key-type := raw + cbfs-files-y += apu/smuscs apu/smuscs-file := $(CONFIG_SMUSCS_FILE) apu/smuscs-position := $(SMUSCS_POS)

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New patch to review for coreboot: 5ad88aa arch/arm64: provide boot_cpu()
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10105 -gerrit commit 5ad88aa551667ca4d1a828d1abc4ccc0ff8f6f5e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 arch/arm64: provide boot_cpu() Change-Id: I708041133dfafdc97e052952ad9d8f2e4164209c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/arm64/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/arch/arm64/cpu.c b/src/arch/arm64/cpu.c index cd8dd38..7965577 100644 --- a/src/arch/arm64/cpu.c +++ b/src/arch/arm64/cpu.c @@ -22,6 +22,7 @@ #include <arch/lib_helpers.h> #include <cpu/cpu.h> #include <console/console.h> +#include <smp/node.h> #include "cpu-internal.h" struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; @@ -218,3 +219,8 @@ void arch_cpu_wait_for_action(void) action_queue_complete(q, orig); } } + +int boot_cpu(void) +{ + return cpu_is_bsp(); +}

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New patch to review for coreboot: 7babeb1 timestamp: provide weak default implementation of timestamp_get
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10104 -gerrit commit 7babeb15a4b1efe8298484366cd4c61710271680 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 timestamp: provide weak default implementation of timestamp_get Change-Id: I2e7f17a686f6af3426c9d68cd9394e9a88dbf358 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/lib/timestamp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 9a0e631..0c9c884 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -174,3 +174,14 @@ void timestamp_reinit(void) /* Call timestamp_reinit at CAR migration time. */ CAR_MIGRATE(timestamp_reinit) + +/* Provide default timestamp implementation using monotonic timer. */ +uint64_t __attribute__((weak)) timestamp_get(void) +{ + struct mono_time t1, t2; + + mono_time_set_usecs(&t1, 0); + timer_monotonic_get(&t2); + + return mono_time_diff_microseconds(&t1, &t2); +}

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New patch to review for coreboot: ff0f072 vboot: add cbfs_core
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10103 -gerrit commit ff0f072ef538aa989306d2f4f36590706668a012 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot: add cbfs_core And we don't support lzma compressed data in verstage. Change-Id: I3d8d3290f147871c49e9440e9b54bbf2742aaa9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/lib/Makefile.inc | 1 + src/lib/cbfs_core.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 82dd5c5..ef4e2aa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -33,6 +33,7 @@ bootblock-y += memcmp.c verstage-y += prog_ops.c verstage-y += delay.c verstage-y += cbfs.c +verstage-y += cbfs_core.c verstage-y += memcmp.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/cbfs_core.h b/src/lib/cbfs_core.h index c301c33..f9aeaa8 100644 --- a/src/lib/cbfs_core.h +++ b/src/lib/cbfs_core.h @@ -15,6 +15,8 @@ # define CBFS_MINI_BUILD #elif defined(__BOOTBLOCK__) /* No LZMA in boot block. */ +#elif defined(__VERSTAGE__) + /* No LZMA in verstage. */ #elif defined(__PRE_RAM__) && !CONFIG_COMPRESS_RAMSTAGE /* No LZMA in romstage if ramstage is not compressed. */ #else

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New patch to review for coreboot: 4cc31dc timestamp: refine boot CPU test
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10102 -gerrit commit 4cc31dc680b1fe28e0d0924c83618fcead77d62b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 timestamp: refine boot CPU test The timestamp code's restriction to run only on the BSP is for AMD systems. No need to run it everywhere, so tighten the test (and only run boot_cpu() when required). Change-Id: I800e817cc89e8688a671672961cab15c7f788ba8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/lib/timestamp.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 5846781..9a0e631 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -21,8 +21,10 @@ #include <stdint.h> #include <console/console.h> #include <cbmem.h> +#include <timer.h> #include <timestamp.h> #include <arch/early_variables.h> +#include <rules.h> #include <smp/node.h> #define MAX_TIMESTAMPS 60 @@ -52,12 +54,24 @@ static void timestamp_real_init(uint64_t base) car_set_var(ts_table_p, tst); } +/* Determine if one should proceed into timestamp code. This is for protecting + * systems that have multiple processors running in romstage -- namely AMD + * based x86 platforms. */ +static int timestamp_should_run(void) +{ + /* Only check boot_cpu() in other stages than ramstage on x86. */ + if ((!ENV_RAMSTAGE && IS_ENABLED(CONFIG_ARCH_X86)) && !boot_cpu()) + return 0; + + return 1; +} + void timestamp_add(enum timestamp_id id, uint64_t ts_time) { struct timestamp_entry *tse; struct timestamp_table *ts_table = NULL; - if (!boot_cpu()) + if (!timestamp_should_run()) return; ts_table = car_get_var(ts_table_p); @@ -121,7 +135,7 @@ static void timestamp_do_sync(void) void timestamp_init(uint64_t base) { - if (!boot_cpu()) + if (!timestamp_should_run()) return; #ifdef __PRE_RAM__ @@ -145,7 +159,7 @@ void timestamp_init(uint64_t base) void timestamp_reinit(void) { - if (!boot_cpu()) + if (!timestamp_should_run()) return; #ifdef __PRE_RAM__

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coreboot-gerrit May 2015