coreboot-gerrit May 2015

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New patch to review for coreboot: 9b234e5 3rdparty: Move to 3rdparty/blobs
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10106 -gerrit commit 9b234e51926c6aa0c43ae18ac145555f04e4865d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue May 5 20:39:38 2015 +0200 3rdparty: Move to 3rdparty/blobs Make room for vboot (and potentially other 3rdparty repositories) Change-Id: Ia69ead2ed88d0e7da29f94abc369115ee74f1e8d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- .gitmodules | 2 +- 3rdparty | 1 - 3rdparty/blobs | 1 + Makefile.inc | 4 ++-- src/cpu/amd/geode_gx2/Makefile.inc | 2 +- src/cpu/amd/geode_lx/Kconfig | 2 +- src/cpu/amd/geode_lx/Makefile.inc | 2 +- src/cpu/intel/haswell/microcode_blob.c | 4 ++-- src/cpu/intel/model_1067x/microcode_blob.c | 2 +- src/cpu/intel/model_106cx/microcode_blob.c | 2 +- src/cpu/intel/model_2065x/microcode_blob.c | 2 +- src/cpu/intel/model_206ax/microcode_blob.c | 2 +- src/cpu/intel/model_65x/microcode_blob.c | 2 +- src/cpu/intel/model_67x/microcode_blob.c | 2 +- src/cpu/intel/model_68x/microcode_blob.c | 2 +- src/cpu/intel/model_69x/microcode_blob.c | 2 +- src/cpu/intel/model_6bx/microcode_blob.c | 2 +- src/cpu/intel/model_6dx/microcode_blob.c | 2 +- src/cpu/intel/model_6ex/microcode_blob.c | 2 +- src/cpu/intel/model_6fx/microcode_blob.c | 2 +- src/cpu/intel/model_6xx/microcode_blob.c | 2 +- src/cpu/intel/model_f0x/microcode_blob.c | 2 +- src/cpu/intel/model_f1x/microcode_blob.c | 2 +- src/cpu/intel/model_f2x/microcode_blob.c | 2 +- src/cpu/intel/model_f3x/microcode_blob.c | 2 +- src/cpu/intel/model_f4x/microcode_blob.c | 2 +- src/cpu/samsung/exynos5250/update-bl1.sh | 2 +- src/mainboard/amd/lamar/Kconfig | 2 +- src/northbridge/amd/pi/00630F01/Kconfig | 2 +- src/northbridge/amd/pi/00730F01/Kconfig | 2 +- src/northbridge/intel/sandybridge/Kconfig | 2 +- src/soc/intel/baytrail/Kconfig | 8 ++++---- src/soc/intel/baytrail/microcode/microcode_blob.c | 2 +- src/soc/intel/broadwell/Kconfig | 6 +++--- src/soc/intel/broadwell/microcode/microcode_blob.c | 2 +- src/soc/nvidia/tegra132/Kconfig | 2 +- src/soc/qualcomm/ipq806x/Kconfig | 2 +- src/soc/qualcomm/ipq806x/Makefile.inc | 2 +- src/soc/samsung/exynos5250/Makefile.inc | 2 +- src/soc/samsung/exynos5420/Makefile.inc | 2 +- src/southbridge/amd/agesa/hudson/Kconfig | 12 ++++++------ src/southbridge/amd/agesa/hudson/Makefile.inc | 4 ++-- src/southbridge/amd/cimx/sb800/Kconfig | 2 +- src/southbridge/amd/pi/hudson/Kconfig | 6 +++--- src/southbridge/amd/pi/hudson/Makefile.inc | 4 ++-- src/southbridge/intel/bd82x6x/Kconfig | 8 ++++---- src/southbridge/intel/ibexpeak/Kconfig | 6 +++--- src/southbridge/intel/lynxpoint/Kconfig | 6 +++--- src/vendorcode/amd/Kconfig | 2 +- src/vendorcode/amd/pi/00630F01/Kconfig | 2 +- src/vendorcode/amd/pi/00730F01/Kconfig | 2 +- src/vendorcode/google/chromeos/build-snow | 2 +- 52 files changed, 74 insertions(+), 74 deletions(-) diff --git a/.gitmodules b/.gitmodules index ee3f1ea..cf32923 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,5 +1,5 @@ [submodule "3rdparty"] - path = 3rdparty + path = 3rdparty/blobs url = ../blobs.git update = none ignore = dirty diff --git a/3rdparty b/3rdparty deleted file mode 160000 index 892a697..0000000 --- a/3rdparty +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 892a6976ba8c7d14e1aaa518d4d02923d51b22c3 diff --git a/3rdparty/blobs b/3rdparty/blobs new file mode 160000 index 0000000..892a697 --- /dev/null +++ b/3rdparty/blobs @@ -0,0 +1 @@ +Subproject commit 892a6976ba8c7d14e1aaa518d4d02923d51b22c3 diff --git a/Makefile.inc b/Makefile.inc index 6403977..ca9c4ce 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -131,9 +131,9 @@ endif # try to fetch non-optional submodules if the source is under git forgetthis:=$(if $(GIT),$(shell git submodule update --init)) ifeq ($(CONFIG_USE_BLOBS),y) -# this is necessary because 3rdparty is update=none, and so is ignored +# this is necessary because blobs is update=none, and so is ignored # unless explicitly requested and enabled through --checkout -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty)) +forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) endif ramstage-c-deps:=$$(OPTION_TABLE_H) diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc index 7511926..be9e1be 100644 --- a/src/cpu/amd/geode_gx2/Makefile.inc +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage -vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository) +vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository) diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index e3e2d2e..6001cc7 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -37,7 +37,7 @@ config GEODE_VSA_FILE config VSA_FILENAME string "AMD Geode LX VSA path and filename" depends on GEODE_VSA_FILE - default "3rdparty/cpu/amd/geode_lx/gpl_vsa_lx_102.bin" + default "3rdparty/blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin" help The path and filename of the file to use as VSA. diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc index 4eb57ba..9edb332 100644 --- a/src/cpu/amd/geode_lx/Makefile.inc +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-type = stage -vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository) +vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository) diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c index df54ddb..31bb14b 100644 --- a/src/cpu/intel/haswell/microcode_blob.c +++ b/src/cpu/intel/haswell/microcode_blob.c @@ -23,8 +23,8 @@ unsigned microcode[] = { * a very good reason why we only use one at a time? */ #if CONFIG_INTEL_LYNXPOINT_LP - #include "../../../../3rdparty/cpu/intel/model_4065x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h" #else - #include "../../../../3rdparty/cpu/intel/model_306cx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h" #endif }; diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c index 36f4caf..88e95db 100644 --- a/src/cpu/intel/model_1067x/microcode_blob.c +++ b/src/cpu/intel/model_1067x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_1067ax[] = { - #include "../../../../3rdparty/cpu/intel/model_1067x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h" }; diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c index 97d36ed..5a0257a 100644 --- a/src/cpu/intel/model_106cx/microcode_blob.c +++ b/src/cpu/intel/model_106cx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_106cx[] = { - #include "../../../../3rdparty/cpu/intel/model_106cx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h" }; diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c index df2e85b..53b21b4 100644 --- a/src/cpu/intel/model_2065x/microcode_blob.c +++ b/src/cpu/intel/model_2065x/microcode_blob.c @@ -18,5 +18,5 @@ */ unsigned microcode[] = { - #include "../../../../3rdparty/cpu/intel/model_2065x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h" }; diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c index 197daf2..5d725ff 100644 --- a/src/cpu/intel/model_206ax/microcode_blob.c +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -18,5 +18,5 @@ */ unsigned microcode[] = { - #include "../../../../3rdparty/cpu/intel/model_206ax/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h" }; diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c index d0f6a2a..8511708 100644 --- a/src/cpu/intel/model_65x/microcode_blob.c +++ b/src/cpu/intel/model_65x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_65x[] = { - #include "../../../../3rdparty/cpu/intel/model_65x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h" }; diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c index 1302928..672dee3 100644 --- a/src/cpu/intel/model_67x/microcode_blob.c +++ b/src/cpu/intel/model_67x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_67x[] = { - #include "../../../../3rdparty/cpu/intel/model_67x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h" }; diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c index fa72086..db32f34 100644 --- a/src/cpu/intel/model_68x/microcode_blob.c +++ b/src/cpu/intel/model_68x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_68x[] = { - #include "../../../../3rdparty/cpu/intel/model_68x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h" }; diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c index a06c859..04bc717 100644 --- a/src/cpu/intel/model_69x/microcode_blob.c +++ b/src/cpu/intel/model_69x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_69x[] = { - #include "../../../../3rdparty/cpu/intel/model_69x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h" }; diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c index debd650..dbfab5d 100644 --- a/src/cpu/intel/model_6bx/microcode_blob.c +++ b/src/cpu/intel/model_6bx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6bx[] = { - #include "../../../../3rdparty/cpu/intel/model_6bx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h" }; diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c index 8f13d1b..50e15cc 100644 --- a/src/cpu/intel/model_6dx/microcode_blob.c +++ b/src/cpu/intel/model_6dx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6dx[] = { - #include "../../../../3rdparty/cpu/intel/model_6dx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h" }; diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c index e270059..2c749a7 100644 --- a/src/cpu/intel/model_6ex/microcode_blob.c +++ b/src/cpu/intel/model_6ex/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6ex[] = { - #include "../../../../3rdparty/cpu/intel/model_6ex/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h" }; diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c index 67a10cd..8044e51 100644 --- a/src/cpu/intel/model_6fx/microcode_blob.c +++ b/src/cpu/intel/model_6fx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6fx[] = { - #include "../../../../3rdparty/cpu/intel/model_6fx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h" }; diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c index ab082da..463faf0 100644 --- a/src/cpu/intel/model_6xx/microcode_blob.c +++ b/src/cpu/intel/model_6xx/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_6xx[] = { - #include "../../../../3rdparty/cpu/intel/model_6xx/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h" }; diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c index 96577fa..7cef6d1 100644 --- a/src/cpu/intel/model_f0x/microcode_blob.c +++ b/src/cpu/intel/model_f0x/microcode_blob.c @@ -1,4 +1,4 @@ /* 256KB cache */ unsigned microcode_updates_f0x[] = { - #include "../../../../3rdparty/cpu/intel/model_f0x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h" }; diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c index bf2fe92..a9b25d7 100644 --- a/src/cpu/intel/model_f1x/microcode_blob.c +++ b/src/cpu/intel/model_f1x/microcode_blob.c @@ -1,4 +1,4 @@ /* 256KB cache */ unsigned microcode_updates_f1x[] = { - #include "../../../../3rdparty/cpu/intel/model_f1x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h" }; diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c index 55133f2..3815f06 100644 --- a/src/cpu/intel/model_f2x/microcode_blob.c +++ b/src/cpu/intel/model_f2x/microcode_blob.c @@ -1,4 +1,4 @@ /* 512KB cache */ unsigned microcode_updates_f2x[] = { - #include "../../../../3rdparty/cpu/intel/model_f2x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h" }; diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c index 80a0af7..fb46747 100644 --- a/src/cpu/intel/model_f3x/microcode_blob.c +++ b/src/cpu/intel/model_f3x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_f3x[] = { - #include "../../../../3rdparty/cpu/intel/model_f3x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h" }; diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c index 2d98508..b061dcc 100644 --- a/src/cpu/intel/model_f4x/microcode_blob.c +++ b/src/cpu/intel/model_f4x/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode_updates_f4x[] = { - #include "../../../../3rdparty/cpu/intel/model_f4x/microcode.h" + #include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h" }; diff --git a/src/cpu/samsung/exynos5250/update-bl1.sh b/src/cpu/samsung/exynos5250/update-bl1.sh index e47b25d..7fede4c 100644 --- a/src/cpu/samsung/exynos5250/update-bl1.sh +++ b/src/cpu/samsung/exynos5250/update-bl1.sh @@ -1,7 +1,7 @@ #!/bin/sh BL1_NAME="E5250.nbl1.bin" -BL1_PATH="3rdparty/cpu/samsung/exynos5250/" +BL1_PATH="3rdparty/blobs/cpu/samsung/exynos5250/" BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exyn…" get_bl1() { diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 338a675..2b0b73e 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -79,7 +79,7 @@ config ONBOARD_VGA_IS_PRIMARY config HUDSON_XHCI_FWM_FILE string - default "3rdparty/southbridge/amd/bolton/xhci.bin" + default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" config AZ_PIN hex diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 4e71895..cb6ab95 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -48,6 +48,6 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string - default "3rdparty/northbridge/amd/00630F01/VBIOS.bin" + default "3rdparty/blobs/northbridge/amd/00630F01/VBIOS.bin" endif diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index ab605f3..fc825dd 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -49,6 +49,6 @@ config VGA_BIOS_ID config VGA_BIOS_FILE string - default "3rdparty/northbridge/amd/00730F01/VBIOS.bin" + default "3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin" endif diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 11370f5..fc6d6a4 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -105,7 +105,7 @@ config HAVE_MRC config MRC_FILE string "Intel System Agent path and filename" depends on HAVE_MRC - default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" + default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" help The path and filename of the file to use as System Agent binary. diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 0b3e176..85631fc 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -75,7 +75,7 @@ if HAVE_MRC config MRC_FILE string "Intel memory refeference code path and filename" - default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" + default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" help The path and filename of the file to use as System Agent binary. Note that this points to the sandybridge binary file @@ -174,7 +174,7 @@ config HAVE_ME_BIN help The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty repository. If + firmware might be provided in coreboot's 3rdparty/blobs repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM. @@ -182,7 +182,7 @@ config HAVE_ME_BIN config ME_BIN_PATH string "Path to management engine firmware" depends on HAVE_ME_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" config HAVE_IFD_BIN bool @@ -223,7 +223,7 @@ config IFD_PLATFORM_SECTION config IFD_BIN_PATH string "Path to intel firmware descriptor" depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config HAVE_REFCODE_BLOB depends on ARCH_X86 diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c index 7c7b6f1..a69990f 100644 --- a/src/soc/intel/baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/baytrail/microcode/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode[] = { -#include "../../../../../3rdparty/soc/intel/baytrail/microcode_blob.h" +#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h" }; diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6cec3db..4a71aa7 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -211,7 +211,7 @@ config HAVE_ME_BIN help The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty repository. If + firmware might be provided in coreboot's 3rdparty/blobs repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM. @@ -219,7 +219,7 @@ config HAVE_ME_BIN config ME_BIN_PATH string "Path to management engine firmware" depends on HAVE_ME_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" config HAVE_IFD_BIN bool "Use Intel Firmware Descriptor from existing binary" @@ -260,7 +260,7 @@ config IFD_PLATFORM_SECTION config IFD_BIN_PATH string "Path to intel firmware descriptor" depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config LOCK_MANAGEMENT_ENGINE bool "Lock Management Engine section" diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c index cd7fad6..4f06cb2 100644 --- a/src/soc/intel/broadwell/microcode/microcode_blob.c +++ b/src/soc/intel/broadwell/microcode/microcode_blob.c @@ -18,6 +18,6 @@ */ unsigned microcode[] = { -#include "../../../../../3rdparty/soc/intel/broadwell/microcode_blob.h" +#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h" }; diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index fc32102..ee0a0ef 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -49,7 +49,7 @@ config MAX_CPUS config MTS_DIRECTORY string "Directory where MTS microcode files are located" - default "3rdparty/cpu/nvidia/tegra132/current/prod" + default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod" help Path to directory where MTS microcode files are located. diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 5c03d52..4132708 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -30,7 +30,7 @@ config MBN_ENCAPSULATION config SBL_BLOB depends on USE_BLOBS string "file name of the Qualcomm SBL blob" - default "3rdparty/cpu/qualcomm/ipq806x/uber-sbl.mbn" + default "3rdparty/blobs/cpu/qualcomm/ipq806x/uber-sbl.mbn" help The path and filename of the binary blob containing ipq806x early initialization code, as supplied by the diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 8cf8d7a..4910d95 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -83,7 +83,7 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn # Location of the binary blobs -mbn-root := 3rdparty/cpu/qualcomm/ipq806x +mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq806x # Create make variables to aid cbfs-files-handler in processing the blobs (add # them all as raw binaries at the root level). diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 1cde349..9f49134 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -52,6 +52,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" util/exynos/fixed_cksum.py $< $<.cksum 32768 - cat 3rdparty/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@ + cat 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@ endif diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index e42fc9a..753e6d0 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -54,6 +54,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" util/exynos/variable_cksum.py $< $<.cksum - cat 3rdparty/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@ + cat 3rdparty/blobs/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@ endif diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index acc2d72..ac56849 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -74,20 +74,20 @@ config HUDSON_GEC_FWM config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM config HUDSON_GEC_FWM_FILE string "GEC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM config HUDSON_FWM diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index bcadd8d..ea86a32 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -89,7 +89,7 @@ cbfs-files-y += hudson/xhci hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) hudson/xhci-position := $(HUDSON_XHCI_POSITION) hudson/xhci-type := raw -hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty if enabled) +hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled) endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) @@ -97,7 +97,7 @@ cbfs-files-y += hudson/imc hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) hudson/imc-position := $(HUDSON_IMC_POSITION) hudson/imc-type := raw -hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled) +hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled) endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 891a8e0..28f2d19 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -134,7 +134,7 @@ if SB800_IMC_FWM config SB800_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/southbridge/amd/sb800/imc.bin" + default "3rdparty/blobs/southbridge/amd/sb800/imc.bin" choice prompt "SB800 Firmware ROM Position" diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 9d1010f..cbfb4f9 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -83,12 +83,12 @@ config HUDSON_PSP config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "3rdparty/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON + default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON + default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON depends on HUDSON_IMC_FWM config HUDSON_GEC_FWM_FILE @@ -126,7 +126,7 @@ endif # HUDSON_FWM config AMD_PUBKEY_FILE depends on HUDSON_PSP string "AMD public Key" - default "3rdparty/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 + default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 config HUDSON_SATA_MODE int "SATA Mode" diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c66d541..c5978f1 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -133,7 +133,7 @@ cbfs-files-y += fch/xhci fch/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) fch/xhci-position := $(HUDSON_XHCI_POSITION) fch/xhci-type := raw -fch/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty if enabled) +fch/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled) endif ifeq ($(CONFIG_HUDSON_IMC_FWM), y) @@ -141,7 +141,7 @@ cbfs-files-y += fch/imc fch/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) fch/imc-position := $(HUDSON_IMC_POSITION) fch/imc-type := raw -fch/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled) +fch/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled) endif ifeq ($(CONFIG_HUDSON_GEC_FWM), y) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 970605c..8c51520 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -106,7 +106,7 @@ config IFD_PLATFORM_SECTION config IFD_BIN_PATH string "Path to intel firmware descriptor" depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config HAVE_GBE_BIN bool "Add gigabit ethernet firmware" @@ -119,7 +119,7 @@ config HAVE_GBE_BIN config GBE_BIN_PATH string "Path to gigabit ethernet firmware" depends on HAVE_GBE_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/gbe.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" config HAVE_ME_BIN bool "Add Intel Management Engine firmware" @@ -127,7 +127,7 @@ config HAVE_ME_BIN help The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty repository. If + firmware might be provided in coreboot's 3rdparty/blobs repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM. @@ -135,7 +135,7 @@ config HAVE_ME_BIN config ME_BIN_PATH string "Path to management engine firmware" depends on HAVE_ME_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" config LOCK_MANAGEMENT_ENGINE bool "Lock Management Engine section" diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index b47bf99..c62cf32 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -87,7 +87,7 @@ config IFD_ME_SECTION config IFD_BIN_PATH string "Path to intel firmware descriptor" depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config HAVE_ME_BIN @@ -96,7 +96,7 @@ config HAVE_ME_BIN help The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty repository. If + firmware might be provided in coreboot's 3rdparty/blobs repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM. @@ -104,7 +104,7 @@ config HAVE_ME_BIN config ME_BIN_PATH string "Path to management engine firmware" depends on HAVE_ME_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" config HPET_MIN_TICKS hex diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 4797e96..d0725d2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -98,7 +98,7 @@ config IFD_PLATFORM_SECTION config IFD_BIN_PATH string "Path to intel firmware descriptor" depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" config HAVE_ME_BIN bool "Add Intel Management Engine firmware" @@ -106,7 +106,7 @@ config HAVE_ME_BIN help The Intel processor in the selected system requires a special firmware for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty repository. If + firmware might be provided in coreboot's 3rdparty/blobs repository. If not and if you don't have the firmware elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME firmware on your flash ROM. @@ -114,7 +114,7 @@ config HAVE_ME_BIN config ME_BIN_PATH string "Path to management engine firmware" depends on HAVE_ME_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" config ME_MBP_CLEAR_LATE bool "Defer wait for ME MBP Cleared" diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index d9ac731..5102cef 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -37,7 +37,7 @@ config CPU_AMD_AGESA_BINARY_PI select HUDSON_DISABLE_IMC help Use a binary PI package. Generally, these will be stored in the - "3rdparty" directory. For some processors, these must be obtained + "3rdparty/blobs" directory. For some processors, these must be obtained directly from AMD Embedded Processors Group (http://www.amdcom/embedded). diff --git a/src/vendorcode/amd/pi/00630F01/Kconfig b/src/vendorcode/amd/pi/00630F01/Kconfig index bd49990..b7216de 100644 --- a/src/vendorcode/amd/pi/00630F01/Kconfig +++ b/src/vendorcode/amd/pi/00630F01/Kconfig @@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy config AGESA_BINARY_PI_PATH_DEFAULT string - default "3rdparty/pi/amd/00630F01" + default "3rdparty/blobs/pi/amd/00630F01" help The default binary file name to use for AMD platform initialization. diff --git a/src/vendorcode/amd/pi/00730F01/Kconfig b/src/vendorcode/amd/pi/00730F01/Kconfig index c630a24..9c0af03 100644 --- a/src/vendorcode/amd/pi/00730F01/Kconfig +++ b/src/vendorcode/amd/pi/00730F01/Kconfig @@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy config AGESA_BINARY_PI_PATH_DEFAULT string - default "3rdparty/pi/amd/00730F01" + default "3rdparty/blobs/pi/amd/00730F01" help The default binary file name to use for AMD platform initialization. diff --git a/src/vendorcode/google/chromeos/build-snow b/src/vendorcode/google/chromeos/build-snow index da1566b..5767418 100755 --- a/src/vendorcode/google/chromeos/build-snow +++ b/src/vendorcode/google/chromeos/build-snow @@ -8,7 +8,7 @@ TMP_DIFF="$SCRIPT_DIR/.image-diff.bin" FLASHROM="/usr/local/sbin/flashrom" BL1_NAME="E5250.nbl1.bin" -BL1_PATH="3rdparty/cpu/samsung/exynos5250/" +BL1_PATH="3rdparty/blobs/cpu/samsung/exynos5250/" BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exyn…" die() {

1 0

Patch set updated for coreboot: f90e559 amd/pi: Move AGESA cbfs access into the wrapper
by Marc Jones 05 May '15

05 May '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10058 -gerrit commit f90e55970090f426b231f6af5e00c969fc735604 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue May 5 09:55:57 2015 -0600 amd/pi: Move AGESA cbfs access into the wrapper The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/northbridge/amd/pi/agesawrapper.c | 25 +++++++++++++++++++++++++ src/northbridge/amd/pi/agesawrapper.h | 6 ++++++ src/vendorcode/amd/pi/00630F01/Makefile.inc | 1 + src/vendorcode/amd/pi/00730F01/Makefile.inc | 1 + 4 files changed, 33 insertions(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index efdfdbd..8bcd8ac 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -18,6 +18,7 @@ */ #include <AGESA.h> +#include <cbfs.h> #include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> @@ -589,3 +590,27 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) return Status; } + +const void *agesawrapper_locate_module (const CHAR8 name[8]) +{ + struct cbfs_media media; + struct cbfs_file* file; + const void* agesa; + const AMD_IMAGE_HEADER* image; + const AMD_MODULE_HEADER* module; + size_t file_size; + + if (init_default_cbfs_media(&media)) + return NULL; + file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME); + if (!file) + return NULL; + agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME, + ntohl(file->type), &file_size); + if (!agesa) + return NULL; + image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name); + module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset; + + return module; +} diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index adcc755..b77e04c 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -24,6 +24,11 @@ #include "Porting.h" #include "AGESA.h" +/* TODO: Add a kconfig option to name the AGESA ROM file in CBFS */ +#ifndef CONFIG_CBFS_AGESA_NAME +#define CONFIG_CBFS_AGESA_NAME "AGESA" +#endif + enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ @@ -55,5 +60,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void); VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); VOID amd_initcpuio(void); VOID amd_initmmio(void); +const void *agesawrapper_locate_module (const CHAR8 name[8]); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/vendorcode/amd/pi/00630F01/Makefile.inc b/src/vendorcode/amd/pi/00630F01/Makefile.inc index 7908378..6141763 100644 --- a/src/vendorcode/amd/pi/00630F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00630F01/Makefile.inc @@ -48,6 +48,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include diff --git a/src/vendorcode/amd/pi/00730F01/Makefile.inc b/src/vendorcode/amd/pi/00730F01/Makefile.inc index a302e33..d6ba93c 100644 --- a/src/vendorcode/amd/pi/00730F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00730F01/Makefile.inc @@ -47,6 +47,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include

1 0

Patch set updated for coreboot: 2de9d6c amd/pi: Move AGESA cbfs access into the wrapper
by Marc Jones 05 May '15

05 May '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10058 -gerrit commit 2de9d6cfd31ca26b8eeff8dcdecb988372c2c2df Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue May 5 09:55:57 2015 -0600 amd/pi: Move AGESA cbfs access into the wrapper The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/northbridge/amd/pi/agesawrapper.c | 25 +++++++++++++++++++++++++ src/northbridge/amd/pi/agesawrapper.h | 6 ++++++ src/vendorcode/amd/pi/00630F01/Makefile.inc | 1 + src/vendorcode/amd/pi/00730F01/Makefile.inc | 1 + 4 files changed, 33 insertions(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index efdfdbd..79e3895 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -18,6 +18,7 @@ */ #include <AGESA.h> +#include <cbfs.h> #include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> @@ -589,3 +590,27 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) return Status; } + +const void *agesawrapper_locate_module (const CHAR8 name[8]) +{ + struct cbfs_media media; + struct cbfs_file* file; + const void* agesa; + const AMD_IMAGE_HEADER* image; + const AMD_MODULE_HEADER* module; + size_t file_size; + + if (init_default_cbfs_media(&media)) + return NULL; + file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME); + if (!file) + return NULL; + agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME, + ntohl(file->type), &file_size); + if (!agesa) + return NULL; + image = LibAmdLocateImage(agesa, agesa + ntohl(file->len) - 1, 4096, name); + module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset; + + return module; +} diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index adcc755..b77e04c 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -24,6 +24,11 @@ #include "Porting.h" #include "AGESA.h" +/* TODO: Add a kconfig option to name the AGESA ROM file in CBFS */ +#ifndef CONFIG_CBFS_AGESA_NAME +#define CONFIG_CBFS_AGESA_NAME "AGESA" +#endif + enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ @@ -55,5 +60,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void); VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); VOID amd_initcpuio(void); VOID amd_initmmio(void); +const void *agesawrapper_locate_module (const CHAR8 name[8]); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/vendorcode/amd/pi/00630F01/Makefile.inc b/src/vendorcode/amd/pi/00630F01/Makefile.inc index 7908378..6141763 100644 --- a/src/vendorcode/amd/pi/00630F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00630F01/Makefile.inc @@ -48,6 +48,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include diff --git a/src/vendorcode/amd/pi/00730F01/Makefile.inc b/src/vendorcode/amd/pi/00730F01/Makefile.inc index a302e33..d6ba93c 100644 --- a/src/vendorcode/amd/pi/00730F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00730F01/Makefile.inc @@ -47,6 +47,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include

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Patch merged into coreboot/master: b9cd5ec sandy/ivy boards: Rename defines from onboard.h for ACPI
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit b9cd5ece14f0aeaa713299d114fcdca46276acf9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 24 16:05:58 2015 +0300 sandy/ivy boards: Rename defines from onboard.h for ACPI Adopted style from later Chromebooks. Change-Id: I4993b8f40489b6bf5d08e00089f36f293853629e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/9992 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/9992 for details. -gerrit

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Patch merged into coreboot/master: d914412 cbfs: make cbfs_load_prog_stage_by_offset() public
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit d914412beca76f97fe2f4a5bdbefdfcc398f72c1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 cbfs: make cbfs_load_prog_stage_by_offset() public That function will be used by the vboot loader. Change-Id: I204c6cd5eede3645750b50fe3ed30d77c22dbf43 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10101 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10101 for details. -gerrit

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Patch merged into coreboot/master: 2daadf8 timestamp: refine boot CPU test
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 2daadf8f576363c6d215409b4d7899990344f3b5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 timestamp: refine boot CPU test The timestamp code's restriction to run only on the BSP is for AMD systems. No need to run it everywhere, so tighten the test (and only run boot_cpu() when required). Change-Id: I800e817cc89e8688a671672961cab15c7f788ba8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10102 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10102 for details. -gerrit

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Patch merged into coreboot/master: ae1fcc3 vboot: add cbfs_core
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit ae1fcc3c1d95067e41dbffa6dacb27279ee7a07e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot: add cbfs_core And we don't support lzma compressed data in verstage. Change-Id: I3d8d3290f147871c49e9440e9b54bbf2742aaa9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10103 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10103 for details. -gerrit

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Patch merged into coreboot/master: 9e80e27 timestamp: provide weak default implementation of timestamp_get
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 9e80e27d3874b1eebe06ef90e9af16f0b07ec180 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 timestamp: provide weak default implementation of timestamp_get Change-Id: I2e7f17a686f6af3426c9d68cd9394e9a88dbf358 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10104 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10104 for details. -gerrit

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Patch merged into coreboot/master: 168eda5 arch/arm64: provide boot_cpu()
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 168eda5f0d26a233bd997e0b0597926e80df57a3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 arch/arm64: provide boot_cpu() Change-Id: I708041133dfafdc97e052952ad9d8f2e4164209c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10105 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10105 for details. -gerrit

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Patch merged into coreboot/master: 26681ec vboot2: Fix compiler flags dropped during verstage/libverstage split
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 26681ec2cbe6d7f0b6a441ec817ad0d0a8ddeef9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot2: Fix compiler flags dropped during verstage/libverstage split verstage still needs to be built with its flags. Change-Id: I125e4be283d3838fc7ce6587bf9996731540d517 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10098 Tested-by: build bot (Jenkins) See http://review.coreboot.org/10098 for details. -gerrit

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coreboot-gerrit May 2015