coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 78d2021 cbfs: make cbfs_load_prog_stage_by_offset() public
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10101 -gerrit commit 78d2021f3c1789c2a73de3993407c632d01c9b00 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 cbfs: make cbfs_load_prog_stage_by_offset() public That function will be used by the vboot loader. Change-Id: I204c6cd5eede3645750b50fe3ed30d77c22dbf43 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/include/cbfs.h | 2 ++ src/lib/cbfs.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 05ce2f7..1d7917c 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -60,6 +60,8 @@ void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset); /* Load a stage from a prog structure. Returns < 0 on error. 0 on success. */ struct prog; int cbfs_load_prog_stage(struct cbfs_media *media, struct prog *prog); +int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, + struct prog *prog, ssize_t offset); /* Simple buffer for streaming media. */ struct cbfs_simple_buffer { diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 88a292f..8239f07 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -74,7 +74,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -static int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, +int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, struct prog *prog, ssize_t offset) { struct cbfs_stage stage;

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Patch set updated for coreboot: 6094e05 vboot checkopoint
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10059 -gerrit commit 6094e05de8ace1c148924aee0e1d3099847c1ba5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 1 16:48:54 2015 -0500 vboot checkopoint Change-Id: I2a43c8a2f8f0626a7635150aa3efc44329a477d9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/Makefile.inc | 9 +- src/arch/arm64/Makefile.inc | 5 +- src/include/program_loading.h | 1 + src/lib/Makefile.inc | 1 + src/lib/loaders/Makefile.inc | 1 + src/lib/loaders/load_and_run_payload.c | 4 +- src/lib/loaders/load_and_run_ramstage.c | 7 +- src/lib/loaders/load_and_run_romstage.c | 7 + src/vendorcode/google/chromeos/chromeos.c | 19 +- src/vendorcode/google/chromeos/vboot2/Kconfig | 8 +- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 22 +- src/vendorcode/google/chromeos/vboot2/common.c | 33 --- src/vendorcode/google/chromeos/vboot2/misc.h | 3 +- .../google/chromeos/vboot2/vboot_handoff.c | 53 ++--- .../google/chromeos/vboot2/vboot_loader.c | 243 +++++++++++++++++++++ src/vendorcode/google/chromeos/vboot2/verstub.c | 107 --------- 16 files changed, 321 insertions(+), 202 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index c05b33e..6e52def 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -61,9 +61,9 @@ bootblock-y += memmove.S bootblock-y += div0.c bootblock-y += clock.c -$(objcbfs)/bootblock.debug: $$(bootblock-objs) $$(VERSTAGE_LIB) +$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(objgenerated)/libverstage.a @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) $(objgenerated)/libverstage.a --end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -73,10 +73,11 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group +verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c verstage-y += memset.S diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 3791ae7..095457e 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -84,11 +84,12 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM64 ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) -$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h +$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(libverstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(verstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(libverstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +verstage-y += boot.c verstage-y += div0.c verstage-y += eabi_compat.c verstage-y += ../../lib/memset.c diff --git a/src/include/program_loading.h b/src/include/program_loading.h index ca80b0e..5fc0fd6 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -39,6 +39,7 @@ struct buffer_area { }; enum prog_type { + PROG_VERSTAGE, PROG_ROMSTAGE, PROG_RAMSTAGE, PROG_PAYLOAD, diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ef4e2aa..b50e3aa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -34,6 +34,7 @@ verstage-y += prog_ops.c verstage-y += delay.c verstage-y += cbfs.c verstage-y += cbfs_core.c +verstage-y += halt.c verstage-y += memcmp.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc index fbc7f87..6b22801 100644 --- a/src/lib/loaders/Makefile.inc +++ b/src/lib/loaders/Makefile.inc @@ -23,3 +23,4 @@ romstage-y += cbfs_ramstage_loader.c romstage-y += load_and_run_ramstage.c ramstage-y += cbfs_payload_loader.c ramstage-y += load_and_run_payload.c +verstage-y += load_and_run_romstage.c diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 7a08097..4928e0c 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -27,12 +27,12 @@ #include <symbols.h> #include <timestamp.h> -extern const struct prog_loader_ops vboot_payload_loader; +extern const struct prog_loader_ops vboot_loader; extern const struct prog_loader_ops cbfs_payload_loader; static const struct prog_loader_ops *payload_ops[] = { #if CONFIG_VBOOT_VERIFY_FIRMWARE - &vboot_payload_loader, + &vboot_loader, #endif &cbfs_payload_loader, }; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index fddea4d..af8667a 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -23,17 +23,20 @@ #include <cbfs.h> #include <program_loading.h> #include <romstage_handoff.h> +#include <rules.h> #include <stage_cache.h> #include <timestamp.h> extern const struct prog_loader_ops cbfs_ramstage_loader; -extern const struct prog_loader_ops vboot_ramstage_loader; +extern const struct prog_loader_ops vboot_loader; static const struct prog_loader_ops *loaders[] = { #if CONFIG_VBOOT_VERIFY_FIRMWARE - &vboot_ramstage_loader, + &vboot_loader, #endif +#if !ENV_VERSTAGE &cbfs_ramstage_loader, +#endif }; void __attribute__((weak)) stage_cache_add(int stage_id, struct prog *stage) {} diff --git a/src/lib/loaders/load_and_run_romstage.c b/src/lib/loaders/load_and_run_romstage.c index b54bfc7..25a75bd 100644 --- a/src/lib/loaders/load_and_run_romstage.c +++ b/src/lib/loaders/load_and_run_romstage.c @@ -24,12 +24,19 @@ #include <cbfs.h> #include <halt.h> #include <program_loading.h> +#include <rules.h> #include <timestamp.h> extern const struct prog_loader_ops cbfs_romstage_loader; +extern const struct prog_loader_ops vboot_loader; static const struct prog_loader_ops *loaders[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_loader, +#endif +#if !ENV_VERSTAGE &cbfs_romstage_loader, +#endif }; void run_romstage(void) diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index fb72673..1e49bd1 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "vboot_handoff.h" -int vboot_skip_display_init(void) +static int vboot_handoff_flag(uint32_t flag) { struct vboot_handoff *vbho; @@ -35,7 +35,22 @@ int vboot_skip_display_init(void) if (vbho == NULL) return 0; - return !(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DISPLAY); + return !!(vbho->init_params.out_flags & flag); +} + +int vboot_skip_display_init(void) +{ + return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY); +} + +int vboot_enable_developer(void) +{ + return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER); +} + +int vboot_enable_recovery(void) +{ + return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY); } int __attribute__((weak)) clear_recovery_mode_switch(void) diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig index 8396113..bb6c1ad 100644 --- a/src/vendorcode/google/chromeos/vboot2/Kconfig +++ b/src/vendorcode/google/chromeos/vboot2/Kconfig @@ -17,14 +17,14 @@ ## config VBOOT_STARTS_IN_BOOTBLOCK - bool + bool "Vboot starts verifying in bootblock" default n depends on VBOOT_VERIFY_FIRMWARE help Firmware verification happens during or at the end of bootblock. config VBOOT_STARTS_IN_ROMSTAGE - bool + bool "Vboot starts verifying in romstage" default n depends on VBOOT_VERIFY_FIRMWARE && !VBOOT_STARTS_IN_BOOTBLOCK help @@ -51,12 +51,12 @@ config VBOOT_DISABLE_DEV_ON_RECOVERY handy on embedded devices with limited input capabilities. config SEPARATE_VERSTAGE - bool + bool "Vboot verification is built into a separate stage" default n depends on VBOOT_VERIFY_FIRMWARE config RETURN_FROM_VERSTAGE - bool + bool "The separate verification stage returns to its caller" default n depends on SEPARATE_VERSTAGE help diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index def43ad..bc0ab6b 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -20,13 +20,16 @@ libverstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__ +bootblock-y += vboot_loader.c +romstage-y += vboot_loader.c +ramstage-y += vboot_loader.c +verstage-y += vboot_loader.c + bootblock-y += ../vboot_common.c verstage-y += ../vboot_common.c romstage-y += ../vboot_common.c ramstage-y += ../vboot_common.c -bootblock-y += verstub.c -libverstage-y += verstub.c bootblock-y += common.c libverstage-y += verstage.c verstage-y += common.c @@ -37,9 +40,20 @@ libverstage-y += antirollback.c endif romstage-y += vboot_handoff.c common.c +ramstage-y += common.c + verstage-y += verstage.ld -VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) +ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y)) +else +ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y) +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-bootblock-y)) +else +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-romstage-y)) +endif +endif # CONFIG_SEPARATE_VERSTAGE + VB2_LIB = $(obj)/external/vboot_reference/vboot_fw20.a VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CPPFLAGS_verstage))) VBOOT_CFLAGS += $(libverstage-c-ccopts) @@ -64,7 +78,7 @@ fallback/verstage-file = $(objcbfs)/verstage.elf fallback/verstage-type = stage fallback/verstage-compression = none else -ifeq ($(VBOOT_STARTS_IN_BOOTBLOCK),y) +ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y) bootblock-srcs += $(objgenerated)/libverstage.a else romstage-srcs += $(objgenerated)/libverstage.a diff --git a/src/vendorcode/google/chromeos/vboot2/common.c b/src/vendorcode/google/chromeos/vboot2/common.c index d70a108..beffebe 100644 --- a/src/vendorcode/google/chromeos/vboot2/common.c +++ b/src/vendorcode/google/chromeos/vboot2/common.c @@ -25,39 +25,6 @@ #include "../vboot_handoff.h" #include "misc.h" -void *vboot_load_stage(int stage_index, - struct vboot_region *fw_main, - struct vboot_components *fw_info) -{ - struct cbfs_media default_media, *media = &default_media; - uintptr_t fc_addr; - uint32_t fc_size; - void *entry; - - if (stage_index >= fw_info->num_components) { - printk(BIOS_INFO, "invalid stage index\n"); - return NULL; - } - - fc_addr = fw_main->offset_addr + fw_info->entries[stage_index].offset; - fc_size = fw_info->entries[stage_index].size; - if (fc_size == 0 || - fc_addr + fc_size > fw_main->offset_addr + fw_main->size) { - printk(BIOS_INFO, "invalid stage address or size\n"); - return NULL; - } - - init_default_cbfs_media(media); - - /* we're making cbfs access offset outside of the region managed by - * cbfs. this works because cbfs_load_stage_by_offset does not check - * the offset. */ - entry = cbfs_load_stage_by_offset(media, fc_addr); - if (entry == (void *)-1) - entry = NULL; - return entry; -} - struct vb2_working_data * const vboot_get_working_data(void) { return (struct vb2_working_data *)_vboot2_work; diff --git a/src/vendorcode/google/chromeos/vboot2/misc.h b/src/vendorcode/google/chromeos/vboot2/misc.h index 7425082..d942d56 100644 --- a/src/vendorcode/google/chromeos/vboot2/misc.h +++ b/src/vendorcode/google/chromeos/vboot2/misc.h @@ -22,8 +22,7 @@ #include "../vboot_common.h" -void *vboot2_verify_firmware(void); -void *vboot2_load_ramstage(void); +void vboot_fill_handoff(void); void verstage_main(void); void *vboot_load_stage(int stage_index, struct vboot_region *fw_main, diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c index b84e47e..16261b4 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c @@ -36,30 +36,6 @@ #include "../vboot_handoff.h" #include "misc.h" -static void *load_ramstage(struct vboot_handoff *vboot_handoff, - struct vboot_region *fw_main) -{ - struct vboot_components *fw_info; - void *ret; - int i; - - fw_info = vboot_locate_components(fw_main); - if (fw_info == NULL) - die("failed to locate firmware components\n"); - - /* these offset & size are used to load a rw boot loader */ - for (i = 0; i < fw_info->num_components; i++) { - vboot_handoff->components[i].address = - fw_main->offset_addr + fw_info->entries[i].offset; - vboot_handoff->components[i].size = fw_info->entries[i].size; - } - - timestamp_add_now(TS_START_COPYRAM); - ret = vboot_load_stage(CONFIG_VBOOT_RAMSTAGE_INDEX, fw_main, fw_info); - timestamp_add_now(TS_END_COPYRAM); - return ret; -} - /** * Sets vboot_handoff based on the information in vb2_shared_data * @@ -146,14 +122,13 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, vb_sd->recovery_reason = vb2_sd->recovery_reason; } -/** - * Load ramstage and return the entry point - */ -void *vboot2_load_ramstage(void) +void vboot_fill_handoff(void) { + int i; struct vboot_handoff *vh; struct vb2_shared_data *sd; struct vboot_region fw_main; + struct vboot_components *fw_info; struct vb2_working_data *wd = vboot_get_working_data(); sd = vboot_get_work_buffer(wd); @@ -172,17 +147,15 @@ void *vboot2_load_ramstage(void) /* needed until we finish transtion to vboot2 for kernel verification */ fill_vboot_handoff(vh, sd); - if (vboot_is_readonly_path(wd)) - /* we're on recovery path. continue to ro-ramstage. */ - return NULL; - - if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) { - return cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/ramstage"); - } else { - printk(BIOS_INFO, "loading ramstage from Slot %c\n", - sd->fw_slot ? 'B' : 'A'); - vb2_get_selected_region(wd, &fw_main); - return load_ramstage(vh, &fw_main); + vb2_get_selected_region(wd, &fw_main); + fw_info = vboot_locate_components(&fw_main); + if (fw_info == NULL) + die("failed to locate firmware components\n"); + + /* these offset & size are used to load a rw boot loader */ + for (i = 0; i < fw_info->num_components; i++) { + vh->components[i].address = + fw_main.offset_addr + fw_info->entries[i].offset; + vh->components[i].size = fw_info->entries[i].size; } } diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c new file mode 100644 index 0000000..c731abb --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <program_loading.h> +#include <rules.h> +#include <string.h> +#include "misc.h" +#include "../symbols.h" + +/* The stage loading code is compiled and entered from mutilple stages. The + * helper functions below attempt to provde more clarity on when certain + * code should be called. */ + +static int verification_should_run(void) +{ + if (ENV_VERSTAGE && IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) + return 1; + + if (!IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) { + if (ENV_ROMSTAGE && + IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) + return 1; + if (ENV_BOOTBLOCK && + IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + return 1; + } + + return 0; +} + +static int verstage_should_load(void) +{ + if (!IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) + return 0; + + if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) + return 1; + + if (ENV_BOOTBLOCK && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + return 1; + + return 0; +} + +static void init_vb2_working_data(void) +{ + struct vb2_working_data *wd; + + wd = vboot_get_working_data(); + memset(wd, 0, _vboot2_work_size); + /* + * vboot prefers 16-byte alignment. This takes away 16 bytes + * from the VBOOT2_WORK region, but the vboot devs said that's okay. + */ + wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); + wd->buffer_size = _vboot2_work_size - wd->buffer_offset; +} + +static int vboot_loader_active(struct prog *prog) +{ + struct vb2_working_data *wd; + int run_verification; + + run_verification = verification_should_run(); + + if (run_verification) { + init_vb2_working_data(); + verstage_main(); + } else if (verstage_should_load()) { + struct prog verstage = { + .type = PROG_VERSTAGE, + .name = CONFIG_CBFS_PREFIX "/verstage", + }; + + /* load verstage from RO */ + if (cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, &verstage)) + die("failed to load verstage"); + + /* verify and select a slot */ + prog_run(&verstage); + + /* This is not actually possible to hit this condition at + * runtime, but this provides a hint to the compiler for dead + * code elimination below. */ + if (!IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) + return 0; + } + + wd = vboot_get_working_data(); + + if (vboot_is_slot_selected(wd)) { + if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES) && + run_verification) { + /* RW A or B */ + struct vboot_region fw_main; + + vb2_get_selected_region(wd, &fw_main); + cbfs_set_header_offset(fw_main.offset_addr); + } + return 1; + } + + return 0; +} + +static uintptr_t vboot_fw_region(int fw_index, struct vboot_region *fw_main, + struct vboot_components *fw_info, size_t *size) +{ + uintptr_t fc_addr; + uint32_t fc_size; + + if (fw_index >= fw_info->num_components) { + printk(BIOS_INFO, "invalid stage index: %d\n", fw_index); + return 0; + } + + fc_addr = fw_main->offset_addr + fw_info->entries[fw_index].offset; + fc_size = fw_info->entries[fw_index].size; + if (fc_size == 0 || + fc_addr + fc_size > fw_main->offset_addr + fw_main->size) { + printk(BIOS_INFO, "invalid stage address or size\n"); + return 0; + } + + *size = fc_addr; + return fc_addr; +} + +/* This function is only called when vboot_loader_active() returns 1. That + * means we are taking vboot paths. */ +static int vboot_prepare(struct prog *prog) +{ + struct vb2_working_data *wd; + struct vboot_region fw_main; + struct vboot_components *fw_info; + + /* Code size optimization. We'd never actually get called under the + * followin cirumstances because verstage was loaded and ran -- never + * returning. */ + if (verstage_should_load() && !IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) + return 0; + + /* In the multi cbfs case the cbfs offset pointer has already been + * updated after firmware verification. */ + if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) { + if (!ENV_RAMSTAGE && + cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, prog) != 0) + return -1; + + /* Need to load payload. */ + if (ENV_RAMSTAGE) { + void *payload; + size_t size; + + payload = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + prog->name, + CBFS_TYPE_PAYLOAD, + &size); + + if (payload == NULL) + die("Couldn't load payload\n"); + + prog_set_area(prog, payload, size); + } + return 0; + } + + wd = vboot_get_working_data(); + vb2_get_selected_region(wd, &fw_main); + fw_info = vboot_locate_components(&fw_main); + if (fw_info == NULL) + die("failed to locate firmware components\n"); + + /* Load payload in ramstage. */ + if (ENV_RAMSTAGE) { + uintptr_t payload; + void *payload_ptr; + size_t size; + + payload = vboot_fw_region(CONFIG_VBOOT_BOOT_LOADER_INDEX, + &fw_main, fw_info, &size); + + if (payload == 0) + die("Couldn't load payload."); + + payload_ptr = vboot_get_region(payload, size, NULL); + + if (payload_ptr == NULL) + die("Couldn't load payload."); + + prog_set_area(prog, payload_ptr, size); + } else { + uintptr_t stage; + size_t size; + int stage_index = 0; + + if (prog->type == PROG_ROMSTAGE) + stage_index = CONFIG_VBOOT_ROMSTAGE_INDEX; + else if (prog->type == PROG_RAMSTAGE) + stage_index = CONFIG_VBOOT_RAMSTAGE_INDEX; + else + die("Invalid program type for vboot."); + + stage = vboot_fw_region(stage_index, &fw_main, fw_info, &size); + + if (stage == 0) + die("Vboot stage load failed."); + + if (cbfs_load_prog_stage_by_offset(CBFS_DEFAULT_MEDIA, + prog, stage) < 0) + die("Vboot couldn't load stage"); + } + + /* Fill in vboot handoff structure before moving to ramstage. */ + if (ENV_ROMSTAGE) + vboot_fill_handoff(); + + return 0; +} + +const struct prog_loader_ops vboot_loader = { + .name = "VBOOT", + .is_loader_active = vboot_loader_active, + .prepare = vboot_prepare, +}; diff --git a/src/vendorcode/google/chromeos/vboot2/verstub.c b/src/vendorcode/google/chromeos/vboot2/verstub.c deleted file mode 100644 index c4319ba..0000000 --- a/src/vendorcode/google/chromeos/vboot2/verstub.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/stages.h> -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <timestamp.h> -#include "../chromeos.h" -#include "../symbols.h" -#include "misc.h" - -static struct vb2_working_data *init_vb2_working_data(void) -{ - struct vb2_working_data *wd; - - wd = vboot_get_working_data(); - memset(wd, 0, _vboot2_work_size); - /* - * vboot prefers 16-byte alignment. This takes away 16 bytes - * from the VBOOT2_WORK region, but the vboot devs said that's okay. - */ - wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16); - wd->buffer_size = _vboot2_work_size - wd->buffer_offset; - - return wd; -} - -/** - * Verify a slot and jump to the next stage - * - * This could be either part of the (1) bootblock or the (2) verstage, depending - * on CONFIG_RETURN_FROM_VERSTAGE. - * - * 1) It jumps to the verstage and comes back, then, loads the romstage over the - * verstage space and exits to it. (note the cbfs cache is trashed on return - * from the verstage.) - * - * 2) We're already in the verstage. Verify firmware, then load the romstage and - * exits to it. - */ -void *vboot2_verify_firmware(void) -{ - void *entry; - struct vb2_working_data *wd; - - wd = init_vb2_working_data(); - - if (IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) { - /* load verstage from RO */ - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/verstage"); - if (entry == (void *)-1) - die("failed to load verstage"); - - /* verify and select a slot */ - stage_exit(entry); - } else { - verstage_main(); - } - - /* jump to the selected slot */ - timestamp_add_now(TS_START_COPYROM); - entry = (void *)-1; - if (vboot_is_slot_selected(wd)) { - /* RW A or B */ - struct vboot_region fw_main; - - vb2_get_selected_region(wd, &fw_main); - - if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) { - cbfs_set_header_offset(fw_main.offset_addr); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/romstage"); - } else { - struct vboot_components *fw_info; - fw_info = vboot_locate_components(&fw_main); - if (fw_info == NULL) - die("failed to locate firmware components\n"); - entry = vboot_load_stage(CONFIG_VBOOT_ROMSTAGE_INDEX, - &fw_main, fw_info); - } - } else if (vboot_is_readonly_path(wd)) { - /* RO */ - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/romstage"); - } - timestamp_add_now(TS_END_COPYROM); - - return entry; -}

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New patch to review for coreboot: 75ff69a fsp platforms: Notify FSP after PCI device init
by David Imhoff 05 May '15

05 May '15

David Imhoff (dimhoff_devel(a)xs4all.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10100 -gerrit commit 75ff69a886e3bf62e9787204897e1b67191fd2a1 Author: David Imhoff <dimhoff_devel(a)xs4all.nl> Date: Tue May 5 12:45:54 2015 +0200 fsp platforms: Notify FSP after PCI device init Notify FSP of the EnumInitPhaseAfterPciEnumeration stage after PCI device initialization. As described in fsp-architecture-spec.pdf, April 2014, Par 6.8.3. This fixes shutdown issues on Minnowboard Max. TEST=Built and booted on Minnowboard Max. Verified power LED off after Linux power off. Change-Id: Ia6508c07aa53ba436bb5899a48ecd64a117524e5 Signed-off-by: David Imhoff <dimhoff_devel(a)xs4all.nl> --- src/drivers/intel/fsp1_0/fsp_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 3147b67..93e25a9 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -343,7 +343,7 @@ static void fsp_finalize(void *unused) } /* Set up for the ramstage FSP calls */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, fsp_after_pci_enum, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); /* Update the MRC/fast boot cache as part of the late table writing stage */

1 0

New patch to review for coreboot: 41750ef AGESA PI: Access the binary PI with new cbfs way.
by Zheng Bao 05 May '15

05 May '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10099 -gerrit commit 41750efc2d24813a58e5a2f20394a5d2202c9166 Author: zbao <fishbaozi(a)gmail.com> Date: Wed May 6 01:49:48 2015 +0800 AGESA PI: Access the binary PI with new cbfs way. Change-Id: Id47db5be57e33412fa3a0d229db4260de70726bb Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/northbridge/amd/pi/agesawrapper.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 79e3895..e1e9708 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -593,23 +593,16 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) const void *agesawrapper_locate_module (const CHAR8 name[8]) { - struct cbfs_media media; - struct cbfs_file* file; const void* agesa; const AMD_IMAGE_HEADER* image; const AMD_MODULE_HEADER* module; - size_t file_size; + size_t file_size = -1; - if (init_default_cbfs_media(&media)) - return NULL; - file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME); - if (!file) - return NULL; - agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME, - ntohl(file->type), &file_size); + agesa = cbfs_boot_map_with_leak(CONFIG_CBFS_AGESA_NAME, CBFS_TYPE_RAW, &file_size); if (!agesa) return NULL; - image = LibAmdLocateImage(agesa, agesa + ntohl(file->len) - 1, 4096, name); + + image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name); module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset; return module;

1 0

Patch set updated for coreboot: 151c4b6 amd/pi: Move AGESA cbfs access into the wrapper
by Zheng Bao 05 May '15

05 May '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10058 -gerrit commit 151c4b6931f3b8a5099c68665f32d64ee8687ef7 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 1 14:57:50 2015 -0600 amd/pi: Move AGESA cbfs access into the wrapper The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- 3rdparty | 2 +- src/northbridge/amd/pi/agesawrapper.c | 25 +++++++++++++++++++++++++ src/northbridge/amd/pi/agesawrapper.h | 6 ++++++ src/vendorcode/amd/pi/00630F01/Makefile.inc | 1 + src/vendorcode/amd/pi/00730F01/Makefile.inc | 1 + 5 files changed, 34 insertions(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index 892a697..98bafbe 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit 892a6976ba8c7d14e1aaa518d4d02923d51b22c3 +Subproject commit 98bafbe3730e42e00d111037c2e378e0da085bd8 diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index efdfdbd..79e3895 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -18,6 +18,7 @@ */ #include <AGESA.h> +#include <cbfs.h> #include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> @@ -589,3 +590,27 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) return Status; } + +const void *agesawrapper_locate_module (const CHAR8 name[8]) +{ + struct cbfs_media media; + struct cbfs_file* file; + const void* agesa; + const AMD_IMAGE_HEADER* image; + const AMD_MODULE_HEADER* module; + size_t file_size; + + if (init_default_cbfs_media(&media)) + return NULL; + file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME); + if (!file) + return NULL; + agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME, + ntohl(file->type), &file_size); + if (!agesa) + return NULL; + image = LibAmdLocateImage(agesa, agesa + ntohl(file->len) - 1, 4096, name); + module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset; + + return module; +} diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index adcc755..b77e04c 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -24,6 +24,11 @@ #include "Porting.h" #include "AGESA.h" +/* TODO: Add a kconfig option to name the AGESA ROM file in CBFS */ +#ifndef CONFIG_CBFS_AGESA_NAME +#define CONFIG_CBFS_AGESA_NAME "AGESA" +#endif + enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ @@ -55,5 +60,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void); VOID OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); VOID amd_initcpuio(void); VOID amd_initmmio(void); +const void *agesawrapper_locate_module (const CHAR8 name[8]); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/vendorcode/amd/pi/00630F01/Makefile.inc b/src/vendorcode/amd/pi/00630F01/Makefile.inc index 7908378..6141763 100644 --- a/src/vendorcode/amd/pi/00630F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00630F01/Makefile.inc @@ -48,6 +48,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include diff --git a/src/vendorcode/amd/pi/00730F01/Makefile.inc b/src/vendorcode/amd/pi/00730F01/Makefile.inc index a302e33..d6ba93c 100644 --- a/src/vendorcode/amd/pi/00730F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00730F01/Makefile.inc @@ -47,6 +47,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common +AGESA_INC += -I$(src)/northbridge/amd/pi AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include

1 0

Patch set updated for coreboot: dfd4648 imgtec/pistachio: Add comment on the unusual memory layout
by Patrick Georgi 05 May '15

05 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10039 -gerrit commit dfd4648a458b7cda51560bbdfc77e374eeaab7d3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Apr 30 11:38:13 2015 +0200 imgtec/pistachio: Add comment on the unusual memory layout To avoid having to dig up the constraints again, document the memory layout right in memlayout.ld. Change-Id: I298cc880ae462f5b197ab2f64beb2f0e0d9f5a7d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index e9f6c59..bc67447 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -42,7 +42,10 @@ SECTIONS PRERAM_CBFS_CACHE(0x1a00e000, 72K) SRAM_END(0x1a020000) - /* Bootblock executes out of KSEG0 and sets up the identity mapping. */ + /* Bootblock executes out of KSEG0 and sets up the identity mapping. + * This is identical to SRAM above, and thus also limited 64K and + * needs to avoid conflicts with items set up above. + */ BOOTBLOCK(0x9a000000, 20K) /*

1 0

Patch merged into coreboot/master: c3b0e29 veyron_danger: Turn on backlight enable before VCC_LCD
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit c3b0e29b4396f1fbcc213bf2319c8ffd624bae1a Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Apr 22 15:05:18 2015 -0700 veyron_danger: Turn on backlight enable before VCC_LCD On current Danger boards, VCC_LCD is gated by BL_EN. Thus we need to enable BL_EN in order to power on the display so that we can read the EDID and set things up. Later board revisions may change this ordering, but for now it doesn't seem to be causing a significant issues (no noticable "snow" or other corruption using Pepto display). BUG=none BRANCH=none TEST=booted on Danger, saw dev mode screen come up Change-Id: I70aab8c1f6da2d0fce310d59073026eef0f67821 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1a918824e747600a2f3a88602320f4f563ce17b7 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Iaf17cc4682bd3c46f62cba789e3ecf8d5a474362 Original-Reviewed-on: https://chromium-review.googlesource.com/266913 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/10089 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10089 for details. -gerrit

1 0

Patch merged into coreboot/master: 9ac9ac6 veyron: Initialize EC interrupt GPIO and add them to coreboot tables
by gerrit＠coreboot.org 05 May '15

05 May '15

the following patch was just integrated into master: commit 9ac9ac6309ecd937dedc2b857846158a728aca99 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Apr 24 17:30:36 2015 -0700 veyron: Initialize EC interrupt GPIO and add them to coreboot tables This patch initializes the GPIO for the Chrome EC interrupt line on Veyron boards and passes its description through the coreboot table, so that payloads with keyboard support can use it to detect pending key presses. BRANCH=none BUG=chrome-os-partner:39514 TEST=Booted Jerry, confirmed that it could still detect keypresses. Confirmed that EC log does not show a huge amount of MKBP polls. Change-Id: I4de35ef411c3acc02282ebf8e764785a1e7bf6f1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8ad95d667ef3af3fb217e3c370468dc1d6ec36c9 Original-Change-Id: I8b426621af088460929cfff0a4b46618e2a86725 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/267344 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Reviewed-on: http://review.coreboot.org/10088 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10088 for details. -gerrit

1 0

Patch set updated for coreboot: 91096b5 mainboard/intel/d510mo: Add Intel D510MO mainboard
by Damien Zammit 05 May '15

05 May '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10074 -gerrit commit 91096b561a464eeb6a7235a814badc84a8b4e018 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon May 4 10:41:21 2015 +1000 mainboard/intel/d510mo: Add Intel D510MO mainboard Board currently has no raminit. Board boots to UART console. Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/Kconfig | 57 +++++++++++++ src/mainboard/intel/d510mo/Kconfig.name | 2 + src/mainboard/intel/d510mo/acpi/ec.asl | 49 ++++++++++++ src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl | 82 +++++++++++++++++++ src/mainboard/intel/d510mo/acpi/mainboard.asl | 34 ++++++++ src/mainboard/intel/d510mo/acpi/superio.asl | 45 +++++++++++ src/mainboard/intel/d510mo/acpi_tables.c | 66 +++++++++++++++ src/mainboard/intel/d510mo/board_info.txt | 5 ++ src/mainboard/intel/d510mo/devicetree.cb | 77 ++++++++++++++++++ src/mainboard/intel/d510mo/dsdt.asl | 55 +++++++++++++ src/mainboard/intel/d510mo/hda_verb.c | 7 ++ src/mainboard/intel/d510mo/romstage.c | 97 +++++++++++++++++++++++ 12 files changed, 576 insertions(+) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig new file mode 100644 index 0000000..aed13db --- /dev/null +++ b/src/mainboard/intel/d510mo/Kconfig @@ -0,0 +1,57 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +if BOARD_INTEL_D510MO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_ATOM_D5XX + select CPU_MICROCODE_CBFS_NONE + select NORTHBRIDGE_INTEL_PINEVIEW + #select NORTHBRIDGE_INTEL_SUBTYPE_I945GM + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627THG + #select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES + select BROKEN_CAR_MIGRATE + #select USE_WATCHDOG_ON_BOOT + #select UDELAY_TSC + select EARLY_CBMEM_INIT + select BOARD_ROMSIZE_KB_1024 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 + +config MAINBOARD_DIR + string + default intel/d510mo + +config MAINBOARD_PART_NUMBER + string + default "D510MO" + +config IRQ_SLOT_COUNT + int + default 7 + +endif # BOARD_INTEL_D510MO diff --git a/src/mainboard/intel/d510mo/Kconfig.name b/src/mainboard/intel/d510mo/Kconfig.name new file mode 100644 index 0000000..2df0dca --- /dev/null +++ b/src/mainboard/intel/d510mo/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_D510MO + bool "D510MO" diff --git a/src/mainboard/intel/d510mo/acpi/ec.asl b/src/mainboard/intel/d510mo/acpi/ec.asl new file mode 100644 index 0000000..31c7001 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/ec.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 + // for EC initialization before a driver + // is loaded + } + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + + // TODO EC Query methods + + // TODO Scope _SB devices for AC power, LID, Power button + +} diff --git a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..74c1ca0 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 21}, + Package() { 0x0000ffff, 1, 0, 22}, + Package() { 0x0000ffff, 2, 0, 23}, + Package() { 0x0000ffff, 3, 0, 20}, + + Package() { 0x0001ffff, 0, 0, 22}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 20}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 18}, + Package() { 0x0002ffff, 1, 0, 19}, + Package() { 0x0002ffff, 2, 0, 17}, + Package() { 0x0002ffff, 3, 0, 16}, + + Package() { 0x0003ffff, 0, 0, 19}, + Package() { 0x0003ffff, 1, 0, 18}, + Package() { 0x0003ffff, 2, 0, 21}, + Package() { 0x0003ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 17}, + Package() { 0x0005ffff, 1, 0, 20}, + Package() { 0x0005ffff, 2, 0, 22}, + Package() { 0x0005ffff, 3, 0, 21}, + + Package() { 0x0008ffff, 0, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/intel/d510mo/acpi/mainboard.asl b/src/mainboard/intel/d510mo/acpi/mainboard.asl new file mode 100644 index 0000000..73189be --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/mainboard.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x04}) +} diff --git a/src/mainboard/intel/d510mo/acpi/superio.asl b/src/mainboard/intel/d510mo/acpi/superio.asl new file mode 100644 index 0000000..d615242 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/superio.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c new file mode 100644 index 0000000..35c23a5 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi_tables.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <arch/ioapic.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/intel/d510mo/board_info.txt b/src/mainboard/intel/d510mo/board_info.txt new file mode 100644 index 0000000..192798a --- /dev/null +++ b/src/mainboard/intel/d510mo/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb new file mode 100644 index 0000000..7fca8b4 --- /dev/null +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -0,0 +1,77 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +chip northbridge/intel/pineview # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/model_106cx # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # Integrated graphics controller + chip southbridge/intel/i82801gx # Southbridge + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 off end # Floppy + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 4e.a on end # ACPI + device pnp 4e.b on # HWM + io 0x60 = 0x290 + end + end + end + device pci 1f.1 off end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl new file mode 100644 index 0000000..b6a1b8d --- /dev/null +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + //#include "acpi/platform.asl" + + // global NVS and variables + //#include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + //#include <southbridge/intel/i82801gx/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + //#include "acpi/mainboard.asl" + + // Thermal Zone + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + //#include <northbridge/intel/pineview/acpi/i945.asl> + //#include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + //#include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c new file mode 100644 index 0000000..072a306 --- /dev/null +++ b/src/mainboard/intel/d510mo/hda_verb.c @@ -0,0 +1,7 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c new file mode 100644 index 0000000..391ecbd --- /dev/null +++ b/src/mainboard/intel/d510mo/romstage.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/pineview/pineview.h> +#include <cpu/x86/bist.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <superio/winbond/common/winbond.h> +#include <lib.h> + +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ +static void mb_gpio_init(void) +{ + device_t dev; + + /* Southbridge GPIOs. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000fe, DEFAULT_GPIOBASE + 0x30); + outl(0x0000007e, DEFAULT_GPIOBASE + 0x34); + outl(0x000300f3, DEFAULT_GPIOBASE + 0x38); +} + +static void nm10_enable_lpc(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c); +} + +void main(unsigned long bist) +{ + /* + const u8 spd_addrmap[4] = { 0x50, 0x51 }; + */ + + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; + + /* Set southbridge and Super I/O GPIOs. */ + mb_gpio_init(); + + nm10_enable_lpc(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + report_bist_failure(bist); + enable_smbus(); + die("Waiting here\n"); + + /* + early_initialization(); + sdram_initialize(0, spd_addrmap); + */ +}

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Patch set updated for coreboot: 4ce7bbc northbridge/intel/pineview: Add minimal Pineview northbridge
by Damien Zammit 05 May '15

05 May '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10073 -gerrit commit 4ce7bbc1d617ab4dd5551f5ff401badcc55a6640 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun May 3 21:34:38 2015 +1000 northbridge/intel/pineview: Add minimal Pineview northbridge Based on i945. Tested on Intel D510MO mainboard. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/pineview/Kconfig | 73 ++++++++++++++++ src/northbridge/intel/pineview/Makefile.inc | 35 ++++++++ src/northbridge/intel/pineview/acpi.c | 75 ++++++++++++++++ src/northbridge/intel/pineview/bootblock.c | 22 +++++ src/northbridge/intel/pineview/pineview.h | 129 ++++++++++++++++++++++++++++ src/northbridge/intel/pineview/ram_calc.c | 62 +++++++++++++ src/northbridge/intel/pineview/udelay.c | 82 ++++++++++++++++++ 7 files changed, 478 insertions(+) diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig new file mode 100644 index 0000000..4d6dcc2 --- /dev/null +++ b/src/northbridge/intel/pineview/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_PINEVIEW + bool + +if NORTHBRIDGE_INTEL_PINEVIEW + +config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + #select HAVE_DEBUG_RAM_SETUP + select LAPIC_MONOTONIC_TIMER + select VGA + select PER_DEVICE_ACPI_TABLES + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/pineview/bootblock.c" + +config VGA_BIOS_ID + string + default "8086,a001" + +config CHANNEL_XOR_RANDOMIZATION + bool + default n + +config OVERRIDE_CLOCK_DISABLE + bool + default n + help + Usually system firmware turns off system memory clock + signals to unused SO-DIMM slots to reduce EMI and power + consumption. + However, some boards do not like unused clock signals to + be disabled. + +config MAXIMUM_SUPPORTED_FREQUENCY + int + default 0 + help + If non-zero, this designates the maximum DDR frequency + the board supports, despite what the chipset should be + capable of. + +config CHECK_SLFRCS_ON_RESUME + def_bool n + help + On some boards it may be neccessary to hard reset early + during resume from S3 if the SLFRCS register indicates that + a memory channel is not guaranteed to be in self-refresh. + On other boards the check always creates a false positive, + effectively making it impossible to resume. + +endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc new file mode 100644 index 0000000..8416342 --- /dev/null +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -0,0 +1,35 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) + +ramstage-y += ram_calc.c +#ramstage-y += northbridge.c +#ramstage-y += gma.c +ramstage-y += acpi.c + +romstage-y += ram_calc.c +#romstage-y += raminit.c +#romstage-y += early_init.c +#romstage-y += errata.c +#romstage-y += debug.c + +smm-y += udelay.c + +endif diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c new file mode 100644 index 0000000..b393170 --- /dev/null +++ b/src/northbridge/intel/pineview/acpi.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/acpigen.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <northbridge/intel/pineview/pineview.h> +#include <string.h> +#include <types.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 pciexbar_reg; + int max_buses; + + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + if (!dev) + return current; + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & (1 << 0))) + return current; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + max_buses = 256; + break; + case 1: // 128M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + max_buses = 128; + break; + case 2: // 64M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + max_buses = 64; + break; + default: // RSVD + return current; + } + + if (!pciexbar) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, max_buses - 1); + + return current; +} diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c new file mode 100644 index 0000000..985eddd --- /dev/null +++ b/src/northbridge/intel/pineview/bootblock.c @@ -0,0 +1,22 @@ +#include <arch/io.h> +#include <northbridge/intel/pineview/pineview.h> + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h new file mode 100644 index 0000000..7bd4c44 --- /dev/null +++ b/src/northbridge/intel/pineview/pineview.h @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H +#define NORTHBRIDGE_INTEL_PINEVIEW_H + +/* Northbridge BARs */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#include <southbridge/intel/i82801gx/i82801gx.h> + +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + +#define GGC 0x52 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) +#define DEVEN_D2F0 (1 << 3) +#define DEVEN_D2F1 (1 << 4) + +#ifndef BOARD_DEVEN +#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) +#endif /* BOARD_DEVEN */ + +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 + +#define LAC 0x97 /* Legacy Access Control */ +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAM 0x9e /* Extended System Management RAM Control */ + +#define TOM 0xa0 +#define TOUUD 0xa2 +#define GBSM 0xa4 +#define BGSM 0xa8 +#define TSEGMB 0xac +#define TOLUD 0xb0 /* Top of Low Used Memory */ +#define ERRSTS 0xc8 +#define ERRCMD 0xca +#define SMICMD 0xcc +#define SCICMD 0xce +#define CGDIS 0xd8 +#define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0 0xe0 +#define DEV0T 0xf0 +#define MSLCK 0xf4 +#define MID0 0xf8 +#define DEBUP0 0xfc + +/* Device 0:1.0 PCI configuration space (PCI Express) */ + +#define BCTRL1 0x3e /* 16bit */ +#define PEGSTS 0x214 /* 32bit */ + + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define GMADR 0x18 +#define GTTADR 0x1c +#define BSM 0x5c +#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ + + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +/* + * EPBAR - Egress Port Root Complex Register Block + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +/* provided by mainboard code */ +void setup_ich7_gpios(void); + +#endif /* __ACPI__ */ + +#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */ diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c new file mode 100644 index 0000000..d7cc732 --- /dev/null +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Use simple device model for this file even in ramstage */ +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include <northbridge/intel/pineview/pineview.h> + +static unsigned long find_ramtop(void) +{ + uint32_t tom; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), BSM); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x100000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x200000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x800000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long) tom; +} + +void *cbmem_top(void) +{ + return (void *) find_ramtop(); +} diff --git a/src/northbridge/intel/pineview/udelay.c b/src/northbridge/intel/pineview/udelay.c new file mode 100644 index 0000000..9e68512 --- /dev/null +++ b/src/northbridge/intel/pineview/udelay.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> + +/** + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock + */ + +void udelay(uint32_t us) +{ + uint32_t dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + uint32_t fsb = 0, divisor; + uint32_t d; /* ticks per us */ + + msr = rdmsr(MSR_FSB_FREQ); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + + multiply_to_tsc(&tscd, us, d); + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}

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coreboot-gerrit May 2015