Patch set updated for coreboot: eca0f0b DO NOT MERGE: Intel Common SOC: Add romstage support
by Leroy P Leahy 05 May '15
by Leroy P Leahy 05 May '15
05 May '15
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10050
-gerrit
commit eca0f0b5431b9ee35abe6d57500be34bb3bd65a5
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Apr 20 15:24:54 2015 -0700
DO NOT MERGE: Intel Common SOC: Add romstage support
Provide a common romstage implementation for the Intel SOCs.
BRANCH=none
BUG=None
TEST=Build for Braswell
Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/common/Kconfig | 39 ++++
src/soc/intel/common/Makefile.inc | 10 +-
src/soc/intel/common/fsp_ramstage.c | 153 ++++++++++++++++
src/soc/intel/common/gma.h | 176 ++++++++++++++++++
src/soc/intel/common/junk.c | 21 +++
src/soc/intel/common/memmap.h | 33 ++++
src/soc/intel/common/raminit.c | 275 ++++++++++++++++++++++++++++
src/soc/intel/common/ramstage.h | 36 ++++
src/soc/intel/common/romstage.c | 356 ++++++++++++++++++++++++++++++++++++
src/soc/intel/common/romstage.h | 99 ++++++++++
src/soc/intel/common/spi_loading.c | 152 +++++++++++++++
src/soc/intel/common/stack.c | 173 ++++++++++++++++++
src/soc/intel/common/stack.h | 35 ++++
13 files changed, 1556 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 8b5cef3..7e1cd1a 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -3,6 +3,8 @@ config SOC_INTEL_COMMON
help
common code for Intel SOCs
+if SOC_INTEL_COMMON
+
if HAVE_MRC
config CACHE_MRC_SETTINGS
@@ -27,6 +29,43 @@ endif # CACHE_MRC_SETTINGS
endif # HAVE_MRC
+config CHIPSET_RESERVED_MEM_BYTES
+ hex "Size in bytes of chipset reserved memory area"
+ default 0
+ help
+ If insufficient documentation is available to determine the size of
+ the chipset reserved memory area by walking the chipset registers,
+ the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account
+ for the missing pieces of memory. The value specified in bytes is:
+
+ value = TSEG base - top of low usable memory - (any sizes determined
+ by reading chipset registers)
+
+config SOC_INTEL_COMMON_STACK
+ bool
+ default n
+
+config SOC_INTEL_COMMON_RAM_INIT
+ bool "FSP: Use the common raminit.c module"
+ default n
+ depends on PLATFORM_USES_FSP1_1
+
config SOC_INTEL_COMMON_RESET
bool
default n
+
+config SOC_INTEL_COMMON_ROMSTAGE
+ bool
+ default n
+
+config SOC_INTEL_COMMON_SPI_LOADING
+ bool "Use the common spi_loading.c module"
+ default n
+ depends on ALT_CBFS_LOAD_PAYLOAD
+
+config ROMSTAGE_RAM_STACK_SIZE
+ hex "Size of the romstage RAM stack in bytes"
+ default 0x5000
+
+endif # SOC_INTEL_COMMON
+
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 6d40aa7..86cc8ea 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -1,10 +1,16 @@
ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
+romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_RAM_INIT) += raminit.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_ROMSTAGE) += romstage.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c
+
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c
ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
-romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_LOADING) += spi_loading.c
endif
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
new file mode 100644
index 0000000..301d7a1
--- /dev/null
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -0,0 +1,153 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbmem.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp_util.h>
+#include <romstage_handoff.h>
+#include <soc/intel/common/ramstage.h>
+#include <timestamp.h>
+
+/* SOC initialization after FSP silicon init */
+__attribute__((weak)) void soc_after_silicon_init(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+__attribute__((weak)) void soc_save_support_code(void *start, size_t size,
+ void *entry)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+__attribute__((weak)) void *soc_restore_support_code(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return NULL;
+}
+
+static void fsp_run_silicon_init(void)
+{
+ FSP_INFO_HEADER *fsp_info_header;
+ FSP_SILICON_INIT fsp_silicon_init;
+ EFI_STATUS status;
+
+ /* Find the FSP image */
+ fsp_info_header = fsp_get_fih();
+ if (fsp_info_header == NULL) {
+ printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
+ return;
+ }
+
+ /* Perform silicon initialization after RAM is configured */
+ printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
+ fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
+ + fsp_info_header->FspSiliconInitEntryOffset);
+ timestamp_add_now(TS_FSP_SILICON_INIT_START);
+ status = fsp_silicon_init(NULL);
+ timestamp_add_now(TS_FSP_SILICON_INIT_END);
+ printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
+
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ /* Verify the HOBs */
+ const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
+ void *hob_list_ptr = get_hob_list();
+ int missing_hob = 0;
+
+ if (hob_list_ptr == NULL)
+ die("ERROR - HOB pointer is NULL!\n");
+ print_hob_type_structure(0, hob_list_ptr);
+
+ /*
+ * Verify that FSP is generating the required HOBs:
+ * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
+ * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
+ * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
+ * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
+ */
+ if (NULL == get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) {
+ printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
+ missing_hob = 1;
+ }
+ if (missing_hob)
+ die("ERROR - Missing one or more required FSP HOBs!\n");
+#endif
+
+ soc_after_silicon_init();
+}
+
+static void fsp_cache_save(void)
+{
+ const struct cbmem_entry *fsp_entry;
+ FSP_INFO_HEADER *fih;
+
+ fsp_entry = cbmem_entry_find(CBMEM_ID_REFCODE);
+
+ if (fsp_entry == NULL) {
+ printk(BIOS_ERR, "ERROR: FSP not found in CBMEM.\n");
+ return;
+ }
+
+ fih = fsp_get_fih();
+
+ if (fih == NULL) {
+ printk(BIOS_ERR, "ERROR: No FIH found.\n");
+ return;
+ }
+
+ soc_save_support_code(cbmem_entry_start(fsp_entry),
+ cbmem_entry_size(fsp_entry), fih);
+}
+
+static int fsp_find_and_relocate(void)
+{
+ struct cbfs_file *file;
+ void *fih;
+
+ file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "fsp.bin");
+
+ if (file == NULL) {
+ printk(BIOS_ERR, "Couldn't find fsp.bin in CBFS.\n");
+ return -1;
+ }
+
+ fih = fsp_relocate(CBFS_SUBHEADER(file), ntohl(file->len));
+
+ fsp_update_fih(fih);
+
+ return 0;
+}
+
+void intel_silicon_init(void)
+{
+ struct romstage_handoff *handoff;
+
+ handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
+
+ if (handoff != NULL && handoff->s3_resume)
+ fsp_update_fih(soc_restore_support_code());
+ else {
+ fsp_find_and_relocate();
+ fsp_cache_save();
+ }
+
+ fsp_run_silicon_init();
+}
diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h
new file mode 100644
index 0000000..9666147
--- /dev/null
+++ b/src/soc/intel/common/gma.h
@@ -0,0 +1,176 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Chromium OS Authors
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _GMA_H_
+#define _GMA_H_
+
+#include <types.h>
+
+/* mailbox 0: header */
+typedef struct {
+ u8 signature[16];
+ u32 size;
+ u32 version;
+ u8 sbios_version[32];
+ u8 vbios_version[16];
+ u8 driver_version[16];
+ u32 mailboxes;
+ u8 reserved[164];
+} __attribute__((packed)) opregion_header_t;
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION 2
+
+#define IGD_MBOX1 (1 << 0)
+#define IGD_MBOX2 (1 << 1)
+#define IGD_MBOX3 (1 << 2)
+#define IGD_MBOX4 (1 << 3)
+#define IGD_MBOX5 (1 << 4)
+
+#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+ IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public acpi methods */
+typedef struct {
+ u32 drdy;
+ u32 csts;
+ u32 cevt;
+ u8 reserved1[20];
+ u32 didl[8];
+ u32 cpdl[8];
+ u32 cadl[8];
+ u32 nadl[8];
+ u32 aslp;
+ u32 tidx;
+ u32 chpd;
+ u32 clid;
+ u32 cdck;
+ u32 sxsw;
+ u32 evts;
+ u32 cnot;
+ u32 nrdy;
+ u8 reserved2[60];
+} __attribute__((packed)) opregion_mailbox1_t;
+
+/* mailbox 2: software sci interface */
+typedef struct {
+ u32 scic;
+ u32 parm;
+ u32 dslp;
+ u8 reserved[244];
+} __attribute__((packed)) opregion_mailbox2_t;
+
+/* mailbox 3: power conservation */
+typedef struct {
+ u32 ardy;
+ u32 aslc;
+ u32 tche;
+ u32 alsi;
+ u32 bclp;
+ u32 pfit;
+ u32 cblv;
+ u16 bclm[20];
+ u32 cpfm;
+ u32 epfm;
+ u8 plut[74];
+ u32 pfmb;
+ u32 ccdv;
+ u32 pcft;
+ u8 reserved[94];
+} __attribute__((packed)) opregion_mailbox3_t;
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID (1 << 31)
+#define IGD_WORD_FIELD_VALID (1 << 15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+typedef struct {
+ u8 gvd1[7168];
+} __attribute__((packed)) opregion_vbt_t;
+
+/* IGD OpRegion */
+typedef struct {
+ opregion_header_t header;
+ opregion_mailbox1_t mailbox1;
+ opregion_mailbox2_t mailbox2;
+ opregion_mailbox3_t mailbox3;
+ opregion_vbt_t vbt;
+} __attribute__((packed)) igd_opregion_t;
+
+/* Intel Video BIOS (Option ROM) */
+typedef struct {
+ u16 signature;
+ u8 size;
+ u8 reserved[21];
+ u16 pcir_offset;
+ u16 vbt_offset;
+} __attribute__((packed)) optionrom_header_t;
+
+#define OPROM_SIGNATURE 0xaa55
+
+typedef struct {
+ u32 signature;
+ u16 vendor;
+ u16 device;
+ u16 reserved1;
+ u16 length;
+ u8 revision;
+ u8 classcode[3];
+ u16 imagelength;
+ u16 coderevision;
+ u8 codetype;
+ u8 indicator;
+ u16 reserved2;
+} __attribute__((packed)) optionrom_pcir_t;
+
+typedef struct {
+ u8 hdr_signature[20];
+ u16 hdr_version;
+ u16 hdr_size;
+ u16 hdr_vbt_size;
+ u8 hdr_vbt_checksum;
+ u8 hdr_reserved;
+ u32 hdr_vbt_datablock;
+ u32 hdr_aim[4];
+ u8 datahdr_signature[16];
+ u16 datahdr_version;
+ u16 datahdr_size;
+ u16 datahdr_datablocksize;
+ u8 coreblock_id;
+ u16 coreblock_size;
+ u16 coreblock_biossize;
+ u8 coreblock_biostype;
+ u8 coreblock_releasestatus;
+ u8 coreblock_hwsupported;
+ u8 coreblock_integratedhw;
+ u8 coreblock_biosbuild[4];
+ u8 coreblock_biossignon[155];
+} __attribute__((packed)) optionrom_vbt_t;
+
+#define VBT_SIGNATURE 0x54425624
+
+#endif /* _GMA_H_ */
+
diff --git a/src/soc/intel/common/junk.c b/src/soc/intel/common/junk.c
new file mode 100644
index 0000000..e90c6e8
--- /dev/null
+++ b/src/soc/intel/common/junk.c
@@ -0,0 +1,21 @@
+#include <cbmem.h>
+#include <reg_script.h>
+#include <timestamp.h>
+
+int cbmem_initialize_id_size(u32 id, u64 size)
+{
+ return 0;
+}
+
+void cbmem_initialize_empty_id_size(u32 id, u64 size)
+{
+}
+
+void reg_script_run_on_dev(device_t dev, const struct reg_script *step)
+{
+}
+
+void timestamp_early_init(uint64_t base)
+{
+}
+
diff --git a/src/soc/intel/common/memmap.h b/src/soc/intel/common/memmap.h
new file mode 100644
index 0000000..840b51e
--- /dev/null
+++ b/src/soc/intel/common/memmap.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _COMMON_MEMMAP_H_
+#define _COMMON_MEMMAP_H_
+
+#include <types.h>
+
+/*
+ * mmap_region_granluarity must to return a size which is a positive non-zero
+ * integer multiple of the SMM size when SMM is in use. When not using SMM,
+ * this value should be set to 8 MiB.
+ */
+size_t mmap_region_granluarity(void);
+void smm_region(void **start, size_t *size);
+
+#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
new file mode 100644
index 0000000..4462329
--- /dev/null
+++ b/src/soc/intel/common/raminit.c
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014-2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp_util.h>
+#include <lib.h> /* hexdump */
+#include <reset.h>
+#include <soc/intel/common/memmap.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <string.h>
+#include <timestamp.h>
+
+void raminit(struct romstage_params *params)
+{
+ const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
+ EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
+ FSP_INFO_HEADER *fsp_header;
+ EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory;
+ FSP_MEMORY_INIT fsp_memory_init;
+ FSP_MEMORY_INIT_PARAMS fsp_memory_init_params;
+ const EFI_GUID fsp_reserved_guid =
+ FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
+ void *fsp_reserved_memory_area;
+ FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer;
+ void *hob_list_ptr;
+ const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+ u32 *mrc_hob;
+ u32 fsp_reserved_bytes;
+ EFI_STATUS status;
+ struct pei_data *pei_ptr;
+ VPD_DATA_REGION *vpd_ptr;
+ UPD_DATA_REGION *upd_ptr;
+ UPD_DATA_REGION upd_data_buffer;
+ int fsp_verification_failure = 0;
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ unsigned long int data;
+ EFI_PEI_HOB_POINTERS hob_ptr;
+#endif
+
+ /*
+ * Find and copy the UPD region to the stack so the platform can modify
+ * the settings if needed. Modifications to the UPD buffer are done in
+ * the platform callback code. The platform callback code is also
+ * responsible for assigning the UpdDataRngPtr to this buffer if any
+ * updates are made. The default state is to leave the UpdDataRngPtr
+ * set to NULL. This indicates that the FSP code will use the UPD
+ * region in the FSP binary.
+ */
+ post_code(0x34);
+ fsp_header = params->chipset_context;
+ vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
+ fsp_header->ImageBase);
+ printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
+ upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
+ fsp_header->ImageBase);
+ printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr);
+ memcpy(&upd_data_buffer, upd_ptr, sizeof(upd_data_buffer));
+
+ /* Zero fill RT Buffer data and start populating fields. */
+ memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
+ pei_ptr = params->pei_data;
+ if (pei_ptr->boot_mode == SLEEP_STATE_S3) {
+ fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
+ } else if (pei_ptr->saved_data != NULL) {
+ fsp_rt_common_buffer.BootMode =
+ BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
+ } else {
+ fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION;
+ }
+ fsp_rt_common_buffer.UpdDataRgnPtr = &upd_data_buffer;
+ fsp_rt_common_buffer.BootLoaderTolumSize = CBMEM_ROOT_SIZE;
+
+ /* Get any board specific changes */
+ fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data;
+ fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer;
+ fsp_memory_init_params.HobListPtr = &hob_list_ptr;
+ board_fsp_memory_init_params(params, fsp_header,
+ &fsp_memory_init_params);
+ post_code(0x36);
+
+ /* Display the UPD data */
+#if IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)
+ printk(BIOS_SPEW, "Updated Product Data (UPD):\n");
+ hexdump32(BIOS_SPEW, (void *)&upd_data_buffer, sizeof(upd_data_buffer));
+#endif
+
+ /* Call FspMemoryInit to initialize RAM */
+ fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase
+ + fsp_header->FspMemoryInitEntryOffset);
+ printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init);
+ printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n",
+ fsp_memory_init_params.NvsBufferPtr);
+ printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n",
+ fsp_memory_init_params.RtBufferPtr);
+ printk(BIOS_SPEW, " 0x%p: HobListPtr\n",
+ fsp_memory_init_params.HobListPtr);
+
+ timestamp_add_now(TS_FSP_MEMORY_INIT_START);
+ status = fsp_memory_init(&fsp_memory_init_params);
+ post_code(0x37);
+ timestamp_add_now(TS_FSP_MEMORY_INIT_END);
+
+ printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+ if (status != EFI_SUCCESS)
+ die("ERROR - FspMemoryInit failed to initialize memory!\n");
+
+ /* Locate the FSP reserved memory area */
+ fsp_reserved_bytes = 0;
+ fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr);
+ if (fsp_memory == NULL) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG,
+ "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n");
+ } else {
+ fsp_reserved_bytes = fsp_memory->ResourceLength;
+ printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n",
+ (unsigned long int)fsp_reserved_bytes);
+ }
+
+ /* Display SMM area */
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ char *smm_base;
+ size_t smm_size;
+
+ smm_region((void **)&smm_base, &smm_size);
+ printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
+ printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
+#endif
+
+ /* Migrate CAR data */
+ printk(BIOS_DEBUG, "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n",
+ CONFIG_CHIPSET_RESERVED_MEM_BYTES);
+ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
+ if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
+ cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+ fsp_reserved_bytes);
+ } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+ fsp_reserved_bytes)) {
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ hard_reset();
+#endif
+ }
+
+ /* Save the FSP runtime parameters. */
+ fsp_set_runtime(params->chipset_context, hob_list_ptr);
+
+ /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */
+ cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);
+ if (cbmem_root == NULL) {
+ fsp_verification_failure = 1;
+ printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n");
+ printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n",
+ fsp_rt_common_buffer.BootLoaderTolumSize);
+ }
+
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ if (hob_list_ptr == NULL)
+ die("ERROR - HOB pointer is NULL!\n");
+
+ /*
+ * Verify that FSP is generating the required HOBs:
+ * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
+ * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
+ */
+ if (NULL != cbmem_root) {
+ printk(BIOS_DEBUG,
+ "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
+ cbmem_root);
+ data = cbmem_root->PhysicalStart;
+ printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
+ data = cbmem_root->ResourceLength;
+ printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
+ }
+ hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
+ if (NULL == hob_ptr.Raw) {
+ printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
+ fsp_verification_failure =
+ (params->pei_data->saved_data == NULL) ? 1 : 0;
+ } else {
+ printk(BIOS_DEBUG,
+ "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n",
+ hob_ptr.Raw);
+ }
+ if (fsp_memory != NULL) {
+ printk(BIOS_DEBUG,
+ "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n",
+ fsp_memory);
+ data = fsp_memory->PhysicalStart;
+ printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
+ data = fsp_memory->ResourceLength;
+ printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
+ }
+
+ /* Verify all the HOBs are present */
+ if (fsp_verification_failure)
+ printk(BIOS_DEBUG,
+ "ERROR - Missing one or more required FSP HOBs!\n");
+
+ /* Display the HOBs */
+ print_hob_type_structure(0, hob_list_ptr);
+#endif
+
+ /* Get the address of the CBMEM region for the FSP reserved memory */
+ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
+ printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n",
+ fsp_reserved_memory_area);
+
+ /* Verify the order of CBMEM root and FSP memory */
+ if ((fsp_memory != NULL) && (cbmem_root != NULL) &&
+ (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG,
+ "ERROR - FSP reserved memory above CBMEM root!\n");
+ }
+
+ /* Verify that the FSP memory was properly reserved */
+ if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) ||
+ (fsp_memory->PhysicalStart !=
+ (unsigned int)fsp_reserved_memory_area))) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ if (cbmem_root != NULL) {
+ size_t delta_bytes = (unsigned int)smm_base
+ - cbmem_root->PhysicalStart
+ - cbmem_root->ResourceLength;
+ printk(BIOS_DEBUG,
+ "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n",
+ CONFIG_CHIPSET_RESERVED_MEM_BYTES);
+ printk(BIOS_DEBUG,
+ "0x%08x: Chipset reserved bytes reported by FSP\n",
+ (unsigned int)delta_bytes);
+ die("Please verify the chipset reserved size\n");
+ }
+#endif
+ }
+
+ /* Verify the FSP 1.1 HOB interface */
+ if (fsp_verification_failure)
+ die("ERROR - Coreboot's requirements not met by FSP binary!\n");
+
+ /* Display the memory configuration */
+ report_memory_config();
+
+ /* Locate the memory configuration data to speed up the next reboot */
+ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr);
+ if (mrc_hob == NULL)
+ printk(BIOS_DEBUG,
+ "Memory Configuration Data Hob not present\n");
+ else {
+ pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
+ pei_ptr->data_to_save_size = ALIGN(
+ ((u32)GET_HOB_LENGTH(mrc_hob)), 16);
+ }
+}
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h
new file mode 100644
index 0000000..e46f108
--- /dev/null
+++ b/src/soc/intel/common/ramstage.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _INTEL_COMMON_RAMSTAGE_H_
+#define _INTEL_COMMON_RAMSTAGE_H_
+
+#include <stdint.h>
+
+/* Perform Intel silicon init. */
+void intel_silicon_init(void);
+/* Called after the silicon init code has run. */
+void soc_after_silicon_init(void);
+/* SoC implementation for caching support code. */
+void soc_save_support_code(void *start, size_t size, void *entry);
+/* SoC implementation for restoring support code after S3 resume. Returns
+ * previously passed entry pointer from soc_save_support_code(). */
+void *soc_restore_support_code(void);
+
+#endif /* _INTEL_COMMON_RAMSTAGE_H_ */
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
new file mode 100644
index 0000000..fd7adc9
--- /dev/null
+++ b/src/soc/intel/common/romstage.c
@@ -0,0 +1,356 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/cbfs.h>
+#include <arch/stages.h>
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <elog.h>
+#include <ramstage_cache.h>
+#include <reset.h>
+#include <romstage_handoff.h>
+#include <soc/intel/common/mrc_cache.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <soc/spi.h>
+#include <timestamp.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* Entry from cache-as-ram.inc. */
+asmlinkage void *romstage_main(unsigned int bist,
+ uint32_t tsc_low, uint32_t tsc_high,
+ void *chipset_context)
+{
+ void *top_of_stack;
+ struct pei_data pei_data;
+ struct romstage_params params = {
+ .bist = bist,
+ .pei_data = &pei_data,
+ .chipset_context = chipset_context,
+ };
+
+ post_code(0x30);
+
+ /* Save timestamp data */
+ timestamp_early_init((((uint64_t)tsc_high) << 32) | (uint64_t)tsc_low);
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ memset(&pei_data, 0, sizeof(pei_data));
+
+ /* Call into pre-console init code. */
+ soc_pre_console_init(¶ms);
+ mainboard_pre_console_init(¶ms);
+
+ /* Start console drivers */
+ console_init();
+
+ /* Display parameters */
+ printk(BIOS_SPEW, "bist: 0x%08x\n", bist);
+ printk(BIOS_SPEW, "tsc_low: 0x%08x\n", tsc_low);
+ printk(BIOS_SPEW, "tsc_hi: 0x%08x\n", tsc_high);
+ printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
+ CONFIG_MMCONF_BASE_ADDRESS);
+ printk(BIOS_INFO, "Using: %s\n",
+ IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) ? "FSP 1.1" :
+ (IS_ENABLED(CONFIG_HAVE_MRC) ? "MRC" :
+ "No Memory Support"));
+
+ /* Display FSP banner */
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+ printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
+ print_fsp_info(params.chipset_context);
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+
+ /* Get power state */
+ params.power_state = fill_power_state();
+
+ /* Print useful platform information */
+ report_platform_info();
+
+ /* Set CPU frequency to maximum */
+ set_max_freq();
+
+ /* Perform SOC specific initialization. */
+ soc_romstage_init(¶ms);
+
+ /* Call into mainboard. */
+ mainboard_romstage_entry(¶ms);
+ soc_after_ram_init(¶ms);
+ post_code(0x38);
+
+ top_of_stack = setup_stack_and_mtrrs();
+
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+ printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
+ timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+
+ return top_of_stack;
+}
+
+/* Entry from the mainboard. */
+void romstage_common(struct romstage_params *params)
+{
+ const struct mrc_saved_data *cache;
+ struct romstage_handoff *handoff;
+ struct pei_data *pei_data;
+
+ post_code(0x32);
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
+
+ pei_data = params->pei_data;
+ pei_data->boot_mode = params->power_state->prev_sleep_state;
+
+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+ if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
+ boot_count_increment();
+#endif
+
+ /* Perform remaining SOC initialization */
+ soc_pre_ram_init(params);
+ post_code(0x33);
+
+ /* Check recovery and MRC cache */
+ params->pei_data->saved_data_size = 0;
+ params->pei_data->saved_data = NULL;
+ if (!params->pei_data->disable_saved_data) {
+ if (recovery_mode_enabled()) {
+ /* Recovery mode does not use MRC cache */
+ printk(BIOS_DEBUG,
+ "Recovery mode: not using MRC cache.\n");
+ } else if (!mrc_cache_get_current(&cache)) {
+ /* MRC cache found */
+ params->pei_data->saved_data_size = cache->size;
+ params->pei_data->saved_data = &cache->data[0];
+ } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) {
+ /* Waking from S3 and no cache. */
+ printk(BIOS_DEBUG,
+ "No MRC cache found in S3 resume path.\n");
+ post_code(POST_RESUME_FAILURE);
+ hard_reset();
+ } else {
+ printk(BIOS_DEBUG, "No MRC cache found.\n");
+ mainboard_check_ec_image(params);
+ }
+ }
+
+ /* Initialize RAM */
+ raminit(params);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
+ /* Save MRC output */
+ printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
+ pei_data->data_to_save_size);
+ if (params->pei_data->boot_mode != SLEEP_STATE_S3) {
+ if (params->pei_data->data_to_save_size != 0 &&
+ params->pei_data->data_to_save != NULL) {
+ mrc_cache_stash_data(params->pei_data->data_to_save,
+ params->pei_data->data_to_save_size);
+ }
+ }
+
+ /* Save DIMM information */
+ mainboard_save_dimm_info(params);
+
+ /* Create romstage handof information */
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = (params->power_state->prev_sleep_state ==
+ SLEEP_STATE_S3);
+ else {
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
+ hard_reset();
+ }
+
+#if IS_ENABLED(CONFIG_CHROMEOS)
+ /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */
+ init_chromeos((params->power_state->prev_sleep_state == SLEEP_STATE_S3)
+ ? 2 : 0);
+#endif
+}
+
+asmlinkage void romstage_after_car(void *chipset_context)
+{
+ if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) {
+ timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
+ printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
+ soc_after_temp_ram_exit();
+ }
+
+ timestamp_add_now(TS_END_ROMSTAGE);
+
+ /* Run vboot verification if configured. */
+ vboot_verify_firmware(romstage_handoff_find_or_add());
+
+ /* Load the ramstage. */
+ copy_and_run();
+ die("ERROR - Failed to load ramstage!");
+}
+
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+__attribute__((weak)) void board_fsp_memory_init_params(
+ struct romstage_params *params,
+ FSP_INFO_HEADER *fsp_header,
+ FSP_MEMORY_INIT_PARAMS * fsp_memory_init_params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+
+/* Initialize the power state */
+__attribute__((weak)) struct chipset_power_state *fill_power_state(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return NULL;
+}
+
+__attribute__((weak)) void mainboard_check_ec_image(
+ struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+ struct pei_data *pei_data;
+
+ pei_data = params->pei_data;
+ if (params->pei_data->boot_mode == SLEEP_STATE_S0) {
+ /* Ensure EC is running RO firmware. */
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+#endif
+}
+
+/* Board initialization before the console is enabled */
+__attribute__((weak)) void mainboard_pre_console_init(
+ struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Board initialization before and after RAM is enabled */
+__attribute__((weak)) void mainboard_romstage_entry(
+ struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+
+ post_code(0x31);
+
+ /* Initliaze memory */
+ romstage_common(params);
+}
+
+/* Used by MRC images to save DIMM information */
+__attribute__((weak)) void mainboard_save_dimm_info(
+ struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Get the memory configuration data */
+__attribute__((weak)) int mrc_cache_get_current(
+ const struct mrc_saved_data **cache)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return -1;
+}
+
+/* Save the memory configuration data */
+__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ return -1;
+}
+
+/* Transition RAM from off or self-refresh to active */
+__attribute__((weak)) void raminit(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+ post_code(0x34);
+ die("ERROR - No RAM initialization specified!\n");
+}
+
+/* Display the memory configuration */
+__attribute__((weak)) void report_memory_config(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Display the platform configuration */
+__attribute__((weak)) void report_platform_info(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* Choose top of stack and setup MTRRs */
+__attribute__((weak)) void *setup_stack_and_mtrrs(void)
+{
+ printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__);
+ die("ERROR - Must specify top of stack!\n");
+ return NULL;
+}
+
+/* Speed up the CPU to the maximum frequency */
+__attribute__((weak)) void set_max_freq(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* SOC initialization after RAM is enabled */
+__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* SOC initialization after temporary RAM is disabled */
+__attribute__((weak)) void soc_after_temp_ram_exit(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* SOC initialization before the console is enabled */
+__attribute__((weak)) void soc_pre_console_init(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* SOC initialization before RAM is enabled */
+__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
+/* SOC initialization after console is enabled */
+__attribute__((weak)) void soc_romstage_init(struct romstage_params *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+ /* Ensure the EC is in the right mode for recovery */
+ google_chromeec_early_init();
+#endif
+}
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
new file mode 100644
index 0000000..2747665
--- /dev/null
+++ b/src/soc/intel/common/romstage.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _COMMON_ROMSTAGE_H_
+#define _COMMON_ROMSTAGE_H_
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+#include <fsp_util.h>
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+#include <soc/pei_data.h>
+#include <soc/pm.h> /* chip_power_state */
+
+struct romstage_params {
+ unsigned long bist;
+ struct chipset_power_state *power_state;
+ struct pei_data *pei_data;
+ void *chipset_context;
+};
+
+/*
+ * FSP Boot Flow:
+ * 1. src/cpu/x86/16bit/reset.inc
+ * 2. src/cpu/x86/16bit/entry.inc
+ * 3. other modules
+ * 4. src/drivers/intel/fsp/fsp_1_1.inc
+ * 5. src/drivers/intel/fsp/fsp_util.c/find_fsp
+ * 6. FSP binary/TempRamInit
+ * 7. src/drivers/intel/fsp/fsp_1_1.inc - return
+ * 8. src/soc/intel/common/romstage.c/romstage_main
+ * 9 src/soc/.../romstage/.../soc_pre_console_init
+ * 10 src/console/console.c/console_init
+ * 11 src/soc/.../romstage/.../soc_romstage_init
+ * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry
+ * 13. src/soc/intel/skylake/romstage/romstage.c/romstage_common
+ * 14 src/soc/.../romstage/.../soc_pre_raminit
+ * 15. FSP binary/MemoryInit
+ * 16. src/soc/intel/common/romstage.c/romstage_common - return
+ * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return
+ * 18. src/soc/intel/common/romstage.c/romstage_main - return
+ * 19. src/soc/intel/skylake/stack.c/setup_stack_and_mttrs
+ * 20. src/drivers/intel/fsp/fsp_1_1.inc - return, cleanup
+ * after call to romstage_main
+ * 21. FSP binary/TempRamExit
+ * 22. src/soc/intel/common/romstage.c/romstage_after_car
+ * 23. FSP binary/SiliconInit
+ * 24. src/soc/intel/common/romstage.c/romstage_after_car - return
+ * 25. src/soc/intel/.../chip.c/skylake_final
+ * 26. src/drivers/intel/fsp/fsp_util.c/fsp_notify
+ * 27. FSP binary/FspNotify
+ * 28. src/soc/intel/.../ramstage.c/fsp_final
+ * 29. src/drivers/intel/fsp/fsp_util.c/fsp_notify
+ * 30. FSP binary/FspNotify
+ */
+
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+void board_fsp_memory_init_params(
+ struct romstage_params *params,
+ FSP_INFO_HEADER *fsp_header,
+ FSP_MEMORY_INIT_PARAMS * fsp_memory_init_params);
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+void mainboard_check_ec_image(struct romstage_params *params);
+void mainboard_pre_console_init(struct romstage_params *params);
+void mainboard_romstage_entry(struct romstage_params *params);
+void mainboard_save_dimm_info(struct romstage_params *params);
+void raminit(struct romstage_params *params);
+void report_memory_config(void);
+void report_platform_info(void);
+asmlinkage void romstage_after_car(void *chipset_context);
+void romstage_common(struct romstage_params *params);
+asmlinkage void *romstage_main(unsigned int bist, uint32_t tsc_lo,
+ uint32_t tsc_high, void *chipset_context);
+void *setup_stack_and_mtrrs(void);
+void set_max_freq(void);
+void soc_after_ram_init(struct romstage_params *params);
+void soc_after_temp_ram_exit(void);
+void soc_pre_console_init(struct romstage_params *params);
+void soc_pre_ram_init(struct romstage_params *params);
+void soc_romstage_init(struct romstage_params *params);
+
+#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/soc/intel/common/spi_loading.c b/src/soc/intel/common/spi_loading.c
new file mode 100644
index 0000000..fe3522b
--- /dev/null
+++ b/src/soc/intel/common/spi_loading.c
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/byteorder.h>
+#include <boot/coreboot_tables.h>
+#include <cbmem.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <stdlib.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#define CACHELINE_SIZE 64
+#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1)
+#define CACHELINE_MASK (~INTRA_CACHELINE_MASK)
+
+static void *find_mirror_buffer(int len)
+{
+ int nentries;
+ int i;
+ struct lb_memory *mem;
+ void *buffer;
+
+ len = ALIGN(len, 4096);
+
+ mem = get_lb_mem();
+ nentries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]);
+
+ /*
+ * Find the highest RAM entry that accommodates the lenth provide
+ * while falling below 4GiB.
+ */
+ buffer = NULL;
+ for (i = 0; i < nentries; i++) {
+ const uint64_t max_addr = 1ULL << 32;
+ uint64_t start;
+ uint64_t size;
+ struct lb_memory_range *r;
+
+ r = &mem->map[i];
+
+ if (r->type != LB_MEM_RAM)
+ continue;
+
+ start = unpack_lb64(r->start);
+ if (start >= max_addr)
+ continue;
+
+ size = unpack_lb64(r->size);
+ if (size < len)
+ continue;
+
+ /* Adjust size of buffer if range exceeds max address. */
+ if (start + size > max_addr)
+ size = max_addr - start;
+
+ if (size < len)
+ continue;
+
+ buffer = (void *)(uintptr_t)(start + size - len);
+ }
+
+ return buffer;
+}
+
+/*
+ * Mirror the payload file to the default SMM location if it is small enough.
+ * The default SMM region can be used since no one is using the memory at this
+ * location at this stage in the boot.
+ */
+static void *spi_mirror(void *file_start, int file_len)
+{
+ int alignment_diff;
+ char *src;
+ char *dest;
+
+ alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start);
+
+ /*
+ * Adjust file length so that the start and end points are aligned to a
+ * cacheline. Coupled with the ROM caching in the CPU the SPI hardware
+ * will read and cache full length cachelines. It will also prefetch
+ * data as well. Once things are mirrored in memory all accesses should
+ * hit the CPUs cache.
+ */
+ file_len += alignment_diff;
+ file_len = ALIGN(file_len, CACHELINE_SIZE);
+
+ printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len);
+
+ dest = find_mirror_buffer(file_len);
+
+ /*
+ * Just pass back the pointer to ROM space if a buffer could not
+ * be found to mirror into.
+ */
+ if (dest == NULL)
+ return file_start;
+
+ src = (void *)(CACHELINE_MASK & (long)file_start);
+ /*
+ * Note that if mempcy is not using 32-bit moves the performance will
+ * degrade because the SPI hardware prefetchers look for
+ * cacheline-aligned 32-bit accesses to kick in.
+ */
+ memcpy(dest, src, file_len);
+
+ /* Provide pointer into mirrored space. */
+ return &dest[alignment_diff];
+}
+
+void *cbfs_load_payload(struct cbfs_media *media, const char *name)
+{
+ int file_len;
+ void *file_start;
+ struct cbfs_file *file;
+
+ file_start = vboot_get_payload(&file_len);
+
+ if (file_start != NULL)
+ return spi_mirror(file_start, file_len);
+
+ file = cbfs_get_file(media, name);
+
+ if (file == NULL)
+ return NULL;
+
+ if (ntohl(file->type) != CBFS_TYPE_PAYLOAD)
+ return NULL;
+
+ file_len = ntohl(file->len);
+
+ file_start = CBFS_SUBHEADER(file);
+
+ return spi_mirror(file_start, file_len);
+}
diff --git a/src/soc/intel/common/stack.c b/src/soc/intel/common/stack.c
new file mode 100644
index 0000000..3e6e4b7
--- /dev/null
+++ b/src/soc/intel/common/stack.c
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include "memmap.h"
+#include "romstage.h"
+#include "stack.h"
+#include <stdlib.h>
+
+const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
+
+/*
+ * Romstage needs quite a bit of stack for decompressing images since the lzma
+ * lib keeps its state on the stack during romstage.
+ */
+static unsigned long choose_top_of_stack(void)
+{
+ unsigned long stack_top;
+
+ /* cbmem_add() does a find() before add(). */
+ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
+ romstage_ram_stack_size);
+ stack_top += romstage_ram_stack_size;
+ return stack_top;
+}
+
+/*
+ * setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use.
+ */
+void *setup_stack_and_mtrrs(void)
+{
+ size_t alignment;
+ uint32_t aligned_ram;
+ uint32_t mtrr_mask_upper;
+ int num_mtrrs;
+ uint32_t *slot;
+ unsigned long top_of_stack;
+
+ /* Top of stack needs to be aligned to a 8-byte boundary. */
+ top_of_stack = choose_top_of_stack();
+ slot = (void *)top_of_stack;
+ num_mtrrs = 0;
+
+ /*
+ * The upper bits of the MTRR mask need to set according to the number
+ * of physical address bits.
+ */
+ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
+
+ /*
+ * The order for each MTRR is value then base with upper 32-bits of
+ * each value coming before the lower 32-bits. The reasoning for
+ * this ordering is to create a stack layout like the following:
+ * +0: Number of MTRRs
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
+ */
+
+ /* Cache the ROM as WP just below 4GiB. */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ num_mtrrs++;
+
+ /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /*
+ * +-------------------------+ Top of RAM (aligned)
+ * | System Management Mode |
+ * | code and data | Length: CONFIG_TSEG_SIZE
+ * | (TSEG) |
+ * +-------------------------+ SMM base (aligned)
+ * | |
+ * | Chipset Reserved Memory |
+ * | |
+ * +-------------------------+ Chipset reserved mem base (aligned)
+ * | |
+ * | FSP Reserved Memory |
+ * | |
+ * +-------------------------+ top_of_ram (not aligned)
+ * | |
+ * | CBMEM Root |
+ * | |
+ * +-------------------------+
+ * | |
+ * | Various CBMEM Entries |
+ * | |
+ * +-------------------------+ top_of_stack (8 byte aligned)
+ * | |
+ * | stack (CBMEM Entry) |
+ * | |
+ * +-------------------------+
+ *
+ * Requirement:
+ * Chipset reserved memory base needs to be aligned to a multiple
+ * of TSEG size when SMM is in use or 8 Mib when SMM is not supported
+ * by the SOC/board configuration.
+ */
+
+ /*
+ * Cache the stack and the other CBMEM entries as well as part or all
+ * of the FSP reserved memory region.
+ */
+ alignment = mmap_region_granluarity();
+ aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size,
+ alignment);
+
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ void *smm_base;
+ size_t smm_size;
+ uint32_t tseg_base;
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is not
+ * restricted to SMM mode until SMM has been relocated. By setting
+ * the region to cacheable it provides faster access when relocating
+ * the SMM handler as well as using the TSEG region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ tseg_base = (uint32_t)smm_base;
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+#endif
+
+ /*
+ * Save the number of MTRRs to setup. Return the stack location
+ * pointing to the number of MTRRs.
+ */
+ slot = stack_push32(slot, num_mtrrs);
+ return slot;
+}
+
diff --git a/src/soc/intel/common/stack.h b/src/soc/intel/common/stack.h
new file mode 100644
index 0000000..850a070
--- /dev/null
+++ b/src/soc/intel/common/stack.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _COMMON_STACK_H_
+#define _COMMON_STACK_H_
+
+#include <stdint.h>
+
+static inline void *stack_push32(void *stack, uint32_t value)
+{
+ uint32_t *stack32 = stack;
+
+ stack32 = &stack32[-1];
+ *stack32 = value;
+ return stack32;
+}
+
+#endif /* _COMMON_STACK_H_ */
1
0
Patch set updated for coreboot: 3cbb8ff DO NOT MERGE: drivers/intel: Update FSP 1.1 Driver
by Leroy P Leahy 05 May '15
by Leroy P Leahy 05 May '15
05 May '15
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10049
-gerrit
commit 3cbb8ff05446454b5730e874dbe97412a6809350
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Mon Apr 20 15:29:16 2015 -0700
DO NOT MERGE: drivers/intel: Update FSP 1.1 Driver
Update the FSP driver files from 1.0 to 1.1.
Updates will occur manually to these files only for FSP 1.1 support. An
fsp_x_y should be added in the future to support newer versions of the
FSP specification.
Please note that due to the interface with EDK2, these files make
references to data structures and fields that use CamelCase.
BRANCH=none
BUG=None
TEST=Build for Braswell or Skylake boards using FSP 1.1.
Change-Id: I2914c047d786a3060075356783ac9758bc41f633
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/drivers/intel/Kconfig | 1 +
src/drivers/intel/Makefile.inc | 1 +
src/drivers/intel/fsp1_1/Kconfig | 166 ++++++---
src/drivers/intel/fsp1_1/Makefile.inc | 34 +-
src/drivers/intel/fsp1_1/cache_as_ram.inc | 265 +++++++++++---
src/drivers/intel/fsp1_1/fastboot_cache.c | 41 ++-
src/drivers/intel/fsp1_1/fsp_gop.c | 101 ++++++
src/drivers/intel/fsp1_1/fsp_gop.h | 34 ++
src/drivers/intel/fsp1_1/fsp_relocate.c | 458 ++++++++++++++++++++++++
src/drivers/intel/fsp1_1/fsp_util.c | 451 ++++++++++--------------
src/drivers/intel/fsp1_1/fsp_util.h | 108 +++---
src/drivers/intel/fsp1_1/fsp_values.h | 41 ---
src/drivers/intel/fsp1_1/hob.c | 556 +++++++++++++++++++++---------
13 files changed, 1584 insertions(+), 673 deletions(-)
diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig
index 511cf5c..f405927 100644
--- a/src/drivers/intel/Kconfig
+++ b/src/drivers/intel/Kconfig
@@ -17,5 +17,6 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+source src/drivers/intel/fsp1_1/Kconfig
source src/drivers/intel/gma/Kconfig
source src/drivers/intel/i210/Kconfig
diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc
index dc947ff..3ddb05f 100644
--- a/src/drivers/intel/Makefile.inc
+++ b/src/drivers/intel/Makefile.inc
@@ -1,4 +1,5 @@
subdirs-y += gma
subdirs-y += wifi
subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0
+subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1
subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 2492298..6455962 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -17,18 +17,14 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-if PLATFORM_USES_FSP1_0
-
comment "Intel FSP"
-config HAVE_FSP_BIN
+config PLATFORM_USES_FSP1_1
bool "Use Intel Firmware Support Package"
help
- Select this option to add an Intel FSP binary to
- the resulting coreboot image.
+ Does the code require the Intel Firmware Support Package?
- Note: Without this binary, coreboot builds relying on the FSP
- will not boot
+if PLATFORM_USES_FSP1_1
config DCACHE_RAM_BASE
hex
@@ -38,13 +34,61 @@ config DCACHE_RAM_SIZE
hex
default 0x4000
+config HAVE_FSP_BIN
+ bool "Should the Intel FSP binary be added to the flash image"
+ help
+ Select this option to add an Intel FSP binary to
+ the resulting coreboot image.
+
+ Note: Without this binary, coreboot builds relying on the FSP
+ will not boot
+
if HAVE_FSP_BIN
+config CPU_MICROCODE_CBFS_LEN
+ hex "Microcode update region length in bytes"
+ default 0
+ help
+ The length in bytes of the microcode update region.
+
+config CPU_MICROCODE_CBFS_LOC
+ hex "Microcode update base address in CBFS"
+ default 0
+ help
+ The location (base address) in CBFS that contains the microcode update
+ binary.
+
+config ENABLE_MRC_CACHE
+ bool
+ default y if HAVE_ACPI_RESUME
+ default n
+ help
+ Enabling this feature will cause MRC data to be cached in NV storage.
+ This can either be used for fast boot, or just because the FSP wants
+ it to be saved.
+
config FSP_FILE
string "Intel FSP binary path and filename"
help
The path and filename of the Intel FSP binary for this platform.
+config FSP_IMAGE_ID_DWORD0
+ hex "First 4 bytes of 8 byte platform string"
+ help
+ The first four bytes of the eight byte platform specific string
+ used to identify the FSP binary that should be used.
+
+config FSP_IMAGE_ID_DWORD1
+ hex "Second 4 bytes of 8 byte platform string"
+ help
+ The second four bytes of the eight byte platform specific string
+ used to identify the FSP binary that should be used.
+
+config FSP_INCLUDE_PATH
+ string "Path for FSP specific include files"
+ help
+ The path and filename of the Intel FSP binary for this platform.
+
config FSP_LOC
hex "Intel FSP Binary location in CBFS"
help
@@ -52,23 +96,34 @@ config FSP_LOC
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
-config ENABLE_FSP_FAST_BOOT
- bool "Enable Fast Boot"
- select ENABLE_MRC_CACHE
- default n
+config FSP_RESERVED_MEM_SIZE
+ hex "FSP Reserved Memory"
+ default 0x00100000
help
- Enabling this feature will force the MRC data to be cached in NV
- storage to be used for speeding up boot time on future reboots
- and/or power cycles.
+ Memory size in bytes reserved by FSP between PEI Memory and the
+ base of TSEG.
-config ENABLE_MRC_CACHE
- bool
- default y if HAVE_ACPI_RESUME
- default n
+config MRC_CACHE_FILE
+ string "File containing the cached MRC values"
help
- Enabling this feature will cause MRC data to be cached in NV storage.
- This can either be used for fast boot, or just because the FSP wants
- it to be saved.
+ The path and filename of the cached MRC values.
+
+config MRC_CACHE_LOC
+ hex "Fast Boot Data Cache location in CBFS"
+ default MRC_CACHE_LOC_OVERRIDE if OVERRIDE_CACHE_CACHE_LOC
+ default 0xfff50000
+ depends on ENABLE_MRC_CACHE
+ help
+ The location in CBFS for the MRC data to be cached.
+
+ WARNING: This should be on a sector boundary of the BIOS ROM chip
+ and nothing else should be included in that sector, or IT WILL BE
+ ERASED.
+
+config MRC_CACHE_LOC_OVERRIDE
+ hex
+ help
+ Sets the override CBFS location of the MRC/fast boot cache.
config MRC_CACHE_SIZE
hex "Fast Boot Data Cache Size"
@@ -88,23 +143,6 @@ config OVERRIDE_CACHE_CACHE_LOC
Selected by the platform to set a new default location for the
MRC/fast boot cache.
-config MRC_CACHE_LOC_OVERRIDE
- hex
- help
- Sets the override CBFS location of the MRC/fast boot cache.
-
-config MRC_CACHE_LOC
- hex "Fast Boot Data Cache location in CBFS"
- default MRC_CACHE_LOC_OVERRIDE if OVERRIDE_CACHE_CACHE_LOC
- default 0xfff50000
- depends on ENABLE_MRC_CACHE
- help
- The location in CBFS for the MRC data to be cached.
-
- WARNING: This should be on a sector boundary of the BIOS ROM chip
- and nothing else should be included in that sector, or IT WILL BE
- ERASED.
-
config VIRTUAL_ROM_SIZE
hex "Virtual ROM Size"
default ROM_SIZE
@@ -126,20 +164,54 @@ config CACHE_ROM_SIZE_OVERRIDE
default CBFS_SIZE
help
This is the size of the cachable area that is passed into the FSP in
- the early initialization. Typically this should be the size of the CBFS
- area, but the size must be a power of 2 whereas the CBFS size does not
- have this limitation.
+ the early initialization. Typically this should be the size of the
+ CBFS area, but the size must be a power of 2 whereas the CBFS size
+ does not have this limitation.
-config USE_GENERIC_FSP_CAR_INC
- bool
+config DISPLAY_FAST_BOOT_DATA
+ bool "Display fast boot data"
+ default n
+
+config DISPLAY_HOBS
+ bool "Display hand-off-blocks (HOBs)"
+ default n
+
+config DISPLAY_VBT
+ bool "Display Video BIOS Table (VBT)"
+ default n
+
+config DISPLAY_FSP_ENTRY_POINTS
+ bool "Display FSP entry points"
+ default n
+
+config DISPLAY_UPD_DATA
+ bool "Display UPD data"
default n
help
- The chipset can select this to use a generic cache_as_ram.inc file
- that should be good for all FSP based platforms.
+ Display the user specified product data prior to memory
+ initialization.
config FSP_USES_UPD
bool
default n
help
- If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
-endif #PLATFORM_USES_FSP1_0
+ If this FSP uses UPD/VPD data regions, select this in the chipset
+ Kconfig.
+
+config GOP_SUPPORT
+ bool "Enable GOP support"
+ default y
+
+config USE_GENERIC_FSP_CAR_INC
+ bool
+ default n
+ help
+ The chipset can select this to use a generic cache_as_ram.inc file
+ that should be good for all FSP based platforms.
+
+config VBT_FILE
+ string "GOP Video BIOS table binary path"
+ depends on GOP_SUPPORT
+ default "3rdparty/mainboard/$(MAINBOARDDIR)/vbt.bin"
+
+endif #PLATFORM_USES_FSP1_1
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 4931cb7..f789d8c 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+# Copyright (C) 2015 Intel Corp.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -17,33 +18,48 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-ramstage-y += fsp_util.c hob.c
-romstage-y += fsp_util.c hob.c
+romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
+romstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
+romstage-y += fsp_util.c
+romstage-y += hob.c
ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
-romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
+ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
+ramstage-y += fsp_relocate.c
+ramstage-y += fsp_util.c
+ramstage-y += hob.c
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1
ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y)
-cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc
+cpu_incs-y += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
endif
+
+# Add the GOP Video BIOS Table to the cbfs image
+cbfs-files-$(CONFIG_GOP_SUPPORT) += vbt.bin
+vbt.bin-file := $(call strip_quotes,$(CONFIG_VBT_FILE))
+vbt.bin-type := optionrom
+
+
+# Add the FSP binary to the cbfs image
ifeq ($(CONFIG_HAVE_FSP_BIN),y)
cbfs-files-y += fsp.bin
fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
fsp.bin-position := $(CONFIG_FSP_LOC)
-fsp.bin-type := fsp
+fsp.bin-type := 0xab
endif
-ifeq ($(CONFIG_ENABLE_MRC_CACHE),y)
+
+# Create and add the MRC cache to the cbfs image
+ifeq ($(CONFIG_ENABLE_MRC_CACHE_FILE),y)
$(obj)/mrc.cache:
dd if=/dev/zero count=1 \
bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
tr '\000' '\377' > $@
cbfs-files-y += mrc.cache
-mrc.cache-file := $(obj)/mrc.cache
+mrc.cache-file := $(call strip_quotes,$(CONFIG_MRC_CACHE_FILE))
mrc.cache-position := $(CONFIG_MRC_CACHE_LOC)
-mrc.cache-type := mrc_cache
+mrc.cache-type := 0xac
endif
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 8604c3b..ef6510e 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -4,6 +4,7 @@
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,10 +20,17 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+/*
+ * This code locates the FSP binary, initializes the cache as RAM and
+ * performs the first stage of initialization. Next this code switches
+ * the stack from the cache to RAM and then disables the cache as RAM.
+ * Finally this code performs the final stage of initialization.
+ */
+
+#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#include <microcode_size.h>
#include <cbmem.h>
#ifndef CONFIG_FSP_LOC
@@ -33,7 +41,7 @@
# error "CONFIG_POST_IO must be set."
#endif
-#if CONFIG_POST_IO
+#if IS_ENABLED(CONFIG_POST_IO)
# ifndef CONFIG_POST_IO_PORT
# error "CONFIG_POST_IO_PORT must be set."
# endif
@@ -45,75 +53,211 @@
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
- cmp $0, %eax
- jne bisthalt
+ /*
+ * eax: BIST value
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ */
+
+ mov %eax, %edi
cache_as_ram:
post_code(0x20)
/*
+ * edi: BIST value
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ */
+
+ /*
* Find the FSP binary in cbfs.
* Make a fake stack that has the return value back to this code.
*/
- lea fake_fsp_stack, %esp
- jmp find_fsp
+ lea fake_fsp_stack, %esp
+ jmp find_fsp
find_fsp_ret:
/* Save the FSP location */
- mov %eax, %ebp
- cmp $CONFIG_FSP_LOC, %eax
- jb halt1
+ mov %eax, %ebp
+
+ /*
+ * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
+ * the returned FSP_INFO_HEADER structure address above the base
+ * address of FSP binary specified by the CONFIG_FSP_LOC value.
+ * All of the error values are in the 0x8xxxxxxx range which are
+ * below the CONFIG_FSP_LOC value.
+ */
+ cmp $CONFIG_FSP_LOC, %eax
+ jbe halt1
post_code(0x22)
/* Calculate entry into FSP */
- mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
- add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for FSP */
/*
* Pass early init variables on a fake stack (no memory yet)
* as well as the return location
*/
- lea CAR_init_stack, %esp
+ lea CAR_init_stack, %esp
+
+ /*
+ * BIST value is zero
+ * eax: TempRamInitApi address
+ * ebp: FSP_INFO_HEADER address
+ * edi: BIST value
+ * esi: Not used
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ */
/* call FSP binary to setup temporary stack */
- jmp *%eax
+ jmp *%eax
CAR_init_done:
- addl $4, %esp
- cmp $0, %eax
- jne halt2
+ addl $4, %esp
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ */
+
+ cmp $0, %eax
+ jne halt2
+
+ /* Setup bootloader stack */
+ movl %edx, %esp
+
+ /* Save BIST value */
+ movd %edi, %mm2
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * esp: Top of stack in temp RAM
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ * mm2: BIST value
+ */
+
+ /* Coreboot assumes stack/heap region will be zero */
+ cld
+ movl %ecx, %edi
+ neg %ecx
+ add %edx, %ecx
+ shrl $2, %ecx
+ xorl %eax, %eax
+ rep stosl
/* Save FSP_INFO_HEADER location in ebx */
- mov %ebp, %ebx
+ mov %ebp, %ebx
/*
- * set up bootloader stack
- * ecx: stack base
- * edx: stack top
+ * ebx: FSP_INFO_HEADER address
+ * esi: Temp RAM base
+ * esp: Top of stack in temp RAM
+ * mm0: low 32-bits of TSC value
+ * mm1: high 32-bits of TSC value
+ * mm2: BIST value
*/
- mov %edx, %esp
- movl %esp, %ebp
- /* Clear the cbmem CAR memory region. */
- movl %ecx, %edi
- movl %edx, %ecx
- sub %edi, %ecx
- shr $2, %ecx
- xorl %eax, %eax
- rep stosl
+ /* Build frame for romstage_main(bist, tsc_low, tsc_hi) */
+ movd %mm1, %eax
+ pushl %eax
+ movd %mm0, %eax
+ pushl %eax
+ movd %mm2, %eax
+ pushl %eax
before_romstage:
post_code(0x23)
/* Call romstage.c main function. */
- pushl %ebx /* main takes FSP_INFO_HEADER as its argument */
- call main /* does not return */
- movb $0xB8, %ah
- jmp .Lhlt
+ call romstage_main
+
+ /*
+ * eax: New stack address
+ * ebx: FSP_INFO_HEADER address
+ */
+
+ /* Switch to the stack in RAM */
+ movl %eax, %esp
+
+ /* Calculate TempRamExit entry into FSP */
+ movl %ebx, %ebp
+ mov 0x40(%ebp), %eax
+ add 0x1c(%ebp), %eax
+
+ /* Build the call frame */
+ pushl $0
+
+ /* Call TempRamExit */
+ call *%eax
+ add $4, %esp
+ cmp $0, %eax
+ jne halt3
+
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRRphysBase_MSR(0), %ecx
+1:
+ testl %ebx, %ebx
+ jz 1f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 1b
+1:
+ post_code(0x39)
+
+ /* And enable cache again after setting MTRRs. */
+ movl %cr0, %eax
+ andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+ movl %eax, %cr0
+
+ post_code(0x3a)
+
+ /* Enable MTRR. */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $MTRRdefTypeEn, %eax
+ wrmsr
+
+ post_code(0x3b)
-bisthalt:
- movb $0xB9, %ah
- jmp .Lhlt
+ /* Invalidate the cache again. */
+ invd
+
+ post_code(0x3c)
+
+__main:
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
+ call romstage_after_car
+
+
+ movb $0x69, %ah
+ jmp .Lhlt
halt1:
/*
@@ -128,8 +272,8 @@ halt1:
* 0x05 - FSP INFO Header signature "FSPH" not found
* 0x06 - FSP Image ID is not the expected ID.
*/
- movb $0xBA, %ah
- jmp .Lhlt
+ movb $0xBA, %ah
+ jmp .Lhlt
halt2:
/*
@@ -137,25 +281,37 @@ halt2:
*
* 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
- * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
* 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
* 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
*/
- movb $0xBB, %ah
+ movb $0xBB, %ah
+ jmp .Lhlt
+
+halt3:
+ /*
+ * Failures for post code BC - failed in TempRamExit
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed.
+ */
+ movb $0xBC, %ah
.Lhlt:
- xchg %al, %ah
-#if CONFIG_POST_IO
- outb %al, $CONFIG_POST_IO_PORT
+ xchg %al, %ah
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
#else
post_code(POST_DEAD_CODE)
#endif
- movl $LHLT_DELAY, %ecx
+ movl $LHLT_DELAY, %ecx
.Lhlt_Delay:
- outb %al, $0xED
- loop .Lhlt_Delay
- jmp .Lhlt
+ outb %al, $0xED
+ loop .Lhlt_Delay
+ jmp .Lhlt
/*
* esp is set to this location so that the call into and return from the FSP
@@ -163,15 +319,14 @@ halt2:
*/
.align 4
fake_fsp_stack:
- .long find_fsp_ret
+ .long find_fsp_ret
CAR_init_params:
- .long CONFIG_CPU_MICROCODE_CBFS_LOC
- .long MICROCODE_REGION_LENGTH
- .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */
- .long CACHE_ROM_SIZE /* Total Firmware Length */
+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */
+ .long CONFIG_CBFS_SIZE /* Total Firmware Length */
CAR_init_stack:
- .long CAR_init_done
- .long CAR_init_params
-
+ .long CAR_init_done
+ .long CAR_init_params
diff --git a/src/drivers/intel/fsp1_1/fastboot_cache.c b/src/drivers/intel/fsp1_1/fastboot_cache.c
index e8651bb..df762d3 100644
--- a/src/drivers/intel/fsp1_1/fastboot_cache.c
+++ b/src/drivers/intel/fsp1_1/fastboot_cache.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2012 Google Inc.
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,26 +19,23 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <stdint.h>
-#include <string.h>
-#include <bootstate.h>
-#include <console/console.h>
#include <cbfs.h>
-#include <ip_checksum.h>
-#include <device/device.h>
#include <cbmem.h>
-#include <spi-generic.h>
-#include <spi_flash.h>
-#include <lib.h> // hexdump
+#include <console/console.h>
#include "fsp_util.h"
+#include <ip_checksum.h>
+#include <lib.h> // hexdump
+#include <spi_flash.h>
+#include <string.h>
#ifndef CONFIG_VIRTUAL_ROM_SIZE
#error "CONFIG_VIRTUAL_ROM_SIZE must be set."
#endif
/* convert a pointer to flash area into the offset inside the flash */
-static inline u32 to_flash_offset(void *p) {
- return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE);
+static inline u32 to_flash_offset(void *p)
+{
+ return (u32)p + CONFIG_VIRTUAL_ROM_SIZE;
}
static struct mrc_data_container *next_mrc_block(
@@ -50,14 +48,15 @@ static struct mrc_data_container *next_mrc_block(
mrc_size += MRC_DATA_ALIGN;
}
- u8 *region_ptr = (u8*)mrc_cache;
+ u8 *region_ptr = (u8 *)mrc_cache;
region_ptr += mrc_size;
return (struct mrc_data_container *)region_ptr;
}
static int is_mrc_cache(struct mrc_data_container *mrc_cache)
{
- return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE);
+ return (!!mrc_cache)
+ && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE);
}
static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
@@ -96,7 +95,8 @@ static struct mrc_data_container *find_current_mrc_cache_local
}
if (entry_id == 0) {
- printk(BIOS_ERR, "%s: No valid fast boot cache found.\n", __func__);
+ printk(BIOS_ERR, "%s: No valid fast boot cache found.\n",
+ __func__);
return NULL;
}
@@ -104,7 +104,8 @@ static struct mrc_data_container *find_current_mrc_cache_local
if (mrc_cache->mrc_checksum !=
compute_ip_checksum(mrc_cache->mrc_data,
mrc_cache->mrc_data_size)) {
- printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n", __func__);
+ printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n",
+ __func__);
return NULL;
}
@@ -164,6 +165,7 @@ void update_mrc_cache(void *unused)
return;
}
+ cache_base = NULL;
cache_size = get_mrc_cache_region(&cache_base);
if (cache_base == NULL) {
printk(BIOS_ERR, "%s: could not find fast boot cache area\n",
@@ -220,17 +222,19 @@ void update_mrc_cache(void *unused)
#endif /* !defined(__PRE_RAM__) */
-void * find_and_set_fastboot_cache(void)
+void *find_and_set_fastboot_cache(void)
{
struct mrc_data_container *mrc_cache = NULL;
- if (((mrc_cache = find_current_mrc_cache()) == NULL) ||
+ mrc_cache = find_current_mrc_cache();
+ if ((mrc_cache == NULL) ||
(mrc_cache->mrc_data_size == -1UL)) {
printk(BIOS_DEBUG, "FSP MRC cache not present.\n");
return NULL;
}
printk(BIOS_DEBUG, "FSP MRC cache present at %x.\n", (u32)mrc_cache);
printk(BIOS_SPEW, "Saved MRC data:\n");
- hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, (mrc_cache->mrc_data_size) / 4);
+ hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data,
+ mrc_cache->mrc_data_size);
return (void *) mrc_cache->mrc_data;
}
@@ -239,6 +243,7 @@ struct mrc_data_container *find_current_mrc_cache(void)
struct mrc_data_container *cache_base;
u32 cache_size;
+ cache_base = NULL;
cache_size = get_mrc_cache_region(&cache_base);
if (cache_base == NULL) {
printk(BIOS_ERR, "%s: could not find fast boot cache area\n",
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c
new file mode 100644
index 0000000..415333a
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/fsp_gop.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include "fsp_util.h"
+#include <lib.h>
+
+/* Reading VBT table from flash */
+const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len)
+{
+ struct cbfs_file *vbt_file;
+ union {
+ const optionrom_vbt_t *data;
+ uint32_t *signature;
+ } vbt;
+
+ /* Locate the vbt file in cbfs */
+ vbt_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "vbt.bin");
+ if (!vbt_file) {
+ printk(BIOS_INFO,
+ "FSP_INFO: VBT data file (vbt.bin) not found in CBFS");
+ return NULL;
+ }
+
+ /* Validate the vbt file */
+ vbt.data = CBFS_SUBHEADER(vbt_file);
+ if (*vbt.signature != VBT_SIGNATURE) {
+ printk(BIOS_WARNING,
+ "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n");
+ return NULL;
+ }
+ *vbt_len = ntohl(vbt_file->len);
+ printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n",
+ vbt.data, *vbt_len);
+
+#if IS_ENABLED(CONFIG_DISPLAY_VBT)
+ /* Display the vbt file contents */
+ printk(BIOS_DEBUG, "VBT Data:\n");
+ hexdump(vbt.data, *vbt_len);
+ printk(BIOS_DEBUG, "\n");
+#endif
+
+ /* Return the pointer to the vbt file data */
+ return vbt.data;
+}
+
+#ifndef __PRE_RAM__
+void fsp_gop_framebuffer(struct lb_header *header)
+{
+ struct lb_framebuffer *framebuffer;
+ framebuffer = (struct lb_framebuffer *)lb_new_record(header);
+
+ VOID *hob_list_ptr;
+ hob_list_ptr = get_hob_list();
+ const EFI_GUID vbt_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
+ u32 *vbt_hob;
+ EFI_PEI_GRAPHICS_INFO_HOB *vbt_gop;
+ vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr);
+ if (vbt_hob == NULL) {
+ printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n");
+ return;
+ } else {
+ printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
+ vbt_gop = GET_GUID_HOB_DATA(vbt_hob);
+ }
+
+ framebuffer->physical_address = vbt_gop->FrameBufferBase;
+ framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution;
+ framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution;
+ framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine
+ * 4;
+ framebuffer->bits_per_pixel = 32;
+ framebuffer->red_mask_pos = 16;
+ framebuffer->red_mask_size = 8;
+ framebuffer->green_mask_pos = 8;
+ framebuffer->green_mask_size = 8;
+ framebuffer->blue_mask_pos = 0;
+ framebuffer->blue_mask_size = 8;
+ framebuffer->reserved_mask_pos = 24;
+ framebuffer->reserved_mask_size = 8;
+ framebuffer->tag = LB_TAG_FRAMEBUFFER;
+ framebuffer->size = sizeof(*framebuffer);
+}
+#endif /* __PRE_RAM__ */
diff --git a/src/drivers/intel/fsp1_1/fsp_gop.h b/src/drivers/intel/fsp1_1/fsp_gop.h
new file mode 100644
index 0000000..7664a0e
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/fsp_gop.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _FSP_GOP_H_
+#define _FSP_GOP_H_
+
+/* GOP support */
+#if IS_ENABLED(CONFIG_GOP_SUPPORT)
+
+#include <boot/coreboot_tables.h>
+#include <soc/intel/common/gma.h>
+
+const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len);
+#ifndef __PRE_RAM__
+void fsp_gop_framebuffer(struct lb_header *header);
+#endif /* __PRE_RAM__ */
+#endif /* CONFIG_GOP_SUPPORT */
+#endif /* _FSP_GOP_H_ */
diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c
new file mode 100644
index 0000000..db613ee
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/fsp_relocate.c
@@ -0,0 +1,458 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <fsp_util.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <uefi_types.h>
+
+#define FSP_DBG_LVL BIOS_NEVER
+
+static const EFI_GUID ffs2_guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID;
+static const EFI_GUID fih_guid = FSP_INFO_HEADER_GUID;
+
+struct fsp_patch_table {
+ uint32_t signature;
+ uint16_t header_length;
+ uint8_t header_revision;
+ uint8_t reserved;
+ uint32_t patch_entry_num;
+ uint32_t patch_entries[0];
+} __attribute__((packed));
+
+#define FSPP_SIG 0x50505346
+
+static void *relative_offset(void *base, ssize_t offset)
+{
+ uintptr_t loc;
+
+ loc = (uintptr_t)base;
+ loc += offset;
+
+ return (void *)loc;
+}
+
+static uint32_t *fspp_reloc(void *fsp, size_t fsp_size, uint32_t e)
+{
+ size_t offset;
+
+ /* Offsets live in bits 23:0. */
+ offset = e & 0xffffff;
+
+ /* If bit 31 is set then the offset is considered a negative value
+ * relative to the end of the image using 16MiB as the offset's
+ * reference. */
+ if (e & (1 << 31))
+ offset = fsp_size - (16 * MiB - offset);
+
+ /* Determine if offset falls within fsp_size for a 32 bit relocation. */
+ if (offset > fsp_size - sizeof(uint32_t))
+ return NULL;
+
+ return relative_offset(fsp, offset);
+}
+
+static int reloc_type(uint16_t reloc_entry)
+{
+ /* Reloc type in upper 4 bits */
+ return reloc_entry >> 12;
+}
+
+static size_t reloc_offset(uint16_t reloc_entry)
+{
+ /* Offsets are in low 12 bits. */
+ return reloc_entry & ((1 << 12) - 1);
+}
+
+static int te_relocate_in_place(void *te, size_t size)
+{
+ EFI_TE_IMAGE_HEADER *teih;
+ EFI_IMAGE_DATA_DIRECTORY *relocd;
+ EFI_IMAGE_BASE_RELOCATION *relocb;
+ size_t fixup_offset;
+ size_t num_relocs;
+ uint16_t *reloc;
+ size_t relocd_offset;
+ uint8_t *te_base;
+ uint32_t adj;
+
+ teih = te;
+
+ if (teih->Signature != EFI_TE_IMAGE_HEADER_SIGNATURE) {
+ printk(BIOS_ERR, "TE Signature mismatch: %x vs %x\n",
+ teih->Signature, EFI_TE_IMAGE_HEADER_SIGNATURE);
+ return -1;
+ }
+
+ /*
+ * A TE image is created by converting a PE file. Because of this
+ * the offsets within the headers are off. In order to calculate
+ * the correct releative offets one needs to subtract fixup_offset
+ * from the encoded offets. Similarly, the linked address of the
+ * program is found by adding the fixup_offset to the ImageBase.
+ */
+ fixup_offset = teih->StrippedSize - sizeof(EFI_TE_IMAGE_HEADER);
+ /* Keep track of a base that is correctly adjusted so that offsets
+ * can be used directly. */
+ te_base = te;
+ te_base -= fixup_offset;
+
+ adj = (uintptr_t)te - (teih->ImageBase + fixup_offset);
+
+ printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n",
+ (void *)(uintptr_t)(teih->ImageBase + fixup_offset),
+ te, adj);
+
+ /* Adjust ImageBase for consistency. Need to subtract fixup_offset
+ * so the image could be relocated if needed. */
+ teih->ImageBase += adj - fixup_offset;
+
+ relocd = &teih->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC];
+
+ relocd_offset = 0;
+ /* Though the field name is VirtualAddress it's actually relative to
+ * the beginning of the image which is linked at ImageBase. */
+ relocb = relative_offset(te, relocd->VirtualAddress - fixup_offset);
+ while (relocd_offset < relocd->Size) {
+ size_t rva_offset = relocb->VirtualAddress;
+
+ printk(FSP_DBG_LVL, "Relocs for RVA offset %zx\n", rva_offset);
+ num_relocs = relocb->SizeOfBlock - sizeof(*relocb);
+ num_relocs /= sizeof(uint16_t);
+ reloc = relative_offset(relocb, sizeof(*relocb));
+
+ printk(FSP_DBG_LVL, "Num relocs in block: %zx\n", num_relocs);
+
+ while (num_relocs > 0) {
+ int type = reloc_type(*reloc);
+ size_t offset = reloc_offset(*reloc);
+
+ printk(FSP_DBG_LVL, "reloc type %x offset %zx\n",
+ type, offset);
+
+ if (type == EFI_IMAGE_REL_BASED_HIGHLOW) {
+ uint32_t *reloc_addr;
+
+ offset += rva_offset;
+ reloc_addr = (void *)&te_base[offset];
+
+ printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
+ reloc_addr, *reloc_addr,
+ *reloc_addr + adj);
+ *reloc_addr += adj;
+ } else if (type != EFI_IMAGE_REL_BASED_ABSOLUTE) {
+ printk(BIOS_ERR, "Unknown reloc type: %x\n",
+ type);
+ return -1;
+ }
+ num_relocs--;
+ reloc++;
+ }
+
+ /* Track consumption of relocation directory contents. */
+ relocd_offset += relocb->SizeOfBlock;
+ /* Get next relocation block to process. */
+ relocb = relative_offset(relocb, relocb->SizeOfBlock);
+ }
+
+ return 0;
+}
+
+static size_t csh_size(const EFI_COMMON_SECTION_HEADER *csh)
+{
+ size_t size;
+
+ /* Unpack the array into a type that can be used. */
+ size = 0;
+ size |= csh->Size[0] << 0;
+ size |= csh->Size[1] << 8;
+ size |= csh->Size[2] << 16;
+
+ return size;
+}
+
+static size_t section_data_offset(const EFI_COMMON_SECTION_HEADER *csh)
+{
+ if (csh_size(csh) == 0x00ffffff)
+ return sizeof(EFI_COMMON_SECTION_HEADER2);
+ else
+ return sizeof(EFI_COMMON_SECTION_HEADER);
+}
+
+static size_t section_data_size(const EFI_COMMON_SECTION_HEADER *csh)
+{
+ size_t section_size;
+
+ if (csh_size(csh) == 0x00ffffff)
+ section_size = SECTION2_SIZE(csh);
+ else
+ section_size = csh_size(csh);
+
+ return section_size - section_data_offset(csh);
+}
+
+static size_t file_section_offset(const EFI_FFS_FILE_HEADER *ffsfh)
+{
+ if (IS_FFS_FILE2(ffsfh))
+ return sizeof(EFI_FFS_FILE_HEADER2);
+ else
+ return sizeof(EFI_FFS_FILE_HEADER);
+}
+
+static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh)
+{
+ size_t size;
+
+ if (IS_FFS_FILE2(ffsfh))
+ size = FFS_FILE2_SIZE(ffsfh);
+ else {
+ size = ffsfh->Size[0] << 0;
+ size |= ffsfh->Size[1] << 8;
+ size |= ffsfh->Size[2] << 16;
+ }
+ return size;
+}
+
+static int relocate_patch_table(void *fsp, size_t size, size_t offset,
+ ssize_t adjustment)
+{
+ struct fsp_patch_table *table;
+ uint32_t num;
+
+ table = relative_offset(fsp, offset);
+
+ if ((offset + sizeof(*table) > size) ||
+ (table->header_length + offset) > size) {
+ printk(BIOS_ERR, "FSPP not entirely contained in region.\n");
+ return -1;
+ }
+
+ printk(FSP_DBG_LVL, "FSPP relocs: %x\n", table->patch_entry_num);
+
+ for (num = 0; num < table->patch_entry_num; num++) {
+ uint32_t *reloc;
+
+ reloc = fspp_reloc(fsp, size, table->patch_entries[num]);
+
+ if (reloc == NULL) {
+ printk(BIOS_ERR, "Ignoring FSPP entry: %x\n",
+ table->patch_entries[num]);
+ continue;
+ }
+
+ printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
+ reloc, *reloc, (unsigned int)(*reloc + adjustment));
+
+ *reloc += adjustment;
+ }
+
+ return 0;
+}
+
+static void *relocate_remaining_items(void *fsp, size_t size, size_t fih_offset)
+{
+ EFI_FFS_FILE_HEADER *ffsfh;
+ EFI_COMMON_SECTION_HEADER *csh;
+ FSP_INFO_HEADER *fih;
+ ssize_t adjustment;
+ size_t offset;
+
+ printk(FSP_DBG_LVL, "FSP_INFO_HEADER offset is %zx\n", fih_offset);
+
+ if (fih_offset == 0) {
+ printk(BIOS_ERR, "FSP_INFO_HEADER offset is 0.\n");
+ return NULL;
+ }
+
+ /* FSP_INFO_HEADER at first file in FV within first RAW section. */
+ ffsfh = relative_offset(fsp, fih_offset);
+ fih_offset += file_section_offset(ffsfh);
+ csh = relative_offset(fsp, fih_offset);
+ fih_offset += section_data_offset(csh);
+ fih = relative_offset(fsp, fih_offset);
+
+ if (memcmp(&ffsfh->Name, &fih_guid, sizeof(fih_guid))) {
+ printk(BIOS_ERR, "Bad FIH GUID.\n");
+ return NULL;
+ }
+
+ if (csh->Type != EFI_SECTION_RAW) {
+ printk(BIOS_ERR, "FIH file should have raw section: %x\n",
+ csh->Type);
+ return NULL;
+ }
+
+ if (fih->Signature != FSP_SIG) {
+ printk(BIOS_ERR, "Unexpected FIH signature: %08x\n",
+ fih->Signature);
+ return NULL;
+ }
+
+ adjustment = (intptr_t)fsp - fih->ImageBase;
+
+ /* Update ImageBase to reflect FSP's new home. */
+ fih->ImageBase += adjustment;
+
+ /* Need to find patch table and adjust each entry. The tables
+ * following FSP_INFO_HEADER have a 32-bit signature and header
+ * length. The patch table is denoted as having a 'FSPP' signature;
+ * the table format doesn't follow the other tables. */
+ offset = fih_offset + fih->HeaderLength;
+ while (offset + 2 * sizeof(uint32_t) <= size) {
+ uint32_t *table_headers;
+
+ table_headers = relative_offset(fsp, offset);
+
+ printk(FSP_DBG_LVL, "Checking offset %zx for 'FSPP'\n",
+ offset);
+
+ if (table_headers[0] != FSPP_SIG) {
+ offset += table_headers[1];
+ continue;
+ }
+
+ if (relocate_patch_table(fsp, size, offset, adjustment)) {
+ printk(BIOS_ERR, "FSPP relocation failed.\n");
+ return NULL;
+ }
+
+ return fih;
+ }
+
+ printk(BIOS_ERR, "Could not find the FSP patch table.\n");
+ return NULL;
+}
+
+static FSP_INFO_HEADER *fsp_relocate_in_place(void *fsp, size_t size)
+{
+ EFI_FIRMWARE_VOLUME_HEADER *fvh;
+ EFI_FFS_FILE_HEADER *ffsfh;
+ EFI_COMMON_SECTION_HEADER *csh;
+ size_t offset;
+ size_t file_offset;
+ size_t fih_offset;
+
+ fih_offset = 0;
+ offset = 0;
+ fvh = fsp;
+
+ if (fvh->Signature != EFI_FVH_SIGNATURE)
+ return NULL;
+
+ printk(FSP_DBG_LVL, "FVH length: %zx Mapping length: %zx\n",
+ (size_t)fvh->FvLength, size);
+
+ if (fvh->FvLength != size)
+ return NULL;
+
+ if (memcmp(&fvh->FileSystemGuid, &ffs2_guid, sizeof(ffs2_guid))) {
+ printk(BIOS_ERR, "FVH not an FFS2 type.\n");
+ return NULL;
+ }
+
+ if (fvh->ExtHeaderOffset != 0) {
+ EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh;
+
+ offset += fvh->ExtHeaderOffset;
+ fveh = relative_offset(fsp, offset);
+ printk(FSP_DBG_LVL, "Extended Header Offset: %zx Size: %zx\n",
+ (size_t)fvh->ExtHeaderOffset,
+ (size_t)fveh->ExtHeaderSize);
+ offset += fveh->ExtHeaderSize;
+ /* FFS files are 8 byte aligned after extended header. */
+ offset = ALIGN_UP(offset, 8);
+ } else {
+ offset += fvh->HeaderLength;
+ }
+
+ file_offset = offset;
+ while (file_offset + sizeof(*ffsfh) < size) {
+ offset = file_offset;
+ printk(FSP_DBG_LVL, "file offset: %zx\n", file_offset);
+
+ /* First file and section should be FSP info header. */
+ if (fih_offset == 0)
+ fih_offset = file_offset;
+
+ ffsfh = relative_offset(fsp, file_offset);
+
+ printk(FSP_DBG_LVL, "file type = %x\n", ffsfh->Type);
+ printk(FSP_DBG_LVL, "file attribs = %x\n", ffsfh->Attributes);
+
+ /* Next file on 8 byte alignment. */
+ file_offset += ffs_file_size(ffsfh);
+ file_offset = ALIGN_UP(file_offset, 8);
+
+ /* Padding files have no section information. */
+ if (ffsfh->Type == EFI_FV_FILETYPE_FFS_PAD)
+ continue;
+
+ offset += file_section_offset(ffsfh);
+
+ while (offset + sizeof(*csh) < file_offset) {
+ size_t data_size;
+ size_t data_offset;
+
+ csh = relative_offset(fsp, offset);
+
+ printk(FSP_DBG_LVL, "section offset: %zx\n", offset);
+ printk(FSP_DBG_LVL, "section type: %x\n", csh->Type);
+
+ data_size = section_data_size(csh);
+ data_offset = section_data_offset(csh);
+
+ if (data_size + data_offset + offset > file_offset) {
+ printk(BIOS_ERR, "Section exceeds FV size.\n");
+ return NULL;
+ }
+
+ if (csh->Type == EFI_SECTION_TE) {
+ void *te;
+ size_t te_offset = offset + data_offset;
+
+ printk(FSP_DBG_LVL, "TE image at offset %zx\n",
+ te_offset);
+ te = relative_offset(fsp, te_offset);
+ te_relocate_in_place(te, data_size);
+ }
+
+ offset += data_size + data_offset;
+ /* Sections are aligned to 4 bytes. */
+ offset = ALIGN_UP(offset, 4);
+ }
+ }
+
+ return relocate_remaining_items(fsp, size, fih_offset);
+}
+
+FSP_INFO_HEADER *fsp_relocate(void *fsp_src, size_t size)
+{
+ void *new_loc;
+
+ new_loc = cbmem_add(CBMEM_ID_REFCODE, size);
+ if (new_loc == NULL) {
+ printk(BIOS_ERR, "Unable to load FSP into memory.\n");
+ return NULL;
+ }
+ memcpy(new_loc, fsp_src, size);
+ return fsp_relocate_in_place(new_loc, size);
+}
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 3147b67..105f46c 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,336 +18,236 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <types.h>
-#include <string.h>
-#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
+#include <console/console.h>
#include "fsp_util.h"
-#include <lib.h> // hexdump
-#include <ip_checksum.h>
#include <timestamp.h>
-#ifndef __PRE_RAM__
-/* Globals pointers for FSP structures */
-void *FspHobListPtr = NULL;
-FSP_INFO_HEADER *fsp_header_ptr = NULL;
-
-void FspNotify (u32 Phase)
+/* Locate the FSP binary in the coreboot filesystem */
+FSP_INFO_HEADER *find_fsp(void)
{
- FSP_NOTFY_PHASE NotifyPhaseProc;
- NOTIFY_PHASE_PARAMS NotifyPhaseParams;
- EFI_STATUS Status;
-
- if (fsp_header_ptr == NULL) {
- fsp_header_ptr = (void *)find_fsp();
- if ((u32)fsp_header_ptr < 0xff) {
- post_code(0x4F); /* output something in case there is no serial */
- die("Can't find the FSP!\n");
- }
- }
-
- /* call FSP PEI to Notify PostPciEnumeration */
- NotifyPhaseProc = (FSP_NOTFY_PHASE)(fsp_header_ptr->ImageBase +
- fsp_header_ptr->NotifyPhaseEntry);
- NotifyPhaseParams.Phase = Phase;
+ union {
+ EFI_FFS_FILE_HEADER *ffh;
+ FSP_INFO_HEADER *fih;
+ EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh;
+ EFI_FIRMWARE_VOLUME_HEADER *fvh;
+ EFI_RAW_SECTION *rs;
+ u8 *u8;
+ u32 u32;
+ } fsp_ptr;
+ u32 *image_id;
- timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ?
- TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE);
+#ifndef CONFIG_FSP_LOC
+#error "CONFIG_FSP_LOC must be set."
+#endif
- Status = NotifyPhaseProc (&NotifyPhaseParams);
+ for (;;) {
+ /* Get the FSP binary base address in CBFS */
+ fsp_ptr.u8 = (u8 *)CONFIG_FSP_LOC;
- timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ?
- TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
+ /* Check the FV signature, _FVH */
+ if (fsp_ptr.fvh->Signature != 0x4856465F) {
+ fsp_ptr.u8 = (u8 *)ERROR_NO_FV_SIG;
+ break;
+ }
- if (Status != 0)
- printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status);
-}
-#endif /* #ifndef __PRE_RAM__ */
+ /* Locate the file header which follows the FV header. */
+ fsp_ptr.u8 += fsp_ptr.fvh->ExtHeaderOffset;
+ fsp_ptr.u8 += fsp_ptr.fveh->ExtHeaderSize;
+ fsp_ptr.u8 = (u8 *)((fsp_ptr.u32 + 7) & 0xFFFFFFF8);
+
+ /* Check the FFS GUID */
+ if ((((u32 *)&fsp_ptr.ffh->Name)[0] != 0x912740BE)
+ || (((u32 *)&fsp_ptr.ffh->Name)[1] != 0x47342284)
+ || (((u32 *)&fsp_ptr.ffh->Name)[2] != 0xB08471B9)
+ || (((u32 *)&fsp_ptr.ffh->Name)[3] != 0x0C3F3527)) {
+ fsp_ptr.u8 = (u8 *)ERROR_NO_FFS_GUID;
+ break;
+ }
-#ifdef __PRE_RAM__
+ /* Locate the Raw Section Header */
+ fsp_ptr.u8 += sizeof(EFI_FFS_FILE_HEADER);
-/*
- * Call the FSP to do memory init. The FSP doesn't return to this function.
- * The FSP returns to the romstage_main_continue().
- */
-void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
-{
- FSP_FSP_INIT FspInitApi;
- FSP_INIT_PARAMS FspInitParams;
- FSP_INIT_RT_BUFFER FspRtBuffer;
-#if IS_ENABLED(CONFIG_FSP_USES_UPD)
- UPD_DATA_REGION fsp_upd_data;
-#endif
-
- memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
- FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;
- FspInitParams.NvsBufferPtr = NULL;
+ if (fsp_ptr.rs->Type != EFI_SECTION_RAW) {
+ fsp_ptr.u8 = (u8 *)ERROR_NO_INFO_HEADER;
+ break;
+ }
-#if IS_ENABLED(CONFIG_FSP_USES_UPD)
- FspRtBuffer.Common.UpdDataRgnPtr = &fsp_upd_data;
-#endif
- FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer;
- FspInitParams.ContinuationFunc = (CONTINUATION_PROC)ChipsetFspReturnPoint;
- FspInitApi = (FSP_FSP_INIT)(fsp_ptr->ImageBase + fsp_ptr->FspInitEntry);
+ /* Locate the FSP INFO Header which follows the Raw Header. */
+ fsp_ptr.u8 += sizeof(EFI_RAW_SECTION);
- /* Call the chipset code to fill in the chipset specific structures */
- chipset_fsp_early_init(&FspInitParams, fsp_ptr);
+ /* Verify that the FSP base address.*/
+ if (fsp_ptr.fih->ImageBase != CONFIG_FSP_LOC) {
+ fsp_ptr.u8 = (u8 *)ERROR_IMAGEBASE_MISMATCH;
+ break;
+ }
- /* Call back to romstage for board specific changes */
- romstage_fsp_rt_buffer_callback(&FspRtBuffer);
+ /* Verify the FSP Signature */
+ if (fsp_ptr.fih->Signature != FSP_SIG) {
+ fsp_ptr.u8 = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH;
+ break;
+ }
- FspInitApi(&FspInitParams);
+ /* Verify the FSP ID */
+ image_id = (u32 *)&fsp_ptr.fih->ImageId[0];
+ if ((image_id[0] != CONFIG_FSP_IMAGE_ID_DWORD0)
+ || (image_id[1] != CONFIG_FSP_IMAGE_ID_DWORD1))
+ fsp_ptr.u8 = (u8 *)ERROR_FSP_SIG_MISMATCH;
+ break;
+ }
- /* Should never return. Control will continue from ContinuationFunc */
- die("Uh Oh! FspInitApi returned");
+ return fsp_ptr.fih;
}
-#endif /* __PRE_RAM__ */
-volatile u8 * find_fsp ()
+void print_fsp_info(FSP_INFO_HEADER *fsp_header)
{
-
-#ifdef __PRE_RAM__
- volatile register u8 *fsp_ptr asm ("eax");
-
- /* Entry point for CAR assembly routine */
- __asm__ __volatile__ (
- ".global find_fsp\n\t"
- "find_fsp:\n\t"
- );
-#else
- volatile u8 *fsp_ptr;
-#endif /* __PRE_RAM__ */
-
-#ifndef CONFIG_FSP_LOC
-#error "CONFIG_FSP_LOC must be set."
-#endif
-
- /* The FSP is stored in CBFS */
- fsp_ptr = (u8 *) CONFIG_FSP_LOC;
-
- /* Check the FV signature, _FVH */
- if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == 0x4856465F) {
- /* Go to the end of the FV header and align the address. */
- fsp_ptr += ((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->ExtHeaderOffset;
- fsp_ptr += ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)fsp_ptr)->ExtHeaderSize;
- fsp_ptr = (u8 *)(((u32)fsp_ptr + 7) & 0xFFFFFFF8);
- } else {
- fsp_ptr = (u8*)ERROR_NO_FV_SIG;
- }
-
- /* Check the FFS GUID */
- if (((u32)fsp_ptr > 0xff) &&
- (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[0] == 0x912740BE) &&
- (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[1] == 0x47342284) &&
- (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[2] == 0xB08471B9) &&
- (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[3] == 0x0C3F3527)) {
- /* Add the FFS Header size to the base to find the Raw section Header */
- fsp_ptr += sizeof(EFI_FFS_FILE_HEADER);
- } else {
- fsp_ptr = (u8 *)ERROR_NO_FFS_GUID;
+ u8 *fsp_base;
+
+ fsp_base = (u8 *)fsp_header->ImageBase;
+ printk(BIOS_SPEW, "FSP_INFO_HEADER: %p\n", fsp_header);
+ printk(BIOS_INFO, "FSP Signature: %c%c%c%c%c%c%c%c\n",
+ fsp_header->ImageId[0], fsp_header->ImageId[1],
+ fsp_header->ImageId[2], fsp_header->ImageId[3],
+ fsp_header->ImageId[4], fsp_header->ImageId[5],
+ fsp_header->ImageId[6], fsp_header->ImageId[7]);
+ printk(BIOS_INFO, "FSP Header Version: %d\n",
+ fsp_header->HeaderRevision);
+ printk(BIOS_INFO, "FSP Revision: %d.%d\n",
+ (u8)((fsp_header->ImageRevision >> 8) & 0xff),
+ (u8)(fsp_header->ImageRevision & 0xff));
+#if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS)
+ printk(BIOS_SPEW, "FSP Entry Points:\n");
+ printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base);
+ printk(BIOS_SPEW, " 0x%p: TempRamInit\n",
+ &fsp_base[fsp_header->TempRamInitEntryOffset]);
+ printk(BIOS_SPEW, " 0x%p: FspInit\n",
+ &fsp_base[fsp_header->FspInitEntryOffset]);
+ if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) {
+ printk(BIOS_SPEW, " 0x%p: MemoryInit\n",
+ &fsp_base[fsp_header->FspMemoryInitEntryOffset]);
+ printk(BIOS_SPEW, " 0x%p: TempRamExit\n",
+ &fsp_base[fsp_header->TempRamExitEntryOffset]);
+ printk(BIOS_SPEW, " 0x%p: SiliconInit\n",
+ &fsp_base[fsp_header->FspSiliconInitEntryOffset]);
}
+ printk(BIOS_SPEW, " 0x%p: NotifyPhase\n",
+ &fsp_base[fsp_header->NotifyPhaseEntryOffset]);
+ printk(BIOS_SPEW, " 0x%p: Image End\n",
+ &fsp_base[fsp_header->ImageSize]);
+#endif
+}
- if (((u32)fsp_ptr > 0xff) &&
- ((EFI_RAW_SECTION *)fsp_ptr)->Type == EFI_SECTION_RAW) {
- /* Add the Raw Header size to the base to find the FSP INFO Header */
- fsp_ptr += sizeof(EFI_RAW_SECTION);
- } else {
- fsp_ptr = (u8 *)ERROR_NO_INFO_HEADER;
- }
+#ifndef __PRE_RAM__
- /* Verify that the FSP is set to the base address we're expecting.*/
- if (((u32)fsp_ptr > 0xff) &&
- (*(u32*)(fsp_ptr + FSP_IMAGE_BASE_LOC) != CONFIG_FSP_LOC)) {
- fsp_ptr = (u8 *)ERROR_IMAGEBASE_MISMATCH;
- }
+void fsp_notify(u32 phase)
+{
+ FSP_NOTIFY_PHASE notify_phase_proc;
+ NOTIFY_PHASE_PARAMS notify_phase_params;
+ EFI_STATUS status;
+ FSP_INFO_HEADER *fsp_header_ptr;
- /* Verify the FSP Signature */
- if (((u32)fsp_ptr > 0xff) &&
- (*(u32*)(fsp_ptr + FSP_IMAGE_SIG_LOC) != FSP_SIG)){
- fsp_ptr = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH;
+ fsp_header_ptr = fsp_get_fih();
+ if (fsp_header_ptr == NULL) {
+ fsp_header_ptr = (void *)find_fsp();
+ if ((u32)fsp_header_ptr < 0xff) {
+ /* output something in case there is no serial */
+ post_code(0x4F);
+ die("Can't find the FSP!\n");
+ }
}
- /* Verify the FSP ID */
- if (((u32)fsp_ptr > 0xff) &&
- ((*(u32 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID_DWORD0) ||
- (*(u32 *)(fsp_ptr + (FSP_IMAGE_ID_LOC + 4)) != FSP_IMAGE_ID_DWORD1))) {
- fsp_ptr = (u8 *)ERROR_FSP_SIG_MISMATCH;
- }
+ /* call FSP PEI to Notify PostPciEnumeration */
+ notify_phase_proc = (FSP_NOTIFY_PHASE)(fsp_header_ptr->ImageBase +
+ fsp_header_ptr->NotifyPhaseEntryOffset);
+ notify_phase_params.Phase = phase;
- return (fsp_ptr);
-}
+ timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
+ TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE);
-/** finds the saved temporary memory information in the FSP HOB list
- *
- * @param hob_list_ptr pointer to the start of the hob list
- * @return pointer to saved CAR MEM or NULL if not found.
- */
-void * find_saved_temp_mem(void *hob_list_ptr)
-{
- EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID;
- EFI_HOB_GUID_TYPE *saved_mem_hob =
- (EFI_HOB_GUID_TYPE *) find_hob_by_guid(
- hob_list_ptr, &temp_hob_guid);
+ status = notify_phase_proc(¬ify_phase_params);
- if (saved_mem_hob == NULL)
- return NULL;
+ timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
+ TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
- return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE));
+ if (status != 0)
+ printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n",
+ phase, status);
}
-#ifndef FSP_RESERVE_MEMORY_SIZE
-/** @brief locates the HOB containing the location of the fsp reserved mem area
- *
- * @param hob_list_ptr pointer to the start of the hob list
- * @return pointer to the start of the FSP reserved memory or NULL if not found.
- */
-void * find_fsp_reserved_mem(void *hob_list_ptr)
+static void fsp_notify_boot_state_callback(void *arg)
{
- EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
- EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem =
- (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid(
- hob_list_ptr, &fsp_reserved_guid);
+ u32 phase = (u32)arg;
- if (fsp_reserved_mem == NULL)
- return NULL;
-
- return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart);
+ printk(BIOS_SPEW, "Calling FspNotify(0x%08x)\n", phase);
+ fsp_notify(phase);
}
-#endif /* FSP_RESERVE_MEMORY_SIZE */
-
-#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */
-void print_fsp_info(void) {
+BOOT_STATE_INIT_ENTRIES(fsp_bscbs) = {
+ BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT,
+ fsp_notify_boot_state_callback,
+ (void *)EnumInitPhaseAfterPciEnumeration),
+ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT,
+ fsp_notify_boot_state_callback,
+ (void *)EnumInitPhaseReadyToBoot),
+ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
+ fsp_notify_boot_state_callback,
+ (void *)EnumInitPhaseReadyToBoot)
+};
- if (fsp_header_ptr == NULL)
- fsp_header_ptr = (void *)find_fsp();
- if ((u32)fsp_header_ptr < 0xff) {
- post_code(0x4F); /* output something in case there is no serial */
- die("Can't find the FSP!\n");
- }
-
- if (FspHobListPtr == NULL) {
- FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
- }
+#endif /* #ifndef __PRE_RAM__ */
- printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr);
- printk(BIOS_INFO,"FSP Header Version: %d\n", fsp_header_ptr->HeaderRevision);
- printk(BIOS_INFO,"FSP Revision: %d.%d\n",
- (u8)((fsp_header_ptr->ImageRevision >> 8) & 0xff),
- (u8)(fsp_header_ptr->ImageRevision & 0xff));
-}
+struct fsp_runtime {
+ uint32_t fih;
+ uint32_t hob_list;
+} __attribute__((packed));
-#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
-/**
- * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM
- */
-int save_mrc_data(void *hob_start)
+void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list)
{
- u32 *mrc_hob;
- u32 *mrc_hob_data;
- u32 mrc_hob_size;
- struct mrc_data_container *mrc_data;
- int output_len;
- const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
-
- mrc_hob = GetNextGuidHob(&mrc_guid, hob_start);
- if (mrc_hob == NULL){
- printk(BIOS_DEBUG, "Memory Configure Data Hob is not present\n");
- return(0);
- }
+ struct fsp_runtime *fspr;
- mrc_hob_data = GET_GUID_HOB_DATA (mrc_hob);
- mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob);
+ fspr = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*fspr));
- printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n",
- (void *)mrc_hob_data, mrc_hob_size);
+ if (fspr == NULL)
+ die("Can't save FSP runtime information.\n");
- output_len = ALIGN(mrc_hob_size, 16);
+ fspr->fih = (uintptr_t)fih;
+ fspr->hob_list = (uintptr_t)hob_list;
+}
- /* Save the MRC S3/fast boot/ADR restore data to cbmem */
- mrc_data = cbmem_add (CBMEM_ID_MRCDATA,
- output_len + sizeof(struct mrc_data_container));
+FSP_INFO_HEADER *fsp_get_fih(void)
+{
+ struct fsp_runtime *fspr;
- /* Just return if there was a problem with getting CBMEM */
- if (mrc_data == NULL) {
- printk(BIOS_WARNING, "CBMEM was not available to save the fast boot cache data.\n");
- return 0;
- }
+ fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
- printk(BIOS_DEBUG, "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n",
- (void *)mrc_hob_data, mrc_data, output_len);
+ if (fspr == NULL)
+ return NULL;
- mrc_data->mrc_signature = MRC_DATA_SIGNATURE;
- mrc_data->mrc_data_size = output_len;
- mrc_data->reserved = 0;
- memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size);
+ return (void *)(uintptr_t)fspr->fih;
+}
- /* Zero the unused space in aligned buffer. */
- if (output_len > mrc_hob_size)
- memset((mrc_data->mrc_data + mrc_hob_size), 0,
- output_len - mrc_hob_size);
+void *fsp_get_hob_list(void)
+{
+ struct fsp_runtime *fspr;
- mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data,
- mrc_data->mrc_data_size);
+ fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
- printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n");
- hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4);
- return (1);
-}
-#endif /* CONFIG_ENABLE_MRC_CACHE */
+ if (fspr == NULL)
+ return NULL;
-static void find_fsp_hob_update_mrc(void *unused)
-{
- /* Set the global HOB list pointer */
- FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
-
- if (!FspHobListPtr){
- printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n");
- } else {
- /* 0x0000: Print all types */
- print_hob_type_structure(0x000, FspHobListPtr);
-
- #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
- if(save_mrc_data(FspHobListPtr))
- update_mrc_cache(NULL);
- else
- printk(BIOS_DEBUG,"Not updating MRC data in flash.\n");
- #endif
- }
+ return (void *)(uintptr_t)fspr->hob_list;
}
-/** @brief Notify FSP for PostPciEnumeration
- *
- * @param unused
- */
-static void fsp_after_pci_enum(void *unused)
+void fsp_update_fih(FSP_INFO_HEADER *fih)
{
- /* This call needs to be done before resource allocation. */
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
- FspNotify(EnumInitPhaseAfterPciEnumeration);
- printk(BIOS_DEBUG,
- "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
-}
+ struct fsp_runtime *fspr;
-/** @brief Notify FSP for ReadyToBoot
- *
- * @param unused
- */
-static void fsp_finalize(void *unused)
-{
- printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n");
- print_fsp_info();
- FspNotify(EnumInitPhaseReadyToBoot);
- printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n");
-}
+ fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME);
-/* Set up for the ramstage FSP calls */
-BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL);
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
+ if (fspr == NULL)
+ die("Can't update FSP runtime information.\n");
-/* Update the MRC/fast boot cache as part of the late table writing stage */
-BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
- find_fsp_hob_update_mrc, NULL);
-#endif /* #ifndef __PRE_RAM__ */
+ fspr->fih = (uintptr_t)fih;
+}
diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h
index d65b842..377f6d9 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.h
+++ b/src/drivers/intel/fsp1_1/fsp_util.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,35 +21,52 @@
#ifndef FSP_UTIL_H
#define FSP_UTIL_H
+#include <types.h>
+#include <arch/cpu.h>
+#include <fsp_gop.h>
+
+/*
+ * The following are functions with prototypes defined in the EDK2 headers. The
+ * EDK2 headers are included with chipset_fsp_util.h. Define the following
+ * names to reduce the use of CamelCase in the other source files.
+ */
+#define GetHobList get_hob_list
+#define GetNextHob get_next_hob
+#define GetFirstHob get_first_hob
+#define GetNextGuidHob get_next_guid_hob
+#define GetFirstGuidHob get_first_guid_hob
+
+/* Include the EDK2 headers */
#include <chipset_fsp_util.h>
-#include "fsp_values.h"
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
int save_mrc_data(void *hob_start);
void * find_and_set_fastboot_cache(void);
#endif
-volatile u8 * find_fsp (void);
+/* find_fsp() should only be called from assembly code. */
+FSP_INFO_HEADER *find_fsp(void);
+/* Set FSP's runtime information. */
+void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list);
+/* Use a new FSP_INFO_HEADER at runtime. */
+void fsp_update_fih(FSP_INFO_HEADER *fih);
+/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */
+FSP_INFO_HEADER *fsp_get_fih(void);
+/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
+void *fsp_get_hob_list(void);
void fsp_early_init(FSP_INFO_HEADER *fsp_info);
-void FspNotify(u32 Phase);
-void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer);
-void print_fsp_info(void);
-void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams,
- FSP_INFO_HEADER *fsp_ptr);
-void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
-void * find_saved_temp_mem(void *hob_list_ptr);
-void * find_fsp_reserved_mem(void *hob_list_ptr);
-
-/* functions in hob.c */
-void print_hob_mem_attributes(void *Hobptr);
-void print_hob_type_structure(u16 Hobtype, void *Hoblistptr);
-void print_hob_resource_attributes(void *Hobptr);
-void print_guid_type_attributes(void *Hobptr);
-const char * get_hob_type_string(void *Hobptr);
-void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1);
-uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2);
-void printguid(EFI_GUID *guid);
+void fsp_notify(u32 phase);
+void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
+void print_fsp_info(FSP_INFO_HEADER *fsp_header);
+void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid,
+ const void *hob_start);
+void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
+void *get_first_resource_hob(const EFI_GUID *guid);
+/*
+ * Relocate FSP entire binary into ram. Returns NULL on error. Otherwise the
+ * FSP_INFO_HEADER pointer to the relocated FSP.
+ */
+FSP_INFO_HEADER *fsp_relocate(void *fsp_src, size_t size);
/* Additional HOB types not included in the FSP:
* #define EFI_HOB_TYPE_HANDOFF 0x0001
@@ -73,63 +91,31 @@ struct mrc_data_container {
u32 mrc_signature; // "MRCD"
u32 mrc_data_size; // Actual total size of this structure
u32 mrc_checksum; // IP style checksum
- u32 reserved; // For header alignment
+ u32 reserved; // For header alignment
u8 mrc_data[0]; // Variable size, platform/run time dependent.
} __attribute__ ((packed));
struct mrc_data_container *find_current_mrc_cache(void);
-
-#if !defined(__PRE_RAM__)
void update_mrc_cache(void *unused);
-#endif
-#endif
+#endif /* CONFIG_ENABLE_MRC_CACHE */
/* The offset in bytes from the start of the info structure */
-#define FSP_IMAGE_SIG_LOC 0
-#define FSP_IMAGE_ID_LOC 16
-#define FSP_IMAGE_BASE_LOC 28
+#define FSP_IMAGE_SIG_LOC 0
+#define FSP_IMAGE_ID_LOC 16
+#define FSP_IMAGE_BASE_LOC 28
-#define FSP_SIG 0x48505346 /* 'FSPH' */
+#define FSP_SIG 0x48505346 /* 'FSPH' */
#define ERROR_NO_FV_SIG 1
-#define ERROR_NO_FFS_GUID 2
+#define ERROR_NO_FFS_GUID 2
#define ERROR_NO_INFO_HEADER 3
#define ERROR_IMAGEBASE_MISMATCH 4
-#define ERROR_INFO_HEAD_SIG_MISMATCH 5
+#define ERROR_INFO_HEAD_SIG_MISMATCH 5
#define ERROR_FSP_SIG_MISMATCH 6
#ifndef __PRE_RAM__
extern void *FspHobListPtr;
#endif
-#define UPD_DEFAULT_CHECK(member) \
- if (config->member != UPD_DEFAULT) { \
- UpdData->member = config->member - 1; \
- } \
- printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
- config->member ? "(set)" : "(default)");
-
-#define UPD_SPD_CHECK(member) \
- if (config->member == UPD_SPD_ADDR_DISABLED) { \
- UpdData->member = 0x00; \
- } else if (config->member != UPD_SPD_ADDR_DEFAULT) { \
- UpdData->member = config->member; \
- } \
- printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
- config->member ? "(set)" : "(default)");
-
-#define UPD_DEVICE_CHECK(devicename, member, statement) \
- case devicename: \
- UpdData->member = dev->enabled; \
- printk(FSP_INFO_LEVEL, statement "%s\n", \
- UpdData->member?"Enabled":"Disabled"); \
- break;
-
-
-#ifndef FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID
-#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \
- { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } };
-#endif
-
#endif /* FSP_UTIL_H */
diff --git a/src/drivers/intel/fsp1_1/fsp_values.h b/src/drivers/intel/fsp1_1/fsp_values.h
deleted file mode 100644
index e5098bb..0000000
--- a/src/drivers/intel/fsp1_1/fsp_values.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef FSP_VALUES_H
-#define FSP_VALUES_H
-
-#ifndef FSP_DEBUG_LEVEL
-# define FSP_DEBUG_LEVEL BIOS_SPEW
-#endif
-
-#ifndef FSP_INFO_LEVEL
-# define FSP_INFO_LEVEL BIOS_DEBUG
-#endif
-
-#define INCREMENT_FOR_DEFAULT(x) (x+1)
-
-#define UPD_DEFAULT 0x00
-#define UPD_DISABLE INCREMENT_FOR_DEFAULT(0)
-#define UPD_ENABLE INCREMENT_FOR_DEFAULT(1)
-#define UPD_USE_DEVICETREE 0xff
-
-#define UPD_SPD_ADDR_DEFAULT UPD_DEFAULT
-#define UPD_SPD_ADDR_DISABLED 0xFF
-
-#endif
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
index 99c4ba1..5722255 100644
--- a/src/drivers/intel/fsp1_1/hob.c
+++ b/src/drivers/intel/fsp1_1/hob.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,150 +18,329 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <types.h>
-#include <string.h>
+#include <arch/early_variables.h>
+#include <arch/hlt.h>
+#include <bootstate.h>
+#include <cbmem.h>
#include <console/console.h>
-#include <lib.h> // hexdump
#include "fsp_util.h"
+#include <ip_checksum.h>
+#include <lib.h> // hexdump
+#include <string.h>
+
+/*
+ * Reads a 64-bit value from memory that may be unaligned.
+ *
+ * This function returns the 64-bit value pointed to by buffer. The
+ * function guarantees that the read operation does not produce an
+ * alignment fault.
+ *
+ * If buffer is NULL, then ASSERT().
+ *
+ * buffer: Pointer to a 64-bit value that may be unaligned.
+ *
+ * Returns the 64-bit value read from buffer.
+ *
+ */
+static
+uint64_t
+read_unaligned_64(
+ const uint64_t *buffer
+ )
+{
+ ASSERT(buffer != NULL);
+ return *buffer;
+}
-/** Displays a GUID's address and value
+/*
+ * Compares two GUIDs.
+ *
+ * This function compares guid1 to guid2. If the GUIDs are identical then
+ * TRUE is returned. If there are any bit differences in the two GUIDs,
+ * then FALSE is returned.
+ *
+ * If guid1 is NULL, then ASSERT().
+ * If guid2 is NULL, then ASSERT().
+ *
+ * guid1: A pointer to a 128 bit GUID.
+ * guid2: A pointer to a 128 bit GUID.
*
- * @param guid pointer to the GUID to display
+ * Returns non-zero if guid1 and guid2 are identical, otherwise returns 0.
+ *
+ */
+static
+long
+compare_guid(
+ const EFI_GUID * guid1,
+ const EFI_GUID * guid2
+ )
+{
+ uint64_t low_part_of_guid1;
+ uint64_t low_part_of_guid2;
+ uint64_t high_part_of_guid1;
+ uint64_t high_part_of_guid2;
+
+ low_part_of_guid1 = read_unaligned_64((const uint64_t *) guid1);
+ low_part_of_guid2 = read_unaligned_64((const uint64_t *) guid2);
+ high_part_of_guid1 = read_unaligned_64((const uint64_t *) guid1 + 1);
+ high_part_of_guid2 = read_unaligned_64((const uint64_t *) guid2 + 1);
+
+ return ((low_part_of_guid1 == low_part_of_guid2)
+ && (high_part_of_guid1 == high_part_of_guid2));
+}
+
+/* Returns the pointer to the HOB list. */
+VOID *
+EFIAPI
+get_hob_list(
+ VOID
+ )
+{
+ void *hob_list;
+
+ hob_list = fsp_get_hob_list();
+ if (hob_list == NULL)
+ die("Call fsp_set_runtime() before this call!\n");
+ return hob_list;
+}
+
+/* Returns the next instance of a HOB type from the starting HOB. */
+VOID *
+EFIAPI
+get_next_hob(
+ UINT16 type,
+ CONST VOID *hob_start
+ )
+{
+ EFI_PEI_HOB_POINTERS hob;
+
+ ASSERT(hob_start != NULL);
+
+ hob.Raw = (UINT8 *)hob_start;
+
+ /* Parse the HOB list until end of list or matching type is found. */
+ while (!END_OF_HOB_LIST(hob.Raw)) {
+ if (hob.Header->HobType == type)
+ return hob.Raw;
+ if (GET_HOB_LENGTH(hob.Raw) < sizeof(*hob.Header))
+ break;
+ hob.Raw = GET_NEXT_HOB(hob.Raw);
+ }
+ return NULL;
+}
+
+/* Returns the first instance of a HOB type among the whole HOB list. */
+VOID *
+EFIAPI
+get_first_hob(
+ UINT16 type
+ )
+{
+ VOID *hob_list;
+
+ hob_list = get_hob_list();
+ return get_next_hob(type, hob_list);
+}
+
+/* Returns the next instance of the matched GUID HOB from the starting HOB. */
+VOID *
+EFIAPI
+get_next_guid_hob(
+ CONST EFI_GUID * guid,
+ CONST VOID *hob_start
+ )
+{
+ EFI_PEI_HOB_POINTERS hob;
+
+ hob.Raw = (UINT8 *)hob_start;
+ while ((hob.Raw = get_next_hob(EFI_HOB_TYPE_GUID_EXTENSION, hob.Raw))
+ != NULL) {
+ if (compare_guid(guid, &hob.Guid->Name))
+ break;
+ hob.Raw = GET_NEXT_HOB(hob.Raw);
+ }
+ return hob.Raw;
+}
+
+/*
+ * Returns the first instance of the matched GUID HOB among the whole HOB list.
+ */
+VOID *
+EFIAPI
+get_first_guid_hob(
+ CONST EFI_GUID * guid
+ )
+{
+ return get_next_guid_hob(guid, get_hob_list());
+}
+
+/*
+ * Returns the next instance of the matching resource HOB from the starting HOB.
+ */
+void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start)
+{
+ EFI_PEI_HOB_POINTERS hob;
+
+ hob.Raw = (UINT8 *)hob_start;
+ while ((hob.Raw = get_next_hob(EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
+ hob.Raw)) != NULL) {
+ if (compare_guid(guid, &hob.ResourceDescriptor->Owner))
+ break;
+ hob.Raw = GET_NEXT_HOB(hob.Raw);
+ }
+ return hob.Raw;
+}
+
+/*
+ * Returns the first instance of the matching resource HOB among the whole HOB
+ * list.
*/
-void printguid(EFI_GUID *guid)
+void *get_first_resource_hob(const EFI_GUID *guid)
{
- printk(BIOS_SPEW,"Address: %p Guid: %08lx-%04x-%04x-",
- guid, (unsigned long)guid->Data1,
- guid->Data2, guid->Data3);
- printk(BIOS_SPEW,"%02x%02x%02x%02x%02x%02x%02x%02x\n",
- guid->Data4[0], guid->Data4[1],
- guid->Data4[2], guid->Data4[3],
- guid->Data4[4], guid->Data4[5],
- guid->Data4[6], guid->Data4[7] );
+ return get_next_resource_hob(guid, get_hob_list());
}
-void print_hob_mem_attributes(void *Hobptr)
+static void print_hob_mem_attributes(void *hob_ptr)
{
- EFI_HOB_MEMORY_ALLOCATION *HobMemoryPtr = (EFI_HOB_MEMORY_ALLOCATION *)Hobptr;
- EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType;
- u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress;
- u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength;
- const char * Hobmemtypenames[15];
-
- Hobmemtypenames[0] = "EfiReservedMemoryType";
- Hobmemtypenames[1] = "EfiLoaderCode";
- Hobmemtypenames[2] = "EfiLoaderData";
- Hobmemtypenames[3] = "EfiBootServicesCode";
- Hobmemtypenames[4] = "EfiBootServicesData";
- Hobmemtypenames[5] = "EfiRuntimeServicesCode";
- Hobmemtypenames[6] = "EfiRuntimeServicesData";
- Hobmemtypenames[7] = "EfiConventionalMemory";
- Hobmemtypenames[8] = "EfiUnusableMemory";
- Hobmemtypenames[9] = "EfiACPIReclaimMemory";
- Hobmemtypenames[10] = "EfiACPIMemoryNVS";
- Hobmemtypenames[11] = "EfiMemoryMappedIO";
- Hobmemtypenames[12] = "EfiMemoryMappedIOPortSpace";
- Hobmemtypenames[13] = "EfiPalCode";
- Hobmemtypenames[14] = "EfiMaxMemoryType";
+ EFI_HOB_MEMORY_ALLOCATION *hob_memory_ptr =
+ (EFI_HOB_MEMORY_ALLOCATION *)hob_ptr;
+ EFI_MEMORY_TYPE hob_mem_type =
+ hob_memory_ptr->AllocDescriptor.MemoryType;
+ u64 hob_mem_addr = hob_memory_ptr->AllocDescriptor.MemoryBaseAddress;
+ u64 hob_mem_length = hob_memory_ptr->AllocDescriptor.MemoryLength;
+ const char *hob_mem_type_names[15];
+
+ hob_mem_type_names[0] = "EfiReservedMemoryType";
+ hob_mem_type_names[1] = "EfiLoaderCode";
+ hob_mem_type_names[2] = "EfiLoaderData";
+ hob_mem_type_names[3] = "EfiBootServicesCode";
+ hob_mem_type_names[4] = "EfiBootServicesData";
+ hob_mem_type_names[5] = "EfiRuntimeServicesCode";
+ hob_mem_type_names[6] = "EfiRuntimeServicesData";
+ hob_mem_type_names[7] = "EfiConventionalMemory";
+ hob_mem_type_names[8] = "EfiUnusableMemory";
+ hob_mem_type_names[9] = "EfiACPIReclaimMemory";
+ hob_mem_type_names[10] = "EfiACPIMemoryNVS";
+ hob_mem_type_names[11] = "EfiMemoryMappedIO";
+ hob_mem_type_names[12] = "EfiMemoryMappedIOPortSpace";
+ hob_mem_type_names[13] = "EfiPalCode";
+ hob_mem_type_names[14] = "EfiMaxMemoryType";
printk(BIOS_SPEW, " Memory type %s (0x%x)\n",
- Hobmemtypenames[(u32)Hobmemtype], (u32) Hobmemtype);
+ hob_mem_type_names[(u32)hob_mem_type],
+ (u32)hob_mem_type);
printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
- (unsigned long)Hobmemaddr, (unsigned long)Hobmemlength);
+ (unsigned long)hob_mem_addr,
+ (unsigned long)hob_mem_length);
}
-void print_hob_resource_attributes(void *Hobptr)
+static void print_hob_resource_attributes(void *hob_ptr)
{
- EFI_HOB_RESOURCE_DESCRIPTOR *HobResourcePtr =
- (EFI_HOB_RESOURCE_DESCRIPTOR *)Hobptr;
- u32 Hobrestype = HobResourcePtr->ResourceType;
- u32 Hobresattr = HobResourcePtr->ResourceAttribute;
- u64 Hobresaddr = HobResourcePtr->PhysicalStart;
- u64 Hobreslength = HobResourcePtr->ResourceLength;
- const char *Hobrestypestr = NULL;
-
- // HOB Resource Types
- switch (Hobrestype) {
+ EFI_HOB_RESOURCE_DESCRIPTOR *hob_resource_ptr =
+ (EFI_HOB_RESOURCE_DESCRIPTOR *)hob_ptr;
+ u32 hob_res_type = hob_resource_ptr->ResourceType;
+ u32 hob_res_attr = hob_resource_ptr->ResourceAttribute;
+ u64 hob_res_addr = hob_resource_ptr->PhysicalStart;
+ u64 hob_res_length = hob_resource_ptr->ResourceLength;
+ const char *hob_res_type_str = NULL;
+
+ /* HOB Resource Types */
+ switch (hob_res_type) {
case EFI_RESOURCE_SYSTEM_MEMORY:
- Hobrestypestr = "EFI_RESOURCE_SYSTEM_MEMORY"; break;
+ hob_res_type_str = "EFI_RESOURCE_SYSTEM_MEMORY";
+ break;
case EFI_RESOURCE_MEMORY_MAPPED_IO:
- Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO"; break;
+ hob_res_type_str = "EFI_RESOURCE_MEMORY_MAPPED_IO";
+ break;
case EFI_RESOURCE_IO:
- Hobrestypestr = "EFI_RESOURCE_IO"; break;
+ hob_res_type_str = "EFI_RESOURCE_IO";
+ break;
case EFI_RESOURCE_FIRMWARE_DEVICE:
- Hobrestypestr = "EFI_RESOURCE_FIRMWARE_DEVICE"; break;
+ hob_res_type_str = "EFI_RESOURCE_FIRMWARE_DEVICE";
+ break;
case EFI_RESOURCE_MEMORY_MAPPED_IO_PORT:
- Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT"; break;
+ hob_res_type_str = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT";
+ break;
case EFI_RESOURCE_MEMORY_RESERVED:
- Hobrestypestr = "EFI_RESOURCE_MEMORY_RESERVED"; break;
+ hob_res_type_str = "EFI_RESOURCE_MEMORY_RESERVED";
+ break;
case EFI_RESOURCE_IO_RESERVED:
- Hobrestypestr = "EFI_RESOURCE_IO_RESERVED"; break;
+ hob_res_type_str = "EFI_RESOURCE_IO_RESERVED";
+ break;
case EFI_RESOURCE_MAX_MEMORY_TYPE:
- Hobrestypestr = "EFI_RESOURCE_MAX_MEMORY_TYPE"; break;
+ hob_res_type_str = "EFI_RESOURCE_MAX_MEMORY_TYPE";
+ break;
default:
- Hobrestypestr = "EFI_RESOURCE_UNKNOWN"; break;
+ hob_res_type_str = "EFI_RESOURCE_UNKNOWN";
+ break;
}
printk(BIOS_SPEW, " Resource %s (0x%0x) has attributes 0x%0x\n",
- Hobrestypestr, Hobrestype, Hobresattr);
+ hob_res_type_str, hob_res_type, hob_res_attr);
printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n",
- (unsigned long)Hobresaddr, (unsigned long)Hobreslength);
+ (unsigned long)hob_res_addr,
+ (unsigned long)hob_res_length);
}
-const char * get_hob_type_string(void *Hobptr)
+static const char *get_hob_type_string(void *hob_ptr)
{
- EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr;
- u16 Hobtype = HobHeaderPtr->HobType;
- const char *Hobtypestring = NULL;
+ EFI_PEI_HOB_POINTERS hob;
+ const char *hob_type_string = NULL;
+ const EFI_GUID fsp_reserved_guid =
+ FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
+ const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+ const EFI_GUID bootldr_tmp_mem_guid =
+ FSP_BOOTLOADER_TEMP_MEMORY_HOB_GUID;
+ const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
+ const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
- switch (Hobtype) {
+ hob.Header = (EFI_HOB_GENERIC_HEADER *)hob_ptr;
+ switch (hob.Header->HobType) {
case EFI_HOB_TYPE_HANDOFF:
- Hobtypestring = "EFI_HOB_TYPE_HANDOFF"; break;
+ hob_type_string = "EFI_HOB_TYPE_HANDOFF";
+ break;
case EFI_HOB_TYPE_MEMORY_ALLOCATION:
- Hobtypestring = "EFI_HOB_TYPE_MEMORY_ALLOCATION"; break;
+ hob_type_string = "EFI_HOB_TYPE_MEMORY_ALLOCATION";
+ break;
case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
- Hobtypestring = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR"; break;
+ hob_type_string = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR";
+ break;
case EFI_HOB_TYPE_GUID_EXTENSION:
- Hobtypestring = "EFI_HOB_TYPE_GUID_EXTENSION"; break;
+ hob_type_string = "EFI_HOB_TYPE_GUID_EXTENSION";
+ if (compare_guid(&bootldr_tmp_mem_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_BOOTLOADER_TEMP_MEMORY_HOB";
+ else if (compare_guid(&fsp_reserved_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_RESERVED_MEMORY_RESOURCE_HOB";
+ else if (compare_guid(&mrc_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_NON_VOLATILE_STORAGE_HOB";
+ else if (compare_guid(&bootldr_tolum_guid, &hob.Guid->Name))
+ hob_type_string = "FSP_BOOTLOADER_TOLUM_HOB_GUID";
+ else if (compare_guid(&graphics_info_guid, &hob.Guid->Name))
+ hob_type_string = "EFI_PEI_GRAPHICS_INFO_HOB_GUID";
+ break;
case EFI_HOB_TYPE_MEMORY_POOL:
- Hobtypestring = "EFI_HOB_TYPE_MEMORY_POOL"; break;
+ hob_type_string = "EFI_HOB_TYPE_MEMORY_POOL";
+ break;
case EFI_HOB_TYPE_UNUSED:
- Hobtypestring = "EFI_HOB_TYPE_UNUSED"; break;
+ hob_type_string = "EFI_HOB_TYPE_UNUSED";
+ break;
case EFI_HOB_TYPE_END_OF_HOB_LIST:
- Hobtypestring = "EFI_HOB_TYPE_END_OF_HOB_LIST"; break;
+ hob_type_string = "EFI_HOB_TYPE_END_OF_HOB_LIST";
+ break;
default:
- Hobtypestring = "EFI_HOB_TYPE_UNRECOGNIZED"; break;
+ hob_type_string = "EFI_HOB_TYPE_UNRECOGNIZED";
+ break;
}
- return Hobtypestring;
+ return hob_type_string;
}
-/** Displays the length, location, and GUID value of a GUID extension
- *
- * The EFI_HOB_GUID_TYPE is very basic - it just contains the standard
- * HOB header containing the HOB type and length, and a GUID for
- * identification. The rest of the data is undefined and must be known
- * based on the GUID.
- *
- * This displays the entire HOB length, and the location of the start
- * of the HOB, *NOT* the length of or the start of the data inside the HOB.
- *
- * @param Hobptr
- */
-void print_guid_type_attributes(void *Hobptr)
-{
- printk(BIOS_SPEW, " at location %p with length0x%0lx\n ",
- Hobptr, (unsigned long)(((EFI_PEI_HOB_POINTERS *) \
- Hobptr)->Guid->Header.HobLength));
- printguid(&(((EFI_HOB_GUID_TYPE *)Hobptr)->Name));
-
-}
-
-/* Print out a structure of all the HOBs
+/*
+ * Print out a structure of all the HOBs
* that match a certain type:
* Print all types (0x0000)
- * EFI_HOB_TYPE_HANDOFF (0x0001)
+ * EFI_HOB_TYPE_HANDOFF (0x0001)
* EFI_HOB_TYPE_MEMORY_ALLOCATION (0x0002)
* EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (0x0003)
* EFI_HOB_TYPE_GUID_EXTENSION (0x0004)
@@ -168,102 +348,144 @@ void print_guid_type_attributes(void *Hobptr)
* EFI_HOB_TYPE_UNUSED (0xFFFE)
* EFI_HOB_TYPE_END_OF_HOB_LIST (0xFFFF)
*/
-void print_hob_type_structure(u16 Hobtype, void *Hoblistptr)
+void print_hob_type_structure(u16 hob_type, void *hob_list_ptr)
{
- u32 *Currenthob;
- u32 *Nexthob = 0;
- u8 Lasthob = 0;
- u32 Currenttype;
- const char *Currenttypestr;
+ u32 *current_hob;
+ u32 *next_hob = 0;
+ u8 last_hob = 0;
+ u32 current_type;
+ const char *current_type_str;
- Currenthob = Hoblistptr;
+ current_hob = hob_list_ptr;
- /* Print out HOBs of our desired type until
+ /*
+ * Print out HOBs of our desired type until
* the end of the HOB list
*/
printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n");
- printk(BIOS_DEBUG, "FSP Hoblistptr: 0x%0x\n",
- (u32) Hoblistptr);
+ printk(BIOS_DEBUG, "0x%p: hob_list_ptr\n", hob_list_ptr);
do {
- EFI_HOB_GENERIC_HEADER *CurrentHeaderPtr =
- (EFI_HOB_GENERIC_HEADER *)Currenthob;
- Currenttype = CurrentHeaderPtr->HobType; /* Get the type of this HOB */
- Currenttypestr = get_hob_type_string(Currenthob);
+ EFI_HOB_GENERIC_HEADER *current_header_ptr =
+ (EFI_HOB_GENERIC_HEADER *)current_hob;
+
+ /* Get the type of this HOB */
+ current_type = current_header_ptr->HobType;
+ current_type_str = get_hob_type_string(current_hob);
- if (Currenttype == Hobtype || Hobtype == 0x0000) {
+ if (current_type == hob_type || hob_type == 0x0000) {
printk(BIOS_DEBUG, "HOB 0x%0x is an %s (type 0x%0x)\n",
- (u32) Currenthob, Currenttypestr, Currenttype);
- switch (Currenttype) {
+ (u32)current_hob, current_type_str,
+ current_type);
+ switch (current_type) {
case EFI_HOB_TYPE_MEMORY_ALLOCATION:
- print_hob_mem_attributes(Currenthob); break;
+ print_hob_mem_attributes(current_hob);
+ break;
case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
- print_hob_resource_attributes(Currenthob); break;
- case EFI_HOB_TYPE_GUID_EXTENSION:
- print_guid_type_attributes(Currenthob); break;
+ print_hob_resource_attributes(current_hob);
+ break;
}
}
- Lasthob = END_OF_HOB_LIST(Currenthob); /* Check for end of HOB list */
- if (!Lasthob) {
- Nexthob = GET_NEXT_HOB(Currenthob); /* Get next HOB pointer */
- Currenthob = Nexthob; // Start on next HOB
+ /* Check for end of HOB list */
+ last_hob = END_OF_HOB_LIST(current_hob);
+ if (!last_hob) {
+ /* Get next HOB pointer */
+ next_hob = GET_NEXT_HOB(current_hob);
+
+ /* Start on next HOB */
+ current_hob = next_hob;
}
- } while (!Lasthob);
+ } while (!last_hob);
printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n");
}
-
-/** Finds a HOB entry based on type and guid
- *
- * @param current_hob pointer to the start of the HOB list
- * @param guid the GUID of the HOB entry to find
- * @return pointer to the start of the requested HOB or NULL if not found.
+#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
+/*
+ * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM
*/
-void * find_hob_by_guid(void *current_hob, EFI_GUID *guid)
+int save_mrc_data(void *hob_start)
{
- do {
- switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) {
+ u32 *mrc_hob;
+ u32 *mrc_hob_data;
+ u32 mrc_hob_size;
+ struct mrc_data_container *mrc_data;
+ int output_len;
+ const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
- case EFI_HOB_TYPE_MEMORY_ALLOCATION:
- if (guids_are_equal(guid, &(((EFI_HOB_MEMORY_ALLOCATION *) \
- current_hob)->AllocDescriptor.Name)))
- return current_hob;
- break;
- case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR:
- if (guids_are_equal(guid,
- &(((EFI_HOB_RESOURCE_DESCRIPTOR *) \
- current_hob)->Owner)))
- return current_hob;
- break;
- case EFI_HOB_TYPE_GUID_EXTENSION:
- if (guids_are_equal(guid, &(((EFI_HOB_GUID_TYPE *) \
- current_hob)->Name)))
- return current_hob;
- break;
- }
+ mrc_hob = get_next_guid_hob(&mrc_guid, hob_start);
+ if (mrc_hob == NULL) {
+ printk(BIOS_DEBUG,
+ "Memory Configure Data Hob is not present\n");
+ return 0;
+ }
- if (!END_OF_HOB_LIST(current_hob))
- current_hob = GET_NEXT_HOB(current_hob); /* Get next HOB pointer */
- } while (!END_OF_HOB_LIST(current_hob));
+ mrc_hob_data = GET_GUID_HOB_DATA(mrc_hob);
+ mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob);
- return NULL;
-}
+ printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n",
+ (void *)mrc_hob_data, mrc_hob_size);
-/** Compares a pair of GUIDs to see if they are equal
- *
- * GUIDs are 128 bits long, so compare them as pairs of quadwords.
- *
- * @param guid1 pointer to the first of the GUIDs to compare
- * @param guid2 pointer to the second of the GUIDs to compare
- * @return 1 if the GUIDs were equal, 0 if GUIDs were not equal
- */
-uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2)
-{
- uint64_t* guid_1 = (void *) guid1;
- uint64_t* guid_2 = (void *) guid2;
+ output_len = ALIGN(mrc_hob_size, 16);
+
+ /* Save the MRC S3/fast boot/ADR restore data to cbmem */
+ mrc_data = cbmem_add(CBMEM_ID_MRCDATA,
+ output_len + sizeof(struct mrc_data_container));
- if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1)))
+ /* Just return if there was a problem with getting CBMEM */
+ if (mrc_data == NULL) {
+ printk(BIOS_WARNING,
+ "CBMEM was not available to save the fast boot cache data.\n");
return 0;
+ }
+ printk(BIOS_DEBUG,
+ "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n",
+ (void *)mrc_hob_data, mrc_data, output_len);
+
+ mrc_data->mrc_signature = MRC_DATA_SIGNATURE;
+ mrc_data->mrc_data_size = output_len;
+ mrc_data->reserved = 0;
+ memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size);
+
+ /* Zero the unused space in aligned buffer. */
+ if (output_len > mrc_hob_size)
+ memset((mrc_data->mrc_data + mrc_hob_size), 0,
+ output_len - mrc_hob_size);
+
+ mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data,
+ mrc_data->mrc_data_size);
+
+#if IS_ENABLED(CONFIG_DISPLAY_FAST_BOOT_DATA)
+ printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n");
+ hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len);
+#endif
return 1;
}
+
+void __attribute__ ((weak)) update_mrc_cache(void *unused)
+{
+ printk(BIOS_ERR, "Add routine %s to save the MRC data.\n", __func__);
+}
+#endif /* CONFIG_ENABLE_MRC_CACHE */
+
+static void find_fsp_hob_update_mrc(void *unused)
+{
+ void *hob_list_ptr;
+
+ /* 0x0000: Print all types */
+ hob_list_ptr = get_hob_list();
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ print_hob_type_structure(0x000, hob_list_ptr);
+#endif
+
+ #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
+ if (save_mrc_data(hob_list_ptr))
+ update_mrc_cache(NULL);
+ else
+ printk(BIOS_DEBUG, "Not updating MRC data in flash.\n");
+ #endif
+}
+
+/* Update the MRC/fast boot cache as part of the late table writing stage */
+BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
+ find_fsp_hob_update_mrc, NULL);
1
0
New patch to review for coreboot: b652c2c Fix Kconfig option list generator
by Stefan Reinauer 05 May '15
by Stefan Reinauer 05 May '15
05 May '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10115
-gerrit
commit b652c2c14f0c5561f55f293dd686f4ad466d6ddf
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue May 5 16:20:07 2015 -0700
Fix Kconfig option list generator
The Kconfig option list generator was broken by two different changes
to the project in the last few years:
- the switch to git from svn
- allowing wild card includes in Kconfig
Change-Id: I6bc5024a04958e9718d2e3a3a3bb6d69d4277eb6
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
util/optionlist/Makefile | 6 ++----
util/optionlist/kconfig2wiki | 5 ++++-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/util/optionlist/Makefile b/util/optionlist/Makefile
index 8e78c9a..592d286 100644
--- a/util/optionlist/Makefile
+++ b/util/optionlist/Makefile
@@ -15,12 +15,10 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-
-SVNVERSION := $(shell LC_ALL=C svnversion -cn ../.. | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/" | grep "[0-9]" || LC_ALL=C svn info . | grep ^Revision | sed "s/.*[[:blank:]]\+\([0-9]*\)[^0-9]*/\1/" | grep "[0-9]" || echo unknown)
+VERSION := $(shell git describe --dirty --always || git describe)
all:
- cd ../..; util/optionlist/kconfig2wiki src/Kconfig $(SVNVERSION) > util/optionlist/Options.wiki
+ cd ../..; util/optionlist/kconfig2wiki src/Kconfig $(VERSION) > util/optionlist/Options.wiki
clean:
rm -rf Options.wiki
-
diff --git a/util/optionlist/kconfig2wiki b/util/optionlist/kconfig2wiki
index b73afa5..4265d37 100755
--- a/util/optionlist/kconfig2wiki
+++ b/util/optionlist/kconfig2wiki
@@ -21,6 +21,8 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+import glob
+
helplen = 0
extra_chapters = 0
@@ -105,7 +107,8 @@ def readfile(filename):
sys.stdout.write("\n")
elif words[0] == "source":
fn=zapquotes(words[1])
- readfile(fn)
+ for name in glob.glob(fn):
+ readfile(name)
elif words[0] in ("default","depends", "select", "if", "endif", "#"): pass
#else: sys.stderr.write("unknown: %s\n" % i)
if helplen: sys.stdout.write("||\n")
1
0
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10114
-gerrit
commit 40c26df2609759b1b9d4c2266c020fcaa7dc25ff
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue May 5 13:53:58 2015 -0700
Drop i915tool
This tool has had its own repository since a long time:
https://code.google.com/p/i915tool/
Drop the obsolete copy we kept in the tree.
Change-Id: Idee4ea3423453f6ced6e95c0bd2e45d95ca61851
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
util/i915tool/Makefile | 20 --
util/i915tool/README | 11 -
util/i915tool/main.c | 255 --------------
util/i915tool/pci.c | 97 -----
util/i915tool/plusplusplus | 3 -
util/i915tool/spatches/deldev.cocci | 29 --
util/i915tool/spatches/drm_crtc.cocci | 32 --
util/i915tool/spatches/fixcalls.cocci | 148 --------
util/i915tool/spatches/fx.cocci | 10 -
util/i915tool/spatches/getdrmmodefn.cocci | 6 -
util/i915tool/spatches/getfn.cocci | 61 ----
util/i915tool/spatches/i915_dma.c.cocci | 3 -
util/i915tool/spatches/i915_drv.c.cocci | 8 -
util/i915tool/spatches/i915_drv.cocci | 178 ----------
util/i915tool/spatches/intel_bios.cocci | 7 -
util/i915tool/spatches/intel_display.c.cocci | 507 ---------------------------
util/i915tool/spatches/removeinclude.cocci | 6 -
util/i915tool/spatches/ringbuffer.cocci | 14 -
util/i915tool/transform | 151 --------
util/i915tool/video.h | 133 -------
20 files changed, 1679 deletions(-)
diff --git a/util/i915tool/Makefile b/util/i915tool/Makefile
deleted file mode 100644
index 4cd807a..0000000
--- a/util/i915tool/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-source=main.c pci.c final/intel_bios.c final/drm_modes.c final/i915_drv.c
-
-all: probe
-
-broken: video
-
-video: $(source) final/intel_display.c
- cc -include video.h -Iinputs -static -g -o video $(source) \
- -lpci final/intel_display.c
-
-probe: $(source)
- cc -include video.h -Iinputs -static -g -o probe $(source) -lpci
-clean:
- rm -f *.o video probe
-
-moreclean: clean
- rm final/* per-file-changes/* tmp/*
-
-superclean: moreclean
- rm inputs/*
diff --git a/util/i915tool/README b/util/i915tool/README
deleted file mode 100644
index cb5f986..0000000
--- a/util/i915tool/README
+++ /dev/null
@@ -1,11 +0,0 @@
-spatches are the semantic patches
-tmp is just tmp
-inputs are copied from $LINUX
-per-file-changes contain input files that have specific transforms
-final contains the final form of the file, with 'global' changes applied (e.g. kzalloc -> calloc)
-
-transform copies files from $LINUX and then transforms them for use by stand-alone program/coreboot
-
-The Makefile is simple; this runs 'fast enough' that a complicated Makefile is not worth it.
-
-There's still some duct tape here but it's getting there.
diff --git a/util/i915tool/main.c b/util/i915tool/main.c
deleted file mode 100644
index a0b4dec..0000000
--- a/util/i915tool/main.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * This file is part of i915tool
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "video.h"
-
-int verbose = 1;
-static unsigned short addrport, dataport;
-struct drm_device *i915;
-unsigned short vendor=0x8086, device=0x0116;
-struct pci_dev fake = {.vendor_id=0x8086, .device_id = 0x0116};
-int dofake = 0;
-u8 *bios_image = NULL;
-u8 *mmiobase;
-u32 mmiophys;
-int mmiosize;
-size_t bios_image_size;
-/* temporary */
-unsigned int i915_lvds_downclock = 0;
-int i915_vbt_sdvo_panel_type = -1;
-
-/* */
-
-/* not sure how we want to do this so let's guess */
-/* to make it easy, we start at zero and assume 250 hz. */
-unsigned long msecs(void)
-{
- struct timeval start, now;
- static int first = 0;
- unsigned long j;
- if (! first++)
- gettimeofday(&start, NULL);
- gettimeofday(&now, NULL);
- j = (now.tv_sec - start.tv_sec)*1000 + (now.tv_usec-start.tv_usec)/1000;
- return j;
-}
-
-void
-mdelay(unsigned long ms)
-{
- unsigned long start;
- start = msecs();
- while (msecs() < (start + ms))
- ;
-}
-
-void
-hexdump(u8 *base, int size)
-{
- int i, j;
- for(i = 0; i < size/sizeof(u32); i += 8) {
- printf("%#x: ", i);
- for(j = 0; j < 8; j++)
- printf("%08x", base[i+j]);
- printf("\n");
- }
-}
-void udelay(int i)
-{
- printf("UDELAY!\n");
-}
-
-unsigned long io_I915_READ(unsigned long addr)
-{
- unsigned long val;
- if (dofake)
- return 0xcafebabe;
- outl(addr, addrport);
- val = inl(dataport);
- if (verbose)
- fprintf(stderr, "%s: %x <- %x\n", __func__, val, addr);
- return val;
-}
-
-void io_I915_WRITE(unsigned long addr, unsigned long val)
-{
- if (dofake)
- return;
- outl(addr, addrport);
- outl(val, dataport);
- if (verbose)
- fprintf(stderr, "%s: %x -> %x\n", __func__, val, addr);
-}
-
-unsigned long I915_READ(unsigned long addr)
-{
- volatile u32 *ptr = (u32 *)(mmiobase + addr);
- unsigned long val;
- if (dofake)
- return 0xcafebabe;
- val = *ptr;
- if (verbose)
- fprintf(stderr, "%s: %x <- %x\n", __func__, val, addr);
- return val;
-}
-
-void I915_WRITE(unsigned long addr, unsigned long val)
-{
- volatile u32 *ptr = (u32 *)(mmiobase + addr);
- if (dofake)
- return;
- *ptr = val;
- if (verbose)
- fprintf(stderr, "%s: %x -> %x\n", __func__, val, addr);
-}
-
-u16 I915_READ16(unsigned long addr)
-{
- volatile u16 *ptr = (u16 *)(mmiobase + addr);
- unsigned long val;
- if (dofake)
- return 0xbabe;
- val = *ptr;
- if (verbose)
- fprintf(stderr, "%s: %x <- %x\n", __func__, val, addr);
- return val;
-}
-
-void I915_WRITE16(unsigned long addr, u16 val)
-{
- volatile u16 *ptr = (u16 *)(mmiobase + addr);
- if (dofake)
- return;
- *ptr = val;
- if (verbose)
- fprintf(stderr, "%s: %x -> %x\n", __func__, val, addr);
-}
-
-#define GTT_RETRY 1000
-static int gtt_poll(u32 reg, u32 mask, u32 value)
-{
- unsigned try = GTT_RETRY;
- u32 data;
-
- while (try--) {
- data = I915_READ(reg);
- if ((data & mask) == value){
- printf("succeeds after %d tries\n", GTT_RETRY-try);
- return 1;
- }
- udelay(10);
- }
-
- fprintf(stderr, "GT init timeout\n");
- return 0;
-}
-void *pci_map_rom(struct pci_dev *dev, size_t *size)
-{
- *size = bios_image_size;
- return bios_image;
-}
-
-void *pci_unmap_rom(struct pci_dev *dev, void *bios)
-{
- return NULL;
-}
-
-void *dmi_check_system(unsigned long ignore)
-{
- return NULL;
-}
-
-void
-mapit(void)
-{
- int kfd;
- kfd = open("/dev/mem", O_RDWR);
- if (kfd < 0)
- errx(1, "/dev/kmem");
- mmiobase = mmap(NULL, mmiosize, PROT_WRITE|PROT_READ, MAP_SHARED, kfd,
- mmiophys);
- if ((void *)-1 == mmiobase)
- errx(1, "mmap");
-}
-
-void
-devinit()
-{
- u32 val;
- /* force wake. */
- I915_WRITE(0xa18c, 1);
- gtt_poll(0x130090, 1, 1);
-}
-int main(int argc, char *argv[])
-{
- struct pci_dev *pci_dev_find(struct drm_device *dev);
-
- for(argc--, argv++; argc; argc--, argv++) {
- if (argv[0][0] != '-')
- break;
- if (!strcmp(argv[0], "-f"))
- dofake++;
- }
- i915 = calloc(1, sizeof(*i915));
- i915->dev_private = calloc(1, sizeof(*i915->dev_private));
- /* until we do a bit more w/ coccinelle */
- i915->dev_private->dev = i915;
-
- if (dofake) {
- i915->pdev = &fake;
- if (! find_idlist(i915, vendor, device))
- errx(1, "can't find fake device in pciidlist");
- } else {
- if (! pci_dev_find(i915))
- errx(1, "No VGA device of any kind found\n");
- }
-
- if (argc) {
- FILE *fd;
- int amt;
- /* size it later */
- bios_image = malloc(8*1048576);
- fd = fopen(argv[0], "r");
- amt = fread(bios_image, 65536, 128, fd);
- fclose(fd);
- if (amt < 1) {
- free(bios_image);
- } else {
- i915->bios_bin = bios_image;
- i915->dev_private->opregion.vbt = bios_image;
- bios_image_size = amt * 65536;
- }
- }
- /* get the base address for the mmio indirection registers -- BAR 2 */
- addrport = i915->pdev->base_addr[4] & ~3;
- dataport = addrport + 4;
- printf("Addrport is at %x, dataport at %x\n", addrport, dataport);
- /* get the base of the mmio space */
- mmiophys = i915->pdev->base_addr[0] & ~0xf;
- mmiosize = i915->pdev->size[0];
- printf("phys base is %#x, size %d\n", mmiophys, mmiosize);
- mapit();
- devinit();
- //hexdump(mmiobase, mmiosize);
- /* we should use ioperm but hey ... it's had troubles */
- iopl(3);
- intel_setup_bios(i915);
- if (i915->bios_bin)
- intel_parse_bios(i915);
-}
diff --git a/util/i915tool/pci.c b/util/i915tool/pci.c
deleted file mode 100644
index 5a0021c..0000000
--- a/util/i915tool/pci.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of i915tool
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "video.h"
-
-int find_idlist(struct drm_device *dev, u16 vendor, u16 device)
-{
- extern const struct pci_device_id pciidlist[];
- int succ = 0;
- int i;
- for(i = 0; pciidlist[i].vendor && !succ; i++){
- if (vendor == pciidlist[i].vendor && device ==
- pciidlist[i].device){
- dev->dev_private->info =
- (void *)(pciidlist[i].driver_data);
- succ = 1;
- }
- }
- return succ;
-}
-
-/* there's only going to be one device ... */
-int pci_dev_find(struct drm_device *dev)
-{
- struct pci_access *pacc = NULL;
- struct pci_dev *temp;
- int succ = 0;
- pacc = pci_alloc();
- if (! pacc)
- return 0;
- pci_init(pacc);
- pci_scan_bus(pacc);
-
- for (temp = pacc->devices; temp && ! dev->pdev; temp = temp->next){
- if ((temp->device_class & 0xff00) == PCI_CLASS_DISPLAY_VGA ) {
- pci_fill_info(temp, PCI_FILL_IDENT |
- PCI_FILL_BASES | PCI_FILL_CLASS);
- dev->pdev = temp;
- }
- }
-
- if (dev->pdev)
- succ = find_idlist(dev, dev->pdev->vendor_id,
- dev->pdev->device_id);
- return succ;
-}
-
-/* Support library for kernel style pci functions. We could do a semantic
- * patch for it but this is easier to debug as we can fill it with prints
- * if we want. And no cpp abuse here. Keep it simple.
- */
-
-void pci_read_config_byte(struct pci_dev *dev, unsigned long offset, u8 *val)
-{
- *val = pci_read_byte(dev, offset);
-}
-
-void pci_write_config_byte(struct pci_dev *dev, unsigned long offset, u8 val)
-{
- pci_write_byte(dev, offset, val);
-}
-
-void pci_read_config_word(struct pci_dev *dev, unsigned long offset, u16 *val)
-{
- *val = pci_read_word(dev, offset);
-}
-
-void pci_write_config_word(struct pci_dev *dev, unsigned long offset, u16 val)
-{
- pci_write_word(dev, offset, val);
-}
-
-void pci_read_config_dword(struct pci_dev *dev, unsigned long offset, u32 *val)
-{
- *val = pci_read_long(dev, offset);
-}
-
-void pci_write_config_dword(struct pci_dev *dev, unsigned long offset, u32 val)
-{
- pci_write_long(dev, offset, val);
-}
diff --git a/util/i915tool/plusplusplus b/util/i915tool/plusplusplus
deleted file mode 100644
index a5dcd19..0000000
--- a/util/i915tool/plusplusplus
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/bash
-sed 's,^\+\+\+.*,+++ '$2',' < $1 > $1.pat
-
diff --git a/util/i915tool/spatches/deldev.cocci b/util/i915tool/spatches/deldev.cocci
deleted file mode 100644
index 504dae7..0000000
--- a/util/i915tool/spatches/deldev.cocci
+++ /dev/null
@@ -1,29 +0,0 @@
-@@
-identifier dev;
-expression i;
-@@
--struct drm_i915_private *dev = i;
-+extern struct drm_device *i915; struct drm_i915_private *dev = i915->dev_private;
-@@
-identifier dev;
-expression i;
-@@
--struct pci_dev *dev = i;
-+extern struct drm_device *i915; struct pci_dev *dev = i915->pdev;
-@@
-@@
--#include "i915_drm.h"
-@@
-@@
--#include "drm.h"
-@@
-@@
--#include "drmP.h"
-@@
-@@
--#include "i915_trace.h"
-@@
-identifier d;
-@@
--(d)->pci_device
-+(d)->pdev->device_id
diff --git a/util/i915tool/spatches/drm_crtc.cocci b/util/i915tool/spatches/drm_crtc.cocci
deleted file mode 100644
index 662f253..0000000
--- a/util/i915tool/spatches/drm_crtc.cocci
+++ /dev/null
@@ -1,32 +0,0 @@
-@@
-identifier s;
-identifier head;
-@@
-struct s {...
-- struct list_head head;
-...};
-@@
-@@
--#include <...>
-@@
-@@
-(
--struct drm_crtc_funcs{...};
-|
--struct drm_crtc{...};
-|
--struct drm_connector_funcs{...};
-|
--struct drm_encoder_funcs{...};
-|
--struct drm_encoder{...};
-|
--struct drm_connector{...};
-|
--struct drm_mode_config_funcs{...};
-|
--struct drm_mode_config{...};
-|
--struct drm_framebuffer_funcs{...};
-)
-
diff --git a/util/i915tool/spatches/fixcalls.cocci b/util/i915tool/spatches/fixcalls.cocci
deleted file mode 100644
index 11cbe4a..0000000
--- a/util/i915tool/spatches/fixcalls.cocci
+++ /dev/null
@@ -1,148 +0,0 @@
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--vga_get_uninterruptible(...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--vga_put(...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--intel_init_quirks(...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--drm_mode_config_init(...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--INIT_WORK(...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--setup_timer(...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--DRM_DEBUG_KMS(
-+fprintf(stderr,
-...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--DRM_ERROR(
-+fprintf(stderr,
-...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--DRM_DEBUG(
-+fprintf(stderr,
-...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--DRM_DEBUG_DRIVER(
-+fprintf(stderr,
-...);
-...>}
-@@
-identifier f;
-type T;
-@@
-T f(...){<...
--intel_init_display(...);
-...>}
-@ rulekz @
-identifier t;
-identifier f;
-expression E1, E2;
-type T;
-@@
-T f(...){<...
-t = kzalloc(E1, E2);
-...>}
-@@
-identifier rulekz.f;
-expression E1, E2;
-@@
-
-- kzalloc(E1
-+ calloc(1, E1
-- ,E2
- )
-@@
-identifier d;
-@@
--static
-const struct pci_device_id d[] = {...};
-@@
-expression E1;
-@@
--WARN(
-+if (
-E1
--,
-+) fprintf(stderr,
-...);
-@@
-expression E1;
-@@
--BUG_ON(
-+assert(
-E1);
-@@
-@@
--jiffies
-+msecs()
-@@
-expression E1;
-@@
--jiffies_to_msecs(
-E1
--)
-@@
-expression E1;
-@@
--msecs_to_jiffies(
-E1
--)
-@@
-expression E1, E2;
-@@
--time_after(
-+(
-E1
--,
-+>
-E2)
diff --git a/util/i915tool/spatches/fx.cocci b/util/i915tool/spatches/fx.cocci
deleted file mode 100644
index 576cfcc..0000000
--- a/util/i915tool/spatches/fx.cocci
+++ /dev/null
@@ -1,10 +0,0 @@
-@@
-identifier f;
-type T;
-@@
-T f(...){...
--\(DRM_DEBUG_KMS|DRM_ERRRO\)(
-+fprintf(stderr,
-...);
-...}
-
diff --git a/util/i915tool/spatches/getdrmmodefn.cocci b/util/i915tool/spatches/getdrmmodefn.cocci
deleted file mode 100644
index d5cd17e..0000000
--- a/util/i915tool/spatches/getdrmmodefn.cocci
+++ /dev/null
@@ -1,6 +0,0 @@
-@@
-@@
-- drm_mode_set_name(...) {...}
-@@
-@@
-- drm_mode_debug_printmodeline(...) {...}
diff --git a/util/i915tool/spatches/getfn.cocci b/util/i915tool/spatches/getfn.cocci
deleted file mode 100644
index 8dea561..0000000
--- a/util/i915tool/spatches/getfn.cocci
+++ /dev/null
@@ -1,61 +0,0 @@
-@@
-@@
-- get_blocksize(...) {...}
-@@
-@@
-- lvds_dvo_timing_equal_size(...) {...}
-@@
-@@
-- fill_detail_timing_data(...) {...}
-@@
-@@
-- intel_setup_bios(...) {...}
-@@
-@@
-- intel_parse_bios(...){...}
-@@
-@@
-- init_vbt_defaults(...){...}
-@@
-@@
-- parse_general_features(...){...}
-@@
-@@
-- parse_general_definitions(...){...}
-@@
-@@
-- parse_lfp_panel_data(...){...}
-@@
-@@
-- parse_sdvo_panel_data(...){...}
-@@
-@@
-- parse_sdvo_device_mapping(...){...}
-@@
-@@
-- parse_device_mapping(...){...}
-@@
-@@
-- parse_driver_features(...){...}
-@@
-@@
-- parse_edp(...){...}
-@@
-@@
-- find_section(...){...}
-@@
-@@
-- get_lvds_dvo_timing(...){...}
-@@
-@@
-- intel_bios_ssc_frequency(...){...}
-@@
-identifier d;
-type T;
-@@
-- static T d;
-@@
-expression S;
-identifier d;
-@@
--#define d S
diff --git a/util/i915tool/spatches/i915_dma.c.cocci b/util/i915tool/spatches/i915_dma.c.cocci
deleted file mode 100644
index 0ae2d55..0000000
--- a/util/i915tool/spatches/i915_dma.c.cocci
+++ /dev/null
@@ -1,3 +0,0 @@
-@@
-@@
-- i915_driver_load(...) {...}
diff --git a/util/i915tool/spatches/i915_drv.c.cocci b/util/i915tool/spatches/i915_drv.c.cocci
deleted file mode 100644
index 0d64d93..0000000
--- a/util/i915tool/spatches/i915_drv.c.cocci
+++ /dev/null
@@ -1,8 +0,0 @@
-@inteldeviceinfo@
-identifier d;
-@@
--const struct intel_device_info d = {...};
-@@
-identifier d;
-@@
--static const struct pci_device_id d[] = {...};
diff --git a/util/i915tool/spatches/i915_drv.cocci b/util/i915tool/spatches/i915_drv.cocci
deleted file mode 100644
index 633e270..0000000
--- a/util/i915tool/spatches/i915_drv.cocci
+++ /dev/null
@@ -1,178 +0,0 @@
-@@
-identifier d;
-@@
-(
--struct drm_i915_fence_reg{...};
-|
--struct drm_i915_error_state{...};
-|
--struct drm_i915_gem_object{...};
-|
--struct drm_i915_display_funcs {...};
-|
--struct drm_i915_gem_phys_object{...};
-|
--struct mem_block{...};
-|
--struct drm_i915_gem_request{...};
-|
--struct drm_i915_file_private{...};
-|
--struct drm_i915_master_private{...};
-|
--struct intel_gmbus{...};
-|
--struct work_struct d;
-|
--struct mem_*d;
-|
--struct timer_list d;
-|
--struct intel_fbc_work *d;
-|
--struct drm_i915_error_state *d;
-|
--struct i2c_adapter d;
-|
--struct i2c_adapter *d;
-|
--struct intel_hw_status_page{...};
-|
--struct intel_hw_status_page d;
-)
-@@
-@@
--#include<...>
-@@
-identifier d;
-@@
-struct s {...
-- struct drm_i915_display_funcs d;
-...
-};
-@@
-identifier d;
-@@
-struct s {...
--struct notifier_block d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--spinlock_t d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--atomic_t d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--drm_dma_handle_t *d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--drm_local_map_t d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--spinlock_t *d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--struct i2c_adapter d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--struct i2c_adapter *d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
-(
--struct inteL_gmbus {...} *d;
-|
--struct drm_i915_gem_object *d;
-)
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--struct work_struct d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--struct resource d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--struct timer_list d;
-...
-};
-@@
-identifier s;
-identifier d;
-@@
-struct s {...
--wait_queue_head_t d;
-...
-};
-@@
-identifier s;
-identifier d;
-constant c;
-@@
-struct s {...
--struct intel_ring_buffer d[c];
-...
-};
-@@
-identifier s;
-identifier d;
-constant c;
-@@
-struct s {...
--struct drm_i915_fence_reg d[c];
-...
-};
-
diff --git a/util/i915tool/spatches/intel_bios.cocci b/util/i915tool/spatches/intel_bios.cocci
deleted file mode 100644
index 2e71363..0000000
--- a/util/i915tool/spatches/intel_bios.cocci
+++ /dev/null
@@ -1,7 +0,0 @@
-@@
-@@
--#include<...>
-+#include "video.h"
-@@
-@@
--#include"..."
diff --git a/util/i915tool/spatches/intel_display.c.cocci b/util/i915tool/spatches/intel_display.c.cocci
deleted file mode 100644
index 6e16bbd..0000000
--- a/util/i915tool/spatches/intel_display.c.cocci
+++ /dev/null
@@ -1,507 +0,0 @@
-@@
-@@
--struct intel_limit {... };
-@@
-identifier d;
-@@
-- intel_limit_t d = {...};
-@@
-@@
-- intel_connector_attach_encoder(...){...}
-@@
-@@
-- intel_modeset_cleanup(...){...}
-@@
-@@
-- intel_modeset_gem_init(...){...}
-@@
-@@
-- intel_modeset_init(...){...}
-@@
-@@
-- i915_disable_vga(...){...}
-@@
-@@
-- intel_init_quirks(...){...}
-@@
-@@
-- quirk_ssc_force_disable(...){...}
-@@
-@@
-- quirk_pipea_force (...){...}
-@@
-@@
-- intel_init_display(...){...}
-@@
-@@
-- intel_init_clock_gating(...){...}
-@@
-@@
-- ironlake_enable_rc6(...){...}
-@@
-@@
-- ironlake_disable_rc6(...){...}
-@@
-@@
-- ironlake_teardown_rc6(...){...}
-@@
-@@
-- cpt_init_clock_gating(...){...}
-@@
-@@
-- ibx_init_clock_gating(...){...}
-@@
-@@
-- i830_init_clock_gating(...){...}
-@@
-@@
-- i85x_init_clock_gating(...){...}
-@@
-@@
-- gen3_init_clock_gating(...){...}
-@@
-@@
-- broadwater_init_clock_gating(...){...}
-@@
-@@
-- crestline_init_clock_gating(...){...}
-@@
-@@
-- g4x_init_clock_gating(...){...}
-@@
-@@
-- ivybridge_init_clock_gating(...){...}
-@@
-@@
-- gen6_init_clock_gating(...){...}
-@@
-@@
-- ironlake_init_clock_gating(...){...}
-@@
-@@
-- gen6_update_ring_freq(...){...}
-@@
-@@
-- gen6_enable_rps(...){...}
-@@
-@@
-- intel_init_emon(...){...}
-@@
-@@
-- gen6_disable_rps(...){...}
-@@
-@@
-- gen6_set_rps(...){...}
-@@
-@@
-- ironlake_disable_drps(...){...}
-@@
-@@
-- ironlake_enable_drps(...){...}
-@@
-@@
-- intel_user_framebuffer_destroy(...){...}
-@@
-@@
-- intel_setup_outputs(...){...}
-@@
-@@
-- intel_crtc_init(...){...}
-@@
-@@
-- intel_crtc_reset(...){...}
-@@
-@@
-- intel_prepare_page_flip(...){...}
-@@
-@@
-- intel_finish_page_flip_plane(...){...}
-@@
-@@
-- intel_finish_page_flip(...){...}
-@@
-@@
-- intel_unpin_work_fn(...){...}
-@@
-@@
-- intel_crtc_destroy(...){...}
-@@
-@@
-- intel_mark_busy(...){...}
-@@
-@@
-- intel_idle_update(...){...}
-@@
-@@
-- intel_decrease_pllclock(...){...}
-@@
-@@
-- intel_increase_pllclock(...){...}
-@@
-@@
-- intel_crtc_idle_timer(...){...}
-@@
-@@
-- intel_gpu_idle_timer(...){...}
-@@
-@@
-- ivb_update_cursor(...){...}
-@@
-@@
-- i9xx_update_cursor(...){...}
-@@
-@@
-- i845_update_cursor(...){...}
-@@
-@@
-- intel_crtc_load_lut(...){...}
-@@
-@@
-- ironlake_update_pch_refclk(...){...}
-@@
-@@
-- intel_update_watermarks(...){...}
-@@
-@@
-- sandybridge_update_wm(...){...}
-@@
-@@
-- ironlake_update_wm(...){...}
-@@
-@@
-- i830_update_wm(...){...}
-@@
-@@
-- i9xx_update_wm(...){...}
-@@
-@@
-- i965_update_wm(...){...}
-@@
-@@
-- g4x_update_wm(...){...}
-@@
-@@
-- pineview_update_wm(...){...}
-@@
-@@
-- pineview_disable_cxsr(...){...}
-@@
-@@
-- intel_encoder_destroy(...){...}
-@@
-@@
-- intel_encoder_commit (...){...}
-@@
-@@
-- intel_encoder_prepare (...){...}
-@@
-@@
-- ironlake_crtc_commit(...){...}
-@@
-@@
-- ironlake_crtc_prepare(...){...}
-@@
-@@
-- i9xx_crtc_commit(...){...}
-@@
-@@
-- i9xx_crtc_prepare(...){...}
-@@
-@@
-- intel_crtc_disable(...){...}
-@@
-@@
-- intel_crtc_dpms(...){...}
-@@
-@@
-- i9xx_crtc_dpms(...){...}
-@@
-@@
-- i9xx_crtc_disable(...){...}
-@@
-@@
-- i9xx_crtc_enable(...){...}
-@@
-@@
-- intel_crtc_dpms_overlay(...){...}
-@@
-@@
-- ironlake_crtc_dpms(...){...}
-@@
-@@
-- ironlake_crtc_disable(...){...}
-@@
-@@
-- ironlake_crtc_enable(...){...}
-@@
-@@
-- intel_cpt_verify_modeset(...){...}
-@@
-@@
-- ironlake_pch_enable(...){...}
-@@
-@@
-- intel_crtc_wait_for_pending_flips(...){...}
-@@
-@@
-- intel_clear_scanline_wait(...){...}
-@@
-@@
-- ironlake_fdi_disable(...){...}
-@@
-@@
-- cpt_phase_pointer_disable(...){...}
-@@
-@@
-- ironlake_fdi_pll_enable(...){...}
-@@
-@@
-- ivb_manual_fdi_link_train(...){...}
-@@
-@@
-- gen6_fdi_link_train(...){...}
-@@
-@@
-- ironlake_fdi_link_train(...){...}
-@@
-@@
-- cpt_phase_pointer_enable(...){...}
-@@
-@@
-- intel_fdi_normal_train(...){...}
-@@
-@@
-- ironlake_set_pll_edp(...){...}
-@@
-@@
-- intel_update_fbc(...){...}
-@@
-@@
-- intel_disable_fbc(...){...}
-@@
-@@
-- intel_enable_fbc(...){...}
-@@
-@@
-- intel_cancel_fbc_work(...){...}
-@@
-@@
-- intel_fbc_work_fn(...){...}
-@@
-@@
-- ironlake_disable_fbc(...){...}
-@@
-@@
-- ironlake_enable_fbc(...){...}
-@@
-@@
-- sandybridge_blit_fbc_update(...){...}
-@@
-@@
-- g4x_disable_fbc(...){...}
-@@
-@@
-- g4x_enable_fbc(...){...}
-@@
-@@
-- i8xx_enable_fbc(...){...}
-@@
-@@
-- i8xx_disable_fbc(...){...}
-@@
-@@
-- intel_disable_pll(...){...}
-@@
-@@
-- intel_enable_pll(...){...}
-@@
-@@
-- intel_clock(...){...}
-@@
-@@
-- pineview_clock(...){...}
-@@
-@@
-- intel_ironlake_limit(...){...}
-@@
-@@
-- intel_g4x_limit(...){...}
-@@
-@@
-- intel_limit(...){...}
-@@
-@@
-- intel_pipe_has_type(...){...}
-@@
-@@
-- intel_PLL_is_valid(...){...}
-@@
-@@
-- intel_find_best_PLL(...){...}
-@@
-@@
-- intel_g4x_find_best_PLL(...){...}
-@@
-@@
-- intel_find_pll_ironlake_dp(...){...}
-@@
-@@
-- intel_fbc_enabled(...){...}
-@@
-@@
-- intel_pin_and_fence_fb_obj(...){...}
-@@
-@@
-- i9xx_update_plane(...){...}
-@@
-@@
-- ironlake_update_plane(...){...}
-@@
-@@
-- intel_pipe_set_base_atomic(...){...}
-@@
-@@
-- intel_pipe_set_base(...){...}
-@@
-@@
-- intel_crtc_driving_pch(...){...}
-@@
-@@
-- intel_crtc_mode_fixup(...){...}
-@@
-@@
-- single_enabled_crtc(...){...}
-@@
-@@
-- g4x_compute_wm0(...){...}
-@@
-@@
-- g4x_compute_srwm(...){...}
-@@
-@@
-- ironlake_compute_srwm(...){...}
-@@
-@@
-- intel_panel_use_ssc(...){...}
-@@
-@@
-- intel_choose_pipe_bpp_dither(...){...}
-@@
-@@
-- i9xx_crtc_mode_set(...){...}
-@@
-@@
-- ironlake_crtc_mode_set(...){...}
-@@
-@@
-- intel_crtc_mode_set(...){...}
-@@
-@@
-- intel_crtc_update_cursor(...){...}
-@@
-@@
-- intel_crtc_cursor_set(...){...}
-@@
-@@
-- intel_crtc_cursor_move(...){...}
-@@
-@@
-- intel_crtc_fb_gamma_set(...){...}
-@@
-@@
-- intel_crtc_fb_gamma_get(...){...}
-@@
-@@
-- intel_crtc_gamma_set(...){...}
-@@
-@@
-- intel_framebuffer_create(...){...}
-@@
-@@
-- intel_framebuffer_size_for_mode(...){...}
-@@
-@@
-- intel_framebuffer_create_for_mode(...){...}
-@@
-@@
-- mode_fits_in_fbdev(...){...}
-@@
-@@
-- intel_get_load_detect_pipe(...){...}
-@@
-@@
-- intel_release_load_detect_pipe(...){...}
-@@
-@@
-- intel_crtc_clock_get(...){...}
-@@
-@@
-- intel_crtc_mode_get(...){...}
-@@
-@@
-- do_intel_finish_page_flip(...){...}
-@@
-@@
-- intel_gen2_queue_flip(...){...}
-@@
-@@
-- intel_gen3_queue_flip(...){...}
-@@
-@@
-- intel_gen4_queue_flip(...){...}
-@@
-@@
-- intel_gen6_queue_flip(...){...}
-@@
-@@
-- intel_gen7_queue_flip(...){...}
-@@
-@@
-- intel_default_queue_flip(...){...}
-@@
-@@
-- intel_crtc_page_flip(...){...}
-@@
-@@
-- intel_get_pipe_from_crtc_id(...){...}
-@@
-@@
-- intel_encoder_clones(...){...}
-@@
-@@
-- intel_user_framebuffer_create_handle(...){...}
-@@
-@@
-- intel_framebuffer_init(...){...}
-@@
-@@
-- intel_user_framebuffer_create(...){...}
-@@
-@@
-- intel_alloc_context_page(...){...}
-@@
-@@
-- ironlake_setup_rc6(...){...}
-@@
-@@
-- intel_best_encoder(...){...}
-@@
-identifier d;
-@@
-- struct drm_framebuffer_funcs d = {...};
-@@
-identifier d;
-@@
-- struct drm_mode_config_funcs d = {...};
-@@
-identifier d;
-@@
--static struct drm_crtc_helper_funcs d = {...};
-@@
-identifier d;
-@@
--static struct drm_crtc_funcs d = {...};
-@@
-identifier d;
-@@
-- struct intel_quirk d[] = {...};
diff --git a/util/i915tool/spatches/removeinclude.cocci b/util/i915tool/spatches/removeinclude.cocci
deleted file mode 100644
index ff1bfea..0000000
--- a/util/i915tool/spatches/removeinclude.cocci
+++ /dev/null
@@ -1,6 +0,0 @@
-@@
-@@
--#include<...>
-@@
-@@
--#include"..."
diff --git a/util/i915tool/spatches/ringbuffer.cocci b/util/i915tool/spatches/ringbuffer.cocci
deleted file mode 100644
index 68f0c98..0000000
--- a/util/i915tool/spatches/ringbuffer.cocci
+++ /dev/null
@@ -1,14 +0,0 @@
-@@
-identifier d;
-type T;
-@@
--T d(...){...}
-@@
-identifier d;
-type T;
-@@
--T d(...);
-@@
-identifier d;
-@@
--struct d{...};
diff --git a/util/i915tool/transform b/util/i915tool/transform
deleted file mode 100644
index 3e191cb..0000000
--- a/util/i915tool/transform
+++ /dev/null
@@ -1,151 +0,0 @@
-#!/bin/bash
-# This script has been honed over quite a few iterations. The trick is to make
-# it easy for you to see what transformations occur
-# without burying you in files.
-# Also, coccinelle is not perfect, so we have to help her at times. As she
-# gets smarter, we can shrink thigns we do in here.
-# So we get input files, then do per-file changes, then do all-file changes
-# I've deliberately made this script simple. Please don't decide it needs to
-# be automagic. Just let it work in its simple way. Also, if you change even
-# one simple thing, ALWAYS rerun this script do make sure you did not make a
-# global test. NEVER test one little thing in isolation. That way
-# lies madness.
-# The only thing you need to set is
-# export LINUX=/path/to/your/linux/tree.
-# Order in which we do things.
-# 1. Get source files into inputs.
-# 2. cp them to per-file-changes
-# Note that we even copy ones that might not currently need per-file
-# changes. Because they may in future and it keeps the script simple.
-# We tried both ways and like this best.
-# 3. run 'ed' across a few files that need it
-# 4. run coccinelle with any per-file changes
-# There is some ugliness here as we have to do a reverse patch step. Sorry.
-# 5. cp per-file-changes/* to final
-# 6. run coccinelle files that apply to more than one file
-# it's best to run coccinelle on as many files as possible, she's pretty
-# smart about
-# certain transformations, e.g. if you remove a function definition she can
-# remove all calls to that function (usually)
-#
-# Now you can
-# make (will build all working tools)
-# or
-# make broken
-# for things that don't build yet.
-
-# Step 1
-rm inputs/* per-file-changes/* final/* tmp/*
-cp $LINUX/drivers/gpu/drm/i915/i915_reg.h inputs
-cp $LINUX/drivers/gpu/drm/i915/i915_drv.? inputs
-cp $LINUX/drivers/gpu/drm/i915/intel_display.c inputs
-cp $LINUX/drivers/gpu/drm/i915/intel_bios.c inputs
-cp $LINUX/drivers/gpu/drm/i915/intel_bios.h inputs
-cp $LINUX/drivers/gpu/drm/i915/intel_ringbuffer.h inputs
-cp $LINUX/drivers/gpu/drm/i915/i915_dma.c inputs
-cp $LINUX/include/drm/drm_crtc.h inputs
-cp $LINUX/include/drm/drm_mode.h inputs
-cp $LINUX/include/drm/drm_dp_helper.h inputs
-cp $LINUX/drivers/gpu/drm/drm_modes.c inputs
-
-# Step 2
-cp inputs/* per-file-changes
-
-# Step 3
-# We tried sed but it had some issues that ed did not
-# coccinelle can't handle anonymous structs
-# also some stuff is easier with ed.
-# also there are bugs spatches/in coccinelle it seems :-(
-# the literal deletes below suck and we need to figure
-# out wtf went wrong.
-ed per-file-changes/i915_drv.h << EOF
-/intel_gtt/
-.
-?struct *{?,/mm;/d
-.
-/i915_trace.h/
-.
-.,/#define POSTING_READ16/d
-/struct *intel_gmbus/
-.,/\*gmb/d
-.
-g/notifier_block/d
-g/struct *drm_i915_display_funcs *display;/d
-g/struct *completion *[a-z].*;/d
-w
-q
-EOF
-
-ed per-file-changes/drm_crtc.h <<EOF
-/drm_crtc_init/,/endif/-d
-w
-q
-EOF
-
-ed per-file-changes/intel_display.c << EOF
-g/mode_config.funcs *=/d
-g/fb_base/d
-g/const/s///
-w
-q
-EOF
-
-# Reverse patches. We hope these will go away someday.
->per-file-changes/intel_bios.c
-spatch -sp_file spatches/getfn.cocci inputs/intel_bios.c -U 0 > tmp/res
-./plusplusplus tmp/res per-file-changes/intel_bios.c
-(cd per-file-changes/; patch -p1 -R ) < tmp/res.pat
-
->per-file-changes/drm_modes.c
-spatch -sp_file spatches/getdrmmodefn.cocci inputs/drm_modes.c -U 0 \
- > tmp/drm_modes
-./plusplusplus tmp/drm_modes per-file-changes/drm_modes.c
-(cd per-file-changes/; patch -p1 -R ) < tmp/drm_modes.pat
-
-spatch -sp_file spatches/i915_dma.c.cocci inputs/i915_dma.c -U 0 \
- > tmp/i915_dma.c.patch
-./plusplusplus tmp/i915_dma.c.patch per-file-changes/i915_dma.c
-# This is the only way I can make sure the right file gets patched!
-# someone tell me why. It keeps picking the wrong one.
-(cd per-file-changes/; patch -p1 -R ) < tmp/i915_dma.c.patch.pat
-spatch --in-place -sp_file spatches/fixcalls.cocci per-file-changes/i915_dma.c
-#patch -p0 -R < tmp/i915_dma.c.patch.pat
-
-#echo '#include "video.h"'
->per-file-changes/i915_drv.c
-spatch -sp_file spatches/i915_drv.c.cocci inputs/i915_drv.c -U 0 \
- > tmp/i915_drv.c.patch
-./plusplusplus tmp/i915_drv.c.patch per-file-changes/i915_drv.c
-# This is the only way I can make sure the right file gets patched!
-# someone tell me why. It keeps picking the wrong one.
-(cd per-file-changes/; patch -p1 -R ) < tmp/i915_drv.c.patch.pat
-spatch --in-place -sp_file spatches/fixcalls.cocci per-file-changes/i915_drv.c
-
-# Finally, a basic spatch sequence!
-
-spatch --in-place -sp_file \
- spatches/intel_display.c.cocci per-file-changes/intel_display.c \
- > /dev/null
-
-spatch --in-place -sp_file spatches/i915_drv.cocci \
- per-file-changes/i915_drv.h >/dev/null
-
-# Now do the common changes to all files.
-cp per-file-changes/* final
-spatch --in-place -sp_file spatches/ringbuffer.cocci \
- final/intel_ringbuffer.h >/dev/null
-spatch --in-place -sp_file spatches/removeinclude.cocci \
- final/intel_display.c > /dev/null
-spatch --in-place -sp_file spatches/fixcalls.cocci final/intel_display.c \
- >/dev/null
-spatch --in-place -sp_file spatches/ringbuffer.cocci final/drm_dp_helper.h\
- >/dev/null
-spatch --in-place -sp_file spatches/removeinclude.cocci final/drm_dp_helper.h\
- >/dev/null
-spatch --in-place -sp_file spatches/i915_drv.cocci final/intel_ringbuffer.h\
- >/dev/null
-spatch --in-place -sp_file spatches/deldev.cocci final/intel_bios.c \
- final/intel_bios.h final/i915_drv.h final/intel_ringbuffer.h>/dev/null
-spatch --in-place -sp_file spatches/fixcalls.cocci final/intel_bios.c \
- >/dev/null
-spatch --in-place -sp_file spatches/drm_crtc.cocci final/drm_crtc.h >/dev/null
diff --git a/util/i915tool/video.h b/util/i915tool/video.h
deleted file mode 100644
index 6919830..0000000
--- a/util/i915tool/video.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* cocci issues ;-( */
-#ifndef VIDEO_H
-#define VIDEO_H 1
-#include <stdio.h>
-#include <stdlib.h>
-#include <assert.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/mman.h>
-#include <fcntl.h>
-#include <string.h>
-#include <pci/pci.h>
-#include <sys/io.h>
-#include <sys/time.h>
-#include <linux/types.h>
-/* stuff we can't get coccinelle to do yet */
-#define __iomem
-#define __read_mostly
-#define __always_unused
-#define module_param_named(a, b, c, d)
-#define MODULE_PARM_DESC(a, b)
-#define DRM_DEBUG_KMS printf
-#define CONFIG_DRM_I915_KMS 1
-#define module_init(x);
-#define module_exit(x);
-
-#define MODULE_AUTHOR(x)
-#define MODULE_DESCRIPTION(x)
-#define MODULE_LICENSE(a)
-#define MODULE_DEVICE_TABLE(a, b)
-
-/* constants that will never change from linux/vga.h */
-/* Legacy VGA regions */
-#define VGA_RSRC_NONE 0x00
-#define VGA_RSRC_LEGACY_IO 0x01
-#define VGA_RSRC_LEGACY_MEM 0x02
-#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
-/* Non-legacy access */
-#define VGA_RSRC_NORMAL_IO 0x04
-#define VGA_RSRC_NORMAL_MEM 0x08
-
-
-/* define in pci.h! */
-#include <pci/pci.h>
-/* idiocy. how many names to we need for a type? */
-typedef u32 uint32_t;
-typedef u64 uint64_t;
-/* WTF */
-typedef int bool;
-enum {false = 0, true};
-
-/* we define our own. The kernel one is too full of stuff. */
-struct mode_config {
- int num_fb;
- int num_connector;
- int num_crtc;
- int num_encoder;
- int min_width, min_height, max_width, max_height;
-};
-
-struct drm_device {
- struct pci_dev *pdev;
- u8 *bios_bin;
- struct drm_i915_private *dev_private;
- struct mode_config mode_config;
-};
-
-/* we're willing to define our own here because it's relatively unchanging */
-#define PCI_ANY_ID (~0)
-
-struct pci_device_id {
- u32 vendor, device; /* Vendor and device ID or PCI_ANY_ID*/
- u32 subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
- u32 class, class_mask; /* (class,subclass,prog-if) triplet */
- unsigned long driver_data; /* Data private to the driver */
-};
-
-
-/* per the cocinelle people, they can't handle this.
- * It also almost never changes */
-#define INTEL_VGA_DEVICE(id, info) { \
- .class = PCI_CLASS_DISPLAY_VGA << 8, \
- .class_mask = 0xff0000, \
- .vendor = 0x8086, \
- .device = id, \
- .subvendor = PCI_ANY_ID, \
- .subdevice = PCI_ANY_ID, \
- .driver_data = (unsigned long) info }
-
-#define wait_for(condition, time) (sleep(1+time/50) && (!condition))
-
-
-/* random crap from kernel.h.
- * Kernel.h is a catch-all for all kinds of junk and it's
- * not worth using coccinelle (yet) to pull it apart. Maybe later.
- * And, yes, gcc still does not have nelem!
- */
-#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
-#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
-#define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask))
-#define ALIGN(x, a) __ALIGN_KERNEL((x), (a))
-#define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask))
-#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
-#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
-
-
-/* temporary. */
-void *dmi_check_system(unsigned long);
-
-#include "final/drm_dp_helper.h"
-#include "final/i915_reg.h"
-#include "final/i915_drv.h"
-#include "final/drm_mode.h"
-#include "final/drm_crtc.h"
-
-unsigned long I915_READ(unsigned long addr);
-void I915_WRITE(unsigned long addr, unsigned long val);
-u16 I915_READ16(unsigned long addr);
-void I915_WRITE16(unsigned long addr, u16 val);
-unsigned long msecs(void);
-void mdelay(unsigned long ms);
-
-/* these should be the same. */
-#define POSTING_READ I915_READ
-#define POSTING_READ16 I915_READ16
-
-void *pci_map_rom(struct pci_dev *dev, size_t *size);
-void *pci_unmap_rom(struct pci_dev *dev, void *p);
-extern unsigned int i915_lvds_downclock;
-extern int i915_vbt_sdvo_panel_type;
-unsigned long lvds_do_not_use_alternate_frequency;
-#endif /* VIDEO_H */
1
0
New patch to review for coreboot: 4c97ed2 vboot2: Replace hard coded 'fallback' prefix with Kconfig variable
by Patrick Georgi 05 May '15
by Patrick Georgi 05 May '15
05 May '15
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10113
-gerrit
commit 4c97ed2eda6f5a3c45eb733891be0042f5a39bd9
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue May 5 22:47:00 2015 +0200
vboot2: Replace hard coded 'fallback' prefix with Kconfig variable
Change-Id: I9cbdf06f4d0956b5374915f8af7501c6f75b4687
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/vendorcode/google/chromeos/vboot2/Makefile.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index bc0ab6b..6ec352f 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -74,9 +74,9 @@ libverstage-srcs += $(VB2_LIB)
ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/verstage
-fallback/verstage-file = $(objcbfs)/verstage.elf
-fallback/verstage-type = stage
-fallback/verstage-compression = none
+$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/verstage-file = $(objcbfs)/verstage.elf
+$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/verstage-type = stage
+$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/verstage-compression = none
else
ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y)
bootblock-srcs += $(objgenerated)/libverstage.a
1
0
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10059
-gerrit
commit 85a1a75906db4137265e79cfc170a0e1bbd1e08b
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri May 1 16:48:54 2015 -0500
vboot checkopoint
Change-Id: I2a43c8a2f8f0626a7635150aa3efc44329a477d9
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/arch/arm/Makefile.inc | 9 +-
src/arch/arm64/Makefile.inc | 5 +-
src/include/program_loading.h | 1 +
src/lib/Makefile.inc | 1 +
src/lib/loaders/Makefile.inc | 1 +
src/lib/loaders/load_and_run_payload.c | 4 +-
src/lib/loaders/load_and_run_ramstage.c | 7 +-
src/lib/loaders/load_and_run_romstage.c | 7 +
src/vendorcode/google/chromeos/chromeos.c | 19 +-
src/vendorcode/google/chromeos/vboot2/Kconfig | 8 +-
src/vendorcode/google/chromeos/vboot2/Makefile.inc | 22 +-
src/vendorcode/google/chromeos/vboot2/common.c | 33 ---
src/vendorcode/google/chromeos/vboot2/misc.h | 3 +-
.../google/chromeos/vboot2/vboot_handoff.c | 53 ++---
.../google/chromeos/vboot2/vboot_loader.c | 243 +++++++++++++++++++++
src/vendorcode/google/chromeos/vboot2/verstub.c | 107 ---------
16 files changed, 321 insertions(+), 202 deletions(-)
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index c05b33e..6e52def 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -61,9 +61,9 @@ bootblock-y += memmove.S
bootblock-y += div0.c
bootblock-y += clock.c
-$(objcbfs)/bootblock.debug: $$(bootblock-objs) $$(VERSTAGE_LIB)
+$(objcbfs)/bootblock.debug: $$(bootblock-objs) $(objgenerated)/libverstage.a
@printf " LINK $(subst $(obj)/,,$(@))\n"
- $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group
+ $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) $(objgenerated)/libverstage.a --end-group
endif # CONFIG_ARCH_BOOTBLOCK_ARM
@@ -73,10 +73,11 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM
ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y)
-$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
- $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(objgenerated)/libverstage.a $$(verstage-objs) --end-group
+ $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group
+verstage-y += boot.c
verstage-y += div0.c
verstage-y += eabi_compat.c
verstage-y += memset.S
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index 3791ae7..095457e 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -84,11 +84,12 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM64
ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y)
-$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h
+$(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(libverstage-objs) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h
@printf " LINK $(subst $(obj)/,,$(@))\n"
- $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(verstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
+ $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(objgenerated)/libverstage.a $$(libverstage-objs)--end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld
verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
+verstage-y += boot.c
verstage-y += div0.c
verstage-y += eabi_compat.c
verstage-y += ../../lib/memset.c
diff --git a/src/include/program_loading.h b/src/include/program_loading.h
index ca80b0e..5fc0fd6 100644
--- a/src/include/program_loading.h
+++ b/src/include/program_loading.h
@@ -39,6 +39,7 @@ struct buffer_area {
};
enum prog_type {
+ PROG_VERSTAGE,
PROG_ROMSTAGE,
PROG_RAMSTAGE,
PROG_PAYLOAD,
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index ef4e2aa..b50e3aa 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -34,6 +34,7 @@ verstage-y += prog_ops.c
verstage-y += delay.c
verstage-y += cbfs.c
verstage-y += cbfs_core.c
+verstage-y += halt.c
verstage-y += memcmp.c
verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc
index fbc7f87..6b22801 100644
--- a/src/lib/loaders/Makefile.inc
+++ b/src/lib/loaders/Makefile.inc
@@ -23,3 +23,4 @@ romstage-y += cbfs_ramstage_loader.c
romstage-y += load_and_run_ramstage.c
ramstage-y += cbfs_payload_loader.c
ramstage-y += load_and_run_payload.c
+verstage-y += load_and_run_romstage.c
diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c
index 7a08097..4928e0c 100644
--- a/src/lib/loaders/load_and_run_payload.c
+++ b/src/lib/loaders/load_and_run_payload.c
@@ -27,12 +27,12 @@
#include <symbols.h>
#include <timestamp.h>
-extern const struct prog_loader_ops vboot_payload_loader;
+extern const struct prog_loader_ops vboot_loader;
extern const struct prog_loader_ops cbfs_payload_loader;
static const struct prog_loader_ops *payload_ops[] = {
#if CONFIG_VBOOT_VERIFY_FIRMWARE
- &vboot_payload_loader,
+ &vboot_loader,
#endif
&cbfs_payload_loader,
};
diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c
index fddea4d..af8667a 100644
--- a/src/lib/loaders/load_and_run_ramstage.c
+++ b/src/lib/loaders/load_and_run_ramstage.c
@@ -23,17 +23,20 @@
#include <cbfs.h>
#include <program_loading.h>
#include <romstage_handoff.h>
+#include <rules.h>
#include <stage_cache.h>
#include <timestamp.h>
extern const struct prog_loader_ops cbfs_ramstage_loader;
-extern const struct prog_loader_ops vboot_ramstage_loader;
+extern const struct prog_loader_ops vboot_loader;
static const struct prog_loader_ops *loaders[] = {
#if CONFIG_VBOOT_VERIFY_FIRMWARE
- &vboot_ramstage_loader,
+ &vboot_loader,
#endif
+#if !ENV_VERSTAGE
&cbfs_ramstage_loader,
+#endif
};
void __attribute__((weak)) stage_cache_add(int stage_id, struct prog *stage) {}
diff --git a/src/lib/loaders/load_and_run_romstage.c b/src/lib/loaders/load_and_run_romstage.c
index b54bfc7..25a75bd 100644
--- a/src/lib/loaders/load_and_run_romstage.c
+++ b/src/lib/loaders/load_and_run_romstage.c
@@ -24,12 +24,19 @@
#include <cbfs.h>
#include <halt.h>
#include <program_loading.h>
+#include <rules.h>
#include <timestamp.h>
extern const struct prog_loader_ops cbfs_romstage_loader;
+extern const struct prog_loader_ops vboot_loader;
static const struct prog_loader_ops *loaders[] = {
+#if CONFIG_VBOOT_VERIFY_FIRMWARE
+ &vboot_loader,
+#endif
+#if !ENV_VERSTAGE
&cbfs_romstage_loader,
+#endif
};
void run_romstage(void)
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index fb72673..1e49bd1 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -26,7 +26,7 @@
#include <console/console.h>
#include "vboot_handoff.h"
-int vboot_skip_display_init(void)
+static int vboot_handoff_flag(uint32_t flag)
{
struct vboot_handoff *vbho;
@@ -35,7 +35,22 @@ int vboot_skip_display_init(void)
if (vbho == NULL)
return 0;
- return !(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DISPLAY);
+ return !!(vbho->init_params.out_flags & flag);
+}
+
+int vboot_skip_display_init(void)
+{
+ return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
+}
+
+int vboot_enable_developer(void)
+{
+ return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
+}
+
+int vboot_enable_recovery(void)
+{
+ return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
}
int __attribute__((weak)) clear_recovery_mode_switch(void)
diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig
index 8396113..bb6c1ad 100644
--- a/src/vendorcode/google/chromeos/vboot2/Kconfig
+++ b/src/vendorcode/google/chromeos/vboot2/Kconfig
@@ -17,14 +17,14 @@
##
config VBOOT_STARTS_IN_BOOTBLOCK
- bool
+ bool "Vboot starts verifying in bootblock"
default n
depends on VBOOT_VERIFY_FIRMWARE
help
Firmware verification happens during or at the end of bootblock.
config VBOOT_STARTS_IN_ROMSTAGE
- bool
+ bool "Vboot starts verifying in romstage"
default n
depends on VBOOT_VERIFY_FIRMWARE && !VBOOT_STARTS_IN_BOOTBLOCK
help
@@ -51,12 +51,12 @@ config VBOOT_DISABLE_DEV_ON_RECOVERY
handy on embedded devices with limited input capabilities.
config SEPARATE_VERSTAGE
- bool
+ bool "Vboot verification is built into a separate stage"
default n
depends on VBOOT_VERIFY_FIRMWARE
config RETURN_FROM_VERSTAGE
- bool
+ bool "The separate verification stage returns to its caller"
default n
depends on SEPARATE_VERSTAGE
help
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index def43ad..bc0ab6b 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -20,13 +20,16 @@
libverstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__
verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__
+bootblock-y += vboot_loader.c
+romstage-y += vboot_loader.c
+ramstage-y += vboot_loader.c
+verstage-y += vboot_loader.c
+
bootblock-y += ../vboot_common.c
verstage-y += ../vboot_common.c
romstage-y += ../vboot_common.c
ramstage-y += ../vboot_common.c
-bootblock-y += verstub.c
-libverstage-y += verstub.c
bootblock-y += common.c
libverstage-y += verstage.c
verstage-y += common.c
@@ -37,9 +40,20 @@ libverstage-y += antirollback.c
endif
romstage-y += vboot_handoff.c common.c
+ramstage-y += common.c
+
verstage-y += verstage.ld
-VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y))
+ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
+VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y))
+else
+ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y)
+VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-bootblock-y))
+else
+VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-romstage-y))
+endif
+endif # CONFIG_SEPARATE_VERSTAGE
+
VB2_LIB = $(obj)/external/vboot_reference/vboot_fw20.a
VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CPPFLAGS_verstage)))
VBOOT_CFLAGS += $(libverstage-c-ccopts)
@@ -64,7 +78,7 @@ fallback/verstage-file = $(objcbfs)/verstage.elf
fallback/verstage-type = stage
fallback/verstage-compression = none
else
-ifeq ($(VBOOT_STARTS_IN_BOOTBLOCK),y)
+ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y)
bootblock-srcs += $(objgenerated)/libverstage.a
else
romstage-srcs += $(objgenerated)/libverstage.a
diff --git a/src/vendorcode/google/chromeos/vboot2/common.c b/src/vendorcode/google/chromeos/vboot2/common.c
index d70a108..beffebe 100644
--- a/src/vendorcode/google/chromeos/vboot2/common.c
+++ b/src/vendorcode/google/chromeos/vboot2/common.c
@@ -25,39 +25,6 @@
#include "../vboot_handoff.h"
#include "misc.h"
-void *vboot_load_stage(int stage_index,
- struct vboot_region *fw_main,
- struct vboot_components *fw_info)
-{
- struct cbfs_media default_media, *media = &default_media;
- uintptr_t fc_addr;
- uint32_t fc_size;
- void *entry;
-
- if (stage_index >= fw_info->num_components) {
- printk(BIOS_INFO, "invalid stage index\n");
- return NULL;
- }
-
- fc_addr = fw_main->offset_addr + fw_info->entries[stage_index].offset;
- fc_size = fw_info->entries[stage_index].size;
- if (fc_size == 0 ||
- fc_addr + fc_size > fw_main->offset_addr + fw_main->size) {
- printk(BIOS_INFO, "invalid stage address or size\n");
- return NULL;
- }
-
- init_default_cbfs_media(media);
-
- /* we're making cbfs access offset outside of the region managed by
- * cbfs. this works because cbfs_load_stage_by_offset does not check
- * the offset. */
- entry = cbfs_load_stage_by_offset(media, fc_addr);
- if (entry == (void *)-1)
- entry = NULL;
- return entry;
-}
-
struct vb2_working_data * const vboot_get_working_data(void)
{
return (struct vb2_working_data *)_vboot2_work;
diff --git a/src/vendorcode/google/chromeos/vboot2/misc.h b/src/vendorcode/google/chromeos/vboot2/misc.h
index 7425082..d942d56 100644
--- a/src/vendorcode/google/chromeos/vboot2/misc.h
+++ b/src/vendorcode/google/chromeos/vboot2/misc.h
@@ -22,8 +22,7 @@
#include "../vboot_common.h"
-void *vboot2_verify_firmware(void);
-void *vboot2_load_ramstage(void);
+void vboot_fill_handoff(void);
void verstage_main(void);
void *vboot_load_stage(int stage_index,
struct vboot_region *fw_main,
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
index b84e47e..16261b4 100644
--- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c
@@ -36,30 +36,6 @@
#include "../vboot_handoff.h"
#include "misc.h"
-static void *load_ramstage(struct vboot_handoff *vboot_handoff,
- struct vboot_region *fw_main)
-{
- struct vboot_components *fw_info;
- void *ret;
- int i;
-
- fw_info = vboot_locate_components(fw_main);
- if (fw_info == NULL)
- die("failed to locate firmware components\n");
-
- /* these offset & size are used to load a rw boot loader */
- for (i = 0; i < fw_info->num_components; i++) {
- vboot_handoff->components[i].address =
- fw_main->offset_addr + fw_info->entries[i].offset;
- vboot_handoff->components[i].size = fw_info->entries[i].size;
- }
-
- timestamp_add_now(TS_START_COPYRAM);
- ret = vboot_load_stage(CONFIG_VBOOT_RAMSTAGE_INDEX, fw_main, fw_info);
- timestamp_add_now(TS_END_COPYRAM);
- return ret;
-}
-
/**
* Sets vboot_handoff based on the information in vb2_shared_data
*
@@ -146,14 +122,13 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff,
vb_sd->recovery_reason = vb2_sd->recovery_reason;
}
-/**
- * Load ramstage and return the entry point
- */
-void *vboot2_load_ramstage(void)
+void vboot_fill_handoff(void)
{
+ int i;
struct vboot_handoff *vh;
struct vb2_shared_data *sd;
struct vboot_region fw_main;
+ struct vboot_components *fw_info;
struct vb2_working_data *wd = vboot_get_working_data();
sd = vboot_get_work_buffer(wd);
@@ -172,17 +147,15 @@ void *vboot2_load_ramstage(void)
/* needed until we finish transtion to vboot2 for kernel verification */
fill_vboot_handoff(vh, sd);
- if (vboot_is_readonly_path(wd))
- /* we're on recovery path. continue to ro-ramstage. */
- return NULL;
-
- if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) {
- return cbfs_load_stage(CBFS_DEFAULT_MEDIA,
- CONFIG_CBFS_PREFIX "/ramstage");
- } else {
- printk(BIOS_INFO, "loading ramstage from Slot %c\n",
- sd->fw_slot ? 'B' : 'A');
- vb2_get_selected_region(wd, &fw_main);
- return load_ramstage(vh, &fw_main);
+ vb2_get_selected_region(wd, &fw_main);
+ fw_info = vboot_locate_components(&fw_main);
+ if (fw_info == NULL)
+ die("failed to locate firmware components\n");
+
+ /* these offset & size are used to load a rw boot loader */
+ for (i = 0; i < fw_info->num_components; i++) {
+ vh->components[i].address =
+ fw_main.offset_addr + fw_info->entries[i].offset;
+ vh->components[i].size = fw_info->entries[i].size;
}
}
diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
new file mode 100644
index 0000000..c731abb
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c
@@ -0,0 +1,243 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <rules.h>
+#include <string.h>
+#include "misc.h"
+#include "../symbols.h"
+
+/* The stage loading code is compiled and entered from mutilple stages. The
+ * helper functions below attempt to provde more clarity on when certain
+ * code should be called. */
+
+static int verification_should_run(void)
+{
+ if (ENV_VERSTAGE && IS_ENABLED(CONFIG_SEPARATE_VERSTAGE))
+ return 1;
+
+ if (!IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) {
+ if (ENV_ROMSTAGE &&
+ IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE))
+ return 1;
+ if (ENV_BOOTBLOCK &&
+ IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
+ return 1;
+ }
+
+ return 0;
+}
+
+static int verstage_should_load(void)
+{
+ if (!IS_ENABLED(CONFIG_SEPARATE_VERSTAGE))
+ return 0;
+
+ if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE))
+ return 1;
+
+ if (ENV_BOOTBLOCK && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
+ return 1;
+
+ return 0;
+}
+
+static void init_vb2_working_data(void)
+{
+ struct vb2_working_data *wd;
+
+ wd = vboot_get_working_data();
+ memset(wd, 0, _vboot2_work_size);
+ /*
+ * vboot prefers 16-byte alignment. This takes away 16 bytes
+ * from the VBOOT2_WORK region, but the vboot devs said that's okay.
+ */
+ wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
+ wd->buffer_size = _vboot2_work_size - wd->buffer_offset;
+}
+
+static int vboot_loader_active(struct prog *prog)
+{
+ struct vb2_working_data *wd;
+ int run_verification;
+
+ run_verification = verification_should_run();
+
+ if (run_verification) {
+ init_vb2_working_data();
+ verstage_main();
+ } else if (verstage_should_load()) {
+ struct prog verstage = {
+ .type = PROG_VERSTAGE,
+ .name = CONFIG_CBFS_PREFIX "/verstage",
+ };
+
+ /* load verstage from RO */
+ if (cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, &verstage))
+ die("failed to load verstage");
+
+ /* verify and select a slot */
+ prog_run(&verstage);
+
+ /* This is not actually possible to hit this condition at
+ * runtime, but this provides a hint to the compiler for dead
+ * code elimination below. */
+ if (!IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE))
+ return 0;
+ }
+
+ wd = vboot_get_working_data();
+
+ if (vboot_is_slot_selected(wd)) {
+ if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES) &&
+ run_verification) {
+ /* RW A or B */
+ struct vboot_region fw_main;
+
+ vb2_get_selected_region(wd, &fw_main);
+ cbfs_set_header_offset(fw_main.offset_addr);
+ }
+ return 1;
+ }
+
+ return 0;
+}
+
+static uintptr_t vboot_fw_region(int fw_index, struct vboot_region *fw_main,
+ struct vboot_components *fw_info, size_t *size)
+{
+ uintptr_t fc_addr;
+ uint32_t fc_size;
+
+ if (fw_index >= fw_info->num_components) {
+ printk(BIOS_INFO, "invalid stage index: %d\n", fw_index);
+ return 0;
+ }
+
+ fc_addr = fw_main->offset_addr + fw_info->entries[fw_index].offset;
+ fc_size = fw_info->entries[fw_index].size;
+ if (fc_size == 0 ||
+ fc_addr + fc_size > fw_main->offset_addr + fw_main->size) {
+ printk(BIOS_INFO, "invalid stage address or size\n");
+ return 0;
+ }
+
+ *size = fc_addr;
+ return fc_addr;
+}
+
+/* This function is only called when vboot_loader_active() returns 1. That
+ * means we are taking vboot paths. */
+static int vboot_prepare(struct prog *prog)
+{
+ struct vb2_working_data *wd;
+ struct vboot_region fw_main;
+ struct vboot_components *fw_info;
+
+ /* Code size optimization. We'd never actually get called under the
+ * followin cirumstances because verstage was loaded and ran -- never
+ * returning. */
+ if (verstage_should_load() && !IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE))
+ return 0;
+
+ /* In the multi cbfs case the cbfs offset pointer has already been
+ * updated after firmware verification. */
+ if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) {
+ if (!ENV_RAMSTAGE &&
+ cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, prog) != 0)
+ return -1;
+
+ /* Need to load payload. */
+ if (ENV_RAMSTAGE) {
+ void *payload;
+ size_t size;
+
+ payload = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
+ prog->name,
+ CBFS_TYPE_PAYLOAD,
+ &size);
+
+ if (payload == NULL)
+ die("Couldn't load payload\n");
+
+ prog_set_area(prog, payload, size);
+ }
+ return 0;
+ }
+
+ wd = vboot_get_working_data();
+ vb2_get_selected_region(wd, &fw_main);
+ fw_info = vboot_locate_components(&fw_main);
+ if (fw_info == NULL)
+ die("failed to locate firmware components\n");
+
+ /* Load payload in ramstage. */
+ if (ENV_RAMSTAGE) {
+ uintptr_t payload;
+ void *payload_ptr;
+ size_t size;
+
+ payload = vboot_fw_region(CONFIG_VBOOT_BOOT_LOADER_INDEX,
+ &fw_main, fw_info, &size);
+
+ if (payload == 0)
+ die("Couldn't load payload.");
+
+ payload_ptr = vboot_get_region(payload, size, NULL);
+
+ if (payload_ptr == NULL)
+ die("Couldn't load payload.");
+
+ prog_set_area(prog, payload_ptr, size);
+ } else {
+ uintptr_t stage;
+ size_t size;
+ int stage_index = 0;
+
+ if (prog->type == PROG_ROMSTAGE)
+ stage_index = CONFIG_VBOOT_ROMSTAGE_INDEX;
+ else if (prog->type == PROG_RAMSTAGE)
+ stage_index = CONFIG_VBOOT_RAMSTAGE_INDEX;
+ else
+ die("Invalid program type for vboot.");
+
+ stage = vboot_fw_region(stage_index, &fw_main, fw_info, &size);
+
+ if (stage == 0)
+ die("Vboot stage load failed.");
+
+ if (cbfs_load_prog_stage_by_offset(CBFS_DEFAULT_MEDIA,
+ prog, stage) < 0)
+ die("Vboot couldn't load stage");
+ }
+
+ /* Fill in vboot handoff structure before moving to ramstage. */
+ if (ENV_ROMSTAGE)
+ vboot_fill_handoff();
+
+ return 0;
+}
+
+const struct prog_loader_ops vboot_loader = {
+ .name = "VBOOT",
+ .is_loader_active = vboot_loader_active,
+ .prepare = vboot_prepare,
+};
diff --git a/src/vendorcode/google/chromeos/vboot2/verstub.c b/src/vendorcode/google/chromeos/vboot2/verstub.c
deleted file mode 100644
index c4319ba..0000000
--- a/src/vendorcode/google/chromeos/vboot2/verstub.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/stages.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <string.h>
-#include <timestamp.h>
-#include "../chromeos.h"
-#include "../symbols.h"
-#include "misc.h"
-
-static struct vb2_working_data *init_vb2_working_data(void)
-{
- struct vb2_working_data *wd;
-
- wd = vboot_get_working_data();
- memset(wd, 0, _vboot2_work_size);
- /*
- * vboot prefers 16-byte alignment. This takes away 16 bytes
- * from the VBOOT2_WORK region, but the vboot devs said that's okay.
- */
- wd->buffer_offset = ALIGN_UP(sizeof(*wd), 16);
- wd->buffer_size = _vboot2_work_size - wd->buffer_offset;
-
- return wd;
-}
-
-/**
- * Verify a slot and jump to the next stage
- *
- * This could be either part of the (1) bootblock or the (2) verstage, depending
- * on CONFIG_RETURN_FROM_VERSTAGE.
- *
- * 1) It jumps to the verstage and comes back, then, loads the romstage over the
- * verstage space and exits to it. (note the cbfs cache is trashed on return
- * from the verstage.)
- *
- * 2) We're already in the verstage. Verify firmware, then load the romstage and
- * exits to it.
- */
-void *vboot2_verify_firmware(void)
-{
- void *entry;
- struct vb2_working_data *wd;
-
- wd = init_vb2_working_data();
-
- if (IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)) {
- /* load verstage from RO */
- entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
- CONFIG_CBFS_PREFIX "/verstage");
- if (entry == (void *)-1)
- die("failed to load verstage");
-
- /* verify and select a slot */
- stage_exit(entry);
- } else {
- verstage_main();
- }
-
- /* jump to the selected slot */
- timestamp_add_now(TS_START_COPYROM);
- entry = (void *)-1;
- if (vboot_is_slot_selected(wd)) {
- /* RW A or B */
- struct vboot_region fw_main;
-
- vb2_get_selected_region(wd, &fw_main);
-
- if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) {
- cbfs_set_header_offset(fw_main.offset_addr);
- entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
- CONFIG_CBFS_PREFIX "/romstage");
- } else {
- struct vboot_components *fw_info;
- fw_info = vboot_locate_components(&fw_main);
- if (fw_info == NULL)
- die("failed to locate firmware components\n");
- entry = vboot_load_stage(CONFIG_VBOOT_ROMSTAGE_INDEX,
- &fw_main, fw_info);
- }
- } else if (vboot_is_readonly_path(wd)) {
- /* RO */
- entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
- CONFIG_CBFS_PREFIX "/romstage");
- }
- timestamp_add_now(TS_END_COPYROM);
-
- return entry;
-}
1
0
05 May '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10112
-gerrit
commit 3fbe799d2c8f70622c973d39dc5240ab6c6c4c19
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue May 5 13:35:18 2015 -0700
vgabios: fix compilation
This utility links in coreboot code, and has been broken for a long
time. These changes get it to compile again.
Change-Id: I69445a8b3cbfc9a2b560c68b8de2e080837ec502
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
util/vgabios/Makefile | 4 ++--
util/vgabios/include/stdtypes.h | 18 ++++++++++++++++++
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/util/vgabios/Makefile b/util/vgabios/Makefile
index e187122..8c8ddff 100644
--- a/util/vgabios/Makefile
+++ b/util/vgabios/Makefile
@@ -12,7 +12,7 @@ CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
CFLAGS += -Wstrict-aliasing -Wshadow -Wextra
-INCLUDES = -Iinclude -I../../src/device/oprom/include/
+INCLUDES = -Iinclude -I../../src/device/oprom/include/ -I../../src --include include/stdtypes.h
INTOBJS = int10.o int15.o int16.o int1a.o inte6.o
X86EMUOBJS = sys.o decode.o ops.o ops2.o prim_ops.o fpu.o debug.o
@@ -33,7 +33,7 @@ helper_exec.o: helper_exec.c test.h
clean:
rm -f *.o *~ testbios
-%.o: ../../src/devices/oprom/x86emu/%.c
+%.o: ../../src/device/oprom/x86emu/%.c
$(CC) $(CFLAGS) $(INCLUDES) -include stdio.h -c -o $@ $^
%.o: %.c
diff --git a/util/vgabios/include/stdtypes.h b/util/vgabios/include/stdtypes.h
new file mode 100644
index 0000000..62c254d
--- /dev/null
+++ b/util/vgabios/include/stdtypes.h
@@ -0,0 +1,18 @@
+#ifndef _STDTYPES_H
+#define _STDTYPES_H
+
+#include <stdint.h>
+
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+
+typedef uint8_t bool;
+#define true 1
+#define false 0
+
+#endif /* _STDTYPES_H */
1
0
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10111
-gerrit
commit 9bcba4437230df25d3674a17f0bac9a5c13e6096
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue May 5 13:12:58 2015 -0700
Drop util/runfw
This utility was only used to debug the initial ARM Chromebook bringup,
but it's not really useful anymore.
Change-Id: Icff0a80f244adae3c35a8430c54de9e415fbd7d0
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
util/runfw/Makefile | 26 ---------
util/runfw/googlesnow.c | 137 ------------------------------------------------
2 files changed, 163 deletions(-)
diff --git a/util/runfw/Makefile b/util/runfw/Makefile
deleted file mode 100644
index 5f07e3c..0000000
--- a/util/runfw/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# runfw -- run firmware in user mode.
-#
-# Copyright (C) 2013 The ChromiumOS Authors. All rights reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
-#
-
-all: googlesnow
-
-googlesnow: googlesnow.c
- cc -g -o googlesnow googlesnow.c
-
-clean:
- rm -f googlesnow
diff --git a/util/runfw/googlesnow.c b/util/runfw/googlesnow.c
deleted file mode 100644
index 125e0a2..0000000
--- a/util/runfw/googlesnow.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * googlesnow - run google snow firmware in user mode
- *
- * Copyright (C) 2013 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
- */
-
-#include <stdio.h>
-#include <err.h>
-#include <sys/mman.h>
-
-#include <string.h>
-
-enum addresses {
- regs = 0x10000000,
- sram = 0x2020000,
- sramsize = 0x77fff,
-};
-
-// 0x20234b0
-main(int argc, char *argv[])
-{
- int fd;
- int devmem;
- void *regbase;
- void *srambase;
- void (*coreboot)(void) = (void *)0x2023400;
-
- if (argc != 3)
- errx(1, "usage: runbios rom-file start-address");
-
- fd = open(argv[1], 2);
- if (fd < 0)
- err(1, argv[1]);
- devmem = open("/dev/mem", 2);
- if (devmem < 0)
- err(1, argv[1]);
- srambase = mmap((void *)sram, sramsize, PROT_EXEC|PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
- if (-1 == (int)sram)
- err(1, "mmap");
- memset((void *)sram, 0xff, sramsize);
-
- /* now sort of do what bl1 does: read the 'rom' into the sram */
- /* skip the bl1. We don't run it. */
- if (pread(fd, coreboot, 30*1024, 0x2000) < 30*1024)
- err(1, "read 'rom'");
- /* you want to be in gdb at this point. */
- coreboot = (void *) (strtoul(argv[2], 0, 0));
- coreboot();
-}
-#if 0
-/* cc -g googlesnow.c */
-/* typical run
-gdb a.out
-(gdb) list 50
-
-45 i2c = mmap((void *)0x12c60000, 0x10000, PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE, devmem, (off_t) 0x12c60000);
-46 if (-1 == (int)i2c)
-47 err(1, "mmap i2c");
-48
-49 /* now sort of do what bl1 does: read the 'rom' into the sram */
-50 if (pread(fd, coreboot, 30*1024, 0x2000) < 30*1024)
-51 err(1, "read 'rom'");
-52 /* you want to be in gdb at this point. */
-53 coreboot = (void *) strtoull(argv[2], 0, 0);
-54 coreboot();
-(gdb) br 54
-Breakpoint 3 at 0x8798: file runbios.c, line 54.
-(gdb) run ~/coreboot/build/coreboot.rom 0x020234b0
-The program being debugged has been started already.
-Start it from the beginning? (y or n) y
-
-Starting program: /root/coreboot/util/runarmbios/a.out ~/coreboot/build/coreboot.rom 0x020234b0
-
-Breakpoint 3, main (argc=3, argv=0x7efff7c4) at runbios.c:54
-54 coreboot();
-(gdb) symbol-file ~/coreboot/build/cbfs/fallback/bootblock.debug
-Load new symbol table from "/root/coreboot/build/cbfs/fallback/bootblock.debug"? (y or n) y
-Reading symbols from /root/coreboot/build/cbfs/fallback/bootblock.debug...done.
-Error in re-setting breakpoint 3: No source file named runbios.c.
-(gdb) display/i $pc
-1: x/i $pc
-=> 0x8798: ldr r3, [r11, #-8]
-(gdb) stepi
-0x0000879c in ?? ()
-1: x/i $pc
-=> 0x879c: blx r3
-(gdb)
-0x020234b0 in call_bootblock ()
-1: x/i $pc
-=> 0x20234b0 <call_bootblock>: ldr sp, [pc, #3800] ; 0x2024390
-(gdb)
-0x020234b4 in call_bootblock ()
-1: x/i $pc
-=> 0x20234b4 <call_bootblock+4>: bic sp, sp, #7
-(gdb)
-0x020234b8 in call_bootblock ()
-1: x/i $pc
-=> 0x20234b8 <call_bootblock+8>: mov r0, #0
-(gdb)
-0x020234bc in call_bootblock ()
-1: x/i $pc
-=> 0x20234bc <call_bootblock+12>: blx 0x20244b8 <main>
-(gdb)
-main (bist=0) at src/arch/arm/bootblock_simple.c:37
-37 {
-1: x/i $pc
-=> 0x20244b8 <main>: push {r3, lr}
-(gdb)
-42 bootblock_mainboard_init();
-1: x/i $pc
-=> 0x20244ba <main+2>: bl 0x2023c08 <bootblock_mainboard_init>
-(gdb)
-bootblock_mainboard_init () at src/mainboard/google/snow/bootblock.c:2124
-2124 {
-1: x/i $pc
-=> 0x2023c08 <bootblock_mainboard_init>: stmdb sp!, {r4, r5, r6, r7, r9, r10, r11, lr}
-(gdb)
-2127 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-1: x/i $pc
-=> 0x2023c0c <bootblock_mainboard_init+4>: movs r1, #0
-
-Note you are now debugging source, and pretty much all commands work.
-*/
-#endif
1
0
New patch to review for coreboot: 7373906 Rename documentation -> Documentation
by Stefan Reinauer 05 May '15
by Stefan Reinauer 05 May '15
05 May '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10110
-gerrit
commit 73739063812df6ab8a593cd9e930173c1a7f99aa
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Tue May 5 13:10:04 2015 -0700
Rename documentation -> Documentation
In order to be closer to the Linux kernel source tree
structure, rename documentation to Documentation.
Change-Id: I8690f666638ef352d201bd3c3dc1923b0d24cb12
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
Documentation/AMD-S3.txt | 153 +++
Documentation/CorebootBuildingGuide.tex | 1797 +++++++++++++++++++++++++++++++
Documentation/Doxyfile.coreboot | 1639 ++++++++++++++++++++++++++++
Documentation/Doxyfile.coreboot_simple | 259 +++++
Documentation/Kconfig.tex | 480 +++++++++
Documentation/Makefile | 71 ++
Documentation/POSTCODES | 26 +
Documentation/RFC/chip.tex | 266 +++++
Documentation/RFC/config.tex | 291 +++++
Documentation/abi-data-consumption.txt | 22 +
Documentation/beginverbatim.tex | 1 +
Documentation/cbfs.txt | 421 ++++++++
Documentation/codeflow.svg | 234 ++++
Documentation/coreboot_logo.png | Bin 0 -> 2236 bytes
Documentation/endverbatim.tex | 1 +
Documentation/gcov.txt | 227 ++++
Documentation/hypertransport.svg | 59 +
Documentation/submodules.txt | 46 +
documentation/AMD-S3.txt | 153 ---
documentation/CorebootBuildingGuide.tex | 1797 -------------------------------
documentation/Doxyfile.coreboot | 1639 ----------------------------
documentation/Doxyfile.coreboot_simple | 259 -----
documentation/Kconfig.tex | 480 ---------
documentation/Makefile | 71 --
documentation/POSTCODES | 26 -
documentation/RFC/chip.tex | 266 -----
documentation/RFC/config.tex | 291 -----
documentation/abi-data-consumption.txt | 22 -
documentation/beginverbatim.tex | 1 -
documentation/cbfs.txt | 421 --------
documentation/codeflow.svg | 234 ----
documentation/coreboot_logo.png | Bin 2236 -> 0 bytes
documentation/endverbatim.tex | 1 -
documentation/gcov.txt | 227 ----
documentation/hypertransport.svg | 59 -
documentation/submodules.txt | 46 -
36 files changed, 5993 insertions(+), 5993 deletions(-)
diff --git a/Documentation/AMD-S3.txt b/Documentation/AMD-S3.txt
new file mode 100644
index 0000000..48d4c8f
--- /dev/null
+++ b/Documentation/AMD-S3.txt
@@ -0,0 +1,153 @@
+ _____ ____ _____ ______ ____ ____ ____ _______
+ / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __|
+ | | | | | | |__) | |__ | |_) | | | | | | | | |
+ | | | | | | _ /| __| | _ <| | | | | | | | |
+ | |___| |__| | | \ \| |____| |_) | |__| | |__| | | |
+ \_____\____/|_| \_\______|____/ \____/ \____/ |_|
+
+ __ __ _____ _____ ____
+ /\ | \/ | __ \ / ____| |___ \
+ / \ | \ / | | | | | (___ __) |
+ / /\ \ | |\/| | | | | \___ \ |__ <
+ / ____ \| | | | |__| | ____) | ___) |
+ /_/ \_\_| |_|_____/ |_____/ |____/
+
+
+ S3 in Coreboot (V 1.2)
+----------------------------------------
+ Zheng Bao
+ <zheng.bao(a)amd.com>
+ <fishbaozi(a)gmail.com>
+
+Introduction
+============
+This document is about how the feature S3 is implemented on coreboot,
+specifically on AMD platform. This topic deals with ACPI spec, hardware,
+BIOS, OS. We try to help coreboot users to realize their own S3.
+
+S3 in a nutshell
+================
+The S3 sleeping state is a low wake latency sleeping state where all
+system context is lost except system memory. [1]. S3 is a ACPI
+definition.
+To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI
+registers). But if you do that, board can not resume at where it
+sleeps, because you don't save the context. More often than not, we
+make the board go into S3 by the tools which OSes provide. For
+windows, click Start->sleep. For linux, some distribution provide a
+tools called pm-suspend, which can make the system goto S3. If
+pm-suspend is not available, we can run "echo mem > /sys/power/state",
+but this way may not save all the needed context.
+In S3 state, the power is off. So when the power button is pressed,
+BIOS runs as it does in cold boot. If BIOS didn't detect whether
+board boots or resumes, it would go the same way as boot. It is not
+what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS
+are waking up.
+BIOS is responsible for restore the machine state as it is before
+sleep. It needs restore the memory controller, not overwriting memory
+which is not marked as reserved. For the peripheral which loses its
+registers, BIOS needs to write the original value.
+When everything is done, BIOS needs to find out the wakeup vector
+provided by OSes and jump there. OSes also have work to do. We can go
+to linux kernel or some other open source projects to find out how they
+handle S3 resume.
+
+ACPI registers
+==============
+ACPI specification defines a group of registers. OSes handle all these
+registers to read and write status to all the platform.
+On AMD platform, these registers are provided by southbridge. For
+example, Hudson uses PMIO 60:6F to define ACPI registers.
+OSes don't have any specific driver to know where these registers
+are. BIOS has the responsibility to allocated the IO resources and
+write all these address to FADT, a ACPI defined table.
+
+Memory Layout
+=============
+Restoring memory is the most important job done by BIOS. When the
+power is off, the memory is maintained by standby power. BIOS need to
+make sure that when flow goes to OS, everything in memory should be
+the same as it was.
+
+The chip vendor will provide a way, or code, to wake up the memory
+from sleeping. In AGESA 2008 arch, it is called AmdInitResume.
+
+The BIOS itself needs some memory to run. Either, BIOS marks the erea
+as reserved in e820, or BIOS saves the content into reserved space.
+
+Here is the address Map for S3 Resume. Assumingly the total memory is 1GB.
+00000000 --- 00100000 BIOS Reserved area.
+00100000 --- 00200000 Free
+00200000 --- 01000000 Coreboot ramstage area.
+01000000 --- 2e160000 Free
+2e160000 --- 2e170000 ACPI table
+2e170000 --- 2ef70000 OSRAM
+2ef70000 --- 2efe0000 Stack in highmem
+2efe0000 --- 2f000000 heap in highmem
+2f000000 TOM
+
+AMD requirements in S3
+======================
+Chip vendor like AMD will provide bunch of routines to restore the
+board.[2]
+ * AmdS3Save: It is called in cold boot, save required register into
+ non-volatile storage. Currently, we use SPI flash to store the data.
+ * AmdInitResume: Restore the memory controller.
+ * AmdS3LateRestore: Called after AmdInitResume, restore other
+ register that memory.
+ * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore:
+ Provided by Southbridge vendor code. Early is called before PCI
+ enumeration, and Late is called after that.
+
+Lifecycle of booting, sleeping and waking Coreboot and Ubuntu
+=============================================================
+1. Cold boot.
+For a system with S3 feature, the BIOS needs to save some data to
+non-volatile storage at cold boot stage. What data need to be save are
+provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets
+the VolatileStorage and NvStorage, which are where the data are
+located. It is the wrappers's responsibility to save the data.[3][4]
+Currently, the wrappers allocate a CBFS modules in BIOS image. To do
+that, the wrapper needs to have the ability to write flash chips. It
+is not as comprehensive as flashrom. But for the SST chip on Parmer,
+MX chip on Thather, coreboot works well.[5]
+
+2. OS goes in S3.
+For Linux, besides the kernel needs to do some saving, most distributions
+run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d.
+ # ls /usr/lib/pm-utils/sleep.d
+ 000kernel-change 49bluetooth 90clock 95led
+ 00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler
+ 00powersave 60_wpa_supplicant 95anacron 99video
+ 01PulseAudio 75modules 95hdparm-apm
+The script with lower prefix runs before the one with higher prefix.
+99video is the last one.
+Those scripts have hooks called hibernate, suspend, thaw, resume. For
+each script, suspend is called when system sleeps and wakeup is called
+when system wakeups.
+
+3. Firmware detects S3 wakeup
+As we mentioned, Firmware detects the SLP_TYPx to find out if the board
+wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called
+as they are during cold boot. AmdInitResume and AmdS3LateRestore are
+called only during resume. For whole ramstage, Coreboot goes through
+almost the same way as cold boot, other than not calling the AmdInitMid,
+AmdInitLate and AmdS3Save, and restoring all the MTRRs.
+At last step of coreboot stage, coreboot finds out the wakeup vector in FADT,
+written by OS, and jump.
+
+4. OS resumes.
+When Linux resumes, all the sleeping scripts call their resume
+hooks. If we are more lucky, all the scripts can go through. More
+chances that the 99video hangs or fails to get the display
+back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in
+Coreboot/Kconfig. That needs more troubleshooting.
+
+
+Reference
+=========
+[1] ACPI40a, http://www.acpi.info/spec40a.htm
+[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/
+[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c
+[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c
+[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c
diff --git a/Documentation/CorebootBuildingGuide.tex b/Documentation/CorebootBuildingGuide.tex
new file mode 100644
index 0000000..5b3eacf
--- /dev/null
+++ b/Documentation/CorebootBuildingGuide.tex
@@ -0,0 +1,1797 @@
+%
+% This document is released under the GPL
+% Initially written by Stefan Reinauer, <stepan(a)coresystems.de>
+%
+
+\documentclass[titlepage,12pt]{article}
+\usepackage{a4}
+\usepackage{graphicx}
+\usepackage{url}
+\usepackage[pdftex]{hyperref}
+% \usepackage{makeidx}
+% \makeindex
+
+\hypersetup{
+ urlbordercolor={1 1 1},
+ menubordercolor={1 1 1},
+ linkbordercolor={1 1 1},
+ colorlinks=false,
+ % pdfpagemode=None, % PDF-Viewer starts without TOC
+ % pdfstartview=FitH,
+ pdftitle={coreboot on AMD64},
+ pdfauthor={Stefan Reinauer},
+ pdfsubject={coreboot configuration and build process},
+ pdfkeywords={coreboot, Opteron, AMD64, configuration, Build}
+}
+
+
+% \newcommand{\sh}[1]{\begin{verbatim}\texttt{#1}\end{verbatim}}
+% \newcommand{\prog}[1]{\textit{#1}}
+
+\setlength{\parindent}{0pt}
+
+\title{coreboot on AMD64}
+\author{Stefan Reinauer $<$stepan(a)coresystems.de$>$}
+\date{April 19th, 2009}
+
+\begin{document}
+
+\maketitle
+
+\thispagestyle{empty}
+
+\tableofcontents
+
+\newpage
+
+%
+% 1 Abstract
+%
+
+\section{Abstract}
+
+This document targets porting coreboot to new mainboards and creating
+custom firmware images using coreboot. It describes how to build
+coreboot images for the AMD64 platform, including hypertransport
+configuration and pertinent utilities. If you are missing information or
+find errors in the following descriptions, contact
+\href{mailto:stepan@coresystems.de}{\textit{Stefan Reinauer $<$stepan(a)coresystems.de$>$}}
+
+
+%
+% 2 Changes
+%
+
+\section{Changes}
+ \begin{itemize}
+ \item 2009/04/19 replace LinuxBIOS with coreboot
+ \item 2004/06/02 url and language fixes from Ken Fuchs $<$kfuchs(a)winternet.com$>$
+ \item 2004/02/10 acpi and option rom updates
+ \item 2003/11/18 initial release
+ \end{itemize}
+
+
+
+%
+% 3 What is coreboot
+%
+
+\section{What is coreboot?}
+
+coreboot aims to replace the normal BIOS found on x86, AMD64, PPC,
+Alpha, and other machines with a Linux kernel that can boot Linux from a cold
+start. The startup code of an average coreboot port is about 500 lines of
+assembly and 5000 lines of C. It executes 16 instructions to get into 32bit
+protected mode and then performs DRAM and other hardware initializations
+required before Linux can take over.
+
+The projects primary motivation initially was maintenance of large
+clusters. Not surprisingly interest and contributions have come from
+people with varying backgrounds. Nowadays a large and growing number of
+Systems can be booted with coreboot, including embedded systems,
+Desktop PCs and Servers.
+
+%
+% 4 Build Requirements
+%
+
+\section{Build Requirements}
+To build coreboot for AMD64 from the sources you need a recent Linux
+system for x86 or AMD64. SUSE Linux 8.2 or 9.0 are known to work fine.
+The following toolchain is recommended:
+
+ \begin{itemize}
+ \item GCC 3.3.1
+ \item binutils 2.14.90.0.5
+ \item Python 2.3
+ \item CVS 1.11.6
+ \end{itemize}
+
+\textbf{NOTE:} Later versions should also work. Prior versions might lead to problems.
+
+\newpage
+
+%
+% 5 Getting the Sources
+%
+
+\section{Getting the Sources}
+
+The latest coreboot sources are available via subversion. The subversion
+repository is maintained at SourceForge.net (the project name is
+\emph{FreeBIOS}). First you should create a directory for your
+coreboot trees:
+
+{ \small
+\begin{verbatim}
+$ mkdir coreboot
+$ cd coreboot
+\end{verbatim}
+}
+
+You can get the entire source tree via SVN:
+
+{ \small
+\begin{verbatim}
+$ svn co svn://coreboot.org/repos/trunk/coreboot-v2
+\end{verbatim}
+}
+
+Once the source tree is checked out, it can be updated with:
+
+{ \small
+\begin{verbatim}
+% svn update
+\end{verbatim}
+}
+
+For the case your corporate firewall blocks port 3690 (subversion) we set up a
+snapshot site that keeps the last few hundred source code revisions. It
+is available at \url{http://qa.coreboot.org/}.
+Due to major structural enhancements to \hbox{coreboot}, AMD64 support
+is only available in the \texttt{coreboot-v2} tree. This tree reflects (as
+of November 2003) coreboot version 1.1.5 and will lead to coreboot 2.0
+when finished. Most x86 hardware is currently only supported by the
+coreboot 1.0 tree.
+
+%
+% 6 coreboot configuration overview
+%
+
+\section{coreboot configuration overview}
+To support a large variety of existing hardware coreboot allows for a
+lot of configuration options that can be tweaked in several ways:
+
+\begin{itemize}
+\item
+Firmware image specific configuration options can be set in the image
+configuration file which is usually found in
+\texttt{coreboot-v2/targets/$<$vendor$>$/$<$mainboard$>$/}. Such
+options are the default amount of output verbosity during bootup, image
+size, use of fallback mechanisms, firmware image size and payloads
+(Linux Kernel, Bootloader...) The default configuration file name is
+\texttt{Config.lb}, but coreboot allows multiple configurations to
+reside in that directory.
+
+\item Mainboard specific configuration options can be set in the
+mainboard configuration file placed in
+\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$}. The
+mainboard configuration file is always called \texttt{Config.lb}. It
+contains information on the onboard components of the mainboard like
+CPU type, northbridge, southbridge, hypertransport configuration and
+SuperIO configuration. This configuration file also allows to include
+addon code to hook into the coreboot initialization mechanism at
+basically any point.
+
+\end{itemize}
+
+This document describes different approaches of changing and configuring the
+coreboot source tree when building for AMD64.
+
+%
+% 7 Building coreboot
+%
+
+\section{Building coreboot}
+One of the design goals for building coreboot was to keep object files
+out of the source tree in a separate place. This is mandatory for
+building parallel coreboot images for several distinct mainboards
+and/or platforms. Therefore building coreboot consists of two steps:
+\begin{itemize}
+\item
+creating a build tree which holds all files automatically created by the
+configuration utility and the object files
+\item
+compiling the coreboot code and creating a flashable firmware image.
+\end{itemize}
+
+The first of these two steps is accomplished by the \texttt{buildtarget}
+script found in \texttt{coreboot-v2/targets/}. To build coreboot for
+instance for the AMD Solo Athlon64 mainboard enter:
+
+\begin{verbatim}
+% cd coreboot-v2/targets
+% ./buildtarget amd/solo
+\end{verbatim}
+
+This will create a directory containing a Makefile and other software
+components needed for this build. The directory name is defined in the
+firmware image specific configuration file. In the case of AMD's Solo
+mainboard the default directory resides in
+\texttt{coreboot-v2/targets/amd/solo/solo}. To build the coreboot image, do
+
+\begin{verbatim}
+% cd amd/solo/solo
+% make
+\end{verbatim}
+
+The coreboot image filename is specified in the firmware image specific
+configuration file. The default filename for AMD's Solo mainboard is
+\texttt{solo.rom}.
+
+%
+% 8 Programming coreboot to flash memory
+%
+
+\section{Programming coreboot to flash memory}
+The image resulting from a coreboot build can be directly programmed to
+a flash device, either using a hardware flash programmer or by using the
+Linux flash driver devbios or mtd. This document assumes that you use a
+hardware flash programmer. If you are interested in doing in-system
+software flash programming, find detailed information:
+
+\begin{itemize}
+\item \url{http://www.openbios.org/development/devbios.html} (/dev/bios)
+\item \url{http://www.linux-mtd.infradead.org/} (Memory Technology Device Subsystem MTD)
+\end{itemize}
+
+\newpage
+
+%
+% 9 coreboot configuration
+%
+
+\section{coreboot configuration}
+The following chapters will cope with configuring coreboot. All
+configuration files share some basic rules
+\begin{itemize}
+\item
+The default configuration file name in coreboot is \texttt{Config.lb}.
+\item
+All variables used in a configuration file have to be declared in this
+file with \texttt{uses VARNAME} before usage.
+\item
+Comments can be added on a new line by using the comment identifier
+\texttt{\#} at the beginning of the line.
+\item
+coreboot distinguishes between statements and options. Statements cause
+the coreboot configuration mechanism to act, whereas options set
+variables that are used by the build scripts or source code.
+\item
+Default configuration values can be set in the mainboard configuration
+files (keyword default)
+\item
+Option overrides to the default configuration can only be specified in
+the build target configuration file
+\texttt{coreboot-v2/targets/$<$vendor$>$/$<$mainboard$>$/Config.lb}
+(keyword option)
+\end{itemize}
+
+\subsection{Common Configuration Statements}
+
+\begin{itemize}
+
+\item \begin{verbatim}uses\end{verbatim}
+
+All local configuration variables have to be declared before they can be
+used. Example:
+\begin{verbatim}
+ uses CONFIG_ROM_IMAGE_SIZE
+\end{verbatim}
+
+\textbf{NOTE:} Only configuration variables known to the configuration
+system can be used in configuration files. coreboot checks
+\texttt{coreboot-v2/src/config/Options.lb} to see whether a configuration
+variable is known.
+
+\item \begin{verbatim}default\end{verbatim}
+
+The \texttt{default} statement is used to set a configuration variable
+with an overridable default value. It is commonly used in mainboard
+configuration files.
+
+Example:
+
+\begin{verbatim}
+ default CONFIG_ROM_IMAGE_SIZE=0x10000
+\end{verbatim}
+
+It is also possible to assign the value of one configuration variable to
+another one, i.e.:
+
+\begin{verbatim}
+ default CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
+\end{verbatim}
+
+Also, simple expressions are allowed:
+
+\begin{verbatim}
+ default CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE - NORMAL_SIZE)
+\end{verbatim}
+
+If an option contains a string, this string has to be protected with
+quotation marks:
+
+\begin{verbatim}
+ default CC="gcc -m32"
+\end{verbatim}
+
+\item \begin{verbatim}option\end{verbatim}
+
+The \texttt{option} statement basically behaves identically to the
+\texttt{default} statement. But unlike default it can only be used in
+build target configuration files
+(\texttt{coreboot-v2/targets/$<$vendor$>$/$<$mainboard$>$}). The option
+statement allows either to set new options or to override default values
+set with the default statement in a mainboard configuration file.
+Syntax and application are the same as with default.
+
+\end{itemize}
+
+\subsection{Firmware image specific configuration}
+coreboot allows to create different firmware images for the same
+hardware. Such images can differ in the amount of output they produce,
+the payload, the number of subimages they consist of etc.
+
+The firmware image specific configuration file can be found in \\
+\texttt{coreboot-v2/targets/$<$vendor$>$/<mainboard$>$}.
+
+\subsubsection{Firmware image specific keywords}
+In addition to the above described keywords the following statements are
+available in firmware image specific configuration files:
+
+\begin{itemize}
+\item \begin{verbatim}romimage\end{verbatim}
+
+The \texttt{romimage} definition describes a single rom build within the
+final coreboot image. Normally there are two romimage definitions per
+coreboot build: \texttt{normal} and \texttt{fallback}.
+
+Each \texttt{romimage} section needs to specify a mainboard directory and a
+payload. The mainboard directory contains the mainboard specific
+configuration file and source code. It is specified relatively to
+\texttt{coreboot-v2/src/mainboard}. The payload definition is an absolute
+path to a static elf binary (i.e Linux kernel or etherboot)
+
+\begin{verbatim}
+romimage "normal"
+ option CONFIG_USE_FALLBACK_IMAGE=0
+ option CONFIG_ROM_IMAGE_SIZE=0x10000
+ option COREBOOT_EXTRA_VERSION=".0Normal"
+ mainboard amd/solo
+ payload /suse/stepan/tg3ide_
+ disk.zelf
+end
+\end{verbatim}
+
+\item \begin{verbatim}buildrom\end{verbatim}
+
+The \texttt{buildrom} statement is used to determine which of the
+coreboot image builds (created using \texttt{romimage}) are packed
+together to the final coreboot image. It also specifies the order of
+the images and the final image size:
+
+\begin{verbatim}
+ buildrom ./solo.rom CONFIG_ROM_SIZE "normal" "fallback"
+\end{verbatim}
+
+\end{itemize}
+
+
+\subsubsection{Firmware image configuration options}
+In addition to the definitions described above there are a number of
+commonly used options. Configuration options set in the firmware image
+specific configuration file can override default selections from the
+Mainboard specific configuration. See above examples about
+option on how to set them.
+
+\begin{itemize}
+
+\item \begin{verbatim}CC\end{verbatim}
+
+Target C Compiler. Default is \texttt{\$(CROSS\_COMPILE)gcc}. Set to
+\texttt{gcc -m32} for compiling AMD64 coreboot images on an AMD64
+machine.
+
+\item \begin{verbatim}CONFIG_CHIP_CONFIGURE \end{verbatim}
+
+Use new \textit{chip\_configure} method for configuring (nonpci)
+devices. Set to \texttt{1} for all AMD64 mainboards.
+
+\item \begin{verbatim}CONFIG_DEFAULT_CONSOLE_LOGLEVEL\end{verbatim}
+
+Console will log at this level unless changed. Default is \texttt{7},
+minimum is \texttt{0}, maximum is \texttt{10}.
+
+\item \begin{verbatim}CONFIG_CONSOLE_SERIAL8250\end{verbatim}
+
+Log messages to 8250 uart based serial console. Default is \texttt{0}
+(don't log to serial console). This value should be set to \texttt{1}
+for all AMD64 builds.
+
+\item \begin{verbatim}CONFIG_ROM_SIZE\end{verbatim}
+
+Size of final ROM image. This option has no default value.
+
+\item \begin{verbatim}CONFIG_FALLBACK_SIZE\end{verbatim}
+
+Fallback image size. Defaults to \texttt{65536} bytes. \textbf{NOTE:}
+This does not include the fallback payload.
+
+\item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim}
+
+Export CMOS option table. Default is \texttt{0}. Set to \texttt{1} if
+your mainboard has CMOS memory and you want to use it to store
+coreboot parameters (Loglevel, serial line speed, ...)
+
+\item \begin{verbatim}CONFIG_ROM_PAYLOAD\end{verbatim}
+
+Boot image is located in ROM (as opposed to \texttt{CONFIG\_IDE\_PAYLOAD}, which
+will boot from an IDE disk)
+
+\item \begin{verbatim}CONFIG_HAVE_FALLBACK_BOOT\end{verbatim}
+
+Set to \texttt{1} if fallback booting is required. Defaults to
+\texttt{0}.
+
+\end{itemize}
+
+
+The following options should be used within a romimage section:
+
+\begin{itemize}
+
+\item \begin{verbatim}CONFIG_USE_FALLBACK_IMAGE\end{verbatim}
+
+Set to \texttt{1} to build a fallback image. Defaults to \texttt{0}
+
+\item \begin{verbatim}CONFIG_ROM_IMAGE_SIZE\end{verbatim}
+
+Default image size. Defaults to \texttt{65535} bytes.
+
+\item \begin{verbatim}COREBOOT_EXTRA_VERSION\end{verbatim}
+
+coreboot extra version. This option has an empty string as default. Set
+to any string to add an extra version string to your coreboot build.
+
+\end{itemize}
+
+\newpage
+
+\subsection{Mainboard specific configuration}
+
+Mainboard specific configuration files describe the onboard
+mainboard components, i.e. bridges, number and type of CPUs. They also
+contain rules for building the low level start code which is translated
+using romcc and/or the GNU assembler. This code enables caches and
+registers, early mtrr settings, fallback mechanisms, dram init and
+possibly more.
+
+\textbf{NOTE:} The \texttt{option} keyword can not be used in mainboard
+specific configuration files. Options shall instead be set using the
+\texttt{default} keyword so that they can be overridden by the image
+specific configuration files if needed.
+
+\subsubsection{Mainboard specific keywords}
+
+The following statements are used in mainboard specific configuration
+files:
+
+\begin{itemize}
+\item \begin{verbatim}arch\end{verbatim}
+
+Sets the CPU architecture. This should be \texttt{i386} for AMD64 boards.\\
+Example:
+
+\begin{verbatim}
+ arch i386 end
+\end{verbatim}
+
+\item \begin{verbatim}cpu\end{verbatim}
+
+The cpu statement is needed once per possibly available CPU. In a
+one-node system, write:
+
+\begin{verbatim}
+ cpu k8 "cpu0" end
+\end{verbatim}
+
+\item \begin{verbatim}driver\end{verbatim}
+
+The \texttt{driver} keyword adds an object file to the driver section of a
+coreboot image. This means it can be used by the PCI device
+initialization code. Example:
+
+\begin{verbatim}
+ driver mainboard.o
+\end{verbatim}
+
+\item \begin{verbatim}object\end{verbatim}
+
+The \texttt{object} keyword adds an object file to the coreboot image.
+Per default the object file will be compiled from a \texttt{.c} file
+with the same name. Symbols defined in such an object file can be used
+in other object files and drivers. Example:
+
+\begin{verbatim}
+ object reset.o
+\end{verbatim}
+
+\item \begin{verbatim}makerule\end{verbatim}
+
+This keyword can be used to extend the existing file creation rules
+during the build process. This is useful if external utilities have to
+be used for the build. coreboot on AMD64 uses romcc for it's early
+startup code placed in auto.c.
+
+To tell the configuration mechanism how to build \texttt{romcc} files,
+do:
+
+\begin{verbatim}
+makerule ./auto.E
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
+ $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
+ $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+\end{verbatim}
+
+Each \texttt{makerule} section contains file dependencies (using the
+texttt{depends} keyword) and an action that is taken when the dependencies
+are satisfied (using the \texttt{action} keyword).
+
+\item \begin{verbatim}mainboardinit\end{verbatim}
+
+With the mainboardinit keyword it's possible to include assembler code
+directly into the coreboot image. This is used for early infrastructure
+initialization, i.e. to switch to protected mode. Example:
+
+\begin{verbatim}
+ mainboardinit cpu/i386/entry16.inc
+\end{verbatim}
+
+\item \begin{verbatim}ldscript\end{verbatim}
+
+The GNU linker ld is used to link object files together to a coreboot
+ROM image.
+
+Since it is a lot more comfortable and flexible to use the GNU linker
+with linker scripts (ldscripts) than to create complex command line
+calls, coreboot features including linker scripts to control image
+creation. Example:
+
+\begin{verbatim}
+ ldscript /cpu/i386/entry16.lds
+\end{verbatim}
+
+
+\item \begin{verbatim}dir\end{verbatim}
+
+coreboot reuses as much code between the different ports as possible.
+To achieve this, commonly used code can be stored in a separate
+directory. For a new mainboard, it is enough to know that the code in
+that directory can be used as is.
+
+coreboot will also read a \texttt{Config.lb} file stored in that
+directory. This happens with:
+
+\begin{verbatim}
+ dir /pc80
+\end{verbatim}
+
+
+\item \begin{verbatim}config\end{verbatim}
+
+This keyword is needed by the new chip configuration scheme. Should be
+used as:
+
+\begin{verbatim}
+ config chip.h
+\end{verbatim}
+
+\item \begin{verbatim}register\end{verbatim}
+The \texttt{register} keyword can occur in any section, passing
+additional \\
+parameters to the code handling the associated device.
+Example:
+
+\begin{verbatim}
+ register "com1" = "{1, 0, 0x3f8, 4}"
+\end{verbatim}
+
+\item \begin{verbatim}northbridge\end{verbatim}
+
+The \texttt{northbridge} keyword describes a system northbridge. Some
+systems, like AMD64, can have more than one northbridge, i.e. one per
+CPU node. Each northbridge is described by the path to the northbridge
+code in coreboot (relative to \texttt{coreboot-v2/src/northbridge}), i.e.
+\texttt{amd/amdk8} and a unique name (i.e \texttt{mc0}) \\
+Example:
+
+\begin{verbatim}
+ northbridge amd/amdk8 "mc0"
+ [..]
+ end
+\end{verbatim}
+
+\item \begin{verbatim}southbridge\end{verbatim}
+
+To simplify the handling of bus bridges in a coreboot system, all
+bridges available in a system that are not northbridges (i.e AGP, IO,
+PCIX) are seen as southbridges.
+
+Since from the CPUs point of view any southbridge is connected via the
+northbridge, a southbridge section is declared within the northbridge
+section of the north bridge it is attached to.
+
+Like the northbridge, any other bridge is described by the path to it's
+driver code, and a unique name. If the described bridge is a
+hypertransport device, the northbridge's hypertransport link it connects
+to can be specified using the \texttt{link} keyword. Example:
+
+\begin{verbatim}
+northbridge amd/amdk8 "mc0"
+ [..]
+ southbridge amd/amd8111 "amd8111" link 0
+ [..]
+ end
+ [..]
+end
+\end{verbatim}
+
+\item \begin{verbatim}pci\end{verbatim}
+
+The \texttt{pci} keyword can only occur within a \texttt{northbridge} or
+\texttt{southbridge} section. It is used to describe the PCI devices
+that are provided by the bridge. Generally all bridge sections have a
+couple of \texttt{pci} keywords.
+
+The first occurrence of the \texttt{pci} keyword tells coreboot where
+the bridge devices start, relative to the PCI configuration space used
+by the bridge. The following occurences of the \texttt{pci} keyword
+describe the provided devices.
+
+Adding the option \texttt{on} or \texttt{off} to a PCI device will
+enable or disable this device. This feature can be used if some bridge
+devices are not wired to hardware outputs and thus are not used.
+
+Example:
+
+\begin{verbatim}
+northbridge amd/amdk8 "mc1"
+ pci 0:19.0
+ pci 0:19.0
+ pci 0:19.0
+ pci 0:19.1
+ pci 0:19.2
+ pci 0:19.3
+end
+\end{verbatim}
+
+or
+
+\begin{verbatim}
+southbridge amd/amd8111 "amd8111" link 0
+ pci 0:0.0
+ pci 0:1.0 on
+ pci 0:1.1 on
+ pci 0:1.2 on
+ pci 0:1.3 on
+ pci 0:1.5 off
+ pci 0:1.6 off
+ pci 1:0.0 on
+ pci 1:0.1 on
+ pci 1:0.2 on
+ pci 1:1.0 off
+ [..]
+end
+\end{verbatim}
+
+\item \begin{verbatim}superio\end{verbatim}
+
+SuperIO devices are basically handled like brigdes. They are taking
+their driver code from \texttt{coreboot-v2/src/superio/}. They don't
+provide a PCI compatible configuration interface, but instead are ISA
+PnP devices. Normally they are connected to a southbridge. If this is
+the case, the \texttt{superio} section will be a subsection of the
+\texttt{southbridge} section of the southbridge it is connected to.
+Example:
+
+\begin{verbatim}
+superio nsc/pc87360 link 1
+ pnp 2e.0
+ pnp 2e.1
+ pnp 2e.2
+ pnp 2e.3
+ pnp 2e.4
+ pnp 2e.5
+ pnp 2e.6
+ pnp 2e.7
+ pnp 2e.8
+ pnp 2e.9
+ pnp 2e.a
+ register "com1" = "{1, 0, 0x3f8, 4}"
+ register "lpt" = "{1}"
+end
+\end{verbatim}
+
+\end{itemize}
+
+\newpage
+
+\subsubsection{Mainboard specific configuration options}
+
+The following options are commonly used in mainboard specific
+configuration files.
+
+They should be set using the \texttt{default} keyword:
+
+\begin{itemize}
+
+\item \begin{verbatim}CONFIG_HAVE_HARD_RESET\end{verbatim}
+
+If set to \texttt{1}, this option defines that there is a hard reset
+function for this mainboard. This option is not defined per default.
+
+\item \begin{verbatim}CONFIG_HAVE_PIRQ_TABLE\end{verbatim}
+
+If set to \texttt{1}, this option defines that there is an IRQ Table for
+this mainboard. This option is not defined per default.
+
+\item \begin{verbatim}CONFIG_IRQ_SLOT_COUNT\end{verbatim}
+
+Number of IRQ slots. This option is not defined per default.
+
+\item \begin{verbatim}CONFIG_HAVE_MP_TABLE\end{verbatim}
+
+Define this option to build an MP table (v1.4). The default is not to
+build an MP table.
+
+\item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim}
+
+Define this option to export a CMOS option table. The default is not to
+export a CMOS option table.
+
+\item \begin{verbatim}CONFIG_SMP\end{verbatim}
+
+Set this option to \texttt{1} if the mainboard supports symmetric
+multiprocessing (SMP). This option defaults to \texttt{0} (no SMP).
+
+\item \begin{verbatim}CONFIG_MAX_CPUS\end{verbatim}
+
+If \begin{verbatim}CONFIG_SMP\end{verbatim} is set, this option defines
+the maximum number of CPUs (i.e. the number of CPU sockets) in the
+system. Defaults to \texttt{1}.
+
+\item \begin{verbatim}CONFIG_IOAPIC\end{verbatim}
+
+Set this option to \texttt{1} to enable IOAPIC support. This is
+mandatory if you want to boot a 64bit Linux kernel on an AMD64 system.
+
+\item \begin{verbatim}CONFIG_STACK_SIZE\end{verbatim}
+
+coreboot stack size. The size of the function call stack defaults to
+\texttt{0x2000} (8k).
+
+\item \begin{verbatim}CONFIG_HEAP_SIZE\end{verbatim}
+
+coreboot heap size. The heap is used when coreboot allocates memory
+with malloc(). The default heap size is \texttt{0x2000}, but AMD64 boards
+generally set it to \texttt{0x4000} (16k)
+
+\item \begin{verbatim}CONFIG_XIP_ROM_BASE\end{verbatim}
+
+Start address of area to cache during coreboot execution directly from
+ROM.
+
+\item \begin{verbatim}CONFIG_XIP_ROM_SIZE\end{verbatim}
+
+Size of area to cache during coreboot execution directly from ROM
+
+\item \begin{verbatim}CONFIG_COMPRESS\end{verbatim}
+
+Set this option to \texttt{1} for a compressed image. If set to
+\texttt{0}, the image is bigger but will start slightly faster (since no
+decompression is needed).
+
+\end{itemize}
+
+
+\newpage
+
+%
+% 10. Tweaking the source code
+%
+
+\section{Tweaking the source code}
+Besides configuring the existing code it is sometimes necessary or
+desirable to tweak certain parts of coreboot by direct changes to the
+code. This chapter covers some possible enhancements and changes that
+are needed when porting coreboot to a new mainboard or just come
+handy now and then.
+
+\subsection{Hypertransport configuration}
+Before coreboot is able to activate all CPUs and detect bridges
+attached to these CPUs (and thus, see all devices attached to the
+system) it has to initialize the coherent hypertransport devices.
+
+The current algorithms to do coherent hypertransport initialization are
+not fully, automatically evaluating the hypertransport chain graph.
+Therefore the code needs to be adapted when porting coreboot to a new
+AMD64 mainboard. An example arrangement of hypertransport devices
+looks like this:
+
+\begin{figure}[htb]
+\centering
+\includegraphics[scale=1.0]{hypertransport.pdf}
+\caption{Example: Hypertransport Link Connections}
+\label{fix:hypertransport}
+\end{figure}
+
+Each hypertransport device has one to three hypertransport links that
+are used for device interconnection. These links are called LDT$[$012$]$, or
+accordingly UP, ACROSS, DOWN. Communication between the hypertransport
+devices can be freely routed, honoring the physical wiring. Teaching the
+coherent hypertransport initialization algorithm this wiring happens in
+two steps.
+
+\newpage
+
+\begin{enumerate}
+\item Setting outgoing connections
+The algorithm needs to know which outgoing port of a CPU node is
+connected to the directly succeeding node. This is done in
+\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/auto.c}
+with a number of preprocessor defines (one define for two-node systems,
+three defines for four-node systems).
+
+The ports in question are flagged with a circle in the graph for
+illustration. For the example graph above (all outgoing connections are
+realized using LDT1/ACROSS) the defines are:
+
+\begin{verbatim}
+#define CONNECTION_0_1 ACROSS
+#define CONNECTION_0_2 ACROSS
+#define CONNECTION_1_3 ACROSS
+\end{verbatim}
+
+\item Describing routing information between CPUs.
+
+There are basically three different message types for hypertransport
+communication:
+\begin{enumerate}
+\item request packages
+\item response packages
+\item broadcast packages
+\end{enumerate}
+
+These three message types are routed using different hypertransport
+ports. The routing information is written to the AMD K8 routing table.
+In an Nnode system this routing table consists of 3*N*N entries , one
+for each message type and for each possible CPU --> CPU communication. For
+simplicity coreboot keeps the 3 routing entries for each CPU --> CPU
+communication in one machine word. The routing table of each node looks
+like this:
+
+\begin{verbatim}
+/* Routing Table for Node i
+ *
+ * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
+ * i: 0, 1, 2, 3, 4, 5, 6, 7
+ *
+ * [ 0: 3] Request Route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ * [11: 8] Response Route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ * [19:16] Broadcast route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ */
+\end{verbatim}
+
+The routing table is passed to the coherent hypertransport
+initialization algorithm by defining a function called
+\texttt{generate\_row()} in \texttt{auto.c}:
+
+\begin{verbatim}
+static unsigned int generate_row
+ (uint8_t node, uint8_t row, uint8_t maxnodes)
+\end{verbatim}
+
+This function is trivial if there is only one CPU in the system, since
+no routing has to be done:
+
+\begin{verbatim}
+static unsigned int generate_row
+ (uint8_t node, uint8_t row, uint8_t maxnodes)
+{
+ return 0x00010101; /* default row entry */
+}
+\end{verbatim}
+
+On a two-node system things look slightly more complicated. Since the
+coherent hypertransport initialization algorithm works by consecutively
+enabling CPUs, it contains routing information for driving the system
+with one node and two nodes:
+
+\begin{verbatim}
+static unsigned int generate_row
+ (uint8_t node, uint8_t row, uint8_t maxnodes)
+{
+ uint32_t ret=0x00010101; /* default row entry */
+ static const unsigned int rows_2p[2][2] = {
+ { 0x00050101, 0x00010404 },
+ { 0x00010404, 0x00050101 }
+ };
+ if(maxnodes>2) maxnodes=2;
+ if (!(node>=maxnodes || row>=maxnodes)) {
+ ret=rows_2p[node][row];
+ }
+ return ret;
+}
+\end{verbatim}
+
+Systems with four nodes have to contain routing information for one, two
+and four-node setups:
+
+\begin{verbatim}
+static unsigned int generate_row
+ (uint8_t node, uint8_t row, uint8_t maxnodes)
+{
+ uint32_t ret=0x00010101; /* default row entry */
+ static const unsigned int rows_2p[2][2] = {
+ { 0x00030101, 0x00010202 },
+ { 0x00010202, 0x00030101 }
+ };
+ static const unsigned int rows_4p[4][4] = {
+ { 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
+ { 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
+ { 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
+ { 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
+ };
+ if (!(node>=maxnodes || row>=maxnodes)) {
+ if (maxnodes==2)
+ ret=rows_2p[node][row];
+ if (maxnodes==4)
+ ret=rows_4p[node][row];
+ }
+ return ret;
+}
+\end{verbatim}
+\end{enumerate}
+
+\subsection{DRAM configuration}
+Setting up the RAM controller(s) is probably the most complex part of
+coreboot. Basically coreboot serially initializes all RAM controllers
+in the system, using SPDROM (serial presence detect) data to set
+timings, size and other properties. The SPD data is usually read
+utilizing the I2C SMBUS interface of the southbridge.
+
+There is one central data structure that describes the RAM controllers
+available on an AMD64 system and the associated devices:
+
+\begin{verbatim}
+struct mem_controller {
+ unsigned node_id;
+ device_t f0, f1, f2, f3;
+ uint8_t channel0[4];
+ uint8_t channel1[4];
+};
+\end{verbatim}
+
+Available mainboard implementations and CPUs create the need to add
+special setup code to RAM initialization in a number of places.
+coreboot provides hooks to easily add code in these places without
+having to change the generic code. Whether these hooks have to be used
+depends on the mainboard design. In many cases the functions executed
+by the hooks just carry out trivial default settings or they are even
+empty.
+
+Some mainboard/CPU combinations need to trigger an additional memory
+controller reset before the memory can be initialized properly. This is,
+for example, used to get memory working on preC stepping AMD64
+processors. coreboot provides two hooks for triggering onboard memory
+reset logic:
+
+\begin{itemize}
+\item \begin{verbatim}static void memreset_setup(void)\end{verbatim}
+\item \begin{verbatim}static void memreset(int controllers, const struct
+ mem_controller *ctrl)\end{verbatim}
+\end{itemize}
+
+Some mainboards utilize an SMBUS hub or possibly other mechanisms to
+allow using a large number of SPDROMs and thus ram sockets. The result
+is that only the SPDROM information of one cpu node is visible at a
+time. The following function, defined in \texttt{auto.c}, is called every time
+before a memory controller is initialized and gets the memory controller
+information of the next controller as a parameter:
+
+\begin{verbatim}
+static inline void activate_spd_rom (const struct mem_controller *ctrl)
+\end{verbatim}
+
+The way SMBUS hub information is coded into the \texttt{mem\_controller}
+structure is mainboard implementation specific and not
+described here. See \texttt{coreboot-v2/src/mainboard/amd/quartet/auto.c}
+for an example.
+
+coreboot folks have agreed on SPD data being the central information
+source for RAM specific information. But not all mainboards/RAM
+modules feature a physical SPD ROM. To still allow an easy to use SPD
+driven setup, there is a hook that abstracts reading the SPD ROM
+ingredients that are used by the memory initialization mechanism:
+
+\begin{verbatim}
+static inline int spd_read_byte(unsigned device, unsigned address)
+\end{verbatim}
+
+This function, defined in \texttt{auto.c}, directly maps it's calls to
+\texttt{smbus\_read\_byte()} calls if SPD ROM information is read via
+the I2C SMBUS:
+
+\begin{verbatim}
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device & 0xff, address);
+}
+\end{verbatim}
+
+If there is no SPD ROM available in the system design, this function
+keeps an array of SPD ROM information hard coded per logical RAM module.
+It returns the faked' SPD ROM information using device and address
+as indices to this array.
+
+
+\subsection {IRQ Tables}
+
+Mainboards that provide an IRQ table should have the following two
+variables set in their \texttt{Config.lb} file:
+
+\begin{verbatim}
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=7
+\end{verbatim}
+
+This will make coreboot look for the file \\
+\texttt{coreboot-v2/src/mainboard/<vendor>/<mainboard>/irq\_tables.c} which
+contains the source code definition of the IRQ table. coreboot corrects
+small inconsistencies in the IRQ table during startup (checksum and
+number of entries), but it is not yet writing IRQ tables in a completely
+dynamic way.
+
+\textbf{NOTE:} To get Linux to understand and actually use the IRQ
+table, it is not always a good idea to specify the vendor and device id
+of the actually present interrupt router device. Linux 2.4 for example
+does not know about the interrupt router of the AMD8111 southbridge. In
+such cases it is advised to choose the vendor/device id of a compatible
+device that is supported by the Linux kernel. In case of the AMD8111
+interrupt router it is advised to specify the AMD768/Opus interrupt
+controller instead (vendor id=\texttt{0x1022}, device id=\texttt{0x7443})
+
+\subsection {MP Tables}
+
+coreboot contains code to create MP tables conforming the
+Multiprocessor Specification V1.4. To include an MP Table in a coreboot
+image, the following configuration variables have to be set (in the
+mainboard specific configuration file
+\texttt{coreboot-v2/src/mainboard/<vendor><mainboard>/Config.lb}):
+
+\begin{verbatim}
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=1 # 2,4,..
+default CONFIG_HAVE_MP_TABLE=1
+\end{verbatim}
+
+coreboot will then look for a function for setting up the MP table in
+the file \texttt{coreboot-v2/src/mainboard<vendor>/<mainboard>/mptable.c}:
+
+\begin{verbatim}
+void *smp_write_config_table(void *v, unsigned long * processor_map)
+\end{verbatim}
+
+MP Table generation is still somewhat static, i.e. changing the bus
+numbering will force
+you to adopt the code in mptable.c. This is subject to change in future
+revisions.
+
+\subsection {ACPI Tables}
+
+There is initial ACPI support in coreboot now. Currently the only gain with
+this is the ability to use HPET timers in Linux. To achieve this, there is a
+framework that can generate the following tables:
+\begin{itemize}
+\item RSDP
+\item RSDT
+\item MADT
+\item HPET
+\end{itemize}
+
+To enable ACPI in your coreboot build, add the following lines to your
+configuration files:
+\begin{verbatim}
+uses CONFIG_HAVE_ACPI_TABLES
+[..]
+option CONFIG_HAVE_ACPI_TABLES=1
+\end{verbatim}
+
+To keep Linux doing it's pci ressource allocation based on IRQ tables and MP
+tables, you have to specify the kernel parameter \texttt{pci=noacpi} otherwise
+your PCI devices won't get interrupts.
+It's likely that more ACPI support will follow, when there is need for certain
+features.
+
+\subsection{POST}
+coreboot has three different methods of handling POST codes. They can
+be triggered using configuration file options.
+\begin{itemize}
+\item
+\emph{Ignore POST completely}. No early code debugging is possible with
+this setting. Set the configuration variable \texttt{NO\_POST} to
+\texttt{1} to switch off all POST handling in coreboot.
+\item
+\emph{Normal IO port 80 POST}. This is the default behavior of
+coreboot. No configuration variables have to be set. To be able to see
+port 80 POST output, you need a POST expansion card for ISA or PCI. Port
+80 POST allows simple debugging without any other output method
+available (serial interface or VGA display)
+\item
+\emph{Serial POST}.
+This option allows to push POST messages to the serial interface instead
+of using IO ports. \textbf{NOTE:} The serial interface has to be
+initialized before serial POST can work. To use serial POST, set the
+configuration variable \texttt{CONFIG\_SERIAL\_POST} to the value 1.
+\end{itemize}
+
+
+\subsection{HDT Debugging}
+If you are debugging your coreboot code with a Hardware Debug Tool
+(HDT), you can find the source code line for a given physical EIP
+address as follows: Look the address up in the file linuxbios.map. Then
+search the label Lxx in the file auto.inc created by romcc. The original
+source code file and line number is mentioned in auto.inc.
+
+
+\subsection{Device Drivers}
+With only a few data structures coreboot features a simple but flexible
+device driver interface. This interface is not intended for autonomously
+driving the devices but to initialize all system components so that they
+can be used by the booted operating system.
+
+Since nowadays most systems are PCI centric, the data structures used
+are tuned towards (onboard and expansion bus) PCI devices. Each driver
+consists of at least two structures.
+
+The \texttt{pci\_driver} structure maps PCI vendor/device id pairs to a
+second structure that describes a set of functions that together
+initialize and operate the device:
+
+\begin{verbatim}
+ static void adaptec_scsi_init(struct device *dev)
+ {
+ [..]
+ }
+ static struct device_operations lsi_scsi_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = lsi_scsi_init,
+ .scan_bus = 0,
+ };
+ static const struct pci_driver lsi_scsi_driver __pci_driver = {
+ .ops = &lsi_scsi_ops,
+ .vendor = 0xXXXX,
+ .device = 0xXXXX,
+ };
+\end{verbatim}
+
+By separating the two structures above, M:N relations between compatible
+devices and drivers can be described. The driver source code containing
+above data structures and code have to be added to a coreboot image
+using the driver keyword in the mainboard specific configuration file \\
+\texttt{coreboot-v2/src/mainboard/<vendor>/<mainboard>/Config.lb}:
+
+\begin{verbatim}
+ driver lsi_scsi.o
+\end{verbatim}
+
+\subsection{Bus Bridges}
+
+Currently all bridges supported in the coreboot-v2 tree are transparent
+bridges. This means, once the bridge is initialized, it's remote devices
+are visible on one of the PCI buses without special probing. coreboot
+supports also bridges that are nontransparent. The driver support code
+can provide a \texttt{scan\_bus} function to scan devices behind the bridge.
+
+\subsection{CPU Reset}
+When changing speed and width of hypertransport chain connections
+coreboot has to either assert an LDTSTOP or a reset to make the changes
+become active. Additionally Linux can do a firmware reset, if coreboot
+provides the needed infrastructure. To use this capability, define the
+option \texttt{CONFIG\_HAVE\_HARD\_RESET} and add an object file specifying the
+reset code in your mainboard specific configuration file
+\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/Config.lb}:
+
+\begin{verbatim}
+ default CONFIG_HAVE_HARD_RESET=1
+ object reset.o
+\end{verbatim}
+
+The C source file \texttt{reset.c} (resulting in \texttt{reset.o}
+during compilation) shall define the following function to take care
+of the system reset:
+
+\begin{verbatim}
+ void hard_reset(void);
+\end{verbatim}
+
+See \texttt{coreboot-v2/src/mainboard/arima/hdama/reset.c} for an example
+implementation.
+
+\newpage
+
+%
+% 11. coreboot Internals
+%
+
+\section{coreboot Internals}
+This chapter covers some of the internal structures and algorithms of
+coreboot that have not been mentioned so far.
+
+\subsection{Code Flow}
+
+\begin{figure}[htb]
+\centering
+\includegraphics[scale=0.7]{codeflow.pdf}
+\caption{coreboot rough Code Flow}
+\label{fix:codeflow}
+\end{figure}
+
+\newpage
+
+\subsection{Fallback mechanism}
+coreboot provides a mechanism to pack two different coreboot builds
+within one coreboot ROM image. Using the system CMOS memory coreboot
+determines whether the last boot with a default image succeeded and
+boots a failsafe image on failure. This allows insystem testing without
+the risk to render the system unusable. See
+\texttt{coreboot-v2/src/mainboard/arima/hdama/failover.c} for example
+code. The fallback mechanism can be used with the \texttt{cmos\_util}.
+
+\subsection{(Un) Supported Standards}
+coreboot supports the following standards
+\begin{itemize}
+\item Multiprocessing Specification (MPSPEC) 1.4
+\item IRQ Tables (PIRQ)
+\item ACPI (initial support on AMD64)
+\item Elf Booting
+\end{itemize}
+However, the following standards are not supported until now, and will
+probably not be supported in future revisions:
+\begin{itemize}
+\item APM
+\end{itemize}
+
+\subsection{coreboot table}
+coreboot stores information about the system in a data structure called
+the coreboot table. This table can be read under Linux using the tool
+nvramtool from the Lawrence Livermore National Laboratory.
+
+Get more information about lxbios and the utility itself at
+\url{http://www.llnl.gov/linux/lxbios/lxbios.html}
+
+\subsection{ROMCC limitations}
+ROMCC, part of the coreboot project, is a C compiler that translates to
+completely rommable code. This means the resulting code does not need
+any memory to work. This is one of the major improvements in coreboot
+V2, since it allows almost all code to be written in C. DRAM
+initialization can be factored and reused more easily among mainboards
+and platforms.
+
+Since no memory is available during this early initialization point,
+romcc has to map all used variables in registers for the time being.
+Same applies for their stack usage. Generally the less registers are
+used up by the algorithms, the better code can be factored, resulting in
+a smaller object size. Since getting the best register usage is an NP
+hard problem, some heuristics are used to get reasonable translation
+time. If you run out of registers during compilation, try to refactor
+your code.
+
+\subsection{CMOS handling}
+coreboot can use the mainboard's CMOS memory to store information
+defined in a data structure called the CMOS table . This information
+contains serial line speed, fallback boot control, output verbosity,
+default boot device, ECC control, and more. It can be easily enhanced by
+enhancing the CMOS table. This table, if present, is found at
+\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/cmos.layout}.
+It describes the available options, their possible values and their
+position within the CMOS memory. The layout file looks as follows:
+\begin{verbatim}
+ # startbit length config configID name
+ [..]
+ 392 3 e 5 baud_rate
+ [..]
+
+ # configid value human readable description
+ 5 0 115200
+ 5 1 57600
+ 5 2 38400
+ 5 3 19200
+ 5 4 9600
+ 5 5 4800
+ 5 6 2400
+ 5 7 1200
+
+\end{verbatim}
+
+To change CMOS values from a running Linux system, use the
+\texttt{cmos\_util}, provided by Linux Networks as part of the coreboot
+utilities suite. Get it at
+\textit{ftp://ftp.lnxi.com/pub/linuxbios/utilities/}
+
+\subsection {Booting Payloads}
+coreboot can load a payload binary from a Flash device or IDE. This
+payload can be a boot loader, like FILO or Etherboot, a kernel image, or
+any other static ELF binary. If you specify a bzImage as the payload,
+the cbfs utility will figure out how to create a coreboot payload from it.
+
+\subsection{Kernel on dhcp/tftp}
+
+One possible scenario during testing is that you keep your kernel (or
+any additional payload) on a different machine on the network. This can
+quickly be done using a DHCP and TFTP server.
+
+Use for example following \texttt{/etc/dhcpd.conf} (adapt to your
+network):
+
+\begin{verbatim}
+ subnet 192.168.1.0 netmask 255.255.255.0 {
+ range 192.168.1.0 192.168.1.31;
+ option broadcastaddress 192.168.1.255;
+ }
+
+ ddnsupdatestyle adhoc;
+
+ host hammer12 {
+ hardware ethernet 00:04:76:EA:64:31;
+ fixedaddress 192.168.1.24;
+ filename "vmlinuz.elf";
+ }
+\end{verbatim}
+
+
+Additionally you have to run a \texttt{tftp} server. You can start one
+using \texttt{inetd}. To do this, you have to remove the comment from
+the following line in \texttt{/etc/inetd.conf}:
+
+\begin{verbatim}
+ tftp dgram udp wait root /usr/sbin/in.tftpd in.tftpd -s /tftpboot
+\end{verbatim}
+
+Then put your kernel image \texttt{vmlinuz.elf} in \texttt{/tftpboot} on
+the \texttt{tftp} server.
+
+
+\newpage
+
+%
+% 12. Advanced Device Initialization Mechanisms
+%
+
+\section{Advanced Device Initialization Mechanisms}
+
+Like software, today's hardware is getting more and more complex. To
+stay flexible many hardware vendors start breaking hardware
+compatibility to old standards like VGA. Thus, VGA is still supported by
+most cards, but emulation has to be enabled by the firmware for the
+device to operate properly. Also, many expansion cards are small
+discrete systems that have to initialize attached ram, download
+controller firmware and similar. Without this initialization, an
+operating system can not take advantage of the hardware, so there needs
+to be a way to address this issue. There are several alternatives:
+
+\subsection{Native coreboot Support}
+
+For some devices (ie Trident Cyberblade 3d) there is native coreboot
+support This means there is a small driver bound to the PCI id of the
+device that is called after PCI device ressources are allotted.
+
+PROs:
+ \begin{itemize}
+ \item open source
+ \item minimal driver
+ \item early control
+ \end{itemize}
+
+CONs:
+ \begin{itemize}
+ \item need an additional driver
+ \item viable for onboard devices only
+ \item not flexible for pci cards
+ \end{itemize}
+
+\subsection{Using Native Linux Support}
+
+A simple way of getting a whole lot of drivers available for coreboot
+is to reuse Linux drivers by putting a Linux kernel to flash. This
+works, because no drivers are needed to get the Linux kernel (as opposed
+to store the kernel on a harddisk connected to isa/scsi/raid storage)
+
+PROs:
+ \begin{itemize}
+ \item large number of open source drivers
+ \end{itemize}
+
+CONs:
+ \begin{itemize}
+ \item need Linux in Flash (BLOAT!)
+ \item drivers expect devices to be initialized (LSI1020/1030)
+ \item Linux only
+ \item large flash needed (4MBit minimum, normal operations 8+ MBit)
+ \end{itemize}
+
+
+\subsection{Running X86 Option ROMs}
+
+Especially SCSI/RAID controllers and graphics adapters come with a
+special option rom. This option rom usually contains x86 binary code
+that uses a legacy PCBIOS interface for device interaction. If this code
+gets executed, the device becomes operable in Linux and other operating
+systems.
+
+PROs:
+ \begin{itemize}
+ \item really flexible
+ \item no need for additional drivers on firmware layer
+ \item large number of supported devices
+ \end{itemize}
+
+CONs:
+ \begin{itemize}
+ \item non-x86 platforms need complex emulation
+ \item x86 platforms need legacy API
+ \item outdated concept
+ \end{itemize}
+
+
+\subsection{Running Open Firmware Option ROMs}
+
+Some PCI devices come with open firmware option roms. These devices are
+normally found in computers from SUN, Apple or IBM. Open Firmware is a
+instruction set architecture independent firmware standard that allows
+device specific initialization using simple, small, but flexible
+bytecode that runs with minimal footprint on all architectures that have
+an Open Firmware implementation.
+
+There is a free Open Firmware implementation available, called OpenBIOS,
+that runs on top of coreboot. See www.openbios.org
+
+PROs:
+ \begin{itemize}
+ \item architecture independence
+ \item small footprint
+ \item clean concept, less bugs
+ \end{itemize}
+
+CONs:
+ \begin{itemize}
+ \item only small number of devices come with OpenFirmware capable option roms
+ \end{itemize}
+
+%
+% 13 image types
+%
+
+\section{Image types}
+There used to be one image type for coreboot, as described above. Since this paper was written (2004) there have been many changes. First, the name
+was changed to coreboot, for many reasons. Second, Cache As Ram support (CAR)
+was added for many AMD CPUs, which both simplified and complicated things. Simplification came with the removal of romcc; complication came with the addition of new ways to build.
+
+There are two big additions to the build process and, furthermore, more than two new CONFIG variables to control them.
+
+\begin{itemize}
+\item \begin{verbatim}CONFIG_USE_DCACHE_RAM\end{verbatim}
+
+Set to \texttt{1} to use Cache As Ram (CAR). Defaults to \texttt{0}
+
+\end{itemize}
+
+Before going over the new image types, derived from v3, we will quickly review the standard v2 image types. We are hoping this review will
+aid comprehension.
+
+A coreboot rom file consists of one or more \textit{images}. All images consist of a part that runs in ROM, and a part that runs in RAM. The RAM can be in compressed form and is decompressed when needed by the ROM code. The main function of the ROM code is to get memory working. Both ROM and RAM consist of a very small amount of assembly code and mostly C code.
+
+\subsection{romcc images (from emulation/qemu)}
+ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only
+one file; to get more than one file, one must include the C code via include statements. The main ROM code .c file is usually called auto.c.
+\subsubsection{How it is built}
+Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CONFIG\_CRT0\_INCLUDES variable. crt0.s is then assembled.
+
+File for the ram part are compiled in a conventional manner.
+
+The final step is linking. The use of named sections is used very heavily in coreboot to control where different bits of code go. The reset vector must go in the top 16 bytes. The start portion of the ROM code must go in the top 64K bytes, since most chipsets only enable this much ROM at startup time. Here is a quick look at a typical image:
+\begin{verbatim}
+ [Nr] Name Type Addr Off Size ES Flg Lk Inf Al
+ [ 0] NULL 00000000 000000 000000 00 0 0 0
+ [ 1] .ram PROGBITS ffff0000 001000 005893 00 WA 0 0 1
+ [ 2] .rom PROGBITS ffff5893 006893 00029d 00 AX 0 0 16
+ [ 3] .reset PROGBITS fffffff0 006ff0 000010 00 A 0 0 1
+ [ 4] .id PROGBITS ffffffd1 006fd1 00001f 00 A 0 0 1
+ [ 5] .shstrtab STRTAB 00000000 007000 000030 00 0 0 1
+ [ 6] .symtab SYMTAB 00000000 007170 000c30 10 7 37 4
+ [ 7] .strtab STRTAB 00000000 007da0 000bfd 00 0 0 1
+\end{verbatim}
+
+The only sections that get loaded into a ROM are the Allocated ones. We can see the .ram, .rom, .reset and .id sections.
+\subsubsection{layout}
+As we mentioned, the ROM file consists of multiple images. In the basic file, there are two full coreboot rom images. The build sequence for each is the same, and in fact the ldscript.ld files are almost identical. The only difference is in a few makefile variables, generated by the config tool.
+
+\begin{itemize}
+\item CONFIG\_PAYLOAD\_SIZE. Each image may have a different payload size.
+\item CONFIG\_ROMBASE Each image must have a different base in rom.
+\item CONFIG\_RESET Unclear what this is used for.
+\item CONFIG\_EXCEPTION\_VECTORS where an optional IDT might go.
+\item CONFIG\_USE\_OPTION\_TABLE if set, an option table section will be linked in.
+\item CONFIG\_ROM\_PAYLOAD\_START This is the soon-to-be-deprecated way of locating a payload. cbfs eliminates this.
+\item CONFIG\_USE\_FALLBACK\_IMAGE Whether this is a fallback or normal image
+\item CONFIG\_ROM\_SECTION\_SIZE Essentially, the payload size. Soon to be deprecated.
+\item CONFIG\_ROM\_IMAGE\_SIZE Size of this image (i.e. fallback or normal image)
+\item CONFIG\_ROM\_SIZE Total size of the ROM
+\item CONFIG\_XIP\_RAM\_BASE The start of eXecute In Place code. XIP allows for not copying code to ram, but just running it from ROM.
+\end{itemize}
+
+Each image (normal or fallback) is built completely independently and does not get linked to the other. They are assembled into one ROM image by the (soon to be deprecated) buildrom tool, or by the cbfs tool.
+
+\subsubsection{boot sequence}
+We boot and start at fffffff0. We then jump to the entry point at \_start. \_start does some machine init and an lgdt and jumps to \_\_protected\_start, at which point we are in protected mode. The code does a bit more machine setup and then starts executing the romcc code.
+
+If fallback has been built in, some setup needs to be done. On some machines, it is extensive. Full rom decoding must be enabled. This may in turn require additional PCI setup to enable decoding to be enabled (!). To decided which image to use, hardware registers (cold boot on the Opteron) or CMOS are checked. Finally, once the image to use has been decided, a jmp is performed, viz:
+\begin{verbatim}
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ normal_image:
+ __asm__ volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+ );
+
+ fallback_image:
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+ __asm__ volatile ("jmp __fallback_image"
+ : /* outputs */
+ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+ )
+#endif
+ ;
+\end{verbatim}
+How does the fallback image get the symbol for normal entry? Via magic in the ldscript.ld -- remember, the images are not linked to each other.
+Finally, we can see this in the Config.lb for most mainboards:
+\begin{verbatim}
+if CONFIG_USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+\end{verbatim}
+What does this mean? the non-fallback image has a 32-bit entry point; fallback has a 16-bit entry point. The reason for this is that some code from fallback always runs, so as to pick fallback or normal; but the normal is always called from 32-bit code.
+\subsection{car images (from lippert/roadrunner-lx)}
+CAR images in their simplest form are modified romcc images. The file is usually cache\_as\_ram\_auto.c. C inclusion is still used. The main difference is in the build sequence. The compiler command line is a very slight changed: instead of using romcc to generate an auto.inc include file, gcc us used. Then, two perl scripts are used to rename the .text and .data sections to .rom.text and .rom.data respectively.
+\subsubsection{How it is built}
+The build is almost identical to the romcc build. Since the auto.inc file exists, it can be included as before. The crt0\_includes.h file has one addition: a file that enables CAR, in this case it is \textit{src/cpu/amd/model\_lx/cache\_as\_ram.inc}.
+\subsubsection{layout}
+No significant change from romcc code.
+\subsubsection{boot sequence}
+No significant change from romcc code, except that the CAR code has to set up a stack.
+
+\subsection{car + CONFIG\_USE\_INIT images (new emulation/qemu}
+This type of image makes more use of the C compiler. In this type of image, in fact,
+seperate compilation is possible but is not always used. Oddly enough, this option is only used in PPC boards. That said, we need to move to this way of building. Including C code is poor style.
+\subsubsection{How it is built}
+There is a make variable, INIT-OBJECTS, that for all our other targets is empty. In this type of build, INIT-OBJECTS is a list of C files that are created from the config tool initobject command. Again, with INIT-OBJECTS we can finally stop including .c files and go with seperate compilation.
+\subsubsection{layout}
+No significant change from romcc code.
+\subsubsection{boot sequence}
+No significant change from romcc code, except that the CAR code has to set up a stack.
+
+\subsubsection{layout}
+No significant change from romcc code.
+\subsubsection{boot sequence}
+No significant change from romcc code, except that the CAR code has to set up a stack.
+\subsection{failover}
+Failover is the newest way to lay out a ROM. The choice of which image to run is removed from the fallback image and moved into a small, standalone piece of code. The code is simple enough to show here:
+\begin{verbatim}
+static unsigned long main(unsigned long bist)
+{
+ if (do_normal_boot())
+ goto normal_image;
+ else
+ goto fallback_image;
+
+normal_image:
+ __asm__ __volatile__("jmp __normal_image" : : "a" (bist) : );
+
+cpu_reset:
+ __asm__ __volatile__("jmp __cpu_reset" : : "a" (bist) : );
+
+fallback_image:
+ return bist;
+}
+
+\end{verbatim}
+Some motherboards have a more complex bus structure (e.g. Opteron). In those cases, the failover can be more complex, as it requires some hardware initialization to work correctly. As of this writing (April 2009), these boards have their own failover:
+\begin{quote}
+./src/mainboard/iei/nova4899r/failover.c
+./src/mainboard/emulation/qemu-x86/failover.c
+./src/mainboard/supermicro/x6dhr\_ig/failover.c
+./src/mainboard/supermicro/x6dai\_g/failover.c
+./src/mainboard/supermicro/x6dhe\_g2/failover.c
+./src/mainboard/supermicro/x6dhr\_ig2/failover.c
+./src/mainboard/supermicro/x6dhe\_g/failover.c
+./src/mainboard/dell/s1850/failover.c
+./src/mainboard/intel/xe7501devkit/failover.c
+./src/mainboard/intel/jarrell/failover.c
+./src/mainboard/olpc/btest/failover.c
+./src/mainboard/olpc/rev\_a/failover.c
+./src/mainboard/via/epia-m/failover.c
+\end{quote}
+Here is one of the more complicated ones:
+\begin{verbatim}
+static unsigned long main(unsigned long bist)
+{
+ /* Did just the cpu reset? */
+ if (memory_initialized()) {
+ if (last_boot_normal()) {
+ goto normal_image;
+ } else {
+ goto cpu_reset;
+ }
+ }
+
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
+}
+
+\end{verbatim}
+They're not that different, in fact. So why are there different copies all over the tree? Simple: code inclusion. Most of the failover.c are different because they include different bits of code. Here is a key reason for killing C code inclusion in the tree.
+\subsubsection{How it is built}
+There two additional config variables:
+\begin{itemize}
+\item HAVE\_FAILOVER\_IMAGE Has to be defined when certain files are included.
+\item USE\_FAILOVER\_IMAGE Enables the use of the failover image
+\end{itemize}
+Confusingly enough, almost all the uses of these two variables are either nested or both required to be set, e.g.
+The fallback and normal builds are the same. The target config has a new clause that looks like this:
+\begin{verbatim}
+romimage "failover"
+ option CONFIG_USE_FAILOVER_IMAGE=1
+ option CONFIG_USE_FALLBACK_IMAGE=0
+ option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+ option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
+ option COREBOOT_EXTRA_VERSION="\$(shell cat ../../VERSION)\_Failover"
+end
+\end{verbatim}
+This new section uses some constructs not yet discussed in detail. XIP\_ROM\_SIZE just refers to the
+fact that the failover code is eXecute In Place, i.e. not copied to RAM. Of course, the ROM part of normal/fallback is as well, so the usage of XIP here is somewhat confusing. Finally, the USE\_FAILOVER\_IMAGE variable is set, which changes code compilation in a few places. If we just consider non-mainbard files, there are:
+\begin{verbatim}
+src/cpu/amd/car/cache_as_ram.inc
+src/arch/i386/Config.lb
+\end{verbatim}
+For the cache\_as\_ram.inc file, the changes relate to the fact that failover code sets up CAR, so that fallback code need not.
+
+For the Config.lb, several aspects of build change.
+When USE\_FAILOVER\_IMAGE, entry into both normal and fallback bios images is via a 32-bit entry point (when not defined, entry into fallback is a 16-entry point at the power-on reset vector).
+\subsubsection{layout}
+Failover.c becomes the new bootblock at the top of memory. It calls either normal or fallback. The address of normal and fallback is determined by ldscript magic.
+\subsubsection{boot sequence}
+failover.c tests a few variables and the calls the normal or fallback payload depending on those variables; usually they are CMOS settings.
+\subsection{Proposed new image forat}
+The new image format will use seperate compilation -- no C code included! -- on all files.
+
+The new design has a few key goals:
+\begin{itemize}
+\item Always use a bootblock (currently called failover).
+The name failover.c, being utterly obscure, will not be used; instead, we will name the file bootblock.c. Instead of having a different copy for each mainboard, we can have just one copy.
+\item Always use seperate compilation
+\item Always use printk etc. in the ROM code
+\item (longer term) from the bootblock, always use cbfs to locate the normal/fallback etc. code. This code will be XIP.
+\end{itemize}
+
+\subsubsection{How it is built}
+For now, since we are still using the config tool, we'll need a new command: bootblockobject, which creates a list of files to be included in the bootblock. Not a lot else will have to change. We are going to move to using the v3 CAR code assembly code (one or two files at most, instead of many) and, instead of the thicket of little ldscript files, one ldscript file. This strategy is subject to modification as events dictate.
+\subsubsection{layout}
+Almost the same, for now, as the current failover code.
+\subsubsection{boot sequence}
+%
+% 14 Glossary
+%
+
+\section{Glossary}
+\begin{itemize}
+\item payload
+
+coreboot only cares about low level machine initialization, but also has
+very simple mechanisms to boot a file either from FLASHROM or IDE. That
+file, possibly a Linux Kernel, a boot loader or Etherboot, are called
+payload, since it is the first software executed that does not cope with
+pure initialization.
+
+\item flash device
+
+Flash devices are commonly used in all different computers since unlike
+ROMs they can be electronically erased and reprogrammed.
+\end{itemize}
+
+\newpage
+
+%
+% 14 Bibliography
+%
+
+\section{Bibliography}
+\subsection{Additional Papers on coreboot}
+
+\begin{itemize}
+ \item
+ \textit{\url{http://www.coreboot.org/Documentation}}
+ \item
+ \textit{\url{http://www.lysator.liu.se/upplysning/fa/linuxbios.pdf}}
+ \item
+ \textit{\url{http://portal.acm.org/citation.cfm?id=512627}}
+\end{itemize}
+
+\subsection {Links}
+
+\begin{itemize}
+ \item Etherboot: \textit{\url{http://www.etherboot.org/}}
+ \item Filo: \textit{\url{http://www.coreboot.org/FILO}}
+ \item OpenBIOS: \textit{\url{http://www.openbios.org/}}
+\end{itemize}
+
+\end{document}
diff --git a/Documentation/Doxyfile.coreboot b/Documentation/Doxyfile.coreboot
new file mode 100644
index 0000000..e6c06fe
--- /dev/null
+++ b/Documentation/Doxyfile.coreboot
@@ -0,0 +1,1639 @@
+# Doxyfile 1.7.1
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project
+#
+# All text after a hash (#) is considered a comment and will be ignored
+# The format is:
+# TAG = value [value, ...]
+# For lists items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ")
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+# by quotes) that should identify the project.
+
+PROJECT_NAME = coreboot
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY = doxygen
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 4096 sub-directories (in 2 levels) under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of
+# source files, where putting all generated files in the same directory would
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is
+# used as the annotated text. Otherwise, the brief description is used as-is.
+# If left blank, the following values are used ("$name" is automatically
+# replaced with the name of the entity): "The $name class" "The $name widget"
+# "The $name file" "is" "provides" "specifies" "contains"
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF =
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC = YES
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES = YES
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip.
+
+STRIP_FROM_PATH =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful is your file systems
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like regular Qt-style comments
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF = YES
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
+# interpret the first line (until the first dot) of a Qt-style
+# comment as the brief description. If set to NO, the comments
+# will behave just like regular Qt-style comments (thus requiring
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
+# a new page for each member. If set to NO, the documentation of a member will
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
+# sources only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
+# sources only. Doxygen will then generate output that is more tailored for
+# Java. For instance, namespaces will be presented as packages, qualified
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources only. Doxygen will then generate output that is more tailored for
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given extension.
+# Doxygen has a built-in mapping, but you can override or extend it using this
+# tag. The format is ext=language, where ext is a file extension, and language
+# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C,
+# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make
+# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C
+# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions
+# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
+
+EXTENSION_MAPPING =
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should
+# set this tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
+# func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+
+CPP_CLI_SUPPORT = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
+# Doxygen will parse them like normal C++ but will assume all classes use public
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate getter
+# and setter methods for a property. Setting this option to YES (the default)
+# will make doxygen to replace the get and set methods by a property in the
+# documentation. This will only work if the methods are indeed getting or
+# setting a simple type. If this is not the case, or you want to show the
+# methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING = YES
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
+# is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically
+# be useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT = NO
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
+# determine which symbols to keep in memory and which to flush to disk.
+# When the cache is full, less often used symbols will be written to disk.
+# For small to medium size projects (<1000 input files) the default value is
+# probably good enough. For larger projects a too small cache size can cause
+# doxygen to be busy swapping symbols to and from disk most of the time
+# causing a significant performance penality.
+# If the system has enough physical memory increasing the cache will improve the
+# performance by keeping more symbols in memory. Note that the value works on
+# a logarithmic scale so increasing the size by one will rougly double the
+# memory usage. The cache size is given by this formula:
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols
+
+SYMBOL_CACHE_SIZE = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+
+EXTRACT_ALL = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC = YES
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base
+# name of the file that contains the anonymous namespace. By default
+# anonymous namespace are hidden.
+
+EXTRACT_ANON_NSPACES = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
+# will list include files with double quotes in the documentation
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
+# will sort the (brief and detailed) documentation of class members so that
+# constructors and destructors are listed first. If set to NO (the default)
+# the constructors will appear in the respective orders defined by
+# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
+# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
+# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
+# hierarchy of group names into alphabetical order. If set to NO (the default)
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or define consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and defines in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES = YES
+
+# If the sources in your project are distributed over multiple directories
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
+# in the documentation. The default is NO.
+
+SHOW_DIRECTORIES = YES
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
+# This will remove the Files entry from the Quick Index and from the
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
+# Namespaces page.
+# This will remove the Namespaces entry from the Quick Index
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command <command> <input-file>, where <command> is the value of
+# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file
+# provided by doxygen. Whatever the program writes to standard output
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. The create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option.
+# You can optionally specify a file name after the option, if omitted
+# DoxygenLayout.xml will be used as the name of the layout file.
+
+LAYOUT_FILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET = YES
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR = YES
+
+# This WARN_NO_PARAMDOC option can be abled to get warnings for
+# functions that are documented, but have no documentation for their parameters
+# or return value. If set to NO (the default) doxygen will only warn about
+# wrong or incomplete parameter documentation, but not about the absence of
+# documentation.
+
+WARN_NO_PARAMDOC = YES
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text. Optionally the format may contain
+# $version, which will be replaced by the version of the file (if it could
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT = .
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
+# also the default input encoding. Doxygen uses libiconv (or the iconv built
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
+# the list of possible encodings.
+
+INPUT_ENCODING = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx
+# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90
+
+FILE_PATTERNS =
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE = YES
+
+# The EXCLUDE tag can be used to specify files and/or directories that should
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+
+EXCLUDE = util/romcc/tests \
+ util/vgabios \
+ util/abuild \
+ util/kconfig \
+ payloads
+
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
+# directories that are symbolic links (a Unix filesystem feature) are excluded
+# from the input.
+
+EXCLUDE_SYMLINKS = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories. Note that the wildcards are matched
+# against the file with absolute path, so to exclude all test directories
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command <filter> <input-file>, where <filter>
+# is the value of the INPUT_FILTER tag, and <input-file> is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output.
+# If FILTER_PATTERNS is specified, this tag will be
+# ignored.
+
+INPUT_FILTER =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis.
+# Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match.
+# The filters are a list of the form:
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
+# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
+# is applied to all files.
+
+FILTER_PATTERNS =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER = YES
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C and C++ comments will always remain visible.
+
+STRIP_CODE_COMMENTS = NO
+
+# If the REFERENCED_BY_RELATION tag is set to YES
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = YES
+
+# If the REFERENCES_RELATION tag is set to YES
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION = YES
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
+# link to the source code.
+# Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code
+# will point to the HTML generated by the htags(1) tool instead of doxygen
+# built-in source browser. The htags tool is part of GNU's global source
+# tagging system (see http://www.gnu.org/software/global/global.html). You
+# will need version 4.8.6 or higher.
+
+USE_HTAGS = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS = YES
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX = YES
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header.
+
+HTML_HEADER =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER =
+
+# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will
+# add generated date, project name and doxygen version to HTML footer.
+
+HTML_FOOTER_DESCRIPTION= YES
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If the tag is left blank doxygen
+# will generate a default style sheet. Note that doxygen will try to copy
+# the style sheet file to the HTML output directory, so don't put your own
+# stylesheet in the HTML output directory as well, or it will be erased!
+
+HTML_STYLESHEET =
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
+# Doxygen will adjust the colors in the stylesheet and background images
+# according to this color. Hue is specified as an angle on a colorwheel,
+# see http://en.wikipedia.org/wiki/Hue for more information.
+# For instance the value 0 represents red, 60 is yellow, 120 is green,
+# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
+# The allowed range is 0 to 359.
+
+HTML_COLORSTYLE_HUE = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
+# the colors in the HTML output. For a value of 0 the output will use
+# grayscales only. A value of 255 will produce the most vivid colors.
+
+HTML_COLORSTYLE_SAT = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
+# the luminance component of the colors in the HTML output. Values below
+# 100 gradually make the output lighter, whereas values above 100 make
+# the output darker. The value divided by 100 is the actual gamma applied,
+# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
+# and 100 does not change the gamma.
+
+HTML_COLORSTYLE_GAMMA = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP = NO
+
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
+# files or namespaces will be aligned in HTML using tables. If set to
+# NO a bullet list will be used.
+
+HTML_ALIGN_MEMBERS = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded. For this to work a browser that supports
+# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
+# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
+
+HTML_DYNAMIC_SECTIONS = NO
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files
+# will be generated that can be used as input for Apple's Xcode 3
+# integrated development environment, introduced with OSX 10.5 (Leopard).
+# To create a documentation set, doxygen will generate a Makefile in the
+# HTML output directory. Running make will produce the docset in that
+# directory and running "make install" will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
+# it at startup.
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+
+GENERATE_DOCSET = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
+# feed. A documentation feed provides an umbrella under which multiple
+# documentation sets from a single provider (such as a company or product suite)
+# can be grouped.
+
+DOCSET_FEEDNAME = "Doxygen documentation"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
+# should uniquely identify the documentation set bundle. This should be a
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID = org.doxygen.Project
+
+# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+
+DOCSET_PUBLISHER_ID = org.doxygen.Publisher
+
+# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
+
+DOCSET_PUBLISHER_NAME = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file
+# content.
+
+CHM_INDEX_ENCODING =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
+# that can be used as input for Qt's qhelpgenerator to generate a
+# Qt Compressed Help (.qch) of the generated HTML documentation.
+
+GENERATE_QHP = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
+# be used to specify the file name of the resulting .qch file.
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
+# add. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME =
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see
+# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters">
+# Qt Help Project / Custom Filters</a>.
+
+QHP_CUST_FILTER_ATTRS =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's
+# filter section matches.
+# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes">
+# Qt Help Project / Filter Attributes</a>.
+
+QHP_SECT_FILTER_ATTRS =
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
+# be used to specify the location of Qt's qhelpgenerator.
+# If non-empty doxygen will try to run qhelpgenerator on the generated
+# .qhp file.
+
+QHG_LOCATION =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
+# will be generated, which together with the HTML files, form an Eclipse help
+# plugin. To install this plugin and make it available under the help contents
+# menu in Eclipse, the contents of the directory containing the HTML and XML
+# files needs to be copied into the plugins directory of eclipse. The name of
+# the directory within the plugins directory should be the same as
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
+# the help appears.
+
+GENERATE_ECLIPSEHELP = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have
+# this name.
+
+ECLIPSE_DOC_ID = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
+# top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it.
+
+DISABLE_INDEX = NO
+
+# This tag can be used to set the number of enum values (range [1..20])
+# that doxygen will group on one line in the generated HTML documentation.
+
+ENUM_VALUES_PER_LINE = 4
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information.
+# If the tag value is set to YES, a side panel will be generated
+# containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
+# Windows users are probably better off using the HTML help feature.
+
+GENERATE_TREEVIEW = YES
+
+# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
+# and Class Hierarchy pages using a tree view instead of an ordered list.
+
+USE_INLINE_TREES = YES
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH = 250
+
+# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
+# links to external symbols imported via tag files in a separate window.
+
+EXT_LINKS_IN_WINDOW = NO
+
+# Use this tag to change the font size of Latex formulas included
+# as images in the HTML documentation. The default is 10. Note that
+# when you change the font size after a successful doxygen run you need
+# to manually remove any form_*.png images from the HTML output directory
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are
+# not supported properly for IE 6.0, but are supported on all modern browsers.
+# Note that when changing this option you need to delete any form_*.png files
+# in the HTML output before the changes have effect.
+
+FORMULA_TRANSPARENT = YES
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box
+# for the HTML output. The underlying search engine uses javascript
+# and DHTML and should work on any modern browser. Note that when using
+# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
+# (GENERATE_DOCSET) there is already a search function so this one should
+# typically be disabled. For large projects the javascript based search engine
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a PHP enabled web server instead of at the web client
+# using Javascript. Doxygen will generate the search PHP script and index
+# file to put on the web server. The advantage of the server
+# based approach is that it scales better to large projects and allows
+# full text search. The disadvances is that it is more difficult to setup
+# and does not have live searching capabilities.
+
+SERVER_BASED_SEARCH = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+# Note that when enabling USE_PDFLATEX this option is only used for
+# generating bitmaps for formulas in the HTML output, but not in the
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, a4wide, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE = a4wide
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS = NO
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX = NO
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include
+# source code with syntax highlighting in the LaTeX output.
+# Note that which sources are shown also depends on other settings
+# such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
+# programs which support those fields.
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's
+# config file, i.e. a series of assignments. You only have to provide
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_SCHEMA =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
+# documentation. Note that this feature is still experimental
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
+# the code including all documentation. Note that this
+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader.
+# This is useful
+# if you want to understand what is going on.
+# On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY = YES
+
+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
+# This is useful so different doxyrules.make files included by the same
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
+# files.
+
+ENABLE_PREPROCESSING = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
+# names in the source code. If set to NO (the default) only conditional
+# compilation will be performed. Macro expansion can be done in a controlled
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF = NO
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
+# in the INCLUDE_PATH (see below) will be search if a #include is found.
+
+SEARCH_INCLUDES = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by
+# the preprocessor.
+
+INCLUDE_PATH =
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will
+# be used.
+
+INCLUDE_FILE_PATTERNS =
+
+# The PREDEFINED tag can be used to specify one or more macro names that
+# are defined before the preprocessor is started (similar to the -D option of
+# gcc). The argument of the tag is a list of macros of the form: name
+# or name=definition (no spaces). If the definition and the = are
+# omitted =1 is assumed. To prevent a macro definition from being
+# undefined via #undef or recursively expanded use the := operator
+# instead of the = operator.
+
+PREDEFINED =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
+# this tag can be used to specify a list of macro names that should be expanded.
+# The macro definition that is found in the sources will be used.
+# Use the PREDEFINED tag if you want to use a different macro definition.
+
+EXPAND_AS_DEFINED =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
+# doxygen's preprocessor will remove all function-like macros that are alone
+# on a line, have an all uppercase name, and do not end with a semicolon. Such
+# function macros are typically used for boiler-plate code, and will confuse
+# the parser if not removed.
+
+SKIP_FUNCTION_MACROS = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES option can be used to specify one or more tagfiles.
+# Optionally an initial location of the external documentation
+# can be added for each tagfile. The format of a tag file without
+# this location is as follows:
+#
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+#
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where "loc1" and "loc2" can be relative or absolute paths or
+# URLs. If a location is present for each tag, the installdox tool
+# does not have to be run to correct the links.
+# Note that each tag file must have a unique name
+# (where the name does NOT include the path)
+# If a tag file is not located in the directory in which doxygen
+# is run, you must also specify the path to the tagfile here.
+
+TAGFILES =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE =
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed
+# in the class index. If set to NO only the inherited external classes
+# will be listed.
+
+ALLEXTERNALS = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will
+# be listed.
+
+EXTERNAL_GROUPS = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
+# or super classes. Setting the tag to NO turns the diagrams off. Note that
+# this option is superseded by the HAVE_DOT option below. This is only a
+# fallback. It is recommended to install and use dot, since it yields more
+# powerful graphs.
+
+CLASS_DIAGRAMS = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH =
+
+# If set to YES, the inheritance and collaboration graphs will hide
+# inheritance and usage relations if the target is undocumented
+# or is not a class.
+
+HIDE_UNDOC_RELATIONS = NO
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz, a graph visualization
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT = YES
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
+# allowed to run in parallel. When set to 0 (the default) doxygen will
+# base this on the number of processors available in the system. You can set it
+# explicitly to a value larger than 0 to get control over the balance
+# between CPU load and processing speed.
+
+DOT_NUM_THREADS = 0
+
+# By default doxygen will write a font called FreeSans.ttf to the output
+# directory and reference it in all dot files that doxygen generates. This
+# font does not include all possible unicode characters however, so when you need
+# these (or just want a differently looking font) you can specify the font name
+# using DOT_FONTNAME. You need need to make sure dot is able to find the font,
+# which can be done by putting it in a standard location or by setting the
+# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
+# containing the font.
+
+DOT_FONTNAME = FreeSans
+
+# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
+# The default size is 10pt.
+
+DOT_FONTSIZE = 10
+
+# By default doxygen will tell dot to use the output directory to look for the
+# FreeSans.ttf font (which doxygen will put there itself). If you specify a
+# different font using DOT_FONTNAME you can set the path where dot
+# can find it using this tag.
+
+DOT_FONTPATH =
+
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect inheritance relations. Setting this tag to YES will force the
+# the CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect implementation dependencies (inheritance, containment, and
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH = YES
+
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for groups, showing the direct groups dependencies
+
+GROUP_GRAPHS = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+
+UML_LOOK = YES
+
+# If set to YES, the inheritance and collaboration graphs will show the
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
+# tags are set to YES then doxygen will generate a graph for each documented
+# file showing the direct and indirect include dependencies of the file with
+# other documented files.
+
+INCLUDE_GRAPH = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
+# documented header file showing the documented files that directly or
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH = YES
+
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then
+# doxygen will generate a call dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable call graphs
+# for selected functions only using the \callgraph command.
+
+CALL_GRAPH = YES
+
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
+# doxygen will generate a caller dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable caller
+# graphs for selected functions only using the \callergraph command.
+
+CALLER_GRAPH = YES
+
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
+# will graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY = YES
+
+# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
+# then doxygen will show the dependencies a directory has on other directories
+# in a graphical way. The dependency relations are determined by the #include
+# relations between the files in the directories.
+
+DIRECTORY_GRAPH = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. Possible values are png, jpg, or gif
+# If left blank png will be used.
+
+DOT_IMAGE_FORMAT = png
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+
+DOT_PATH =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the
+# \dotfile command).
+
+DOTFILE_DIRS =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
+# nodes that will be shown in the graph. If the number of nodes in a graph
+# becomes larger than this value, doxygen will truncate the graph, which is
+# visualized by representing a node as a red box. Note that doxygen if the
+# number of direct children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+
+DOT_GRAPH_MAX_NODES = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
+# graphs generated by dot. A depth value of 3 means that only nodes reachable
+# from the root by following a path via at most 3 edges will be shown. Nodes
+# that lay further from the root node will be omitted. Note that setting this
+# option to 1 or 2 may greatly reduce the computation time needed for large
+# code bases. Also note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+
+MAX_DOT_GRAPH_DEPTH = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not
+# seem to support this out of the box. Warning: Depending on the platform used,
+# enabling this option may lead to badly anti-aliased labels on the edges of
+# a graph (i.e. they become hard to read).
+
+DOT_TRANSPARENT = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10)
+# support this, this feature is disabled by default.
+
+DOT_MULTI_TARGETS = YES
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
+# generate a legend page explaining the meaning of the various boxes and
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
+# remove the intermediate dot files that are used to generate
+# the various graphs.
+
+DOT_CLEANUP = YES
diff --git a/Documentation/Doxyfile.coreboot_simple b/Documentation/Doxyfile.coreboot_simple
new file mode 100644
index 0000000..2135d96
--- /dev/null
+++ b/Documentation/Doxyfile.coreboot_simple
@@ -0,0 +1,259 @@
+# Doxyfile 1.8.8
+DOXYFILE_ENCODING = UTF-8
+PROJECT_NAME = coreboot
+PROJECT_NUMBER =
+PROJECT_BRIEF = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers."
+PROJECT_LOGO = documentation/coreboot_logo.png
+OUTPUT_DIRECTORY = doxygen
+CREATE_SUBDIRS = YES
+ALLOW_UNICODE_NAMES = NO
+OUTPUT_LANGUAGE = English
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF =
+ALWAYS_DETAILED_SEC = YES
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = YES
+STRIP_FROM_PATH =
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = YES
+QT_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS = YES
+SEPARATE_MEMBER_PAGES = NO
+TAB_SIZE = 8
+ALIASES =
+TCL_SUBST =
+OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_JAVA = NO
+OPTIMIZE_FOR_FORTRAN = NO
+OPTIMIZE_OUTPUT_VHDL = NO
+EXTENSION_MAPPING =
+MARKDOWN_SUPPORT = YES
+AUTOLINK_SUPPORT = YES
+BUILTIN_STL_SUPPORT = NO
+CPP_CLI_SUPPORT = NO
+SIP_SUPPORT = NO
+IDL_PROPERTY_SUPPORT = YES
+DISTRIBUTE_GROUP_DOC = NO
+SUBGROUPING = YES
+INLINE_GROUPED_CLASSES = NO
+INLINE_SIMPLE_STRUCTS = NO
+TYPEDEF_HIDES_STRUCT = NO
+LOOKUP_CACHE_SIZE = 0
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = NO
+EXTRACT_PACKAGE = NO
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+EXTRACT_ANON_NSPACES = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = YES
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+SHOW_GROUPED_MEMB_INC = NO
+FORCE_LOCAL_INCLUDES = NO
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_MEMBERS_CTORS_1ST = NO
+SORT_GROUP_NAMES = NO
+SORT_BY_SCOPE_NAME = NO
+STRICT_PROTO_MATCHING = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+SHOW_FILES = YES
+SHOW_NAMESPACES = YES
+FILE_VERSION_FILTER =
+LAYOUT_FILE =
+CITE_BIB_FILES =
+QUIET = YES
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = YES
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+INPUT = src \
+ documentation
+INPUT_ENCODING = UTF-8
+FILE_PATTERNS =
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diff --git a/Documentation/Kconfig.tex b/Documentation/Kconfig.tex
new file mode 100644
index 0000000..2b2bf7f
--- /dev/null
+++ b/Documentation/Kconfig.tex
@@ -0,0 +1,480 @@
+\documentclass[10pt,letterpaper]{article}
+\usepackage[latin1]{inputenc}
+\usepackage{amsmath}
+\usepackage{amsfonts}
+\usepackage{amssymb}
+\author{Ron Minnich}
+\title{Kconfig usage in coreboot v2}
+\begin{document}
+\section{Introduction}
+This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them.
+\section{Kconfig variations}
+Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard.
+
+For variables set by the user, see src/console/Kconfig.
+
+For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent.
+
+Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally.
+
+\section{Makefile and Makefile.inc}
+There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y.
+
+Make is not recursive. There is only one make process.
+\subsection{subdirs usage}
+Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y.
+
+We define the common rules for which variation to use below.
+\subsection{object file specification}
+There are several different types of objects specified in the tree. They are:
+\begin{description}
+\item[obj]objects for the ram part of the code
+\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
+\item[initobj]seperately-compiled code for the ROM section of coreboot
+\end{description}
+These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax.
+
+\section{Example: AMD serengeti cheetah}
+\subsection{mainboard/Kconfig}
+Defines Vendor variables. Currently defined variables are:
+Sources all Kconfig files in the vendor directories.
+\input{ mainboardkconfig.tex}
+\subsection{mainboard/Makefile.inc}
+There is none at this time.
+\subsection{mainboard/$<$vendor$>$/Kconfig}
+We use the amd as a model. The only action currently taken is to source all Kconfig's in the
+subdirectories.
+\subsection{mainboard/$<$vendor$>$/Makefile.inc}
+We use amd as a model. There is currently no Makefile.inc at this level.
+\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig}
+The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines
+and rules in here determine everything about how a mainboard target is built.
+We will use serengeti\_cheetah as a model. It defines these variables.
+\input{ mainboardkconfig.tex}
+\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc}
+This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece.
+Note that this is the mainboard as of August, 2009, and it may change over time.
+\subsubsection{objects}
+We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional:
+\begin{verbatim}
+driver-y += mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o
+driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+\end{verbatim}
+\subsubsection{romcc legacy support}
+We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define
+crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the
+old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally.
+\begin{verbatim}
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+\end{verbatim}
+\subsubsection{POST\_EVALUATION}
+POST\_EVALUATION rules should be placed after this section:
+\begin{verbatim}
+ifdef POST_EVALUATION
+\end{verbatim}
+to ensure that the values of variables are correct.
+Here are the post-evaluation rules for this mainboard:
+\begin{verbatim}
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+ mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+ iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+ mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+ iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+ perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+ mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+ iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+ perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+ mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h
+ $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@
+ perl -e 's/\.rodata/.rom.data/g' -pi $@
+ perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+\end{verbatim}
+The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables.
+\subsubsection{devicetree.cb}
+Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard
+properly, as it defines topology and chips that can be defined no other way.
+Let's go through the tree.
+\begin{verbatim}
+chip northbridge/amd/amdk8/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/socket_F
+ device lapic 0 on end
+ end
+ end
+\end{verbatim}
+This topology is always somewhat confusing to newcomers, and even to coreboot veterans.
+
+We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we
+have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge
+somewhere, since it runs memory.
+
+
+What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the
+CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains
+its own APIC, and will define any parameters needed. In this case, we have a northbridge of type
+{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on,
+which connects to a {\it cpu/amd/socket\_F},
+which has a local apic, which is on.
+
+Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here
+is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
+BIOSes) that the BSP be CPU 0; any CPU will do.
+\begin{verbatim}
+ device domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+\end{verbatim}
+Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On
+Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up.
+\begin{verbatim}
+ chip southbridge/amd/amd8132
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+\end{verbatim}
+This is the 8132, a bridge to a secondary PCI bus.
+\begin{verbatim}
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+\end{verbatim}
+The 8111 is a bridge to other busses and to the legacy ISA devices such as superio.
+\begin{verbatim}
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+\end{verbatim}
+The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the
+2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN.
+\begin{verbatim}
+ device pci 1.1 on end
+ device pci 1.2 on end
+\end{verbatim}
+More devices. These statements set up placeholders in the device tree.
+\begin{verbatim}
+ device pci 1.3 on
+ chip drivers/i2c/i2cmux # pca9556 smbus mux
+ device i2c 18 on #0 pca9516 1
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end
+ device i2c 18 on #1 pca9516 2
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-2-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-2-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-3-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-3-1
+ device i2c 57 on end
+ end
+ end
+ end
+ end # acpi
+\end{verbatim}
+These are the i2c devices.
+\begin{verbatim}
+ device pci 1.5 off end
+ device pci 1.6 off end
+\end{verbatim}
+More placeholders.
+\begin{verbatim}
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+\end{verbatim}
+These "register" commands set controls in the southbridge.
+\begin{verbatim}
+ device pci 18.0 on end
+ device pci 18.0 on end
+\end{verbatim}
+These are the other two hypertransport links.
+\begin{verbatim}
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+\end{verbatim}
+The 18.1 devices are, again, northbridge control for various k8 functions.
+\begin{verbatim}
+ end
+ \end{verbatim}
+That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here.
+\begin{verbatim}
+ chip northbridge/amd/amdk8
+ device pci 19.0 on # northbridge
+ chip southbridge/amd/amd8151
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 1.0 on end
+ end
+ end # device pci 19.0
+
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+
+
+\end{verbatim}
+
+\subsection{cpu socket}
+The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only
+the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus
+of all defines and Makefile controls for building the CPU components of a board.
+
+\subsubsection{ cpu/Kconfig}
+Defines variables. Current variables are:
+\input{cpukconfig.tex}
+Sources all Kconfig files in the vendor directories.
+\subsubsection{ cpu/Makefile.inc}
+Unconditionally sources all Makefile.inc in the vendor directories.
+
+\subsection{cpu/$<$vendor$>$/Kconfig}
+The only action currently taken is to source all Kconfig's in the
+subdirectories.
+\subsection{cpu/$<$vendor$>$/Makefile.inc}
+{\em Conditionally} source the socket directories.
+Example:
+\begin{verbatim}
+subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F
+\end{verbatim}
+.
+CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file.
+
+\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig}
+Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that
+the socket, as much as possible, should control the models, because the models may plug into many sockets.
+Socket\_F currently sets:
+\input{socketfkconfig.tex}
+
+It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced.
+
+\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig}
+CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that
+if needed.
+\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc}
+The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional
+compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all}
+objects, because it is not possible to determine at build time what options may be needed for a given model CPU.
+This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc.
+
+\subsection{northbridge}
+\subsubsection{northbridge/Kconfig}
+No variables. Source all vendor directory Kconfigs.
+\subsubsection{northbridge/Makefile.inc}
+No variables. unconditionally include all vendor Makefile.inc
+\subsubsection{northbridge/$<$vendor$>$/Kconfig}
+No variables. Source all chip directory Kconfigs.
+\subsubsection{northbridge/$<$vendor$>$/Makefile.inc}
+No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
+is the name of the part, e.g.
+\begin{verbatim}
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
+\end{verbatim}
+.
+\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
+Typically a small number of variables. One defines the part name. Here is an example
+of the variables defined for the K8.
+\begin{verbatim}
+config NORTHBRIDGE_AMD_AMDK8
+ bool
+ default n
+
+config AGP_APERTURE_SIZE
+ hex
+ default 0x4000000
+\end{verbatim}
+\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
+Typically very small set of rules, and very simple.
+Since this file is already conditionally included,
+we don't need to test for the chipset CONFIG variable. We
+can therefore test other variables (which is part of the reason
+we set up conditional inclusion of this file, instead
+of unconditionally including it). Here is an example from AMD K8.
+Note that we can make a variable conditional on the ACPI tables.
+\begin{verbatim}
+driver-y += northbridge.o
+driver-y += misc_control.o
+obj-y += get_sblk_pci1234.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o
+\end{verbatim}
+
+\subsection{southbridge}
+\subsubsection{southbridge/Kconfig}
+No variables. Source all vendor directory Kconfigs.
+\subsubsection{southbridge/Makefile.inc}
+No variables. {\em Unconditionally} include all vendor Makefile.inc
+\subsubsection{southbridge/$<$vendor$>$/Kconfig}
+No variables. Source all chip directory Kconfigs.
+\subsubsection{southbridge/$<$vendor$>$/Makefile.inc}
+No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
+is the name of the part, e.g.
+\begin{verbatim}
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
+\end{verbatim}
+.
+\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
+Typically a small number of variables. One defines the part name. Here is an example
+of the variables defined for the K8.
+\begin{verbatim}
+config SOUTHBRIDGE_AMD_AMD8111
+ bool
+ default n
+
+\end{verbatim}
+\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
+Typically very small set of rules, and very simple.
+Since this file is already conditionally included,
+we don't need to test for the chipset CONFIG variable. We
+can therefore test other variables (which is part of the reason
+we set up conditional inclusion of this file, instead
+of unconditionally including it). Here is an example from AMD 8111.
+No conditionals in this one yet.
+\begin{verbatim}
+driver-y += amd8111.o
+driver-y += amd8111_usb.o
+driver-y += amd8111_lpc.o
+driver-y += amd8111_ide.o
+driver-y += amd8111_acpi.o
+driver-y += amd8111_usb2.o
+driver-y += amd8111_ac97.o
+driver-y += amd8111_nic.o
+driver-y += amd8111_pci.o
+driver-y += amd8111_smbus.o
+obj-y += amd8111_reset.o
+\end{verbatim}
+
+\subsubsection{vendor and part}
+\subsection{southbridge}
+\subsubsection{vendor and part}
+\subsection{superio}
+\subsection{drivers/i2c}
+This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed.
+To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have:
+\begin{verbatim}
+\end{verbatim}
+
+\subsubsection{vendor and part}
+
+\end{document}
diff --git a/Documentation/Makefile b/Documentation/Makefile
new file mode 100644
index 0000000..1e00444
--- /dev/null
+++ b/Documentation/Makefile
@@ -0,0 +1,71 @@
+#
+# Makefile for coreboot paper.
+# hacked together by Stefan Reinauer <stepan(a)openbios.org>
+#
+
+PDFLATEX=pdflatex -t a4
+
+FIGS=codeflow.pdf hypertransport.pdf
+
+all: CorebootPortingGuide.pdf Kconfig.pdf
+
+SVG2PDF=$(shell which svg2pdf)
+INKSCAPE=$(shell which inkscape)
+CONVERT=$(shell which convert)
+
+codeflow.pdf: codeflow.svg
+ifneq ($(strip $(SVG2PDF)),)
+ svg2pdf $< $@
+else ifneq ($(strip $(INKSCAPE)),)
+ inkscape $< --export-pdf=$@
+else ifneq ($(strip $(CONVERT)),)
+ convert $< $@
+endif
+
+hypertransport.pdf: hypertransport.svg
+ifneq ($(strip $(SVG2PDF)),)
+ svg2pdf $< $@
+else ifneq ($(strip $(INKSCAPE)),)
+ inkscape $< --export-pdf=$@
+else ifneq ($(strip $(CONVERT)),)
+ convert $< $@
+endif
+
+CorebootPortingGuide.toc: $(FIGS) CorebootBuildingGuide.tex
+ # 2 times to make sure we have a current toc.
+ $(PDFLATEX) CorebootBuildingGuide.tex
+ $(PDFLATEX) CorebootBuildingGuide.tex
+
+CorebootPortingGuide.pdf: $(FIGS) CorebootBuildingGuide.tex CorebootPortingGuide.toc
+ $(PDFLATEX) CorebootBuildingGuide.tex
+
+Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex
+ $(PDFLATEX) $<
+
+# quick, somebody! make me a macro!
+mainboardkconfig.tex: ../src/mainboard/Kconfig
+ cat beginverbatim.tex > $@
+ grep '^config' $< | awk '{print $2}' >>$@
+ cat endverbatim.tex >> $@
+
+skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig
+ cat beginverbatim.tex > $@
+ grep '^config' $< | awk '{print $2}' >>$@
+ cat endverbatim.tex >> $@
+
+cpukconfig.tex: ../src/cpu/Kconfig
+ cat beginverbatim.tex > $@
+ grep '^config' $< | awk '{print $2}' >>$@
+ cat endverbatim.tex >> $@
+
+socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig
+ cat beginverbatim.tex > $@
+ grep '^config' $< | awk '{print $2}' >>$@
+ cat endverbatim.tex >> $@
+
+clean:
+ rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex
+
+distclean: clean
+ rm -f CorebootPortingGuide.pdf Kconfig.pdf
+
diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES
new file mode 100644
index 0000000..85ad4d7
--- /dev/null
+++ b/Documentation/POSTCODES
@@ -0,0 +1,26 @@
+-------------------------------------------------------------------------------
+coreboot POST Codes
+-------------------------------------------------------------------------------
+
+This is an (incomplete) list of POST codes emitted by coreboot v4.
+
+0x10 Entry into protected mode
+0x01 Entry into 'crt0.s' reset code jumps to here
+0x11 Start copying coreboot to RAM with decompression if compressed
+0x12 Copy/decompression finished jumping to RAM
+0x80 Entry into coreboot in RAM
+0x13 Entry into c_start
+0xfe Pre call to hardwaremain()
+0x39 Console is initialized
+0x40 Console boot message succeeded
+0x66 Devices have been enumerated
+0x88 Devices have been configured
+0x89 Devices have been enabled
+0xf8 Entry into elf boot
+0xf3 Jumping to payload
+
+Errors (used in several places):
+
+0xee Not supposed to get here
+0xff Elfload fail or die() called
+
diff --git a/Documentation/RFC/chip.tex b/Documentation/RFC/chip.tex
new file mode 100644
index 0000000..5e366b8
--- /dev/null
+++ b/Documentation/RFC/chip.tex
@@ -0,0 +1,266 @@
+ RFC for the chip specification architecture
+
+\begin{abstract}
+At the end of this document is the original message that motivated the
+change.
+\end{abstract}
+
+\section{Scope}
+This document defines how LinuxBIOS programmers can specify chips that
+are used, specified, and initalized. The current scope is for superio
+chips, but the architecture should allow for specification of other chips such
+as southbridges. Multiple chips of same or different type are supported.
+
+\section{Goals}
+The goals of the new chip architecture are these:
+\begin{itemize}
+\item seperate implementation details from specification in the Config file
+(translation: no more C code in Config files)
+\item make the specification easier for people to use and understand
+\item remove private details of a given chip to the chip file as much
+as possible
+\item allow unique register-set-specifiers for each chip
+\end{itemize}
+
+\section{Specification in the Config file}
+The specification looks like this:
+\begin{verbatim}
+chip <name> [path=<path>] ["<configuration>"]
+\end{verbatim}
+The name is in the standard LinuxBIOS form of type/vendor/name, e.g.
+"southbridge/intel/piix4e" or "superio/ite/it8671f". The class of the
+chip is derived from the first pathname component of the name, and the chip
+configuration is derived from the following components.
+
+The path defines the access mechanism to the chip.
+It is optional. If present, it overrides the default path to the chip.
+
+The configuration defines chip-specific configuration details, and is also
+optional. Note that an empty configuration will leave the chip with
+no enabled resources. This may be desirable in some cases.
+
+\section{Results of specifying a chip}
+
+When one or more chips are specified, the data about the chips
+is saved until the entire file is parsed. At this point, the config tool
+creates a file in the build directory called chip.c This file contains
+a common struct containing information about
+each individual chip and an array of pointers to these structures.
+
+For each chip, there are two structures. The structures contain control
+information for the chip, and register initialization information. The
+names of the structures are derived by ``flattening'' the chip name,
+as in the current linuxbios. For example, superio/ite/xyz uses
+two structs, one called superio_ite_xyz_control and one called
+superio_ite_xyz_init. The control struct is initialized from the
+chip name and path information, and has a pointer to the
+config struct. The config struct is initialized from the quote string
+
+\begin{verbatim}
+From rminnich(a)lanl.gov Fri May 16 10:34:13 2003
+Date: Tue, 13 May 2003 08:11:46 -0600 (MDT)
+From: ron minnich <rminnich(a)lanl.gov>
+To: linuxbios(a)clustermatic.org
+Subject: RFC:new superio proposal
+
+Abstract:
+ The superio architecture for linuxbios has worked for the last 2
+years but is being stretched to the limit by the changes in superio chips.
+The architecture depended on superio resources being relatively constant
+between chips, but this assumption no longer holds. In this document we
+propose several alternatives and solicit comments.
+
+Overview:
+The superio architecture in linuxbios was developed over time, and
+modified as circumstances required. In the beginning it was relatively
+simple and assumed only one superio per mainboard. The latest version
+allows an arbitrary number of superios per mainboard, and allows complete
+specification of the superio base I/O address along with the specification
+of reasonable default valures for both the base I/O address and the
+superio parameters such as serial enable, baud rate, and so on.
+
+Specification of superio control parameters is done by a configuration
+line such as:
+
+nsuperio sis/950 com1={1} floppy=1 lpt=1
+
+This fragment sets the superio type to sis/950; sets com1, floppy, and lpt
+to enabled; and leaves the defaults to com1 (baud rate, etc.) to the
+default values.
+
+While it is not obvious, these configuration parameters are fragments of a
+C initializer. The initializers are used to build a statically initialized
+structure of this type:
+
+struct superio {
+ struct superio_control *super; // the ops for the device.
+ unsigned int port; // if non-zero, overrides the default port
+ // com ports. This is not done as an array (yet).
+ // We think it's easier to set up from python if it is not an
+ // array.
+ struct com_ports com1, com2, com3, com4;
+ // DMA, if it exists.
+ struct lpt_ports lpt1, lpt2;
+ /* flags for each device type. Unsigned int. */
+ // low order bit ALWAYS means enable. Next bit means to enable
+ // LPT is in transition, so we leave this here for the moment.
+ // The winbond chips really stretched the way this works.
+ // so many functions!
+ unsigned int ide, floppy, lpt;
+ unsigned int keyboard, cir, game;
+ unsigned int gpio1, gpio2, gpio3;
+ unsigned int acpi,hwmonitor;
+};
+
+These structures are, in turn, created and statically initialized by a
+config-tool-generated structure that defines all the superios. This file
+is called nsuperio.c, is created for each mainboard you build, only
+appears in the build directory, and looks like this:
+
+===
+extern struct superio_control superio_winbond_w83627hf_control;
+
+struct superio superio_winbond_w83627hf= {
+ &superio_winbond_w83627hf_control,
+ .com1={1}, .com2={1}, .floppy=1, .lpt=1, .keyboard=1, .hwmonitor=1};
+
+struct superio *all_superio[] = {&superio_winbond_w83627hf,
+};
+
+unsigned long nsuperio = 1;
+===
+
+This example shows a board with one superio (nsuperio). The superio
+consists of a winbond w83627hf, with com1, com2, floppy, lpt, keyboard,
+and hwmonitor enabled. Note that this structure also allows for
+over-riding the default superio base, although that capability is rarely
+used.
+
+The control structure is used to define how to access the superio for
+purposes of control. It looks like this:
+===
+struct superio_control {
+ void (*pre_pci_init)(struct superio *s);
+ void (*init)(struct superio *s);
+ void (*finishup)(struct superio *s);
+ unsigned int defaultport; /* the defaultport. Can be overridden
+ * by commands in config
+ */
+ // This is the print name for debugging
+ char *name;
+};
+===
+
+There are three methods for stages of hardwaremain. First is pre_pci_init
+(for chips like the acer southbridge that require you to enable some
+resources BEFORE pci scan); init, called during the 'middle' phase of
+hardwaremain; and finishup, called before the payload is loaded.
+
+This approach was inspired by and borrows heavily on the Plan 9 kernel
+configuration tools.
+
+The problem:
+
+When the first version of the superio structure came out it was much
+smaller. It has grown and in the limit this structure is the union of all
+possibly superio chips. Obviously, in the long term, this is not
+practical: we can not anticipate all possible superio chips for all time.
+
+The common PC BIOS solution to this type of problem is to continue with
+binary structures but add version numbers to them, so that all code that
+uses a given structure has to check the version number. Personally, I find
+this grotesque and would rather not work this way.
+
+Using textual strings for configuration is something I find far more
+attractive. Plan 9 has shown that this approach has no real limits and
+suffices for configuration tasks. The Linux kernel does more limited use
+of strings for configuration, but still depends on them. Strings are
+easier to read and work with than binary structures, and more important, a
+lot easier to deal with when things start going wrong.
+
+The proposed solution:
+
+What follows are three possible ideas for specifying superio resources and
+their settings.
+
+A common part of the new idea is to eliminate the common superio
+structure, due to the many variations in chips, and make it invisible
+outside a given superio source file -- the superio structure is now
+private to a given superio. Thus, sis/950/superio.c would contain its own
+superio structure definitions, and also might contain more than once
+instance of these structures (consider a board with 2 sis 950 chips).
+
+The control structure would change as follows:
+struct superio_control {
+ int (*create)(struct superio *s);
+ void (*pre_pci_init)(struct superio *s);
+ void (*init)(struct superio *s);
+ void (*finishup)(struct superio *s);
+ unsigned int defaultport; /* the defaultport. Can be overridden
+ * by commands in config
+ */
+ // This is the print name for debugging
+ char *name;
+};
+
+I.e. we add a new function for creating the superio.
+
+Communication of superio settings from linuxbios to the superio would be
+via textual strings. The superio structure becomes this:
+
+struct superio {
+ struct superio_control *super; // the ops for the device.
+ unsigned int port; // if non-zero, overrides the default port
+ struct configuration *config;
+};
+
+
+So now the question becomes, what is the configuration structure?
+There are several choices. The simplest, from my point of view, are
+keyword-value pairs:
+struct configuration {
+ const char *keyword;
+ const char *value;
+};
+
+These get filled in by the config tool as before. The linuxbios libary can
+then provide a generic parsing function for the superios to use.
+
+The remaining question is how should the superio command look in
+freebios2?
+
+superio sis/950 "com1=115200,8n1 lpt=1 com2=9600"
+
+or
+
+superio sis/950 "com1baud=115200 lpt=1 com1chars=8n1"
+
+or
+
+superio sis/950 ((com1 115200 8n1) (lpt 1))
+
+So, my questions:
+
+1. Does this new scheme look workable. If not, what needs to change?
+2. What should the 'struct configuration' be? does keyword/value work?
+3. what should the superio command look like?
+
+Comments welcome.
+
+I'd like to adopt this "RFC" approach for freebios2 as much as we can.
+There was a lot of give-and-take in the early days of linuxbios about
+structure and it proved useful. There's a lot that will start happening in
+freebios2 now, and we need to try to make sure it will work for everyone.
+
+Those of you who are doing mainboards, please look at freebios2 and see
+how it looks for you. There's a lot of good work that has been done (not
+by me so far, thanks Eric and Stefan), and more that needs to be done.
+Consider trying out romcc as an "assembly code killer". See how it fits
+together and if you can work with it or need changes. Bring comments back
+to this list.
+
+thanks
+
+ron
+
+\end{verbatim}
diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex
new file mode 100644
index 0000000..6d6c433
--- /dev/null
+++ b/Documentation/RFC/config.tex
@@ -0,0 +1,291 @@
+ New config language for LinuxBIOS
+
+\begin{abstract}
+We describe the new configuration language for LinuxBIOS.
+\end{abstract}
+
+\section{Scope}
+This document defines the new configuration language for LinuxBIOS.
+
+\section{Goals}
+The goals of the new language are these:
+\begin{itemize}
+\item Simplified Makefiles so people can see what is set
+\item Move from the regular-expression-based language to something
+a bit more comprehensible and flexible
+\item make the specification easier for people to use and understand
+\item allow unique register-set-specifiers for each chip
+\item allow generic register-set-specifiers for each chip
+\item generate static initialization code, as needed, for the
+specifiers.
+\end{itemize}
+
+\section{Language}
+Here is the new language. It is very similar to the old one, differing
+in only a few respects. It borrows heavily from Greg Watson's suggestions.
+
+I am presenting it in a pseudo-BNF in the hopes it will be easier. Things
+in '' are keywords; things in ``'' are strings in the actual text.
+\begin{verbatim}
+#exprs are composed of factor or factor + factor etc.
+expr ::= factor ( ``+'' factor | ``-'' factor | )*
+#factors are term or term * term or term / term or ...
+factor ::= term ( ``*'' term | ``/'' term | ... )*
+#
+unary-op ::= ``!'' ID
+# term is a number, hexnumber, ID, unary-op, or a full-blown expression
+term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)''
+
+# Option command. Can be an expression or quote-string.
+# Options are used in the config tool itself (in expressions and 'if')
+# and are also passed to the C compiler when building linuxbios.
+# It is an error to have two option commands in a file.
+# It is an error to have an option command after the ID has been used
+# in an expression (i.e. 'set after used' is an error)
+option ::= 'option' ID '=' (``value'' | term)
+
+# Default command. The ID is set to this value if no option command
+# is scanned.
+# Multiple defaults for an ID will produce warning, but not errors.
+# It is OK to scan a default command after use of an ID.
+# Options always over-ride defaults.
+default ::= 'default' ID '=' (``value'' | term)
+
+# the mainboard, southbridge, northbridge commands
+# cause sourcing of Config.lb files as in the old config tool
+# as parts are sourced, a device tree is built. The structure
+# of the tree is determined by the structure of the components
+# as they are specified. To attach a superio to a southbridge, for
+# example, one would do this:
+# southbridge acer/5432
+# superio nsc/123
+# end
+# end
+# the tool generates static initializers for this hierarchy.
+
+# add C code to the current component (motherboard, etc. )
+# to initialise the component-INDEPENDENT structure members
+init ::= 'init' ``CODE''
+
+# add C code to the current component (motherboard, etc. )
+# to initialise the component-DEPENDENT structure members
+register ::= 'register' ``CODE''
+
+
+# mainboard command
+# statements in this block will set variables controlling the mainboard,
+# and will also place components (northbridge etc.) in the device tree
+# under this mainboard
+mainboard ::= 'mainboard' PATH (statements)* 'end'
+
+# standard linuxbios commands
+southbridge ::= 'southbridge' PATH (statemnts)* 'end'
+northbridge ::= 'northbridge' PATH (statemnts)* 'end'
+superio ::= 'superio PATH (statemnts)* 'end'
+cpu ::= 'cpu' PATH (statemnts)* 'end'
+arch ::= 'arch' PATH (statemnts)* 'end'
+
+# files for building linuxbios
+# include a file in crt0.S
+mainboardinit ::= 'mainboardinit' PATH
+
+# object file
+object ::= 'object' PATH
+# driver objects are just built into the image in a different way
+driver ::= 'driver' PATH
+
+# Use the Config.lb file in the PATH
+dir ::= 'dir' PATH
+
+# add a file to the set of ldscript files
+ldscript ::= 'ldscript' PATH
+
+# dependencies or actions for the makerule command
+dep ::= 'dep' ``dependency-string''
+act ::= 'act' ``actions''
+depsacts ::= (dep | act)*
+# set up a makerule
+#
+makerule ::= 'makerule' PATH depsacts
+
+#defines for use in makefiles only
+# note usable in the config tool, not passed to cc
+makedefine ::= 'makedefine' ``RAWTEXT''
+
+# add an action to an existing make rule
+addaction ::= 'addaction' PATH ``ACTION''
+
+# statements
+statement ::=
+ option
+ | default
+ | cpu
+ | arch
+ | northbridge
+ | southbridge
+ | superio
+ | object
+ | driver
+ | mainboardinit
+ | makerule
+ | makedefine
+ | addaction
+ | init
+ | register
+ | iif
+ | dir
+ | ldscript
+
+statements ::= (statement)*
+
+# target directory specification
+target ::= 'target' PATH
+
+# and the whole thing
+board ::= target (option)* mainboard
+
+\end{verbatim}
+
+\subsubsection{Command definitions}
+\subsubsubsection{option}
+\subsubsubsection{default}
+\subsubsubsection{cpu}
+\subsubsubsection{arch}
+\subsubsubsection{northbridge}
+\subsubsubsection{southbridge}
+\subsubsubsection{superio}
+\subsubsubsection{object}
+\subsubsubsection{driver}
+\subsubsubsection{mainboardinit}
+\subsubsubsection{makerule}
+\subsubsubsection{makedefine}
+\subsubsubsection{addaction}
+\subsubsubsection{init}
+\subsubsubsection{register}
+\subsubsubsection{iif}
+\subsubsubsection{dir}
+\subsubsubsection{ldscript}
+
+
+A sample file:
+
+\begin{verbatim}
+target x
+
+# over-ride the default rom size in the mainboard file
+option CONFIG_ROM_SIZE=1024*1024
+mainboard amd/solo
+end
+
+\end{verbatim}
+
+Sample mainboard file
+\begin{verbatim}
+#
+###
+### Set all of the defaults for an x86 architecture
+###
+arch i386 end
+cpu k8 end
+#
+option CONFIG_DEBUG=1
+default CONFIG_USE_FALLBACK_IMAGE=1
+option A=(1+2)
+option B=0xa
+#
+###
+### Build our 16 bit and 32 bit linuxBIOS entry code
+###
+mainboardinit cpu/i386/entry16.inc
+mainboardinit cpu/i386/entry32.inc
+ldscript cpu/i386/entry16.lds
+ldscript cpu/i386/entry32.lds
+#
+###
+### Build our reset vector (This is where linuxBIOS is entered)
+###
+if CONFIG_USE_FALLBACK_IMAGE
+ mainboardinit cpu/i386/reset16.inc
+ ldscript cpu/i386/reset16.lds
+else
+ mainboardinit cpu/i386/reset32.inc
+ ldscript cpu/i386/reset32.lds
+end
+.
+.
+.
+if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
+#
+###
+### Romcc output
+###
+#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E"
+#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
+#mainboardinit ./failover.inc
+makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E"
+makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
+mainboardinit ./auto.inc
+#
+###
+### Include the secondary Configuration files
+###
+northbridge amd/amdk8
+end
+southbridge amd/amd8111
+end
+#mainboardinit arch/i386/smp/secondary.inc
+superio nsc/pc87360
+ register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
+end
+dir /pc80
+##dir /src/superio/winbond/w83627hf
+cpu p5 end
+cpu p6 end
+cpu k7 end
+cpu k8 end
+#
+###
+### Build the objects we have code for in this directory.
+###
+##object mainboard.o
+driver mainboard.o
+object static_devices.o
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+### Location of the DIMM EEPROMS on the SMBUS
+### This is fixed into a narrow range by the DIMM package standard.
+###
+option SMBUS_MEM_DEVICE_START=(0xa << 3)
+option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
+option SMBUS_MEM_DEVICE_INC=1
+#
+### The linuxBIOS bootloader.
+###
+option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
+option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
+#
+
+\end{verbatim}
+
+I've found the output of the new tool to be easier to
+handle. Makefile.settings looks like this, for example:
+\begin{verbatim}
+TOP:=/home/rminnich/src/yapps2/freebios2
+TARGET_DIR:=x
+export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
+export CONFIG_ARCH:=i386
+export CONFIG_RAMBASE:=0x4000
+export CONFIG_ROM_IMAGE_SIZE:=65535
+export CONFIG_PAYLOAD_SIZE:=131073
+export CONFIG_MAX_CPUS:=1
+export CONFIG_HEAP_SIZE:=8192
+export CONFIG_STACK_SIZE:=8192
+export CONFIG_MEMORY_HOLE:=0
+export COREBOOT_VERSION:=1.1.0
+export CC:=$(CONFIG_CROSS_COMPILE)gcc
+
+\end{verbatim}
+
+In other words, instead of expressions, we see the values. It's easier to
+deal with.
+
diff --git a/Documentation/abi-data-consumption.txt b/Documentation/abi-data-consumption.txt
new file mode 100644
index 0000000..81442e7
--- /dev/null
+++ b/Documentation/abi-data-consumption.txt
@@ -0,0 +1,22 @@
+This text describes the ABI coreboot presents to downstream users. Such
+users are payloads and/or operating systems. Therefore, this text serves
+at what can be relied on for downstream consumption. Anything not explicitly
+listed as consumable is subject to change without notice.
+
+Background and Usage
+
+coreboot passes information to downstream users using coreboot tables. These
+table definitions can be found in src/include/boot/coreboot_tables.h and
+payloads/libpayload/include/coreboot_tables.h respectively within coreboot
+and libpayload. One of the most vital and important pieces of information
+found within these tables is the memory map of the system indicating
+available and reserved memory.
+
+In 2009 cbmem was added to coreboot. The "CBMEM high table memory manager"
+serves a way for coreboot to bookkeep its own internal data. While some
+of this data may be exposed through the coreboot tables the data structures
+used to manage the data within the cbmem area is subject to change.
+
+Provided the above, if one needs a piece of data exposed to the OS
+or payload it should reside within the coreboot tables. If it isn't there
+then a code change will be required to add it to the coreboot tables.
diff --git a/Documentation/beginverbatim.tex b/Documentation/beginverbatim.tex
new file mode 100644
index 0000000..453714c
--- /dev/null
+++ b/Documentation/beginverbatim.tex
@@ -0,0 +1 @@
+\begin{verbatim}
diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt
new file mode 100644
index 0000000..7ecc901
--- /dev/null
+++ b/Documentation/cbfs.txt
@@ -0,0 +1,421 @@
+
+Received: from www.crouse-house.com ([199.45.160.146]
+ for coreboot(a)coreboot.org; Fri, 19 Dec 2008 23:11:59 +0100
+From: Jordan Crouse <jordan(a)cosmicpenguin.net>
+
+
+Greetings. I apologize for the incompleteness of what I am about to
+discuss. I was planning on working on it leisurely, but my employment
+circumstances changed and I've been trying to get it completed in a
+hurry before I had to leave it behind.
+
+I've been thinking a lot about LAR lately, and ways to make it more
+extensible and robust. Marc and I have been trading ideas back and
+forth for a number of months, and over time a clear idea of what I
+wanted to do started to take shape.
+
+My goal was to add small things to LAR while retaining the overall
+scheme. Over time, the scheme evolved slightly, but I think you'll find
+that it remains true to the original idea. Below is the beginnings of
+an architecture document - I did it in text form, but if met with
+aclaim, it should be wikified. This presents what I call CBFS - the
+next generation LAR for next generation Coreboot. Its easier to
+describe what it is by describing what changed:
+
+A header has been added somewhere in the bootblock similar to Carl
+Daniel's scheme. In addition to the coreboot information, the header
+reports the size of the ROM, the alignment of the blocks, and the offset
+of the first component in the CBFS. The master header provides all
+the information LAR needs plus the magic number information flashrom needs.
+
+Each "file" (or component, as I style them) now has a type associated
+with it. The type is used by coreboot to identify the type of file that
+it is loading, and it can also be used by payloads to group items in the
+CBFS by type (i.e - bayou can ask for all components that are payloads).
+
+The header on each "file" (or component, as I like to style them) has
+been simplified - We now only store the length, the type, the checksum,
+and the offset to the data. The name scheme remains the same. The
+addtional information, which is component specific, has been moved to
+the component itself (see below).
+
+The components are arranged in the ROM aligned along the specified
+alignment from the master header - this is to facilitate partial re-write.
+
+Other then that, the LAR ideas remain pretty much the same.
+
+The plan for moving the metadata to the components is to allow many
+different kinds of components, not all of which are groked by coreboot.
+ However, there are three essential component types that are groked by
+coreboot, and they are defined:
+
+stage - the stage is being parsed from the original ELF, and stored in
+the ROM as a single blob of binary data. The load address, start
+address, compression type and length are stored in the component sub-header.
+
+payload - this is essentially SELF in different clothing - same idea as
+SELF, with the sub-header as above.
+
+optionrom - This is in flux - right now, the optionrom is stored
+unadulterated and uncompressed, but that is likely to be changed.
+
+Following this email are two replies containing the v3 code and a new
+ROM tool to implement this respectively. I told you that I was trying
+to get this out before I disappear, and I'm not kidding - the code is
+compile tested and not run-tested. I hope that somebody will embrace
+this code and take it the rest of the way, otherwise it will die a
+pretty short death.
+
+I realize that this will start an awesome flamewar, and I'm looking
+forward to it. Thanks for listening to me over the years - and good
+luck with coreboot. When you all make a million dollars, send me a few
+bucks, will you?
+
+Jordan
+
+Coreboot CBFS Specification
+Jordan Crouse <jordan(a)cosmicpenguin.net>
+
+= Introduction =
+
+This document describes the coreboot CBFS specification (from here
+referred to as CBFS). CBFS is a scheme for managing independent chunks
+of data in a system ROM. Though not a true filesystem, the style and
+concepts are similar.
+
+
+= Architecture =
+
+The CBFS architecture looks like the following:
+
+/---------------\ <-- Start of ROM
+| /-----------\ | --|
+| | Header | | |
+| |-----------| | |
+| | Name | | |-- Component
+| |-----------| | |
+| |Data | | |
+| |.. | | |
+| \-----------/ | --|
+| |
+| /-----------\ |
+| | Header | |
+| |-----------| |
+| | Name | |
+| |-----------| |
+| |Data | |
+| |.. | |
+| \-----------/ |
+| |
+| ... |
+| /-----------\ |
+| | | |
+| | Bootblock | |
+| | --------- | |
+| | Reset | | <- 0xFFFFFFF0
+| \-----------/ |
+\---------------/
+
+
+The CBFS architecture consists of a binary associated with a physical
+ROM disk referred hereafter as the ROM. A number of independent of
+components, each with a header prepended on to data are located within
+the ROM. The components are nominally arranged sequentially, though they
+are aligned along a pre-defined boundary.
+
+The bootblock occupies the last 20k of the ROM. Within
+the bootblock is a master header containing information about the ROM
+including the size, alignment of the components, and the offset of the
+start of the first CBFS component within the ROM.
+
+= Master Header =
+
+The master header contains essential information about the ROM that is
+used by both the CBFS implementation within coreboot at runtime as well
+as host based utilities to create and manage the ROM. The master header
+will be located somewhere within the bootblock (last 20k of the ROM). A
+pointer to the location of the header will be located at offset
+-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a
+normal x86 system. The pointer will be to physical memory somewhere
+between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot
+to locate the header at run time. Build time utilities will
+need to read the pointer and do the appropriate math to locate the header.
+
+The following is the structure of the master header:
+
+struct cbfs_header {
+ u32 magic;
+ u32 version;
+ u32 romsize;
+ u32 bootblocksize;
+ u32 align;
+ u32 offset;
+ u32 architecture;
+ u32 pad[1];
+} __attribute__((packed));
+
+The meaning of each member is as follows:
+
+'magic' is a 32 bit number that identifies the ROM as a CBFS type. The
+magic
+number is 0x4F524243, which is 'ORBC' in ASCII.
+
+'version' is a version number for CBFS header. cbfs_header structure may be
+different if version is not matched.
+
+'romsize' is the size of the ROM in bytes. Coreboot will subtract 'size' from
+0xFFFFFFFF to locate the beginning of the ROM in memory.
+
+'bootblocksize' is the size of bootblock reserved in firmware image.
+
+'align' is the number of bytes that each component is aligned to within the
+ROM. This is used to make sure that each component is aligned correctly
+with
+regards to the erase block sizes on the ROM - allowing one to replace a
+component at runtime without disturbing the others.
+
+'offset' is the offset of the the first CBFS component (from the start of
+the ROM). This is to allow for arbitrary space to be left at the beginning
+of the ROM for things like embedded controller firmware.
+
+'architecture' describes which architecture (x86, arm, ...) this CBFS is created
+for.
+
+= Bootblock =
+The bootblock is a mandatory component in the ROM. It is located in the
+last
+20k of the ROM space, and contains, among other things, the location of the
+master header and the entry point for the loader firmware. The bootblock
+does not have a component header attached to it.
+
+= Components =
+
+CBFS components are placed in the ROM starting at 'offset' specified in
+the master header and ending at the bootblock. Thus the total size
+available
+for components in the ROM is (ROM size - 20k - 'offset'). Each CBFS
+component is to be aligned according to the 'align' value in the header.
+Thus, if a component of size 1052 is located at offset 0 with an 'align'
+value
+of 1024, the next component will be located at offset 2048.
+
+Each CBFS component will be indexed with a unique ASCII string name of
+unlimited size.
+
+Each CBFS component starts with a header:
+
+struct cbfs_file {
+ char magic[8];
+ unsigned int len;
+ unsigned int type;
+ unsigned int checksum;
+ unsigned int offset;
+};
+
+'magic' is a magic value used to identify the header. During runtime,
+coreboot will scan the ROM looking for this value. The default magic is
+the string 'LARCHIVE'.
+
+'len' is the length of the data, not including the size of the header and
+the size of the name.
+
+'type' is a 32 bit number indicating the type of data that is attached.
+The data type is used in a number of ways, as detailed in the section
+below.
+
+'checksum' is a 32bit checksum of the entire component, including the
+header and name.
+
+'offset' is the start of the component data, based off the start of the
+header.
+The difference between the size of the header and offset is the size of the
+component name.
+
+Immediately following the header will be the name of the component,
+which will
+null terminated and 16 byte aligned. The following picture shows the
+structure of the header:
+
+/--------\ <- start
+| Header |
+|--------| <- sizeof(struct cbfs_file)
+| Name |
+|--------| <- 'offset'
+| Data |
+| ... |
+\--------/ <- start + 'offset' + 'len'
+
+== Searching Alogrithm ==
+
+To locate a specific component in the ROM, one starts at the 'offset'
+specified in the CBFS master header. For this example, the offset will
+be 0.
+
+ From that offset, the code should search for the magic string on the
+component, jumping 'align' bytes each time. So, assuming that 'align' is
+16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc.
+If the offset ever exceeds the allowable range for CBFS components, then no
+component was found.
+
+Upon recognizing a component, the software then has to search for the
+specific name of the component. This is accomplished by comparing the
+desired name with the string on the component located at
+offset + sizeof(struct cbfs_file). If the string matches, then the
+component
+has been located, otherwise the software should add 'offset' + 'len' to
+the offset and resume the search for the magic value.
+
+== Data Types ==
+
+The 'type' member of struct cbfs_file is used to identify the content
+of the component data, and is used by coreboot and other
+run-time entities to make decisions about how to handle the data.
+
+There are three component types that are essential to coreboot, and so
+are defined here.
+
+=== Stages ===
+
+Stages are code loaded by coreboot during the boot process. They are
+essential to a successful boot. Stages are comprised of a single blob
+of binary data that is to be loaded into a particular location in memory
+and executed. The uncompressed header contains information about how
+large the data is, and where it should be placed, and what additional memory
+needs to be cleared.
+
+Stages are assigned a component value of 0x10. When coreboot sees this
+component type, it knows that it should pass the data to a sub-function
+that will process the stage.
+
+The following is the format of a stage component:
+
+/--------\
+| Header |
+|--------|
+| Binary |
+| .. |
+\--------/
+
+The header is defined as:
+
+struct cbfs_stage {
+ unsigned int compression;
+ unsigned long long entry;
+ unsigned long long load;
+ unsigned int len;
+ unsigned int memlen;
+};
+
+'compression' is an integer defining how the data is compressed. There
+are three compression types defined by this version of the standard:
+none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional
+types may be added assuming that coreboot understands how to handle the scheme.
+
+'entry' is a 64 bit value indicating the location where the program
+counter should jump following the loading of the stage. This should be
+an absolute physical memory address.
+
+'load' is a 64 bit value indicating where the subsequent data should be
+loaded. This should be an absolute physical memory address.
+
+'len' is the length of the compressed data in the component.
+
+'memlen' is the amount of memory that will be used by the component when
+it is loaded.
+
+The component data will start immediately following the header.
+
+When coreboot loads a stage, it will first zero the memory from 'load' to
+'memlen'. It will then decompress the component data according to the
+specified scheme and place it in memory starting at 'load'. Following that,
+it will jump execution to the address specified by 'entry'.
+Some components are designed to execute directly from the ROM - coreboot
+knows which components must do that and will act accordingly.
+
+=== Payloads ===
+
+Payloads are loaded by coreboot following the boot process.
+
+Stages are assigned a component value of 0x20. When coreboot sees this
+component type, it knows that it should pass the data to a sub-function
+that will process the payload. Furthermore, other run time
+applications such as 'bayou' may easily index all available payloads
+on the system by searching for the payload type.
+
+
+The following is the format of a stage component:
+
+/-----------\
+| Header |
+| Segment 1 |
+| Segment 2 |
+| ... |
+|-----------|
+| Binary |
+| .. |
+\-----------/
+
+The header is as follows:
+
+struct cbfs_payload {
+ struct cbfs_payload_segment segments;
+}
+
+The header contains a number of segments corresponding to the segments
+that need to be loaded for the payload.
+
+The following is the structure of each segment header:
+
+struct cbfs_payload_segment {
+ unsigned int type;
+ unsigned int compression;
+ unsigned int offset;
+ unsigned long long load_addr;
+ unsigned int len;
+ unsigned int mem_len;
+};
+
+'type' is the type of segment, one of the following:
+
+PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code
+PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data
+PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment
+ should be zeroed
+PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for
+ the payload
+PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point
+ for the payload
+
+'compression' is the compression scheme for the segment. Each segment can
+be independently compressed. There are three compression types defined by
+this version of the standard: none (0x0), lzma (0x1), and nrv2b
+(0x02, deprecated), though additional types may be added assuming that
+coreboot understands how to handle the scheme.
+
+'offset' is the address of the data within the component, starting from
+the component header.
+
+'load_addr' is a 64 bit value indicating where the segment should be placed
+in memory.
+
+'len' is a 32 bit value indicating the size of the segment within the
+component.
+
+'mem_len' is the size of the data when it is placed into memory.
+
+The data will located immediately following the last segment.
+
+=== Option ROMS ===
+
+The third specified component type will be Option ROMs. Option ROMS will
+have component type '0x30'. They will have no additional header, the
+uncompressed binary data will be located in the data portion of the
+component.
+
+=== NULL ===
+
+There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is
+the "don't care" component type. This can be used when the component
+type is not necessary (such as when the name of the component is unique.
+i.e. option_table). It is recommended that all components be assigned a
+unique type, but NULL can be used when the type does not matter.
diff --git a/Documentation/codeflow.svg b/Documentation/codeflow.svg
new file mode 100644
index 0000000..bed9599
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+++ b/Documentation/codeflow.svg
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diff --git a/Documentation/coreboot_logo.png b/Documentation/coreboot_logo.png
new file mode 100644
index 0000000..dde1aa6
Binary files /dev/null and b/Documentation/coreboot_logo.png differ
diff --git a/Documentation/endverbatim.tex b/Documentation/endverbatim.tex
new file mode 100644
index 0000000..f832f3f
--- /dev/null
+++ b/Documentation/endverbatim.tex
@@ -0,0 +1 @@
+\end{verbatim}
diff --git a/Documentation/gcov.txt b/Documentation/gcov.txt
new file mode 100644
index 0000000..896ec93
--- /dev/null
+++ b/Documentation/gcov.txt
@@ -0,0 +1,227 @@
+This patch contains our local modifications for gcov-io.h and libgcov.c.
+The file gcov-iov.h is taken from a gcc build (produced at compile
+time). The file gcov-io.c is unchanged.
+
+--- gcc-4.7.2/gcc/gcov-io.h 2011-12-04 10:27:19.000000000 -0800
++++ coreboot/src/lib/gcov-io.h 2013-01-12 16:45:57.000000000 -0800
+@@ -163,6 +163,24 @@
+ #ifndef GCC_GCOV_IO_H
+ #define GCC_GCOV_IO_H
+
++#ifdef __COREBOOT__
++#define GCOV_LINKAGE /* nothing */
++/* We need the definitions for
++ BITS_PER_UNIT and
++ LONG_LONG_TYPE_SIZE
++ They are defined in gcc/defaults.h and gcc/config/<arch_depend_files>
++ (like, gcc/config/i386/i386.h). And it can be overridden by setting
++ in build scripts. Here I hardcoded the value for x86. */
++#define BITS_PER_UNIT 8
++#define LONG_LONG_TYPE_SIZE 64
++
++/* There are many gcc_assertions. Set the vaule to 1 if we want a warning
++ message if the assertion fails. */
++#ifndef ENABLE_ASSERT_CHECKING
++#define ENABLE_ASSERT_CHECKING 1
++#endif
++#endif /* __COREBOOT__ */
++
+ #if IN_LIBGCOV
+ /* About the target */
+
+@@ -232,7 +250,9 @@
+ is not also used in a DSO. */
+ #if IN_LIBGCOV
+
++#ifndef __COREBOOT__
+ #include "tconfig.h"
++#endif /* __COREBOOT__ */
+
+ #define gcov_var __gcov_var
+ #define gcov_open __gcov_open
+@@ -455,8 +475,10 @@
+ /* Register a new object file module. */
+ extern void __gcov_init (struct gcov_info *) ATTRIBUTE_HIDDEN;
+
++#ifndef __COREBOOT__
+ /* Called before fork, to avoid double counting. */
+ extern void __gcov_flush (void) ATTRIBUTE_HIDDEN;
++#endif
+
+ /* The merge function that just sums the counters. */
+ extern void __gcov_merge_add (gcov_type *, unsigned) ATTRIBUTE_HIDDEN;
+--- gcc-4.7.2/libgcc/libgcov.c 2012-01-11 10:50:21.000000000 -0800
++++ coreboot/src/lib/libgcov.c 2013-01-16 09:45:11.000000000 -0800
+@@ -25,12 +25,41 @@
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
++#define __COREBOOT__
++#ifdef __COREBOOT__
++#include <stdlib.h>
++#include <string.h>
++#include <console/console.h>
++#include <assert.h>
++typedef s32 pid_t;
++#define gcc_assert(x) ASSERT(x)
++#define fprintf(file, x...) printk(BIOS_ERR, x)
++#define alloca(size) __builtin_alloca (size)
++#include "gcov-glue.c"
++
++/* Define MACROs to be used by coreboot compilation. */
++# define L_gcov
++# define L_gcov_interval_profiler
++# define L_gcov_pow2_profiler
++# define L_gcov_one_value_profiler
++# define L_gcov_indirect_call_profiler
++# define L_gcov_average_profiler
++# define L_gcov_ior_profiler
++
++# define HAVE_CC_TLS 0
++# define __GCOV_KERNEL__
++
++# define IN_LIBGCOV 1
++# define IN_GCOV 0
++#else /* __COREBOOT__ */
+ #include "tconfig.h"
+ #include "tsystem.h"
+ #include "coretypes.h"
+ #include "tm.h"
+ #include "libgcc_tm.h"
++#endif /* __COREBOOT__ */
+
++#ifndef __COREBOOT__
+ #if defined(inhibit_libc)
+ #define IN_LIBGCOV (-1)
+ #else
+@@ -41,6 +70,7 @@
+ #define GCOV_LINKAGE /* nothing */
+ #endif
+ #endif
++#endif /* __COREBOOT__ */
+ #include "gcov-io.h"
+
+ #if defined(inhibit_libc)
+@@ -68,12 +98,17 @@
+
+ #else
+
++#ifndef __COREBOOT__
+ #include <string.h>
+ #if GCOV_LOCKED
+ #include <fcntl.h>
+ #include <errno.h>
+ #include <sys/stat.h>
+ #endif
++#else
++void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)),
++ unsigned n_counters __attribute__ ((unused))) {}
++#endif /* __COREBOOT__ */
+
+ #ifdef L_gcov
+ #include "gcov-io.c"
+@@ -99,6 +134,10 @@
+ static int
+ create_file_directory (char *filename)
+ {
++#ifdef __COREBOOT__
++ (void) filename;
++ return 0;
++#else
+ #if !defined(TARGET_POSIX_IO) && !defined(_WIN32)
+ (void) filename;
+ return -1;
+@@ -137,6 +176,7 @@
+ };
+ return 0;
+ #endif
++#endif
+ }
+
+ static struct gcov_fn_buffer *
+@@ -279,7 +319,7 @@
+ struct gcov_ctr_summary *cs_ptr;
+ const struct gcov_ctr_info *ci_ptr;
+ unsigned t_ix;
+- int f_ix;
++ int f_ix = 0;
+ gcov_unsigned_t c_num;
+ const char *gcov_prefix;
+ int gcov_prefix_strip = 0;
+@@ -329,6 +369,7 @@
+ }
+ }
+
++#ifndef __COREBOOT__
+ {
+ /* Check if the level of dirs to strip off specified. */
+ char *tmp = getenv("GCOV_PREFIX_STRIP");
+@@ -352,6 +393,7 @@
+ prefix_length--;
+ }
+ else
++#endif
+ prefix_length = 0;
+
+ /* If no prefix was specified and a prefix stip, then we assume
+@@ -696,8 +738,10 @@
+ if (filename_length > gcov_max_filename)
+ gcov_max_filename = filename_length;
+
++#ifndef __COREBOOT__
+ if (!gcov_list)
+ atexit (gcov_exit);
++#endif
+
+ info->next = gcov_list;
+ gcov_list = info;
+@@ -767,14 +811,15 @@
+
+ #ifdef L_gcov_merge_single
+ /* The profile merging function for choosing the most common value.
+- It is given an array COUNTERS of N_COUNTERS old counters and it
+- reads the same number of counters from the gcov file. The counters
+- are split into 3-tuples where the members of the tuple have
+- meanings:
+-
+- -- the stored candidate on the most common value of the measured entity
+- -- counter
+- -- total number of evaluations of the value */
++ * It is given an array COUNTERS of N_COUNTERS old counters and it
++ * reads the same number of counters from the gcov file. The counters
++ * are split into 3-tuples where the members of the tuple have
++ * meanings:
++ *
++ * -- the stored candidate on the most common value of the measured entity
++ * -- counter
++ * -- total number of evaluations of the value
++ */
+ void
+ __gcov_merge_single (gcov_type *counters, unsigned n_counters)
+ {
+@@ -805,15 +850,16 @@
+
+ #ifdef L_gcov_merge_delta
+ /* The profile merging function for choosing the most common
+- difference between two consecutive evaluations of the value. It is
+- given an array COUNTERS of N_COUNTERS old counters and it reads the
+- same number of counters from the gcov file. The counters are split
+- into 4-tuples where the members of the tuple have meanings:
+-
+- -- the last value of the measured entity
+- -- the stored candidate on the most common difference
+- -- counter
+- -- total number of evaluations of the value */
++ * difference between two consecutive evaluations of the value. It is
++ * given an array COUNTERS of N_COUNTERS old counters and it reads the
++ * same number of counters from the gcov file. The counters are split
++ * into 4-tuples where the members of the tuple have meanings:
++ *
++ * -- the last value of the measured entity
++ * -- the stored candidate on the most common difference
++ * -- counter
++ * -- total number of evaluations of the value
++ */
+ void
+ __gcov_merge_delta (gcov_type *counters, unsigned n_counters)
+ {
diff --git a/Documentation/hypertransport.svg b/Documentation/hypertransport.svg
new file mode 100644
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@@ -0,0 +1,59 @@
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diff --git a/Documentation/submodules.txt b/Documentation/submodules.txt
new file mode 100644
index 0000000..631e351
--- /dev/null
+++ b/Documentation/submodules.txt
@@ -0,0 +1,46 @@
+Use of git submodules in coreboot
+=================================
+coreboot uses git submodules to keep certain parts of the tree separate,
+with two major use cases:
+
+First, we use a vendor tool by NVIDIA for systems based on their SoC
+and since they publish it through git, we can just import it into our
+tree using submodules.
+
+Second, lots of boards these days require binaries and we want to keep
+them separate from coreboot proper to clearly delineate shiny Open Source
+from ugly blobs.
+Since we don't want to impose blobs on users who really don't need them,
+that repository is only downloaded and checked out on explicit request.
+
+Handling submodules
+-------------------
+For the most part, submodules should be automatically checked out on the
+first execution of the coreboot Makefile.
+
+To manually fetch all repositories (eg. when you want to prepare the tree
+for archiving, or to use it without network access), run
+
+ $ git submodule update --init --checkout
+
+This also checks out the binaries below `3rdparty/`
+
+Mirroring coreboot
+------------------
+When running a coreboot mirror to checkout from, for full operation, you
+should also mirror the blobs and nvidia-cbootimage repository, and place
+them in the same directory as the coreboot repository mirror.
+
+That is, when residing in coreboot's repository, `cd ../blobs.git`
+should move you to the blobs repository.
+
+With that, no matter what the URL of your coreboot repository is, the
+git client (of a sufficiently new version) is able to pick up the other
+repositories transparently.
+
+Minimum requirements
+--------------------
+git needs to be able to handle relative paths to submodule repositories,
+and it needs to know about non-automatic submodules.
+
+For these features, we require git version 1.7.6.1 or newer.
diff --git a/documentation/AMD-S3.txt b/documentation/AMD-S3.txt
deleted file mode 100644
index 48d4c8f..0000000
--- a/documentation/AMD-S3.txt
+++ /dev/null
@@ -1,153 +0,0 @@
- _____ ____ _____ ______ ____ ____ ____ _______
- / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __|
- | | | | | | |__) | |__ | |_) | | | | | | | | |
- | | | | | | _ /| __| | _ <| | | | | | | | |
- | |___| |__| | | \ \| |____| |_) | |__| | |__| | | |
- \_____\____/|_| \_\______|____/ \____/ \____/ |_|
-
- __ __ _____ _____ ____
- /\ | \/ | __ \ / ____| |___ \
- / \ | \ / | | | | | (___ __) |
- / /\ \ | |\/| | | | | \___ \ |__ <
- / ____ \| | | | |__| | ____) | ___) |
- /_/ \_\_| |_|_____/ |_____/ |____/
-
-
- S3 in Coreboot (V 1.2)
-----------------------------------------
- Zheng Bao
- <zheng.bao(a)amd.com>
- <fishbaozi(a)gmail.com>
-
-Introduction
-============
-This document is about how the feature S3 is implemented on coreboot,
-specifically on AMD platform. This topic deals with ACPI spec, hardware,
-BIOS, OS. We try to help coreboot users to realize their own S3.
-
-S3 in a nutshell
-================
-The S3 sleeping state is a low wake latency sleeping state where all
-system context is lost except system memory. [1]. S3 is a ACPI
-definition.
-To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI
-registers). But if you do that, board can not resume at where it
-sleeps, because you don't save the context. More often than not, we
-make the board go into S3 by the tools which OSes provide. For
-windows, click Start->sleep. For linux, some distribution provide a
-tools called pm-suspend, which can make the system goto S3. If
-pm-suspend is not available, we can run "echo mem > /sys/power/state",
-but this way may not save all the needed context.
-In S3 state, the power is off. So when the power button is pressed,
-BIOS runs as it does in cold boot. If BIOS didn't detect whether
-board boots or resumes, it would go the same way as boot. It is not
-what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS
-are waking up.
-BIOS is responsible for restore the machine state as it is before
-sleep. It needs restore the memory controller, not overwriting memory
-which is not marked as reserved. For the peripheral which loses its
-registers, BIOS needs to write the original value.
-When everything is done, BIOS needs to find out the wakeup vector
-provided by OSes and jump there. OSes also have work to do. We can go
-to linux kernel or some other open source projects to find out how they
-handle S3 resume.
-
-ACPI registers
-==============
-ACPI specification defines a group of registers. OSes handle all these
-registers to read and write status to all the platform.
-On AMD platform, these registers are provided by southbridge. For
-example, Hudson uses PMIO 60:6F to define ACPI registers.
-OSes don't have any specific driver to know where these registers
-are. BIOS has the responsibility to allocated the IO resources and
-write all these address to FADT, a ACPI defined table.
-
-Memory Layout
-=============
-Restoring memory is the most important job done by BIOS. When the
-power is off, the memory is maintained by standby power. BIOS need to
-make sure that when flow goes to OS, everything in memory should be
-the same as it was.
-
-The chip vendor will provide a way, or code, to wake up the memory
-from sleeping. In AGESA 2008 arch, it is called AmdInitResume.
-
-The BIOS itself needs some memory to run. Either, BIOS marks the erea
-as reserved in e820, or BIOS saves the content into reserved space.
-
-Here is the address Map for S3 Resume. Assumingly the total memory is 1GB.
-00000000 --- 00100000 BIOS Reserved area.
-00100000 --- 00200000 Free
-00200000 --- 01000000 Coreboot ramstage area.
-01000000 --- 2e160000 Free
-2e160000 --- 2e170000 ACPI table
-2e170000 --- 2ef70000 OSRAM
-2ef70000 --- 2efe0000 Stack in highmem
-2efe0000 --- 2f000000 heap in highmem
-2f000000 TOM
-
-AMD requirements in S3
-======================
-Chip vendor like AMD will provide bunch of routines to restore the
-board.[2]
- * AmdS3Save: It is called in cold boot, save required register into
- non-volatile storage. Currently, we use SPI flash to store the data.
- * AmdInitResume: Restore the memory controller.
- * AmdS3LateRestore: Called after AmdInitResume, restore other
- register that memory.
- * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore:
- Provided by Southbridge vendor code. Early is called before PCI
- enumeration, and Late is called after that.
-
-Lifecycle of booting, sleeping and waking Coreboot and Ubuntu
-=============================================================
-1. Cold boot.
-For a system with S3 feature, the BIOS needs to save some data to
-non-volatile storage at cold boot stage. What data need to be save are
-provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets
-the VolatileStorage and NvStorage, which are where the data are
-located. It is the wrappers's responsibility to save the data.[3][4]
-Currently, the wrappers allocate a CBFS modules in BIOS image. To do
-that, the wrapper needs to have the ability to write flash chips. It
-is not as comprehensive as flashrom. But for the SST chip on Parmer,
-MX chip on Thather, coreboot works well.[5]
-
-2. OS goes in S3.
-For Linux, besides the kernel needs to do some saving, most distributions
-run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d.
- # ls /usr/lib/pm-utils/sleep.d
- 000kernel-change 49bluetooth 90clock 95led
- 00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler
- 00powersave 60_wpa_supplicant 95anacron 99video
- 01PulseAudio 75modules 95hdparm-apm
-The script with lower prefix runs before the one with higher prefix.
-99video is the last one.
-Those scripts have hooks called hibernate, suspend, thaw, resume. For
-each script, suspend is called when system sleeps and wakeup is called
-when system wakeups.
-
-3. Firmware detects S3 wakeup
-As we mentioned, Firmware detects the SLP_TYPx to find out if the board
-wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called
-as they are during cold boot. AmdInitResume and AmdS3LateRestore are
-called only during resume. For whole ramstage, Coreboot goes through
-almost the same way as cold boot, other than not calling the AmdInitMid,
-AmdInitLate and AmdS3Save, and restoring all the MTRRs.
-At last step of coreboot stage, coreboot finds out the wakeup vector in FADT,
-written by OS, and jump.
-
-4. OS resumes.
-When Linux resumes, all the sleeping scripts call their resume
-hooks. If we are more lucky, all the scripts can go through. More
-chances that the 99video hangs or fails to get the display
-back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in
-Coreboot/Kconfig. That needs more troubleshooting.
-
-
-Reference
-=========
-[1] ACPI40a, http://www.acpi.info/spec40a.htm
-[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/
-[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c
-[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c
-[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c
diff --git a/documentation/CorebootBuildingGuide.tex b/documentation/CorebootBuildingGuide.tex
deleted file mode 100644
index 5b3eacf..0000000
--- a/documentation/CorebootBuildingGuide.tex
+++ /dev/null
@@ -1,1797 +0,0 @@
-%
-% This document is released under the GPL
-% Initially written by Stefan Reinauer, <stepan(a)coresystems.de>
-%
-
-\documentclass[titlepage,12pt]{article}
-\usepackage{a4}
-\usepackage{graphicx}
-\usepackage{url}
-\usepackage[pdftex]{hyperref}
-% \usepackage{makeidx}
-% \makeindex
-
-\hypersetup{
- urlbordercolor={1 1 1},
- menubordercolor={1 1 1},
- linkbordercolor={1 1 1},
- colorlinks=false,
- % pdfpagemode=None, % PDF-Viewer starts without TOC
- % pdfstartview=FitH,
- pdftitle={coreboot on AMD64},
- pdfauthor={Stefan Reinauer},
- pdfsubject={coreboot configuration and build process},
- pdfkeywords={coreboot, Opteron, AMD64, configuration, Build}
-}
-
-
-% \newcommand{\sh}[1]{\begin{verbatim}\texttt{#1}\end{verbatim}}
-% \newcommand{\prog}[1]{\textit{#1}}
-
-\setlength{\parindent}{0pt}
-
-\title{coreboot on AMD64}
-\author{Stefan Reinauer $<$stepan(a)coresystems.de$>$}
-\date{April 19th, 2009}
-
-\begin{document}
-
-\maketitle
-
-\thispagestyle{empty}
-
-\tableofcontents
-
-\newpage
-
-%
-% 1 Abstract
-%
-
-\section{Abstract}
-
-This document targets porting coreboot to new mainboards and creating
-custom firmware images using coreboot. It describes how to build
-coreboot images for the AMD64 platform, including hypertransport
-configuration and pertinent utilities. If you are missing information or
-find errors in the following descriptions, contact
-\href{mailto:stepan@coresystems.de}{\textit{Stefan Reinauer $<$stepan(a)coresystems.de$>$}}
-
-
-%
-% 2 Changes
-%
-
-\section{Changes}
- \begin{itemize}
- \item 2009/04/19 replace LinuxBIOS with coreboot
- \item 2004/06/02 url and language fixes from Ken Fuchs $<$kfuchs(a)winternet.com$>$
- \item 2004/02/10 acpi and option rom updates
- \item 2003/11/18 initial release
- \end{itemize}
-
-
-
-%
-% 3 What is coreboot
-%
-
-\section{What is coreboot?}
-
-coreboot aims to replace the normal BIOS found on x86, AMD64, PPC,
-Alpha, and other machines with a Linux kernel that can boot Linux from a cold
-start. The startup code of an average coreboot port is about 500 lines of
-assembly and 5000 lines of C. It executes 16 instructions to get into 32bit
-protected mode and then performs DRAM and other hardware initializations
-required before Linux can take over.
-
-The projects primary motivation initially was maintenance of large
-clusters. Not surprisingly interest and contributions have come from
-people with varying backgrounds. Nowadays a large and growing number of
-Systems can be booted with coreboot, including embedded systems,
-Desktop PCs and Servers.
-
-%
-% 4 Build Requirements
-%
-
-\section{Build Requirements}
-To build coreboot for AMD64 from the sources you need a recent Linux
-system for x86 or AMD64. SUSE Linux 8.2 or 9.0 are known to work fine.
-The following toolchain is recommended:
-
- \begin{itemize}
- \item GCC 3.3.1
- \item binutils 2.14.90.0.5
- \item Python 2.3
- \item CVS 1.11.6
- \end{itemize}
-
-\textbf{NOTE:} Later versions should also work. Prior versions might lead to problems.
-
-\newpage
-
-%
-% 5 Getting the Sources
-%
-
-\section{Getting the Sources}
-
-The latest coreboot sources are available via subversion. The subversion
-repository is maintained at SourceForge.net (the project name is
-\emph{FreeBIOS}). First you should create a directory for your
-coreboot trees:
-
-{ \small
-\begin{verbatim}
-$ mkdir coreboot
-$ cd coreboot
-\end{verbatim}
-}
-
-You can get the entire source tree via SVN:
-
-{ \small
-\begin{verbatim}
-$ svn co svn://coreboot.org/repos/trunk/coreboot-v2
-\end{verbatim}
-}
-
-Once the source tree is checked out, it can be updated with:
-
-{ \small
-\begin{verbatim}
-% svn update
-\end{verbatim}
-}
-
-For the case your corporate firewall blocks port 3690 (subversion) we set up a
-snapshot site that keeps the last few hundred source code revisions. It
-is available at \url{http://qa.coreboot.org/}.
-Due to major structural enhancements to \hbox{coreboot}, AMD64 support
-is only available in the \texttt{coreboot-v2} tree. This tree reflects (as
-of November 2003) coreboot version 1.1.5 and will lead to coreboot 2.0
-when finished. Most x86 hardware is currently only supported by the
-coreboot 1.0 tree.
-
-%
-% 6 coreboot configuration overview
-%
-
-\section{coreboot configuration overview}
-To support a large variety of existing hardware coreboot allows for a
-lot of configuration options that can be tweaked in several ways:
-
-\begin{itemize}
-\item
-Firmware image specific configuration options can be set in the image
-configuration file which is usually found in
-\texttt{coreboot-v2/targets/$<$vendor$>$/$<$mainboard$>$/}. Such
-options are the default amount of output verbosity during bootup, image
-size, use of fallback mechanisms, firmware image size and payloads
-(Linux Kernel, Bootloader...) The default configuration file name is
-\texttt{Config.lb}, but coreboot allows multiple configurations to
-reside in that directory.
-
-\item Mainboard specific configuration options can be set in the
-mainboard configuration file placed in
-\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$}. The
-mainboard configuration file is always called \texttt{Config.lb}. It
-contains information on the onboard components of the mainboard like
-CPU type, northbridge, southbridge, hypertransport configuration and
-SuperIO configuration. This configuration file also allows to include
-addon code to hook into the coreboot initialization mechanism at
-basically any point.
-
-\end{itemize}
-
-This document describes different approaches of changing and configuring the
-coreboot source tree when building for AMD64.
-
-%
-% 7 Building coreboot
-%
-
-\section{Building coreboot}
-One of the design goals for building coreboot was to keep object files
-out of the source tree in a separate place. This is mandatory for
-building parallel coreboot images for several distinct mainboards
-and/or platforms. Therefore building coreboot consists of two steps:
-\begin{itemize}
-\item
-creating a build tree which holds all files automatically created by the
-configuration utility and the object files
-\item
-compiling the coreboot code and creating a flashable firmware image.
-\end{itemize}
-
-The first of these two steps is accomplished by the \texttt{buildtarget}
-script found in \texttt{coreboot-v2/targets/}. To build coreboot for
-instance for the AMD Solo Athlon64 mainboard enter:
-
-\begin{verbatim}
-% cd coreboot-v2/targets
-% ./buildtarget amd/solo
-\end{verbatim}
-
-This will create a directory containing a Makefile and other software
-components needed for this build. The directory name is defined in the
-firmware image specific configuration file. In the case of AMD's Solo
-mainboard the default directory resides in
-\texttt{coreboot-v2/targets/amd/solo/solo}. To build the coreboot image, do
-
-\begin{verbatim}
-% cd amd/solo/solo
-% make
-\end{verbatim}
-
-The coreboot image filename is specified in the firmware image specific
-configuration file. The default filename for AMD's Solo mainboard is
-\texttt{solo.rom}.
-
-%
-% 8 Programming coreboot to flash memory
-%
-
-\section{Programming coreboot to flash memory}
-The image resulting from a coreboot build can be directly programmed to
-a flash device, either using a hardware flash programmer or by using the
-Linux flash driver devbios or mtd. This document assumes that you use a
-hardware flash programmer. If you are interested in doing in-system
-software flash programming, find detailed information:
-
-\begin{itemize}
-\item \url{http://www.openbios.org/development/devbios.html} (/dev/bios)
-\item \url{http://www.linux-mtd.infradead.org/} (Memory Technology Device Subsystem MTD)
-\end{itemize}
-
-\newpage
-
-%
-% 9 coreboot configuration
-%
-
-\section{coreboot configuration}
-The following chapters will cope with configuring coreboot. All
-configuration files share some basic rules
-\begin{itemize}
-\item
-The default configuration file name in coreboot is \texttt{Config.lb}.
-\item
-All variables used in a configuration file have to be declared in this
-file with \texttt{uses VARNAME} before usage.
-\item
-Comments can be added on a new line by using the comment identifier
-\texttt{\#} at the beginning of the line.
-\item
-coreboot distinguishes between statements and options. Statements cause
-the coreboot configuration mechanism to act, whereas options set
-variables that are used by the build scripts or source code.
-\item
-Default configuration values can be set in the mainboard configuration
-files (keyword default)
-\item
-Option overrides to the default configuration can only be specified in
-the build target configuration file
-\texttt{coreboot-v2/targets/$<$vendor$>$/$<$mainboard$>$/Config.lb}
-(keyword option)
-\end{itemize}
-
-\subsection{Common Configuration Statements}
-
-\begin{itemize}
-
-\item \begin{verbatim}uses\end{verbatim}
-
-All local configuration variables have to be declared before they can be
-used. Example:
-\begin{verbatim}
- uses CONFIG_ROM_IMAGE_SIZE
-\end{verbatim}
-
-\textbf{NOTE:} Only configuration variables known to the configuration
-system can be used in configuration files. coreboot checks
-\texttt{coreboot-v2/src/config/Options.lb} to see whether a configuration
-variable is known.
-
-\item \begin{verbatim}default\end{verbatim}
-
-The \texttt{default} statement is used to set a configuration variable
-with an overridable default value. It is commonly used in mainboard
-configuration files.
-
-Example:
-
-\begin{verbatim}
- default CONFIG_ROM_IMAGE_SIZE=0x10000
-\end{verbatim}
-
-It is also possible to assign the value of one configuration variable to
-another one, i.e.:
-
-\begin{verbatim}
- default CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
-\end{verbatim}
-
-Also, simple expressions are allowed:
-
-\begin{verbatim}
- default CONFIG_FALLBACK_SIZE=(CONFIG_ROM_SIZE - NORMAL_SIZE)
-\end{verbatim}
-
-If an option contains a string, this string has to be protected with
-quotation marks:
-
-\begin{verbatim}
- default CC="gcc -m32"
-\end{verbatim}
-
-\item \begin{verbatim}option\end{verbatim}
-
-The \texttt{option} statement basically behaves identically to the
-\texttt{default} statement. But unlike default it can only be used in
-build target configuration files
-(\texttt{coreboot-v2/targets/$<$vendor$>$/$<$mainboard$>$}). The option
-statement allows either to set new options or to override default values
-set with the default statement in a mainboard configuration file.
-Syntax and application are the same as with default.
-
-\end{itemize}
-
-\subsection{Firmware image specific configuration}
-coreboot allows to create different firmware images for the same
-hardware. Such images can differ in the amount of output they produce,
-the payload, the number of subimages they consist of etc.
-
-The firmware image specific configuration file can be found in \\
-\texttt{coreboot-v2/targets/$<$vendor$>$/<mainboard$>$}.
-
-\subsubsection{Firmware image specific keywords}
-In addition to the above described keywords the following statements are
-available in firmware image specific configuration files:
-
-\begin{itemize}
-\item \begin{verbatim}romimage\end{verbatim}
-
-The \texttt{romimage} definition describes a single rom build within the
-final coreboot image. Normally there are two romimage definitions per
-coreboot build: \texttt{normal} and \texttt{fallback}.
-
-Each \texttt{romimage} section needs to specify a mainboard directory and a
-payload. The mainboard directory contains the mainboard specific
-configuration file and source code. It is specified relatively to
-\texttt{coreboot-v2/src/mainboard}. The payload definition is an absolute
-path to a static elf binary (i.e Linux kernel or etherboot)
-
-\begin{verbatim}
-romimage "normal"
- option CONFIG_USE_FALLBACK_IMAGE=0
- option CONFIG_ROM_IMAGE_SIZE=0x10000
- option COREBOOT_EXTRA_VERSION=".0Normal"
- mainboard amd/solo
- payload /suse/stepan/tg3ide_
- disk.zelf
-end
-\end{verbatim}
-
-\item \begin{verbatim}buildrom\end{verbatim}
-
-The \texttt{buildrom} statement is used to determine which of the
-coreboot image builds (created using \texttt{romimage}) are packed
-together to the final coreboot image. It also specifies the order of
-the images and the final image size:
-
-\begin{verbatim}
- buildrom ./solo.rom CONFIG_ROM_SIZE "normal" "fallback"
-\end{verbatim}
-
-\end{itemize}
-
-
-\subsubsection{Firmware image configuration options}
-In addition to the definitions described above there are a number of
-commonly used options. Configuration options set in the firmware image
-specific configuration file can override default selections from the
-Mainboard specific configuration. See above examples about
-option on how to set them.
-
-\begin{itemize}
-
-\item \begin{verbatim}CC\end{verbatim}
-
-Target C Compiler. Default is \texttt{\$(CROSS\_COMPILE)gcc}. Set to
-\texttt{gcc -m32} for compiling AMD64 coreboot images on an AMD64
-machine.
-
-\item \begin{verbatim}CONFIG_CHIP_CONFIGURE \end{verbatim}
-
-Use new \textit{chip\_configure} method for configuring (nonpci)
-devices. Set to \texttt{1} for all AMD64 mainboards.
-
-\item \begin{verbatim}CONFIG_DEFAULT_CONSOLE_LOGLEVEL\end{verbatim}
-
-Console will log at this level unless changed. Default is \texttt{7},
-minimum is \texttt{0}, maximum is \texttt{10}.
-
-\item \begin{verbatim}CONFIG_CONSOLE_SERIAL8250\end{verbatim}
-
-Log messages to 8250 uart based serial console. Default is \texttt{0}
-(don't log to serial console). This value should be set to \texttt{1}
-for all AMD64 builds.
-
-\item \begin{verbatim}CONFIG_ROM_SIZE\end{verbatim}
-
-Size of final ROM image. This option has no default value.
-
-\item \begin{verbatim}CONFIG_FALLBACK_SIZE\end{verbatim}
-
-Fallback image size. Defaults to \texttt{65536} bytes. \textbf{NOTE:}
-This does not include the fallback payload.
-
-\item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim}
-
-Export CMOS option table. Default is \texttt{0}. Set to \texttt{1} if
-your mainboard has CMOS memory and you want to use it to store
-coreboot parameters (Loglevel, serial line speed, ...)
-
-\item \begin{verbatim}CONFIG_ROM_PAYLOAD\end{verbatim}
-
-Boot image is located in ROM (as opposed to \texttt{CONFIG\_IDE\_PAYLOAD}, which
-will boot from an IDE disk)
-
-\item \begin{verbatim}CONFIG_HAVE_FALLBACK_BOOT\end{verbatim}
-
-Set to \texttt{1} if fallback booting is required. Defaults to
-\texttt{0}.
-
-\end{itemize}
-
-
-The following options should be used within a romimage section:
-
-\begin{itemize}
-
-\item \begin{verbatim}CONFIG_USE_FALLBACK_IMAGE\end{verbatim}
-
-Set to \texttt{1} to build a fallback image. Defaults to \texttt{0}
-
-\item \begin{verbatim}CONFIG_ROM_IMAGE_SIZE\end{verbatim}
-
-Default image size. Defaults to \texttt{65535} bytes.
-
-\item \begin{verbatim}COREBOOT_EXTRA_VERSION\end{verbatim}
-
-coreboot extra version. This option has an empty string as default. Set
-to any string to add an extra version string to your coreboot build.
-
-\end{itemize}
-
-\newpage
-
-\subsection{Mainboard specific configuration}
-
-Mainboard specific configuration files describe the onboard
-mainboard components, i.e. bridges, number and type of CPUs. They also
-contain rules for building the low level start code which is translated
-using romcc and/or the GNU assembler. This code enables caches and
-registers, early mtrr settings, fallback mechanisms, dram init and
-possibly more.
-
-\textbf{NOTE:} The \texttt{option} keyword can not be used in mainboard
-specific configuration files. Options shall instead be set using the
-\texttt{default} keyword so that they can be overridden by the image
-specific configuration files if needed.
-
-\subsubsection{Mainboard specific keywords}
-
-The following statements are used in mainboard specific configuration
-files:
-
-\begin{itemize}
-\item \begin{verbatim}arch\end{verbatim}
-
-Sets the CPU architecture. This should be \texttt{i386} for AMD64 boards.\\
-Example:
-
-\begin{verbatim}
- arch i386 end
-\end{verbatim}
-
-\item \begin{verbatim}cpu\end{verbatim}
-
-The cpu statement is needed once per possibly available CPU. In a
-one-node system, write:
-
-\begin{verbatim}
- cpu k8 "cpu0" end
-\end{verbatim}
-
-\item \begin{verbatim}driver\end{verbatim}
-
-The \texttt{driver} keyword adds an object file to the driver section of a
-coreboot image. This means it can be used by the PCI device
-initialization code. Example:
-
-\begin{verbatim}
- driver mainboard.o
-\end{verbatim}
-
-\item \begin{verbatim}object\end{verbatim}
-
-The \texttt{object} keyword adds an object file to the coreboot image.
-Per default the object file will be compiled from a \texttt{.c} file
-with the same name. Symbols defined in such an object file can be used
-in other object files and drivers. Example:
-
-\begin{verbatim}
- object reset.o
-\end{verbatim}
-
-\item \begin{verbatim}makerule\end{verbatim}
-
-This keyword can be used to extend the existing file creation rules
-during the build process. This is useful if external utilities have to
-be used for the build. coreboot on AMD64 uses romcc for it's early
-startup code placed in auto.c.
-
-To tell the configuration mechanism how to build \texttt{romcc} files,
-do:
-
-\begin{verbatim}
-makerule ./auto.E
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
- $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) \
- $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-\end{verbatim}
-
-Each \texttt{makerule} section contains file dependencies (using the
-texttt{depends} keyword) and an action that is taken when the dependencies
-are satisfied (using the \texttt{action} keyword).
-
-\item \begin{verbatim}mainboardinit\end{verbatim}
-
-With the mainboardinit keyword it's possible to include assembler code
-directly into the coreboot image. This is used for early infrastructure
-initialization, i.e. to switch to protected mode. Example:
-
-\begin{verbatim}
- mainboardinit cpu/i386/entry16.inc
-\end{verbatim}
-
-\item \begin{verbatim}ldscript\end{verbatim}
-
-The GNU linker ld is used to link object files together to a coreboot
-ROM image.
-
-Since it is a lot more comfortable and flexible to use the GNU linker
-with linker scripts (ldscripts) than to create complex command line
-calls, coreboot features including linker scripts to control image
-creation. Example:
-
-\begin{verbatim}
- ldscript /cpu/i386/entry16.lds
-\end{verbatim}
-
-
-\item \begin{verbatim}dir\end{verbatim}
-
-coreboot reuses as much code between the different ports as possible.
-To achieve this, commonly used code can be stored in a separate
-directory. For a new mainboard, it is enough to know that the code in
-that directory can be used as is.
-
-coreboot will also read a \texttt{Config.lb} file stored in that
-directory. This happens with:
-
-\begin{verbatim}
- dir /pc80
-\end{verbatim}
-
-
-\item \begin{verbatim}config\end{verbatim}
-
-This keyword is needed by the new chip configuration scheme. Should be
-used as:
-
-\begin{verbatim}
- config chip.h
-\end{verbatim}
-
-\item \begin{verbatim}register\end{verbatim}
-The \texttt{register} keyword can occur in any section, passing
-additional \\
-parameters to the code handling the associated device.
-Example:
-
-\begin{verbatim}
- register "com1" = "{1, 0, 0x3f8, 4}"
-\end{verbatim}
-
-\item \begin{verbatim}northbridge\end{verbatim}
-
-The \texttt{northbridge} keyword describes a system northbridge. Some
-systems, like AMD64, can have more than one northbridge, i.e. one per
-CPU node. Each northbridge is described by the path to the northbridge
-code in coreboot (relative to \texttt{coreboot-v2/src/northbridge}), i.e.
-\texttt{amd/amdk8} and a unique name (i.e \texttt{mc0}) \\
-Example:
-
-\begin{verbatim}
- northbridge amd/amdk8 "mc0"
- [..]
- end
-\end{verbatim}
-
-\item \begin{verbatim}southbridge\end{verbatim}
-
-To simplify the handling of bus bridges in a coreboot system, all
-bridges available in a system that are not northbridges (i.e AGP, IO,
-PCIX) are seen as southbridges.
-
-Since from the CPUs point of view any southbridge is connected via the
-northbridge, a southbridge section is declared within the northbridge
-section of the north bridge it is attached to.
-
-Like the northbridge, any other bridge is described by the path to it's
-driver code, and a unique name. If the described bridge is a
-hypertransport device, the northbridge's hypertransport link it connects
-to can be specified using the \texttt{link} keyword. Example:
-
-\begin{verbatim}
-northbridge amd/amdk8 "mc0"
- [..]
- southbridge amd/amd8111 "amd8111" link 0
- [..]
- end
- [..]
-end
-\end{verbatim}
-
-\item \begin{verbatim}pci\end{verbatim}
-
-The \texttt{pci} keyword can only occur within a \texttt{northbridge} or
-\texttt{southbridge} section. It is used to describe the PCI devices
-that are provided by the bridge. Generally all bridge sections have a
-couple of \texttt{pci} keywords.
-
-The first occurrence of the \texttt{pci} keyword tells coreboot where
-the bridge devices start, relative to the PCI configuration space used
-by the bridge. The following occurences of the \texttt{pci} keyword
-describe the provided devices.
-
-Adding the option \texttt{on} or \texttt{off} to a PCI device will
-enable or disable this device. This feature can be used if some bridge
-devices are not wired to hardware outputs and thus are not used.
-
-Example:
-
-\begin{verbatim}
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
-end
-\end{verbatim}
-
-or
-
-\begin{verbatim}
-southbridge amd/amd8111 "amd8111" link 0
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 off
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 on
- pci 1:1.0 off
- [..]
-end
-\end{verbatim}
-
-\item \begin{verbatim}superio\end{verbatim}
-
-SuperIO devices are basically handled like brigdes. They are taking
-their driver code from \texttt{coreboot-v2/src/superio/}. They don't
-provide a PCI compatible configuration interface, but instead are ISA
-PnP devices. Normally they are connected to a southbridge. If this is
-the case, the \texttt{superio} section will be a subsection of the
-\texttt{southbridge} section of the southbridge it is connected to.
-Example:
-
-\begin{verbatim}
-superio nsc/pc87360 link 1
- pnp 2e.0
- pnp 2e.1
- pnp 2e.2
- pnp 2e.3
- pnp 2e.4
- pnp 2e.5
- pnp 2e.6
- pnp 2e.7
- pnp 2e.8
- pnp 2e.9
- pnp 2e.a
- register "com1" = "{1, 0, 0x3f8, 4}"
- register "lpt" = "{1}"
-end
-\end{verbatim}
-
-\end{itemize}
-
-\newpage
-
-\subsubsection{Mainboard specific configuration options}
-
-The following options are commonly used in mainboard specific
-configuration files.
-
-They should be set using the \texttt{default} keyword:
-
-\begin{itemize}
-
-\item \begin{verbatim}CONFIG_HAVE_HARD_RESET\end{verbatim}
-
-If set to \texttt{1}, this option defines that there is a hard reset
-function for this mainboard. This option is not defined per default.
-
-\item \begin{verbatim}CONFIG_HAVE_PIRQ_TABLE\end{verbatim}
-
-If set to \texttt{1}, this option defines that there is an IRQ Table for
-this mainboard. This option is not defined per default.
-
-\item \begin{verbatim}CONFIG_IRQ_SLOT_COUNT\end{verbatim}
-
-Number of IRQ slots. This option is not defined per default.
-
-\item \begin{verbatim}CONFIG_HAVE_MP_TABLE\end{verbatim}
-
-Define this option to build an MP table (v1.4). The default is not to
-build an MP table.
-
-\item \begin{verbatim}CONFIG_HAVE_OPTION_TABLE\end{verbatim}
-
-Define this option to export a CMOS option table. The default is not to
-export a CMOS option table.
-
-\item \begin{verbatim}CONFIG_SMP\end{verbatim}
-
-Set this option to \texttt{1} if the mainboard supports symmetric
-multiprocessing (SMP). This option defaults to \texttt{0} (no SMP).
-
-\item \begin{verbatim}CONFIG_MAX_CPUS\end{verbatim}
-
-If \begin{verbatim}CONFIG_SMP\end{verbatim} is set, this option defines
-the maximum number of CPUs (i.e. the number of CPU sockets) in the
-system. Defaults to \texttt{1}.
-
-\item \begin{verbatim}CONFIG_IOAPIC\end{verbatim}
-
-Set this option to \texttt{1} to enable IOAPIC support. This is
-mandatory if you want to boot a 64bit Linux kernel on an AMD64 system.
-
-\item \begin{verbatim}CONFIG_STACK_SIZE\end{verbatim}
-
-coreboot stack size. The size of the function call stack defaults to
-\texttt{0x2000} (8k).
-
-\item \begin{verbatim}CONFIG_HEAP_SIZE\end{verbatim}
-
-coreboot heap size. The heap is used when coreboot allocates memory
-with malloc(). The default heap size is \texttt{0x2000}, but AMD64 boards
-generally set it to \texttt{0x4000} (16k)
-
-\item \begin{verbatim}CONFIG_XIP_ROM_BASE\end{verbatim}
-
-Start address of area to cache during coreboot execution directly from
-ROM.
-
-\item \begin{verbatim}CONFIG_XIP_ROM_SIZE\end{verbatim}
-
-Size of area to cache during coreboot execution directly from ROM
-
-\item \begin{verbatim}CONFIG_COMPRESS\end{verbatim}
-
-Set this option to \texttt{1} for a compressed image. If set to
-\texttt{0}, the image is bigger but will start slightly faster (since no
-decompression is needed).
-
-\end{itemize}
-
-
-\newpage
-
-%
-% 10. Tweaking the source code
-%
-
-\section{Tweaking the source code}
-Besides configuring the existing code it is sometimes necessary or
-desirable to tweak certain parts of coreboot by direct changes to the
-code. This chapter covers some possible enhancements and changes that
-are needed when porting coreboot to a new mainboard or just come
-handy now and then.
-
-\subsection{Hypertransport configuration}
-Before coreboot is able to activate all CPUs and detect bridges
-attached to these CPUs (and thus, see all devices attached to the
-system) it has to initialize the coherent hypertransport devices.
-
-The current algorithms to do coherent hypertransport initialization are
-not fully, automatically evaluating the hypertransport chain graph.
-Therefore the code needs to be adapted when porting coreboot to a new
-AMD64 mainboard. An example arrangement of hypertransport devices
-looks like this:
-
-\begin{figure}[htb]
-\centering
-\includegraphics[scale=1.0]{hypertransport.pdf}
-\caption{Example: Hypertransport Link Connections}
-\label{fix:hypertransport}
-\end{figure}
-
-Each hypertransport device has one to three hypertransport links that
-are used for device interconnection. These links are called LDT$[$012$]$, or
-accordingly UP, ACROSS, DOWN. Communication between the hypertransport
-devices can be freely routed, honoring the physical wiring. Teaching the
-coherent hypertransport initialization algorithm this wiring happens in
-two steps.
-
-\newpage
-
-\begin{enumerate}
-\item Setting outgoing connections
-The algorithm needs to know which outgoing port of a CPU node is
-connected to the directly succeeding node. This is done in
-\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/auto.c}
-with a number of preprocessor defines (one define for two-node systems,
-three defines for four-node systems).
-
-The ports in question are flagged with a circle in the graph for
-illustration. For the example graph above (all outgoing connections are
-realized using LDT1/ACROSS) the defines are:
-
-\begin{verbatim}
-#define CONNECTION_0_1 ACROSS
-#define CONNECTION_0_2 ACROSS
-#define CONNECTION_1_3 ACROSS
-\end{verbatim}
-
-\item Describing routing information between CPUs.
-
-There are basically three different message types for hypertransport
-communication:
-\begin{enumerate}
-\item request packages
-\item response packages
-\item broadcast packages
-\end{enumerate}
-
-These three message types are routed using different hypertransport
-ports. The routing information is written to the AMD K8 routing table.
-In an Nnode system this routing table consists of 3*N*N entries , one
-for each message type and for each possible CPU --> CPU communication. For
-simplicity coreboot keeps the 3 routing entries for each CPU --> CPU
-communication in one machine word. The routing table of each node looks
-like this:
-
-\begin{verbatim}
-/* Routing Table for Node i
- *
- * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
- * i: 0, 1, 2, 3, 4, 5, 6, 7
- *
- * [ 0: 3] Request Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [11: 8] Response Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [19:16] Broadcast route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- */
-\end{verbatim}
-
-The routing table is passed to the coherent hypertransport
-initialization algorithm by defining a function called
-\texttt{generate\_row()} in \texttt{auto.c}:
-
-\begin{verbatim}
-static unsigned int generate_row
- (uint8_t node, uint8_t row, uint8_t maxnodes)
-\end{verbatim}
-
-This function is trivial if there is only one CPU in the system, since
-no routing has to be done:
-
-\begin{verbatim}
-static unsigned int generate_row
- (uint8_t node, uint8_t row, uint8_t maxnodes)
-{
- return 0x00010101; /* default row entry */
-}
-\end{verbatim}
-
-On a two-node system things look slightly more complicated. Since the
-coherent hypertransport initialization algorithm works by consecutively
-enabling CPUs, it contains routing information for driving the system
-with one node and two nodes:
-
-\begin{verbatim}
-static unsigned int generate_row
- (uint8_t node, uint8_t row, uint8_t maxnodes)
-{
- uint32_t ret=0x00010101; /* default row entry */
- static const unsigned int rows_2p[2][2] = {
- { 0x00050101, 0x00010404 },
- { 0x00010404, 0x00050101 }
- };
- if(maxnodes>2) maxnodes=2;
- if (!(node>=maxnodes || row>=maxnodes)) {
- ret=rows_2p[node][row];
- }
- return ret;
-}
-\end{verbatim}
-
-Systems with four nodes have to contain routing information for one, two
-and four-node setups:
-
-\begin{verbatim}
-static unsigned int generate_row
- (uint8_t node, uint8_t row, uint8_t maxnodes)
-{
- uint32_t ret=0x00010101; /* default row entry */
- static const unsigned int rows_2p[2][2] = {
- { 0x00030101, 0x00010202 },
- { 0x00010202, 0x00030101 }
- };
- static const unsigned int rows_4p[4][4] = {
- { 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
- { 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
- { 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
- { 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
- };
- if (!(node>=maxnodes || row>=maxnodes)) {
- if (maxnodes==2)
- ret=rows_2p[node][row];
- if (maxnodes==4)
- ret=rows_4p[node][row];
- }
- return ret;
-}
-\end{verbatim}
-\end{enumerate}
-
-\subsection{DRAM configuration}
-Setting up the RAM controller(s) is probably the most complex part of
-coreboot. Basically coreboot serially initializes all RAM controllers
-in the system, using SPDROM (serial presence detect) data to set
-timings, size and other properties. The SPD data is usually read
-utilizing the I2C SMBUS interface of the southbridge.
-
-There is one central data structure that describes the RAM controllers
-available on an AMD64 system and the associated devices:
-
-\begin{verbatim}
-struct mem_controller {
- unsigned node_id;
- device_t f0, f1, f2, f3;
- uint8_t channel0[4];
- uint8_t channel1[4];
-};
-\end{verbatim}
-
-Available mainboard implementations and CPUs create the need to add
-special setup code to RAM initialization in a number of places.
-coreboot provides hooks to easily add code in these places without
-having to change the generic code. Whether these hooks have to be used
-depends on the mainboard design. In many cases the functions executed
-by the hooks just carry out trivial default settings or they are even
-empty.
-
-Some mainboard/CPU combinations need to trigger an additional memory
-controller reset before the memory can be initialized properly. This is,
-for example, used to get memory working on preC stepping AMD64
-processors. coreboot provides two hooks for triggering onboard memory
-reset logic:
-
-\begin{itemize}
-\item \begin{verbatim}static void memreset_setup(void)\end{verbatim}
-\item \begin{verbatim}static void memreset(int controllers, const struct
- mem_controller *ctrl)\end{verbatim}
-\end{itemize}
-
-Some mainboards utilize an SMBUS hub or possibly other mechanisms to
-allow using a large number of SPDROMs and thus ram sockets. The result
-is that only the SPDROM information of one cpu node is visible at a
-time. The following function, defined in \texttt{auto.c}, is called every time
-before a memory controller is initialized and gets the memory controller
-information of the next controller as a parameter:
-
-\begin{verbatim}
-static inline void activate_spd_rom (const struct mem_controller *ctrl)
-\end{verbatim}
-
-The way SMBUS hub information is coded into the \texttt{mem\_controller}
-structure is mainboard implementation specific and not
-described here. See \texttt{coreboot-v2/src/mainboard/amd/quartet/auto.c}
-for an example.
-
-coreboot folks have agreed on SPD data being the central information
-source for RAM specific information. But not all mainboards/RAM
-modules feature a physical SPD ROM. To still allow an easy to use SPD
-driven setup, there is a hook that abstracts reading the SPD ROM
-ingredients that are used by the memory initialization mechanism:
-
-\begin{verbatim}
-static inline int spd_read_byte(unsigned device, unsigned address)
-\end{verbatim}
-
-This function, defined in \texttt{auto.c}, directly maps it's calls to
-\texttt{smbus\_read\_byte()} calls if SPD ROM information is read via
-the I2C SMBUS:
-
-\begin{verbatim}
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device & 0xff, address);
-}
-\end{verbatim}
-
-If there is no SPD ROM available in the system design, this function
-keeps an array of SPD ROM information hard coded per logical RAM module.
-It returns the faked' SPD ROM information using device and address
-as indices to this array.
-
-
-\subsection {IRQ Tables}
-
-Mainboards that provide an IRQ table should have the following two
-variables set in their \texttt{Config.lb} file:
-
-\begin{verbatim}
-default CONFIG_HAVE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=7
-\end{verbatim}
-
-This will make coreboot look for the file \\
-\texttt{coreboot-v2/src/mainboard/<vendor>/<mainboard>/irq\_tables.c} which
-contains the source code definition of the IRQ table. coreboot corrects
-small inconsistencies in the IRQ table during startup (checksum and
-number of entries), but it is not yet writing IRQ tables in a completely
-dynamic way.
-
-\textbf{NOTE:} To get Linux to understand and actually use the IRQ
-table, it is not always a good idea to specify the vendor and device id
-of the actually present interrupt router device. Linux 2.4 for example
-does not know about the interrupt router of the AMD8111 southbridge. In
-such cases it is advised to choose the vendor/device id of a compatible
-device that is supported by the Linux kernel. In case of the AMD8111
-interrupt router it is advised to specify the AMD768/Opus interrupt
-controller instead (vendor id=\texttt{0x1022}, device id=\texttt{0x7443})
-
-\subsection {MP Tables}
-
-coreboot contains code to create MP tables conforming the
-Multiprocessor Specification V1.4. To include an MP Table in a coreboot
-image, the following configuration variables have to be set (in the
-mainboard specific configuration file
-\texttt{coreboot-v2/src/mainboard/<vendor><mainboard>/Config.lb}):
-
-\begin{verbatim}
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=1 # 2,4,..
-default CONFIG_HAVE_MP_TABLE=1
-\end{verbatim}
-
-coreboot will then look for a function for setting up the MP table in
-the file \texttt{coreboot-v2/src/mainboard<vendor>/<mainboard>/mptable.c}:
-
-\begin{verbatim}
-void *smp_write_config_table(void *v, unsigned long * processor_map)
-\end{verbatim}
-
-MP Table generation is still somewhat static, i.e. changing the bus
-numbering will force
-you to adopt the code in mptable.c. This is subject to change in future
-revisions.
-
-\subsection {ACPI Tables}
-
-There is initial ACPI support in coreboot now. Currently the only gain with
-this is the ability to use HPET timers in Linux. To achieve this, there is a
-framework that can generate the following tables:
-\begin{itemize}
-\item RSDP
-\item RSDT
-\item MADT
-\item HPET
-\end{itemize}
-
-To enable ACPI in your coreboot build, add the following lines to your
-configuration files:
-\begin{verbatim}
-uses CONFIG_HAVE_ACPI_TABLES
-[..]
-option CONFIG_HAVE_ACPI_TABLES=1
-\end{verbatim}
-
-To keep Linux doing it's pci ressource allocation based on IRQ tables and MP
-tables, you have to specify the kernel parameter \texttt{pci=noacpi} otherwise
-your PCI devices won't get interrupts.
-It's likely that more ACPI support will follow, when there is need for certain
-features.
-
-\subsection{POST}
-coreboot has three different methods of handling POST codes. They can
-be triggered using configuration file options.
-\begin{itemize}
-\item
-\emph{Ignore POST completely}. No early code debugging is possible with
-this setting. Set the configuration variable \texttt{NO\_POST} to
-\texttt{1} to switch off all POST handling in coreboot.
-\item
-\emph{Normal IO port 80 POST}. This is the default behavior of
-coreboot. No configuration variables have to be set. To be able to see
-port 80 POST output, you need a POST expansion card for ISA or PCI. Port
-80 POST allows simple debugging without any other output method
-available (serial interface or VGA display)
-\item
-\emph{Serial POST}.
-This option allows to push POST messages to the serial interface instead
-of using IO ports. \textbf{NOTE:} The serial interface has to be
-initialized before serial POST can work. To use serial POST, set the
-configuration variable \texttt{CONFIG\_SERIAL\_POST} to the value 1.
-\end{itemize}
-
-
-\subsection{HDT Debugging}
-If you are debugging your coreboot code with a Hardware Debug Tool
-(HDT), you can find the source code line for a given physical EIP
-address as follows: Look the address up in the file linuxbios.map. Then
-search the label Lxx in the file auto.inc created by romcc. The original
-source code file and line number is mentioned in auto.inc.
-
-
-\subsection{Device Drivers}
-With only a few data structures coreboot features a simple but flexible
-device driver interface. This interface is not intended for autonomously
-driving the devices but to initialize all system components so that they
-can be used by the booted operating system.
-
-Since nowadays most systems are PCI centric, the data structures used
-are tuned towards (onboard and expansion bus) PCI devices. Each driver
-consists of at least two structures.
-
-The \texttt{pci\_driver} structure maps PCI vendor/device id pairs to a
-second structure that describes a set of functions that together
-initialize and operate the device:
-
-\begin{verbatim}
- static void adaptec_scsi_init(struct device *dev)
- {
- [..]
- }
- static struct device_operations lsi_scsi_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = lsi_scsi_init,
- .scan_bus = 0,
- };
- static const struct pci_driver lsi_scsi_driver __pci_driver = {
- .ops = &lsi_scsi_ops,
- .vendor = 0xXXXX,
- .device = 0xXXXX,
- };
-\end{verbatim}
-
-By separating the two structures above, M:N relations between compatible
-devices and drivers can be described. The driver source code containing
-above data structures and code have to be added to a coreboot image
-using the driver keyword in the mainboard specific configuration file \\
-\texttt{coreboot-v2/src/mainboard/<vendor>/<mainboard>/Config.lb}:
-
-\begin{verbatim}
- driver lsi_scsi.o
-\end{verbatim}
-
-\subsection{Bus Bridges}
-
-Currently all bridges supported in the coreboot-v2 tree are transparent
-bridges. This means, once the bridge is initialized, it's remote devices
-are visible on one of the PCI buses without special probing. coreboot
-supports also bridges that are nontransparent. The driver support code
-can provide a \texttt{scan\_bus} function to scan devices behind the bridge.
-
-\subsection{CPU Reset}
-When changing speed and width of hypertransport chain connections
-coreboot has to either assert an LDTSTOP or a reset to make the changes
-become active. Additionally Linux can do a firmware reset, if coreboot
-provides the needed infrastructure. To use this capability, define the
-option \texttt{CONFIG\_HAVE\_HARD\_RESET} and add an object file specifying the
-reset code in your mainboard specific configuration file
-\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/Config.lb}:
-
-\begin{verbatim}
- default CONFIG_HAVE_HARD_RESET=1
- object reset.o
-\end{verbatim}
-
-The C source file \texttt{reset.c} (resulting in \texttt{reset.o}
-during compilation) shall define the following function to take care
-of the system reset:
-
-\begin{verbatim}
- void hard_reset(void);
-\end{verbatim}
-
-See \texttt{coreboot-v2/src/mainboard/arima/hdama/reset.c} for an example
-implementation.
-
-\newpage
-
-%
-% 11. coreboot Internals
-%
-
-\section{coreboot Internals}
-This chapter covers some of the internal structures and algorithms of
-coreboot that have not been mentioned so far.
-
-\subsection{Code Flow}
-
-\begin{figure}[htb]
-\centering
-\includegraphics[scale=0.7]{codeflow.pdf}
-\caption{coreboot rough Code Flow}
-\label{fix:codeflow}
-\end{figure}
-
-\newpage
-
-\subsection{Fallback mechanism}
-coreboot provides a mechanism to pack two different coreboot builds
-within one coreboot ROM image. Using the system CMOS memory coreboot
-determines whether the last boot with a default image succeeded and
-boots a failsafe image on failure. This allows insystem testing without
-the risk to render the system unusable. See
-\texttt{coreboot-v2/src/mainboard/arima/hdama/failover.c} for example
-code. The fallback mechanism can be used with the \texttt{cmos\_util}.
-
-\subsection{(Un) Supported Standards}
-coreboot supports the following standards
-\begin{itemize}
-\item Multiprocessing Specification (MPSPEC) 1.4
-\item IRQ Tables (PIRQ)
-\item ACPI (initial support on AMD64)
-\item Elf Booting
-\end{itemize}
-However, the following standards are not supported until now, and will
-probably not be supported in future revisions:
-\begin{itemize}
-\item APM
-\end{itemize}
-
-\subsection{coreboot table}
-coreboot stores information about the system in a data structure called
-the coreboot table. This table can be read under Linux using the tool
-nvramtool from the Lawrence Livermore National Laboratory.
-
-Get more information about lxbios and the utility itself at
-\url{http://www.llnl.gov/linux/lxbios/lxbios.html}
-
-\subsection{ROMCC limitations}
-ROMCC, part of the coreboot project, is a C compiler that translates to
-completely rommable code. This means the resulting code does not need
-any memory to work. This is one of the major improvements in coreboot
-V2, since it allows almost all code to be written in C. DRAM
-initialization can be factored and reused more easily among mainboards
-and platforms.
-
-Since no memory is available during this early initialization point,
-romcc has to map all used variables in registers for the time being.
-Same applies for their stack usage. Generally the less registers are
-used up by the algorithms, the better code can be factored, resulting in
-a smaller object size. Since getting the best register usage is an NP
-hard problem, some heuristics are used to get reasonable translation
-time. If you run out of registers during compilation, try to refactor
-your code.
-
-\subsection{CMOS handling}
-coreboot can use the mainboard's CMOS memory to store information
-defined in a data structure called the CMOS table . This information
-contains serial line speed, fallback boot control, output verbosity,
-default boot device, ECC control, and more. It can be easily enhanced by
-enhancing the CMOS table. This table, if present, is found at
-\texttt{coreboot-v2/src/mainboard/$<$vendor$>$/$<$mainboard$>$/cmos.layout}.
-It describes the available options, their possible values and their
-position within the CMOS memory. The layout file looks as follows:
-\begin{verbatim}
- # startbit length config configID name
- [..]
- 392 3 e 5 baud_rate
- [..]
-
- # configid value human readable description
- 5 0 115200
- 5 1 57600
- 5 2 38400
- 5 3 19200
- 5 4 9600
- 5 5 4800
- 5 6 2400
- 5 7 1200
-
-\end{verbatim}
-
-To change CMOS values from a running Linux system, use the
-\texttt{cmos\_util}, provided by Linux Networks as part of the coreboot
-utilities suite. Get it at
-\textit{ftp://ftp.lnxi.com/pub/linuxbios/utilities/}
-
-\subsection {Booting Payloads}
-coreboot can load a payload binary from a Flash device or IDE. This
-payload can be a boot loader, like FILO or Etherboot, a kernel image, or
-any other static ELF binary. If you specify a bzImage as the payload,
-the cbfs utility will figure out how to create a coreboot payload from it.
-
-\subsection{Kernel on dhcp/tftp}
-
-One possible scenario during testing is that you keep your kernel (or
-any additional payload) on a different machine on the network. This can
-quickly be done using a DHCP and TFTP server.
-
-Use for example following \texttt{/etc/dhcpd.conf} (adapt to your
-network):
-
-\begin{verbatim}
- subnet 192.168.1.0 netmask 255.255.255.0 {
- range 192.168.1.0 192.168.1.31;
- option broadcastaddress 192.168.1.255;
- }
-
- ddnsupdatestyle adhoc;
-
- host hammer12 {
- hardware ethernet 00:04:76:EA:64:31;
- fixedaddress 192.168.1.24;
- filename "vmlinuz.elf";
- }
-\end{verbatim}
-
-
-Additionally you have to run a \texttt{tftp} server. You can start one
-using \texttt{inetd}. To do this, you have to remove the comment from
-the following line in \texttt{/etc/inetd.conf}:
-
-\begin{verbatim}
- tftp dgram udp wait root /usr/sbin/in.tftpd in.tftpd -s /tftpboot
-\end{verbatim}
-
-Then put your kernel image \texttt{vmlinuz.elf} in \texttt{/tftpboot} on
-the \texttt{tftp} server.
-
-
-\newpage
-
-%
-% 12. Advanced Device Initialization Mechanisms
-%
-
-\section{Advanced Device Initialization Mechanisms}
-
-Like software, today's hardware is getting more and more complex. To
-stay flexible many hardware vendors start breaking hardware
-compatibility to old standards like VGA. Thus, VGA is still supported by
-most cards, but emulation has to be enabled by the firmware for the
-device to operate properly. Also, many expansion cards are small
-discrete systems that have to initialize attached ram, download
-controller firmware and similar. Without this initialization, an
-operating system can not take advantage of the hardware, so there needs
-to be a way to address this issue. There are several alternatives:
-
-\subsection{Native coreboot Support}
-
-For some devices (ie Trident Cyberblade 3d) there is native coreboot
-support This means there is a small driver bound to the PCI id of the
-device that is called after PCI device ressources are allotted.
-
-PROs:
- \begin{itemize}
- \item open source
- \item minimal driver
- \item early control
- \end{itemize}
-
-CONs:
- \begin{itemize}
- \item need an additional driver
- \item viable for onboard devices only
- \item not flexible for pci cards
- \end{itemize}
-
-\subsection{Using Native Linux Support}
-
-A simple way of getting a whole lot of drivers available for coreboot
-is to reuse Linux drivers by putting a Linux kernel to flash. This
-works, because no drivers are needed to get the Linux kernel (as opposed
-to store the kernel on a harddisk connected to isa/scsi/raid storage)
-
-PROs:
- \begin{itemize}
- \item large number of open source drivers
- \end{itemize}
-
-CONs:
- \begin{itemize}
- \item need Linux in Flash (BLOAT!)
- \item drivers expect devices to be initialized (LSI1020/1030)
- \item Linux only
- \item large flash needed (4MBit minimum, normal operations 8+ MBit)
- \end{itemize}
-
-
-\subsection{Running X86 Option ROMs}
-
-Especially SCSI/RAID controllers and graphics adapters come with a
-special option rom. This option rom usually contains x86 binary code
-that uses a legacy PCBIOS interface for device interaction. If this code
-gets executed, the device becomes operable in Linux and other operating
-systems.
-
-PROs:
- \begin{itemize}
- \item really flexible
- \item no need for additional drivers on firmware layer
- \item large number of supported devices
- \end{itemize}
-
-CONs:
- \begin{itemize}
- \item non-x86 platforms need complex emulation
- \item x86 platforms need legacy API
- \item outdated concept
- \end{itemize}
-
-
-\subsection{Running Open Firmware Option ROMs}
-
-Some PCI devices come with open firmware option roms. These devices are
-normally found in computers from SUN, Apple or IBM. Open Firmware is a
-instruction set architecture independent firmware standard that allows
-device specific initialization using simple, small, but flexible
-bytecode that runs with minimal footprint on all architectures that have
-an Open Firmware implementation.
-
-There is a free Open Firmware implementation available, called OpenBIOS,
-that runs on top of coreboot. See www.openbios.org
-
-PROs:
- \begin{itemize}
- \item architecture independence
- \item small footprint
- \item clean concept, less bugs
- \end{itemize}
-
-CONs:
- \begin{itemize}
- \item only small number of devices come with OpenFirmware capable option roms
- \end{itemize}
-
-%
-% 13 image types
-%
-
-\section{Image types}
-There used to be one image type for coreboot, as described above. Since this paper was written (2004) there have been many changes. First, the name
-was changed to coreboot, for many reasons. Second, Cache As Ram support (CAR)
-was added for many AMD CPUs, which both simplified and complicated things. Simplification came with the removal of romcc; complication came with the addition of new ways to build.
-
-There are two big additions to the build process and, furthermore, more than two new CONFIG variables to control them.
-
-\begin{itemize}
-\item \begin{verbatim}CONFIG_USE_DCACHE_RAM\end{verbatim}
-
-Set to \texttt{1} to use Cache As Ram (CAR). Defaults to \texttt{0}
-
-\end{itemize}
-
-Before going over the new image types, derived from v3, we will quickly review the standard v2 image types. We are hoping this review will
-aid comprehension.
-
-A coreboot rom file consists of one or more \textit{images}. All images consist of a part that runs in ROM, and a part that runs in RAM. The RAM can be in compressed form and is decompressed when needed by the ROM code. The main function of the ROM code is to get memory working. Both ROM and RAM consist of a very small amount of assembly code and mostly C code.
-
-\subsection{romcc images (from emulation/qemu)}
-ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only
-one file; to get more than one file, one must include the C code via include statements. The main ROM code .c file is usually called auto.c.
-\subsubsection{How it is built}
-Romcc compiles auto.c to produce auto.inc. auto.inc is included in the main crt0.S, which is then preprocessed to produce crt0.s. The inclusion of files into crt0.S is controlled by the CONFIG\_CRT0\_INCLUDES variable. crt0.s is then assembled.
-
-File for the ram part are compiled in a conventional manner.
-
-The final step is linking. The use of named sections is used very heavily in coreboot to control where different bits of code go. The reset vector must go in the top 16 bytes. The start portion of the ROM code must go in the top 64K bytes, since most chipsets only enable this much ROM at startup time. Here is a quick look at a typical image:
-\begin{verbatim}
- [Nr] Name Type Addr Off Size ES Flg Lk Inf Al
- [ 0] NULL 00000000 000000 000000 00 0 0 0
- [ 1] .ram PROGBITS ffff0000 001000 005893 00 WA 0 0 1
- [ 2] .rom PROGBITS ffff5893 006893 00029d 00 AX 0 0 16
- [ 3] .reset PROGBITS fffffff0 006ff0 000010 00 A 0 0 1
- [ 4] .id PROGBITS ffffffd1 006fd1 00001f 00 A 0 0 1
- [ 5] .shstrtab STRTAB 00000000 007000 000030 00 0 0 1
- [ 6] .symtab SYMTAB 00000000 007170 000c30 10 7 37 4
- [ 7] .strtab STRTAB 00000000 007da0 000bfd 00 0 0 1
-\end{verbatim}
-
-The only sections that get loaded into a ROM are the Allocated ones. We can see the .ram, .rom, .reset and .id sections.
-\subsubsection{layout}
-As we mentioned, the ROM file consists of multiple images. In the basic file, there are two full coreboot rom images. The build sequence for each is the same, and in fact the ldscript.ld files are almost identical. The only difference is in a few makefile variables, generated by the config tool.
-
-\begin{itemize}
-\item CONFIG\_PAYLOAD\_SIZE. Each image may have a different payload size.
-\item CONFIG\_ROMBASE Each image must have a different base in rom.
-\item CONFIG\_RESET Unclear what this is used for.
-\item CONFIG\_EXCEPTION\_VECTORS where an optional IDT might go.
-\item CONFIG\_USE\_OPTION\_TABLE if set, an option table section will be linked in.
-\item CONFIG\_ROM\_PAYLOAD\_START This is the soon-to-be-deprecated way of locating a payload. cbfs eliminates this.
-\item CONFIG\_USE\_FALLBACK\_IMAGE Whether this is a fallback or normal image
-\item CONFIG\_ROM\_SECTION\_SIZE Essentially, the payload size. Soon to be deprecated.
-\item CONFIG\_ROM\_IMAGE\_SIZE Size of this image (i.e. fallback or normal image)
-\item CONFIG\_ROM\_SIZE Total size of the ROM
-\item CONFIG\_XIP\_RAM\_BASE The start of eXecute In Place code. XIP allows for not copying code to ram, but just running it from ROM.
-\end{itemize}
-
-Each image (normal or fallback) is built completely independently and does not get linked to the other. They are assembled into one ROM image by the (soon to be deprecated) buildrom tool, or by the cbfs tool.
-
-\subsubsection{boot sequence}
-We boot and start at fffffff0. We then jump to the entry point at \_start. \_start does some machine init and an lgdt and jumps to \_\_protected\_start, at which point we are in protected mode. The code does a bit more machine setup and then starts executing the romcc code.
-
-If fallback has been built in, some setup needs to be done. On some machines, it is extensive. Full rom decoding must be enabled. This may in turn require additional PCI setup to enable decoding to be enabled (!). To decided which image to use, hardware registers (cold boot on the Opteron) or CMOS are checked. Finally, once the image to use has been decided, a jmp is performed, viz:
-\begin{verbatim}
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- __asm__ volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
- );
-
- fallback_image:
-#if CONFIG_HAVE_FAILOVER_BOOT==1
- __asm__ volatile ("jmp __fallback_image"
- : /* outputs */
- : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
- )
-#endif
- ;
-\end{verbatim}
-How does the fallback image get the symbol for normal entry? Via magic in the ldscript.ld -- remember, the images are not linked to each other.
-Finally, we can see this in the Config.lb for most mainboards:
-\begin{verbatim}
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-\end{verbatim}
-What does this mean? the non-fallback image has a 32-bit entry point; fallback has a 16-bit entry point. The reason for this is that some code from fallback always runs, so as to pick fallback or normal; but the normal is always called from 32-bit code.
-\subsection{car images (from lippert/roadrunner-lx)}
-CAR images in their simplest form are modified romcc images. The file is usually cache\_as\_ram\_auto.c. C inclusion is still used. The main difference is in the build sequence. The compiler command line is a very slight changed: instead of using romcc to generate an auto.inc include file, gcc us used. Then, two perl scripts are used to rename the .text and .data sections to .rom.text and .rom.data respectively.
-\subsubsection{How it is built}
-The build is almost identical to the romcc build. Since the auto.inc file exists, it can be included as before. The crt0\_includes.h file has one addition: a file that enables CAR, in this case it is \textit{src/cpu/amd/model\_lx/cache\_as\_ram.inc}.
-\subsubsection{layout}
-No significant change from romcc code.
-\subsubsection{boot sequence}
-No significant change from romcc code, except that the CAR code has to set up a stack.
-
-\subsection{car + CONFIG\_USE\_INIT images (new emulation/qemu}
-This type of image makes more use of the C compiler. In this type of image, in fact,
-seperate compilation is possible but is not always used. Oddly enough, this option is only used in PPC boards. That said, we need to move to this way of building. Including C code is poor style.
-\subsubsection{How it is built}
-There is a make variable, INIT-OBJECTS, that for all our other targets is empty. In this type of build, INIT-OBJECTS is a list of C files that are created from the config tool initobject command. Again, with INIT-OBJECTS we can finally stop including .c files and go with seperate compilation.
-\subsubsection{layout}
-No significant change from romcc code.
-\subsubsection{boot sequence}
-No significant change from romcc code, except that the CAR code has to set up a stack.
-
-\subsubsection{layout}
-No significant change from romcc code.
-\subsubsection{boot sequence}
-No significant change from romcc code, except that the CAR code has to set up a stack.
-\subsection{failover}
-Failover is the newest way to lay out a ROM. The choice of which image to run is removed from the fallback image and moved into a small, standalone piece of code. The code is simple enough to show here:
-\begin{verbatim}
-static unsigned long main(unsigned long bist)
-{
- if (do_normal_boot())
- goto normal_image;
- else
- goto fallback_image;
-
-normal_image:
- __asm__ __volatile__("jmp __normal_image" : : "a" (bist) : );
-
-cpu_reset:
- __asm__ __volatile__("jmp __cpu_reset" : : "a" (bist) : );
-
-fallback_image:
- return bist;
-}
-
-\end{verbatim}
-Some motherboards have a more complex bus structure (e.g. Opteron). In those cases, the failover can be more complex, as it requires some hardware initialization to work correctly. As of this writing (April 2009), these boards have their own failover:
-\begin{quote}
-./src/mainboard/iei/nova4899r/failover.c
-./src/mainboard/emulation/qemu-x86/failover.c
-./src/mainboard/supermicro/x6dhr\_ig/failover.c
-./src/mainboard/supermicro/x6dai\_g/failover.c
-./src/mainboard/supermicro/x6dhe\_g2/failover.c
-./src/mainboard/supermicro/x6dhr\_ig2/failover.c
-./src/mainboard/supermicro/x6dhe\_g/failover.c
-./src/mainboard/dell/s1850/failover.c
-./src/mainboard/intel/xe7501devkit/failover.c
-./src/mainboard/intel/jarrell/failover.c
-./src/mainboard/olpc/btest/failover.c
-./src/mainboard/olpc/rev\_a/failover.c
-./src/mainboard/via/epia-m/failover.c
-\end{quote}
-Here is one of the more complicated ones:
-\begin{verbatim}
-static unsigned long main(unsigned long bist)
-{
- /* Did just the cpu reset? */
- if (memory_initialized()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto cpu_reset;
- }
- }
-
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- cpu_reset:
- asm volatile ("jmp __cpu_reset"
- : /* outputs */
- : "a"(bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
-
-\end{verbatim}
-They're not that different, in fact. So why are there different copies all over the tree? Simple: code inclusion. Most of the failover.c are different because they include different bits of code. Here is a key reason for killing C code inclusion in the tree.
-\subsubsection{How it is built}
-There two additional config variables:
-\begin{itemize}
-\item HAVE\_FAILOVER\_IMAGE Has to be defined when certain files are included.
-\item USE\_FAILOVER\_IMAGE Enables the use of the failover image
-\end{itemize}
-Confusingly enough, almost all the uses of these two variables are either nested or both required to be set, e.g.
-The fallback and normal builds are the same. The target config has a new clause that looks like this:
-\begin{verbatim}
-romimage "failover"
- option CONFIG_USE_FAILOVER_IMAGE=1
- option CONFIG_USE_FALLBACK_IMAGE=0
- option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
- option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
- option COREBOOT_EXTRA_VERSION="\$(shell cat ../../VERSION)\_Failover"
-end
-\end{verbatim}
-This new section uses some constructs not yet discussed in detail. XIP\_ROM\_SIZE just refers to the
-fact that the failover code is eXecute In Place, i.e. not copied to RAM. Of course, the ROM part of normal/fallback is as well, so the usage of XIP here is somewhat confusing. Finally, the USE\_FAILOVER\_IMAGE variable is set, which changes code compilation in a few places. If we just consider non-mainbard files, there are:
-\begin{verbatim}
-src/cpu/amd/car/cache_as_ram.inc
-src/arch/i386/Config.lb
-\end{verbatim}
-For the cache\_as\_ram.inc file, the changes relate to the fact that failover code sets up CAR, so that fallback code need not.
-
-For the Config.lb, several aspects of build change.
-When USE\_FAILOVER\_IMAGE, entry into both normal and fallback bios images is via a 32-bit entry point (when not defined, entry into fallback is a 16-entry point at the power-on reset vector).
-\subsubsection{layout}
-Failover.c becomes the new bootblock at the top of memory. It calls either normal or fallback. The address of normal and fallback is determined by ldscript magic.
-\subsubsection{boot sequence}
-failover.c tests a few variables and the calls the normal or fallback payload depending on those variables; usually they are CMOS settings.
-\subsection{Proposed new image forat}
-The new image format will use seperate compilation -- no C code included! -- on all files.
-
-The new design has a few key goals:
-\begin{itemize}
-\item Always use a bootblock (currently called failover).
-The name failover.c, being utterly obscure, will not be used; instead, we will name the file bootblock.c. Instead of having a different copy for each mainboard, we can have just one copy.
-\item Always use seperate compilation
-\item Always use printk etc. in the ROM code
-\item (longer term) from the bootblock, always use cbfs to locate the normal/fallback etc. code. This code will be XIP.
-\end{itemize}
-
-\subsubsection{How it is built}
-For now, since we are still using the config tool, we'll need a new command: bootblockobject, which creates a list of files to be included in the bootblock. Not a lot else will have to change. We are going to move to using the v3 CAR code assembly code (one or two files at most, instead of many) and, instead of the thicket of little ldscript files, one ldscript file. This strategy is subject to modification as events dictate.
-\subsubsection{layout}
-Almost the same, for now, as the current failover code.
-\subsubsection{boot sequence}
-%
-% 14 Glossary
-%
-
-\section{Glossary}
-\begin{itemize}
-\item payload
-
-coreboot only cares about low level machine initialization, but also has
-very simple mechanisms to boot a file either from FLASHROM or IDE. That
-file, possibly a Linux Kernel, a boot loader or Etherboot, are called
-payload, since it is the first software executed that does not cope with
-pure initialization.
-
-\item flash device
-
-Flash devices are commonly used in all different computers since unlike
-ROMs they can be electronically erased and reprogrammed.
-\end{itemize}
-
-\newpage
-
-%
-% 14 Bibliography
-%
-
-\section{Bibliography}
-\subsection{Additional Papers on coreboot}
-
-\begin{itemize}
- \item
- \textit{\url{http://www.coreboot.org/Documentation}}
- \item
- \textit{\url{http://www.lysator.liu.se/upplysning/fa/linuxbios.pdf}}
- \item
- \textit{\url{http://portal.acm.org/citation.cfm?id=512627}}
-\end{itemize}
-
-\subsection {Links}
-
-\begin{itemize}
- \item Etherboot: \textit{\url{http://www.etherboot.org/}}
- \item Filo: \textit{\url{http://www.coreboot.org/FILO}}
- \item OpenBIOS: \textit{\url{http://www.openbios.org/}}
-\end{itemize}
-
-\end{document}
diff --git a/documentation/Doxyfile.coreboot b/documentation/Doxyfile.coreboot
deleted file mode 100644
index e6c06fe..0000000
--- a/documentation/Doxyfile.coreboot
+++ /dev/null
@@ -1,1639 +0,0 @@
-# Doxyfile 1.7.1
-
-# This file describes the settings to be used by the documentation system
-# doxygen (www.doxygen.org) for a project
-#
-# All text after a hash (#) is considered a comment and will be ignored
-# The format is:
-# TAG = value [value, ...]
-# For lists items can also be appended using:
-# TAG += value [value, ...]
-# Values that contain spaces should be placed between quotes (" ")
-
-#---------------------------------------------------------------------------
-# Project related configuration options
-#---------------------------------------------------------------------------
-
-# This tag specifies the encoding used for all characters in the config file
-# that follow. The default is UTF-8 which is also the encoding used for all
-# text before the first occurrence of this tag. Doxygen uses libiconv (or the
-# iconv built into libc) for the transcoding. See
-# http://www.gnu.org/software/libiconv for the list of possible encodings.
-
-DOXYFILE_ENCODING = UTF-8
-
-# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
-# by quotes) that should identify the project.
-
-PROJECT_NAME = coreboot
-
-# The PROJECT_NUMBER tag can be used to enter a project or revision number.
-# This could be handy for archiving the generated documentation or
-# if some version control system is used.
-
-PROJECT_NUMBER =
-
-# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
-# base path where the generated documentation will be put.
-# If a relative path is entered, it will be relative to the location
-# where doxygen was started. If left blank the current directory will be used.
-
-OUTPUT_DIRECTORY = doxygen
-
-# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
-# 4096 sub-directories (in 2 levels) under the output directory of each output
-# format and will distribute the generated files over these directories.
-# Enabling this option can be useful when feeding doxygen a huge amount of
-# source files, where putting all generated files in the same directory would
-# otherwise cause performance problems for the file system.
-
-CREATE_SUBDIRS = NO
-
-# The OUTPUT_LANGUAGE tag is used to specify the language in which all
-# documentation generated by doxygen is written. Doxygen will use this
-# information to generate all constant output in the proper language.
-# The default language is English, other supported languages are:
-# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
-# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
-# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
-# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
-# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
-# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
-
-OUTPUT_LANGUAGE = English
-
-# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
-# include brief member descriptions after the members that are listed in
-# the file and class documentation (similar to JavaDoc).
-# Set to NO to disable this.
-
-BRIEF_MEMBER_DESC = YES
-
-# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
-# the brief description of a member or function before the detailed description.
-# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
-# brief descriptions will be completely suppressed.
-
-REPEAT_BRIEF = YES
-
-# This tag implements a quasi-intelligent brief description abbreviator
-# that is used to form the text in various listings. Each string
-# in this list, if found as the leading text of the brief description, will be
-# stripped from the text and the result after processing the whole list, is
-# used as the annotated text. Otherwise, the brief description is used as-is.
-# If left blank, the following values are used ("$name" is automatically
-# replaced with the name of the entity): "The $name class" "The $name widget"
-# "The $name file" "is" "provides" "specifies" "contains"
-# "represents" "a" "an" "the"
-
-ABBREVIATE_BRIEF =
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-# Doxygen will generate a detailed section even if there is only a brief
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-
-ALWAYS_DETAILED_SEC = YES
-
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-# inherited members of a class in the documentation of that class as if those
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-# operators of the base classes will not be shown.
-
-INLINE_INHERITED_MEMB = NO
-
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-# If left blank the directory from which doxygen is run is used as the
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-
-STRIP_FROM_PATH =
-
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-# are normally passed to the compiler using the -I flag.
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-# doesn't support long names like on DOS, Mac, or CD-ROM.
-
-SHORT_NAMES = NO
-
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-# will interpret the first line (until the first dot) of a JavaDoc-style
-# comment as the brief description. If set to NO, the JavaDoc
-# comments will behave just like regular Qt-style comments
-# (thus requiring an explicit @brief command for a brief description.)
-
-JAVADOC_AUTOBRIEF = YES
-
-# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
-# interpret the first line (until the first dot) of a Qt-style
-# comment as the brief description. If set to NO, the comments
-# will behave just like regular Qt-style comments (thus requiring
-# an explicit \brief command for a brief description.)
-
-QT_AUTOBRIEF = NO
-
-# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
-# treat a multi-line C++ special comment block (i.e. a block of //! or ///
-# comments) as a brief description. This used to be the default behaviour.
-# The new default is to treat a multi-line C++ comment block as a detailed
-# description. Set this tag to YES if you prefer the old behaviour instead.
-
-MULTILINE_CPP_IS_BRIEF = NO
-
-# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
-# member inherits the documentation from any documented member that it
-# re-implements.
-
-INHERIT_DOCS = YES
-
-# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
-# a new page for each member. If set to NO, the documentation of a member will
-# be part of the file/class/namespace that contains it.
-
-SEPARATE_MEMBER_PAGES = NO
-
-# The TAB_SIZE tag can be used to set the number of spaces in a tab.
-# Doxygen uses this value to replace tabs by spaces in code fragments.
-
-TAB_SIZE = 8
-
-# This tag can be used to specify a number of aliases that acts
-# as commands in the documentation. An alias has the form "name=value".
-# For example adding "sideeffect=\par Side Effects:\n" will allow you to
-# put the command \sideeffect (or @sideeffect) in the documentation, which
-# will result in a user-defined paragraph with heading "Side Effects:".
-# You can put \n's in the value part of an alias to insert newlines.
-
-ALIASES =
-
-# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
-# sources only. Doxygen will then generate output that is more tailored for C.
-# For instance, some of the names that are used will be different. The list
-# of all members will be omitted, etc.
-
-OPTIMIZE_OUTPUT_FOR_C = YES
-
-# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
-# sources only. Doxygen will then generate output that is more tailored for
-# Java. For instance, namespaces will be presented as packages, qualified
-# scopes will look different, etc.
-
-OPTIMIZE_OUTPUT_JAVA = NO
-
-# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
-# sources only. Doxygen will then generate output that is more tailored for
-# Fortran.
-
-OPTIMIZE_FOR_FORTRAN = NO
-
-# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
-# sources. Doxygen will then generate output that is tailored for
-# VHDL.
-
-OPTIMIZE_OUTPUT_VHDL = NO
-
-# Doxygen selects the parser to use depending on the extension of the files it
-# parses. With this tag you can assign which parser to use for a given extension.
-# Doxygen has a built-in mapping, but you can override or extend it using this
-# tag. The format is ext=language, where ext is a file extension, and language
-# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C,
-# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make
-# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C
-# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions
-# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
-
-EXTENSION_MAPPING =
-
-# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
-# to include (a tag file for) the STL sources as input, then you should
-# set this tag to YES in order to let doxygen match functions declarations and
-# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
-# func(std::string) {}). This also make the inheritance and collaboration
-# diagrams that involve STL classes more complete and accurate.
-
-BUILTIN_STL_SUPPORT = NO
-
-# If you use Microsoft's C++/CLI language, you should set this option to YES to
-# enable parsing support.
-
-CPP_CLI_SUPPORT = NO
-
-# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
-# Doxygen will parse them like normal C++ but will assume all classes use public
-# instead of private inheritance when no explicit protection keyword is present.
-
-SIP_SUPPORT = NO
-
-# For Microsoft's IDL there are propget and propput attributes to indicate getter
-# and setter methods for a property. Setting this option to YES (the default)
-# will make doxygen to replace the get and set methods by a property in the
-# documentation. This will only work if the methods are indeed getting or
-# setting a simple type. If this is not the case, or you want to show the
-# methods anyway, you should set this option to NO.
-
-IDL_PROPERTY_SUPPORT = YES
-
-# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
-# tag is set to YES, then doxygen will reuse the documentation of the first
-# member in the group (if any) for the other members of the group. By default
-# all members of a group must be documented explicitly.
-
-DISTRIBUTE_GROUP_DOC = NO
-
-# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
-# the same type (for instance a group of public functions) to be put as a
-# subgroup of that type (e.g. under the Public Functions section). Set it to
-# NO to prevent subgrouping. Alternatively, this can be done per class using
-# the \nosubgrouping command.
-
-SUBGROUPING = YES
-
-# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
-# is documented as struct, union, or enum with the name of the typedef. So
-# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
-# with name TypeT. When disabled the typedef will appear as a member of a file,
-# namespace, or class. And the struct will be named TypeS. This can typically
-# be useful for C code in case the coding convention dictates that all compound
-# types are typedef'ed and only the typedef is referenced, never the tag name.
-
-TYPEDEF_HIDES_STRUCT = NO
-
-# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
-# determine which symbols to keep in memory and which to flush to disk.
-# When the cache is full, less often used symbols will be written to disk.
-# For small to medium size projects (<1000 input files) the default value is
-# probably good enough. For larger projects a too small cache size can cause
-# doxygen to be busy swapping symbols to and from disk most of the time
-# causing a significant performance penality.
-# If the system has enough physical memory increasing the cache will improve the
-# performance by keeping more symbols in memory. Note that the value works on
-# a logarithmic scale so increasing the size by one will rougly double the
-# memory usage. The cache size is given by this formula:
-# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
-# corresponding to a cache size of 2^16 = 65536 symbols
-
-SYMBOL_CACHE_SIZE = 0
-
-#---------------------------------------------------------------------------
-# Build related configuration options
-#---------------------------------------------------------------------------
-
-# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
-# documentation are documented, even if no documentation was available.
-# Private class members and static file members will be hidden unless
-# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
-
-EXTRACT_ALL = YES
-
-# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
-# will be included in the documentation.
-
-EXTRACT_PRIVATE = NO
-
-# If the EXTRACT_STATIC tag is set to YES all static members of a file
-# will be included in the documentation.
-
-EXTRACT_STATIC = YES
-
-# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
-# defined locally in source files will be included in the documentation.
-# If set to NO only classes defined in header files are included.
-
-EXTRACT_LOCAL_CLASSES = YES
-
-# This flag is only useful for Objective-C code. When set to YES local
-# methods, which are defined in the implementation section but not in
-# the interface are included in the documentation.
-# If set to NO (the default) only methods in the interface are included.
-
-EXTRACT_LOCAL_METHODS = NO
-
-# If this flag is set to YES, the members of anonymous namespaces will be
-# extracted and appear in the documentation as a namespace called
-# 'anonymous_namespace{file}', where file will be replaced with the base
-# name of the file that contains the anonymous namespace. By default
-# anonymous namespace are hidden.
-
-EXTRACT_ANON_NSPACES = NO
-
-# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
-# undocumented members of documented classes, files or namespaces.
-# If set to NO (the default) these members will be included in the
-# various overviews, but no documentation section is generated.
-# This option has no effect if EXTRACT_ALL is enabled.
-
-HIDE_UNDOC_MEMBERS = NO
-
-# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
-# undocumented classes that are normally visible in the class hierarchy.
-# If set to NO (the default) these classes will be included in the various
-# overviews. This option has no effect if EXTRACT_ALL is enabled.
-
-HIDE_UNDOC_CLASSES = NO
-
-# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
-# friend (class|struct|union) declarations.
-# If set to NO (the default) these declarations will be included in the
-# documentation.
-
-HIDE_FRIEND_COMPOUNDS = NO
-
-# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
-# documentation blocks found inside the body of a function.
-# If set to NO (the default) these blocks will be appended to the
-# function's detailed documentation block.
-
-HIDE_IN_BODY_DOCS = NO
-
-# The INTERNAL_DOCS tag determines if documentation
-# that is typed after a \internal command is included. If the tag is set
-# to NO (the default) then the documentation will be excluded.
-# Set it to YES to include the internal documentation.
-
-INTERNAL_DOCS = NO
-
-# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
-# file names in lower-case letters. If set to YES upper-case letters are also
-# allowed. This is useful if you have classes or files whose names only differ
-# in case and if your file system supports case sensitive file names. Windows
-# and Mac users are advised to set this option to NO.
-
-CASE_SENSE_NAMES = YES
-
-# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
-# will show members with their full class and namespace scopes in the
-# documentation. If set to YES the scope will be hidden.
-
-HIDE_SCOPE_NAMES = NO
-
-# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
-# will put a list of the files that are included by a file in the documentation
-# of that file.
-
-SHOW_INCLUDE_FILES = YES
-
-# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
-# will list include files with double quotes in the documentation
-# rather than with sharp brackets.
-
-FORCE_LOCAL_INCLUDES = NO
-
-# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
-# is inserted in the documentation for inline members.
-
-INLINE_INFO = YES
-
-# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
-# will sort the (detailed) documentation of file and class members
-# alphabetically by member name. If set to NO the members will appear in
-# declaration order.
-
-SORT_MEMBER_DOCS = YES
-
-# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
-# brief documentation of file, namespace and class members alphabetically
-# by member name. If set to NO (the default) the members will appear in
-# declaration order.
-
-SORT_BRIEF_DOCS = NO
-
-# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
-# will sort the (brief and detailed) documentation of class members so that
-# constructors and destructors are listed first. If set to NO (the default)
-# the constructors will appear in the respective orders defined by
-# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
-# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
-# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
-
-SORT_MEMBERS_CTORS_1ST = NO
-
-# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
-# hierarchy of group names into alphabetical order. If set to NO (the default)
-# the group names will appear in their defined order.
-
-SORT_GROUP_NAMES = NO
-
-# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
-# sorted by fully-qualified names, including namespaces. If set to
-# NO (the default), the class list will be sorted only by class name,
-# not including the namespace part.
-# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
-# Note: This option applies only to the class list, not to the
-# alphabetical list.
-
-SORT_BY_SCOPE_NAME = NO
-
-# The GENERATE_TODOLIST tag can be used to enable (YES) or
-# disable (NO) the todo list. This list is created by putting \todo
-# commands in the documentation.
-
-GENERATE_TODOLIST = YES
-
-# The GENERATE_TESTLIST tag can be used to enable (YES) or
-# disable (NO) the test list. This list is created by putting \test
-# commands in the documentation.
-
-GENERATE_TESTLIST = YES
-
-# The GENERATE_BUGLIST tag can be used to enable (YES) or
-# disable (NO) the bug list. This list is created by putting \bug
-# commands in the documentation.
-
-GENERATE_BUGLIST = YES
-
-# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
-# disable (NO) the deprecated list. This list is created by putting
-# \deprecated commands in the documentation.
-
-GENERATE_DEPRECATEDLIST= YES
-
-# The ENABLED_SECTIONS tag can be used to enable conditional
-# documentation sections, marked by \if sectionname ... \endif.
-
-ENABLED_SECTIONS =
-
-# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
-# the initial value of a variable or define consists of for it to appear in
-# the documentation. If the initializer consists of more lines than specified
-# here it will be hidden. Use a value of 0 to hide initializers completely.
-# The appearance of the initializer of individual variables and defines in the
-# documentation can be controlled using \showinitializer or \hideinitializer
-# command in the documentation regardless of this setting.
-
-MAX_INITIALIZER_LINES = 30
-
-# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
-# at the bottom of the documentation of classes and structs. If set to YES the
-# list will mention the files that were used to generate the documentation.
-
-SHOW_USED_FILES = YES
-
-# If the sources in your project are distributed over multiple directories
-# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
-# in the documentation. The default is NO.
-
-SHOW_DIRECTORIES = YES
-
-# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
-# This will remove the Files entry from the Quick Index and from the
-# Folder Tree View (if specified). The default is YES.
-
-SHOW_FILES = YES
-
-# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
-# Namespaces page.
-# This will remove the Namespaces entry from the Quick Index
-# and from the Folder Tree View (if specified). The default is YES.
-
-SHOW_NAMESPACES = YES
-
-# The FILE_VERSION_FILTER tag can be used to specify a program or script that
-# doxygen should invoke to get the current version for each file (typically from
-# the version control system). Doxygen will invoke the program by executing (via
-# popen()) the command <command> <input-file>, where <command> is the value of
-# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file
-# provided by doxygen. Whatever the program writes to standard output
-# is used as the file version. See the manual for examples.
-
-FILE_VERSION_FILTER =
-
-# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
-# by doxygen. The layout file controls the global structure of the generated
-# output files in an output format independent way. The create the layout file
-# that represents doxygen's defaults, run doxygen with the -l option.
-# You can optionally specify a file name after the option, if omitted
-# DoxygenLayout.xml will be used as the name of the layout file.
-
-LAYOUT_FILE =
-
-#---------------------------------------------------------------------------
-# configuration options related to warning and progress messages
-#---------------------------------------------------------------------------
-
-# The QUIET tag can be used to turn on/off the messages that are generated
-# by doxygen. Possible values are YES and NO. If left blank NO is used.
-
-QUIET = YES
-
-# The WARNINGS tag can be used to turn on/off the warning messages that are
-# generated by doxygen. Possible values are YES and NO. If left blank
-# NO is used.
-
-WARNINGS = YES
-
-# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
-# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
-# automatically be disabled.
-
-WARN_IF_UNDOCUMENTED = YES
-
-# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
-# potential errors in the documentation, such as not documenting some
-# parameters in a documented function, or documenting parameters that
-# don't exist or using markup commands wrongly.
-
-WARN_IF_DOC_ERROR = YES
-
-# This WARN_NO_PARAMDOC option can be abled to get warnings for
-# functions that are documented, but have no documentation for their parameters
-# or return value. If set to NO (the default) doxygen will only warn about
-# wrong or incomplete parameter documentation, but not about the absence of
-# documentation.
-
-WARN_NO_PARAMDOC = YES
-
-# The WARN_FORMAT tag determines the format of the warning messages that
-# doxygen can produce. The string should contain the $file, $line, and $text
-# tags, which will be replaced by the file and line number from which the
-# warning originated and the warning text. Optionally the format may contain
-# $version, which will be replaced by the version of the file (if it could
-# be obtained via FILE_VERSION_FILTER)
-
-WARN_FORMAT = "$file:$line: $text"
-
-# The WARN_LOGFILE tag can be used to specify a file to which warning
-# and error messages should be written. If left blank the output is written
-# to stderr.
-
-WARN_LOGFILE =
-
-#---------------------------------------------------------------------------
-# configuration options related to the input files
-#---------------------------------------------------------------------------
-
-# The INPUT tag can be used to specify the files and/or directories that contain
-# documented source files. You may enter file names like "myfile.cpp" or
-# directories like "/usr/src/myproject". Separate the files or directories
-# with spaces.
-
-INPUT = .
-
-# This tag can be used to specify the character encoding of the source files
-# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
-# also the default input encoding. Doxygen uses libiconv (or the iconv built
-# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
-# the list of possible encodings.
-
-INPUT_ENCODING = UTF-8
-
-# If the value of the INPUT tag contains directories, you can use the
-# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
-# and *.h) to filter out the source-files in the directories. If left
-# blank the following patterns are tested:
-# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx
-# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90
-
-FILE_PATTERNS =
-
-# The RECURSIVE tag can be used to turn specify whether or not subdirectories
-# should be searched for input files as well. Possible values are YES and NO.
-# If left blank NO is used.
-
-RECURSIVE = YES
-
-# The EXCLUDE tag can be used to specify files and/or directories that should
-# excluded from the INPUT source files. This way you can easily exclude a
-# subdirectory from a directory tree whose root is specified with the INPUT tag.
-
-EXCLUDE = util/romcc/tests \
- util/vgabios \
- util/abuild \
- util/kconfig \
- payloads
-
-# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
-# directories that are symbolic links (a Unix filesystem feature) are excluded
-# from the input.
-
-EXCLUDE_SYMLINKS = NO
-
-# If the value of the INPUT tag contains directories, you can use the
-# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
-# certain files from those directories. Note that the wildcards are matched
-# against the file with absolute path, so to exclude all test directories
-# for example use the pattern */test/*
-
-EXCLUDE_PATTERNS =
-
-# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
-# (namespaces, classes, functions, etc.) that should be excluded from the
-# output. The symbol name can be a fully qualified name, a word, or if the
-# wildcard * is used, a substring. Examples: ANamespace, AClass,
-# AClass::ANamespace, ANamespace::*Test
-
-EXCLUDE_SYMBOLS =
-
-# The EXAMPLE_PATH tag can be used to specify one or more files or
-# directories that contain example code fragments that are included (see
-# the \include command).
-
-EXAMPLE_PATH =
-
-# If the value of the EXAMPLE_PATH tag contains directories, you can use the
-# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
-# and *.h) to filter out the source-files in the directories. If left
-# blank all files are included.
-
-EXAMPLE_PATTERNS =
-
-# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
-# searched for input files to be used with the \include or \dontinclude
-# commands irrespective of the value of the RECURSIVE tag.
-# Possible values are YES and NO. If left blank NO is used.
-
-EXAMPLE_RECURSIVE = NO
-
-# The IMAGE_PATH tag can be used to specify one or more files or
-# directories that contain image that are included in the documentation (see
-# the \image command).
-
-IMAGE_PATH =
-
-# The INPUT_FILTER tag can be used to specify a program that doxygen should
-# invoke to filter for each input file. Doxygen will invoke the filter program
-# by executing (via popen()) the command <filter> <input-file>, where <filter>
-# is the value of the INPUT_FILTER tag, and <input-file> is the name of an
-# input file. Doxygen will then use the output that the filter program writes
-# to standard output.
-# If FILTER_PATTERNS is specified, this tag will be
-# ignored.
-
-INPUT_FILTER =
-
-# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
-# basis.
-# Doxygen will compare the file name with each pattern and apply the
-# filter if there is a match.
-# The filters are a list of the form:
-# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
-# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
-# is applied to all files.
-
-FILTER_PATTERNS =
-
-# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
-# INPUT_FILTER) will be used to filter the input files when producing source
-# files to browse (i.e. when SOURCE_BROWSER is set to YES).
-
-FILTER_SOURCE_FILES = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to source browsing
-#---------------------------------------------------------------------------
-
-# If the SOURCE_BROWSER tag is set to YES then a list of source files will
-# be generated. Documented entities will be cross-referenced with these sources.
-# Note: To get rid of all source code in the generated output, make sure also
-# VERBATIM_HEADERS is set to NO.
-
-SOURCE_BROWSER = YES
-
-# Setting the INLINE_SOURCES tag to YES will include the body
-# of functions and classes directly in the documentation.
-
-INLINE_SOURCES = NO
-
-# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
-# doxygen to hide any special comment blocks from generated source code
-# fragments. Normal C and C++ comments will always remain visible.
-
-STRIP_CODE_COMMENTS = NO
-
-# If the REFERENCED_BY_RELATION tag is set to YES
-# then for each documented function all documented
-# functions referencing it will be listed.
-
-REFERENCED_BY_RELATION = YES
-
-# If the REFERENCES_RELATION tag is set to YES
-# then for each documented function all documented entities
-# called/used by that function will be listed.
-
-REFERENCES_RELATION = YES
-
-# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
-# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
-# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
-# link to the source code.
-# Otherwise they will link to the documentation.
-
-REFERENCES_LINK_SOURCE = YES
-
-# If the USE_HTAGS tag is set to YES then the references to source code
-# will point to the HTML generated by the htags(1) tool instead of doxygen
-# built-in source browser. The htags tool is part of GNU's global source
-# tagging system (see http://www.gnu.org/software/global/global.html). You
-# will need version 4.8.6 or higher.
-
-USE_HTAGS = NO
-
-# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
-# will generate a verbatim copy of the header file for each class for
-# which an include is specified. Set to NO to disable this.
-
-VERBATIM_HEADERS = YES
-
-#---------------------------------------------------------------------------
-# configuration options related to the alphabetical class index
-#---------------------------------------------------------------------------
-
-# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
-# of all compounds will be generated. Enable this if the project
-# contains a lot of classes, structs, unions or interfaces.
-
-ALPHABETICAL_INDEX = YES
-
-# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
-# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
-# in which this list will be split (can be a number in the range [1..20])
-
-COLS_IN_ALPHA_INDEX = 5
-
-# In case all classes in a project start with a common prefix, all
-# classes will be put under the same header in the alphabetical index.
-# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
-# should be ignored while generating the index headers.
-
-IGNORE_PREFIX =
-
-#---------------------------------------------------------------------------
-# configuration options related to the HTML output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
-# generate HTML output.
-
-GENERATE_HTML = YES
-
-# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `html' will be used as the default path.
-
-HTML_OUTPUT = html
-
-# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
-# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
-# doxygen will generate files with .html extension.
-
-HTML_FILE_EXTENSION = .html
-
-# The HTML_HEADER tag can be used to specify a personal HTML header for
-# each generated HTML page. If it is left blank doxygen will generate a
-# standard header.
-
-HTML_HEADER =
-
-# The HTML_FOOTER tag can be used to specify a personal HTML footer for
-# each generated HTML page. If it is left blank doxygen will generate a
-# standard footer.
-
-HTML_FOOTER =
-
-# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will
-# add generated date, project name and doxygen version to HTML footer.
-
-HTML_FOOTER_DESCRIPTION= YES
-
-# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
-# style sheet that is used by each HTML page. It can be used to
-# fine-tune the look of the HTML output. If the tag is left blank doxygen
-# will generate a default style sheet. Note that doxygen will try to copy
-# the style sheet file to the HTML output directory, so don't put your own
-# stylesheet in the HTML output directory as well, or it will be erased!
-
-HTML_STYLESHEET =
-
-# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
-# Doxygen will adjust the colors in the stylesheet and background images
-# according to this color. Hue is specified as an angle on a colorwheel,
-# see http://en.wikipedia.org/wiki/Hue for more information.
-# For instance the value 0 represents red, 60 is yellow, 120 is green,
-# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
-# The allowed range is 0 to 359.
-
-HTML_COLORSTYLE_HUE = 220
-
-# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
-# the colors in the HTML output. For a value of 0 the output will use
-# grayscales only. A value of 255 will produce the most vivid colors.
-
-HTML_COLORSTYLE_SAT = 100
-
-# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
-# the luminance component of the colors in the HTML output. Values below
-# 100 gradually make the output lighter, whereas values above 100 make
-# the output darker. The value divided by 100 is the actual gamma applied,
-# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
-# and 100 does not change the gamma.
-
-HTML_COLORSTYLE_GAMMA = 80
-
-# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
-# page will contain the date and time when the page was generated. Setting
-# this to NO can help when comparing the output of multiple runs.
-
-HTML_TIMESTAMP = NO
-
-# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
-# files or namespaces will be aligned in HTML using tables. If set to
-# NO a bullet list will be used.
-
-HTML_ALIGN_MEMBERS = YES
-
-# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
-# documentation will contain sections that can be hidden and shown after the
-# page has loaded. For this to work a browser that supports
-# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
-# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
-
-HTML_DYNAMIC_SECTIONS = NO
-
-# If the GENERATE_DOCSET tag is set to YES, additional index files
-# will be generated that can be used as input for Apple's Xcode 3
-# integrated development environment, introduced with OSX 10.5 (Leopard).
-# To create a documentation set, doxygen will generate a Makefile in the
-# HTML output directory. Running make will produce the docset in that
-# directory and running "make install" will install the docset in
-# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
-# it at startup.
-# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
-# for more information.
-
-GENERATE_DOCSET = NO
-
-# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
-# feed. A documentation feed provides an umbrella under which multiple
-# documentation sets from a single provider (such as a company or product suite)
-# can be grouped.
-
-DOCSET_FEEDNAME = "Doxygen documentation"
-
-# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
-# should uniquely identify the documentation set bundle. This should be a
-# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
-# will append .docset to the name.
-
-DOCSET_BUNDLE_ID = org.doxygen.Project
-
-# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify
-# the documentation publisher. This should be a reverse domain-name style
-# string, e.g. com.mycompany.MyDocSet.documentation.
-
-DOCSET_PUBLISHER_ID = org.doxygen.Publisher
-
-# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
-
-DOCSET_PUBLISHER_NAME = Publisher
-
-# If the GENERATE_HTMLHELP tag is set to YES, additional index files
-# will be generated that can be used as input for tools like the
-# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
-# of the generated HTML documentation.
-
-GENERATE_HTMLHELP = NO
-
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
-# be used to specify the file name of the resulting .chm file. You
-# can add a path in front of the file if the result should not be
-# written to the html output directory.
-
-CHM_FILE =
-
-# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
-# be used to specify the location (absolute path including file name) of
-# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
-# the HTML help compiler on the generated index.hhp.
-
-HHC_LOCATION =
-
-# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
-# controls if a separate .chi index file is generated (YES) or that
-# it should be included in the master .chm file (NO).
-
-GENERATE_CHI = NO
-
-# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
-# is used to encode HtmlHelp index (hhk), content (hhc) and project file
-# content.
-
-CHM_INDEX_ENCODING =
-
-# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
-# controls whether a binary table of contents is generated (YES) or a
-# normal table of contents (NO) in the .chm file.
-
-BINARY_TOC = NO
-
-# The TOC_EXPAND flag can be set to YES to add extra items for group members
-# to the contents of the HTML help documentation and to the tree view.
-
-TOC_EXPAND = NO
-
-# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
-# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
-# that can be used as input for Qt's qhelpgenerator to generate a
-# Qt Compressed Help (.qch) of the generated HTML documentation.
-
-GENERATE_QHP = NO
-
-# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
-# be used to specify the file name of the resulting .qch file.
-# The path specified is relative to the HTML output folder.
-
-QCH_FILE =
-
-# The QHP_NAMESPACE tag specifies the namespace to use when generating
-# Qt Help Project output. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#namespace
-
-QHP_NAMESPACE = org.doxygen.Project
-
-# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
-# Qt Help Project output. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#virtual-folders
-
-QHP_VIRTUAL_FOLDER = doc
-
-# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
-# add. For more information please see
-# http://doc.trolltech.com/qthelpproject.html#custom-filters
-
-QHP_CUST_FILTER_NAME =
-
-# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
-# custom filter to add. For more information please see
-# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters">
-# Qt Help Project / Custom Filters</a>.
-
-QHP_CUST_FILTER_ATTRS =
-
-# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
-# project's
-# filter section matches.
-# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes">
-# Qt Help Project / Filter Attributes</a>.
-
-QHP_SECT_FILTER_ATTRS =
-
-# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
-# be used to specify the location of Qt's qhelpgenerator.
-# If non-empty doxygen will try to run qhelpgenerator on the generated
-# .qhp file.
-
-QHG_LOCATION =
-
-# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
-# will be generated, which together with the HTML files, form an Eclipse help
-# plugin. To install this plugin and make it available under the help contents
-# menu in Eclipse, the contents of the directory containing the HTML and XML
-# files needs to be copied into the plugins directory of eclipse. The name of
-# the directory within the plugins directory should be the same as
-# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
-# the help appears.
-
-GENERATE_ECLIPSEHELP = NO
-
-# A unique identifier for the eclipse help plugin. When installing the plugin
-# the directory name containing the HTML and XML files should also have
-# this name.
-
-ECLIPSE_DOC_ID = org.doxygen.Project
-
-# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
-# top of each HTML page. The value NO (the default) enables the index and
-# the value YES disables it.
-
-DISABLE_INDEX = NO
-
-# This tag can be used to set the number of enum values (range [1..20])
-# that doxygen will group on one line in the generated HTML documentation.
-
-ENUM_VALUES_PER_LINE = 4
-
-# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
-# structure should be generated to display hierarchical information.
-# If the tag value is set to YES, a side panel will be generated
-# containing a tree-like index structure (just like the one that
-# is generated for HTML Help). For this to work a browser that supports
-# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
-# Windows users are probably better off using the HTML help feature.
-
-GENERATE_TREEVIEW = YES
-
-# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
-# and Class Hierarchy pages using a tree view instead of an ordered list.
-
-USE_INLINE_TREES = YES
-
-# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
-# used to set the initial width (in pixels) of the frame in which the tree
-# is shown.
-
-TREEVIEW_WIDTH = 250
-
-# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
-# links to external symbols imported via tag files in a separate window.
-
-EXT_LINKS_IN_WINDOW = NO
-
-# Use this tag to change the font size of Latex formulas included
-# as images in the HTML documentation. The default is 10. Note that
-# when you change the font size after a successful doxygen run you need
-# to manually remove any form_*.png images from the HTML output directory
-# to force them to be regenerated.
-
-FORMULA_FONTSIZE = 10
-
-# Use the FORMULA_TRANPARENT tag to determine whether or not the images
-# generated for formulas are transparent PNGs. Transparent PNGs are
-# not supported properly for IE 6.0, but are supported on all modern browsers.
-# Note that when changing this option you need to delete any form_*.png files
-# in the HTML output before the changes have effect.
-
-FORMULA_TRANSPARENT = YES
-
-# When the SEARCHENGINE tag is enabled doxygen will generate a search box
-# for the HTML output. The underlying search engine uses javascript
-# and DHTML and should work on any modern browser. Note that when using
-# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
-# (GENERATE_DOCSET) there is already a search function so this one should
-# typically be disabled. For large projects the javascript based search engine
-# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
-
-SEARCHENGINE = YES
-
-# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
-# implemented using a PHP enabled web server instead of at the web client
-# using Javascript. Doxygen will generate the search PHP script and index
-# file to put on the web server. The advantage of the server
-# based approach is that it scales better to large projects and allows
-# full text search. The disadvances is that it is more difficult to setup
-# and does not have live searching capabilities.
-
-SERVER_BASED_SEARCH = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the LaTeX output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
-# generate Latex output.
-
-GENERATE_LATEX = NO
-
-# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `latex' will be used as the default path.
-
-LATEX_OUTPUT = latex
-
-# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
-# invoked. If left blank `latex' will be used as the default command name.
-# Note that when enabling USE_PDFLATEX this option is only used for
-# generating bitmaps for formulas in the HTML output, but not in the
-# Makefile that is written to the output directory.
-
-LATEX_CMD_NAME = latex
-
-# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
-# generate index for LaTeX. If left blank `makeindex' will be used as the
-# default command name.
-
-MAKEINDEX_CMD_NAME = makeindex
-
-# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
-# LaTeX documents. This may be useful for small projects and may help to
-# save some trees in general.
-
-COMPACT_LATEX = NO
-
-# The PAPER_TYPE tag can be used to set the paper type that is used
-# by the printer. Possible values are: a4, a4wide, letter, legal and
-# executive. If left blank a4wide will be used.
-
-PAPER_TYPE = a4wide
-
-# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
-# packages that should be included in the LaTeX output.
-
-EXTRA_PACKAGES =
-
-# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
-# the generated latex document. The header should contain everything until
-# the first chapter. If it is left blank doxygen will generate a
-# standard header. Notice: only use this tag if you know what you are doing!
-
-LATEX_HEADER =
-
-# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
-# is prepared for conversion to pdf (using ps2pdf). The pdf file will
-# contain links (just like the HTML output) instead of page references
-# This makes the output suitable for online browsing using a pdf viewer.
-
-PDF_HYPERLINKS = NO
-
-# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
-# plain latex in the generated Makefile. Set this option to YES to get a
-# higher quality PDF documentation.
-
-USE_PDFLATEX = NO
-
-# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
-# command to the generated LaTeX files. This will instruct LaTeX to keep
-# running if errors occur, instead of asking the user for help.
-# This option is also used when generating formulas in HTML.
-
-LATEX_BATCHMODE = NO
-
-# If LATEX_HIDE_INDICES is set to YES then doxygen will not
-# include the index chapters (such as File Index, Compound Index, etc.)
-# in the output.
-
-LATEX_HIDE_INDICES = NO
-
-# If LATEX_SOURCE_CODE is set to YES then doxygen will include
-# source code with syntax highlighting in the LaTeX output.
-# Note that which sources are shown also depends on other settings
-# such as SOURCE_BROWSER.
-
-LATEX_SOURCE_CODE = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the RTF output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
-# The RTF output is optimized for Word 97 and may not look very pretty with
-# other RTF readers or editors.
-
-GENERATE_RTF = NO
-
-# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `rtf' will be used as the default path.
-
-RTF_OUTPUT = rtf
-
-# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
-# RTF documents. This may be useful for small projects and may help to
-# save some trees in general.
-
-COMPACT_RTF = NO
-
-# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
-# will contain hyperlink fields. The RTF file will
-# contain links (just like the HTML output) instead of page references.
-# This makes the output suitable for online browsing using WORD or other
-# programs which support those fields.
-# Note: wordpad (write) and others do not support links.
-
-RTF_HYPERLINKS = NO
-
-# Load stylesheet definitions from file. Syntax is similar to doxygen's
-# config file, i.e. a series of assignments. You only have to provide
-# replacements, missing definitions are set to their default value.
-
-RTF_STYLESHEET_FILE =
-
-# Set optional variables used in the generation of an rtf document.
-# Syntax is similar to doxygen's config file.
-
-RTF_EXTENSIONS_FILE =
-
-#---------------------------------------------------------------------------
-# configuration options related to the man page output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
-# generate man pages
-
-GENERATE_MAN = NO
-
-# The MAN_OUTPUT tag is used to specify where the man pages will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `man' will be used as the default path.
-
-MAN_OUTPUT = man
-
-# The MAN_EXTENSION tag determines the extension that is added to
-# the generated man pages (default is the subroutine's section .3)
-
-MAN_EXTENSION = .3
-
-# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
-# then it will generate one additional man file for each entity
-# documented in the real man page(s). These additional files
-# only source the real man page, but without them the man command
-# would be unable to find the correct page. The default is NO.
-
-MAN_LINKS = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the XML output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_XML tag is set to YES Doxygen will
-# generate an XML file that captures the structure of
-# the code including all documentation.
-
-GENERATE_XML = NO
-
-# The XML_OUTPUT tag is used to specify where the XML pages will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be
-# put in front of it. If left blank `xml' will be used as the default path.
-
-XML_OUTPUT = xml
-
-# The XML_SCHEMA tag can be used to specify an XML schema,
-# which can be used by a validating XML parser to check the
-# syntax of the XML files.
-
-XML_SCHEMA =
-
-# The XML_DTD tag can be used to specify an XML DTD,
-# which can be used by a validating XML parser to check the
-# syntax of the XML files.
-
-XML_DTD =
-
-# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
-# dump the program listings (including syntax highlighting
-# and cross-referencing information) to the XML output. Note that
-# enabling this will significantly increase the size of the XML output.
-
-XML_PROGRAMLISTING = YES
-
-#---------------------------------------------------------------------------
-# configuration options for the AutoGen Definitions output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
-# generate an AutoGen Definitions (see autogen.sf.net) file
-# that captures the structure of the code including all
-# documentation. Note that this feature is still experimental
-# and incomplete at the moment.
-
-GENERATE_AUTOGEN_DEF = NO
-
-#---------------------------------------------------------------------------
-# configuration options related to the Perl module output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_PERLMOD tag is set to YES Doxygen will
-# generate a Perl module file that captures the structure of
-# the code including all documentation. Note that this
-# feature is still experimental and incomplete at the
-# moment.
-
-GENERATE_PERLMOD = NO
-
-# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
-# the necessary Makefile rules, Perl scripts and LaTeX code to be able
-# to generate PDF and DVI output from the Perl module output.
-
-PERLMOD_LATEX = NO
-
-# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
-# nicely formatted so it can be parsed by a human reader.
-# This is useful
-# if you want to understand what is going on.
-# On the other hand, if this
-# tag is set to NO the size of the Perl module output will be much smaller
-# and Perl will parse it just the same.
-
-PERLMOD_PRETTY = YES
-
-# The names of the make variables in the generated doxyrules.make file
-# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
-# This is useful so different doxyrules.make files included by the same
-# Makefile don't overwrite each other's variables.
-
-PERLMOD_MAKEVAR_PREFIX =
-
-#---------------------------------------------------------------------------
-# Configuration options related to the preprocessor
-#---------------------------------------------------------------------------
-
-# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
-# evaluate all C-preprocessor directives found in the sources and include
-# files.
-
-ENABLE_PREPROCESSING = YES
-
-# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
-# names in the source code. If set to NO (the default) only conditional
-# compilation will be performed. Macro expansion can be done in a controlled
-# way by setting EXPAND_ONLY_PREDEF to YES.
-
-MACRO_EXPANSION = NO
-
-# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
-# then the macro expansion is limited to the macros specified with the
-# PREDEFINED and EXPAND_AS_DEFINED tags.
-
-EXPAND_ONLY_PREDEF = NO
-
-# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
-# in the INCLUDE_PATH (see below) will be search if a #include is found.
-
-SEARCH_INCLUDES = YES
-
-# The INCLUDE_PATH tag can be used to specify one or more directories that
-# contain include files that are not input files but should be processed by
-# the preprocessor.
-
-INCLUDE_PATH =
-
-# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
-# patterns (like *.h and *.hpp) to filter out the header-files in the
-# directories. If left blank, the patterns specified with FILE_PATTERNS will
-# be used.
-
-INCLUDE_FILE_PATTERNS =
-
-# The PREDEFINED tag can be used to specify one or more macro names that
-# are defined before the preprocessor is started (similar to the -D option of
-# gcc). The argument of the tag is a list of macros of the form: name
-# or name=definition (no spaces). If the definition and the = are
-# omitted =1 is assumed. To prevent a macro definition from being
-# undefined via #undef or recursively expanded use the := operator
-# instead of the = operator.
-
-PREDEFINED =
-
-# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
-# this tag can be used to specify a list of macro names that should be expanded.
-# The macro definition that is found in the sources will be used.
-# Use the PREDEFINED tag if you want to use a different macro definition.
-
-EXPAND_AS_DEFINED =
-
-# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
-# doxygen's preprocessor will remove all function-like macros that are alone
-# on a line, have an all uppercase name, and do not end with a semicolon. Such
-# function macros are typically used for boiler-plate code, and will confuse
-# the parser if not removed.
-
-SKIP_FUNCTION_MACROS = YES
-
-#---------------------------------------------------------------------------
-# Configuration::additions related to external references
-#---------------------------------------------------------------------------
-
-# The TAGFILES option can be used to specify one or more tagfiles.
-# Optionally an initial location of the external documentation
-# can be added for each tagfile. The format of a tag file without
-# this location is as follows:
-#
-# TAGFILES = file1 file2 ...
-# Adding location for the tag files is done as follows:
-#
-# TAGFILES = file1=loc1 "file2 = loc2" ...
-# where "loc1" and "loc2" can be relative or absolute paths or
-# URLs. If a location is present for each tag, the installdox tool
-# does not have to be run to correct the links.
-# Note that each tag file must have a unique name
-# (where the name does NOT include the path)
-# If a tag file is not located in the directory in which doxygen
-# is run, you must also specify the path to the tagfile here.
-
-TAGFILES =
-
-# When a file name is specified after GENERATE_TAGFILE, doxygen will create
-# a tag file that is based on the input files it reads.
-
-GENERATE_TAGFILE =
-
-# If the ALLEXTERNALS tag is set to YES all external classes will be listed
-# in the class index. If set to NO only the inherited external classes
-# will be listed.
-
-ALLEXTERNALS = NO
-
-# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
-# in the modules index. If set to NO, only the current project's groups will
-# be listed.
-
-EXTERNAL_GROUPS = YES
-
-# The PERL_PATH should be the absolute path and name of the perl script
-# interpreter (i.e. the result of `which perl').
-
-PERL_PATH = /usr/bin/perl
-
-#---------------------------------------------------------------------------
-# Configuration options related to the dot tool
-#---------------------------------------------------------------------------
-
-# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
-# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
-# or super classes. Setting the tag to NO turns the diagrams off. Note that
-# this option is superseded by the HAVE_DOT option below. This is only a
-# fallback. It is recommended to install and use dot, since it yields more
-# powerful graphs.
-
-CLASS_DIAGRAMS = YES
-
-# You can define message sequence charts within doxygen comments using the \msc
-# command. Doxygen will then run the mscgen tool (see
-# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
-# documentation. The MSCGEN_PATH tag allows you to specify the directory where
-# the mscgen tool resides. If left empty the tool is assumed to be found in the
-# default search path.
-
-MSCGEN_PATH =
-
-# If set to YES, the inheritance and collaboration graphs will hide
-# inheritance and usage relations if the target is undocumented
-# or is not a class.
-
-HIDE_UNDOC_RELATIONS = NO
-
-# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
-# available from the path. This tool is part of Graphviz, a graph visualization
-# toolkit from AT&T and Lucent Bell Labs. The other options in this section
-# have no effect if this option is set to NO (the default)
-
-HAVE_DOT = YES
-
-# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
-# allowed to run in parallel. When set to 0 (the default) doxygen will
-# base this on the number of processors available in the system. You can set it
-# explicitly to a value larger than 0 to get control over the balance
-# between CPU load and processing speed.
-
-DOT_NUM_THREADS = 0
-
-# By default doxygen will write a font called FreeSans.ttf to the output
-# directory and reference it in all dot files that doxygen generates. This
-# font does not include all possible unicode characters however, so when you need
-# these (or just want a differently looking font) you can specify the font name
-# using DOT_FONTNAME. You need need to make sure dot is able to find the font,
-# which can be done by putting it in a standard location or by setting the
-# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
-# containing the font.
-
-DOT_FONTNAME = FreeSans
-
-# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
-# The default size is 10pt.
-
-DOT_FONTSIZE = 10
-
-# By default doxygen will tell dot to use the output directory to look for the
-# FreeSans.ttf font (which doxygen will put there itself). If you specify a
-# different font using DOT_FONTNAME you can set the path where dot
-# can find it using this tag.
-
-DOT_FONTPATH =
-
-# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for each documented class showing the direct and
-# indirect inheritance relations. Setting this tag to YES will force the
-# the CLASS_DIAGRAMS tag to NO.
-
-CLASS_GRAPH = YES
-
-# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for each documented class showing the direct and
-# indirect implementation dependencies (inheritance, containment, and
-# class references variables) of the class with other documented classes.
-
-COLLABORATION_GRAPH = YES
-
-# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
-# will generate a graph for groups, showing the direct groups dependencies
-
-GROUP_GRAPHS = YES
-
-# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
-# collaboration diagrams in a style similar to the OMG's Unified Modeling
-# Language.
-
-UML_LOOK = YES
-
-# If set to YES, the inheritance and collaboration graphs will show the
-# relations between templates and their instances.
-
-TEMPLATE_RELATIONS = NO
-
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
-# tags are set to YES then doxygen will generate a graph for each documented
-# file showing the direct and indirect include dependencies of the file with
-# other documented files.
-
-INCLUDE_GRAPH = YES
-
-# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
-# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
-# documented header file showing the documented files that directly or
-# indirectly include this file.
-
-INCLUDED_BY_GRAPH = YES
-
-# If the CALL_GRAPH and HAVE_DOT options are set to YES then
-# doxygen will generate a call dependency graph for every global function
-# or class method. Note that enabling this option will significantly increase
-# the time of a run. So in most cases it will be better to enable call graphs
-# for selected functions only using the \callgraph command.
-
-CALL_GRAPH = YES
-
-# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
-# doxygen will generate a caller dependency graph for every global function
-# or class method. Note that enabling this option will significantly increase
-# the time of a run. So in most cases it will be better to enable caller
-# graphs for selected functions only using the \callergraph command.
-
-CALLER_GRAPH = YES
-
-# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
-# will graphical hierarchy of all classes instead of a textual one.
-
-GRAPHICAL_HIERARCHY = YES
-
-# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
-# then doxygen will show the dependencies a directory has on other directories
-# in a graphical way. The dependency relations are determined by the #include
-# relations between the files in the directories.
-
-DIRECTORY_GRAPH = YES
-
-# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
-# generated by dot. Possible values are png, jpg, or gif
-# If left blank png will be used.
-
-DOT_IMAGE_FORMAT = png
-
-# The tag DOT_PATH can be used to specify the path where the dot tool can be
-# found. If left blank, it is assumed the dot tool can be found in the path.
-
-DOT_PATH =
-
-# The DOTFILE_DIRS tag can be used to specify one or more directories that
-# contain dot files that are included in the documentation (see the
-# \dotfile command).
-
-DOTFILE_DIRS =
-
-# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
-# nodes that will be shown in the graph. If the number of nodes in a graph
-# becomes larger than this value, doxygen will truncate the graph, which is
-# visualized by representing a node as a red box. Note that doxygen if the
-# number of direct children of the root node in a graph is already larger than
-# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
-# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
-
-DOT_GRAPH_MAX_NODES = 50
-
-# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
-# graphs generated by dot. A depth value of 3 means that only nodes reachable
-# from the root by following a path via at most 3 edges will be shown. Nodes
-# that lay further from the root node will be omitted. Note that setting this
-# option to 1 or 2 may greatly reduce the computation time needed for large
-# code bases. Also note that the size of a graph can be further restricted by
-# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
-
-MAX_DOT_GRAPH_DEPTH = 0
-
-# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
-# background. This is disabled by default, because dot on Windows does not
-# seem to support this out of the box. Warning: Depending on the platform used,
-# enabling this option may lead to badly anti-aliased labels on the edges of
-# a graph (i.e. they become hard to read).
-
-DOT_TRANSPARENT = NO
-
-# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
-# files in one run (i.e. multiple -o and -T options on the command line). This
-# makes dot run faster, but since only newer versions of dot (>1.8.10)
-# support this, this feature is disabled by default.
-
-DOT_MULTI_TARGETS = YES
-
-# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
-# generate a legend page explaining the meaning of the various boxes and
-# arrows in the dot generated graphs.
-
-GENERATE_LEGEND = YES
-
-# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
-# remove the intermediate dot files that are used to generate
-# the various graphs.
-
-DOT_CLEANUP = YES
diff --git a/documentation/Doxyfile.coreboot_simple b/documentation/Doxyfile.coreboot_simple
deleted file mode 100644
index 2135d96..0000000
--- a/documentation/Doxyfile.coreboot_simple
+++ /dev/null
@@ -1,259 +0,0 @@
-# Doxyfile 1.8.8
-DOXYFILE_ENCODING = UTF-8
-PROJECT_NAME = coreboot
-PROJECT_NUMBER =
-PROJECT_BRIEF = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers."
-PROJECT_LOGO = documentation/coreboot_logo.png
-OUTPUT_DIRECTORY = doxygen
-CREATE_SUBDIRS = YES
-ALLOW_UNICODE_NAMES = NO
-OUTPUT_LANGUAGE = English
-BRIEF_MEMBER_DESC = YES
-REPEAT_BRIEF = YES
-ABBREVIATE_BRIEF =
-ALWAYS_DETAILED_SEC = YES
-INLINE_INHERITED_MEMB = NO
-FULL_PATH_NAMES = YES
-STRIP_FROM_PATH =
-STRIP_FROM_INC_PATH =
-SHORT_NAMES = NO
-JAVADOC_AUTOBRIEF = YES
-QT_AUTOBRIEF = NO
-MULTILINE_CPP_IS_BRIEF = NO
-INHERIT_DOCS = YES
-SEPARATE_MEMBER_PAGES = NO
-TAB_SIZE = 8
-ALIASES =
-TCL_SUBST =
-OPTIMIZE_OUTPUT_FOR_C = YES
-OPTIMIZE_OUTPUT_JAVA = NO
-OPTIMIZE_FOR_FORTRAN = NO
-OPTIMIZE_OUTPUT_VHDL = NO
-EXTENSION_MAPPING =
-MARKDOWN_SUPPORT = YES
-AUTOLINK_SUPPORT = YES
-BUILTIN_STL_SUPPORT = NO
-CPP_CLI_SUPPORT = NO
-SIP_SUPPORT = NO
-IDL_PROPERTY_SUPPORT = YES
-DISTRIBUTE_GROUP_DOC = NO
-SUBGROUPING = YES
-INLINE_GROUPED_CLASSES = NO
-INLINE_SIMPLE_STRUCTS = NO
-TYPEDEF_HIDES_STRUCT = NO
-LOOKUP_CACHE_SIZE = 0
-EXTRACT_ALL = YES
-EXTRACT_PRIVATE = NO
-EXTRACT_PACKAGE = NO
-EXTRACT_STATIC = YES
-EXTRACT_LOCAL_CLASSES = YES
-EXTRACT_LOCAL_METHODS = NO
-EXTRACT_ANON_NSPACES = NO
-HIDE_UNDOC_MEMBERS = NO
-HIDE_UNDOC_CLASSES = NO
-HIDE_FRIEND_COMPOUNDS = NO
-HIDE_IN_BODY_DOCS = NO
-INTERNAL_DOCS = NO
-CASE_SENSE_NAMES = YES
-HIDE_SCOPE_NAMES = NO
-SHOW_INCLUDE_FILES = YES
-SHOW_GROUPED_MEMB_INC = NO
-FORCE_LOCAL_INCLUDES = NO
-INLINE_INFO = YES
-SORT_MEMBER_DOCS = YES
-SORT_BRIEF_DOCS = NO
-SORT_MEMBERS_CTORS_1ST = NO
-SORT_GROUP_NAMES = NO
-SORT_BY_SCOPE_NAME = NO
-STRICT_PROTO_MATCHING = NO
-GENERATE_TODOLIST = YES
-GENERATE_TESTLIST = YES
-GENERATE_BUGLIST = YES
-GENERATE_DEPRECATEDLIST= YES
-ENABLED_SECTIONS =
-MAX_INITIALIZER_LINES = 30
-SHOW_USED_FILES = YES
-SHOW_FILES = YES
-SHOW_NAMESPACES = YES
-FILE_VERSION_FILTER =
-LAYOUT_FILE =
-CITE_BIB_FILES =
-QUIET = YES
-WARNINGS = YES
-WARN_IF_UNDOCUMENTED = YES
-WARN_IF_DOC_ERROR = YES
-WARN_NO_PARAMDOC = YES
-WARN_FORMAT = "$file:$line: $text"
-WARN_LOGFILE =
-INPUT = src \
- documentation
-INPUT_ENCODING = UTF-8
-FILE_PATTERNS =
-RECURSIVE = YES
-EXCLUDE = src/vendorcode
-EXCLUDE_SYMLINKS = NO
-EXCLUDE_PATTERNS =
-EXCLUDE_SYMBOLS =
-EXAMPLE_PATH =
-EXAMPLE_PATTERNS =
-EXAMPLE_RECURSIVE = NO
-IMAGE_PATH =
-INPUT_FILTER =
-FILTER_PATTERNS =
-FILTER_SOURCE_FILES = NO
-FILTER_SOURCE_PATTERNS =
-USE_MDFILE_AS_MAINPAGE =
-SOURCE_BROWSER = YES
-INLINE_SOURCES = NO
-STRIP_CODE_COMMENTS = NO
-REFERENCED_BY_RELATION = YES
-REFERENCES_RELATION = YES
-REFERENCES_LINK_SOURCE = YES
-SOURCE_TOOLTIPS = YES
-USE_HTAGS = NO
-VERBATIM_HEADERS = YES
-ALPHABETICAL_INDEX = YES
-COLS_IN_ALPHA_INDEX = 5
-IGNORE_PREFIX =
-GENERATE_HTML = YES
-HTML_OUTPUT = html
-HTML_FILE_EXTENSION = .html
-HTML_HEADER =
-HTML_FOOTER =
-HTML_STYLESHEET =
-HTML_EXTRA_STYLESHEET =
-HTML_EXTRA_FILES =
-HTML_COLORSTYLE_HUE = 220
-HTML_COLORSTYLE_SAT = 100
-HTML_COLORSTYLE_GAMMA = 80
-HTML_TIMESTAMP = NO
-HTML_DYNAMIC_SECTIONS = NO
-HTML_INDEX_NUM_ENTRIES = 100
-GENERATE_DOCSET = NO
-DOCSET_FEEDNAME = "Doxygen documentation"
-DOCSET_BUNDLE_ID = org.doxygen.Project
-DOCSET_PUBLISHER_ID = org.doxygen.Publisher
-DOCSET_PUBLISHER_NAME = Publisher
-GENERATE_HTMLHELP = NO
-CHM_FILE =
-HHC_LOCATION =
-GENERATE_CHI = NO
-CHM_INDEX_ENCODING =
-BINARY_TOC = NO
-TOC_EXPAND = NO
-GENERATE_QHP = NO
-QCH_FILE =
-QHP_NAMESPACE = org.doxygen.Project
-QHP_VIRTUAL_FOLDER = doc
-QHP_CUST_FILTER_NAME =
-QHP_CUST_FILTER_ATTRS =
-QHP_SECT_FILTER_ATTRS =
-QHG_LOCATION =
-GENERATE_ECLIPSEHELP = NO
-ECLIPSE_DOC_ID = org.doxygen.Project
-DISABLE_INDEX = NO
-GENERATE_TREEVIEW = YES
-ENUM_VALUES_PER_LINE = 4
-TREEVIEW_WIDTH = 250
-EXT_LINKS_IN_WINDOW = NO
-FORMULA_FONTSIZE = 10
-FORMULA_TRANSPARENT = YES
-USE_MATHJAX = NO
-MATHJAX_FORMAT = HTML-CSS
-MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest
-MATHJAX_EXTENSIONS =
-MATHJAX_CODEFILE =
-SEARCHENGINE = YES
-SERVER_BASED_SEARCH = NO
-EXTERNAL_SEARCH = NO
-SEARCHENGINE_URL =
-SEARCHDATA_FILE = searchdata.xml
-EXTERNAL_SEARCH_ID =
-EXTRA_SEARCH_MAPPINGS =
-GENERATE_LATEX = NO
-LATEX_OUTPUT = latex
-LATEX_CMD_NAME = latex
-MAKEINDEX_CMD_NAME = makeindex
-COMPACT_LATEX = NO
-PAPER_TYPE = a4wide
-EXTRA_PACKAGES =
-LATEX_HEADER =
-LATEX_FOOTER =
-LATEX_EXTRA_FILES =
-PDF_HYPERLINKS = NO
-USE_PDFLATEX = NO
-LATEX_BATCHMODE = NO
-LATEX_HIDE_INDICES = NO
-LATEX_SOURCE_CODE = NO
-LATEX_BIB_STYLE = plain
-GENERATE_RTF = NO
-RTF_OUTPUT = rtf
-COMPACT_RTF = NO
-RTF_HYPERLINKS = NO
-RTF_STYLESHEET_FILE =
-RTF_EXTENSIONS_FILE =
-GENERATE_MAN = NO
-MAN_OUTPUT = man
-MAN_EXTENSION = .3
-MAN_SUBDIR =
-MAN_LINKS = NO
-GENERATE_XML = NO
-XML_OUTPUT = xml
-XML_PROGRAMLISTING = YES
-GENERATE_DOCBOOK = NO
-DOCBOOK_OUTPUT = docbook
-DOCBOOK_PROGRAMLISTING = NO
-GENERATE_AUTOGEN_DEF = NO
-GENERATE_PERLMOD = NO
-PERLMOD_LATEX = NO
-PERLMOD_PRETTY = YES
-PERLMOD_MAKEVAR_PREFIX =
-ENABLE_PREPROCESSING = YES
-MACRO_EXPANSION = YES
-EXPAND_ONLY_PREDEF = YES
-SEARCH_INCLUDES = YES
-INCLUDE_PATH =
-INCLUDE_FILE_PATTERNS =
-PREDEFINED = __attribute__(x)=
-EXPAND_AS_DEFINED =
-SKIP_FUNCTION_MACROS = YES
-TAGFILES =
-GENERATE_TAGFILE =
-ALLEXTERNALS = NO
-EXTERNAL_GROUPS = YES
-EXTERNAL_PAGES = YES
-PERL_PATH = /usr/bin/perl
-CLASS_DIAGRAMS = YES
-MSCGEN_PATH =
-DIA_PATH =
-HIDE_UNDOC_RELATIONS = NO
-HAVE_DOT = NO
-DOT_NUM_THREADS = 0
-DOT_FONTNAME = Helvetica
-DOT_FONTSIZE = 10
-DOT_FONTPATH =
-CLASS_GRAPH = YES
-COLLABORATION_GRAPH = YES
-GROUP_GRAPHS = YES
-UML_LOOK = YES
-UML_LIMIT_NUM_FIELDS = 10
-TEMPLATE_RELATIONS = NO
-INCLUDE_GRAPH = YES
-INCLUDED_BY_GRAPH = YES
-CALL_GRAPH = YES
-CALLER_GRAPH = YES
-GRAPHICAL_HIERARCHY = YES
-DIRECTORY_GRAPH = YES
-DOT_IMAGE_FORMAT = png
-INTERACTIVE_SVG = NO
-DOT_PATH =
-DOTFILE_DIRS =
-MSCFILE_DIRS =
-DIAFILE_DIRS =
-PLANTUML_JAR_PATH =
-DOT_GRAPH_MAX_NODES = 50
-MAX_DOT_GRAPH_DEPTH = 0
-DOT_TRANSPARENT = NO
-DOT_MULTI_TARGETS = YES
-GENERATE_LEGEND = YES
-DOT_CLEANUP = YES
diff --git a/documentation/Kconfig.tex b/documentation/Kconfig.tex
deleted file mode 100644
index 2b2bf7f..0000000
--- a/documentation/Kconfig.tex
+++ /dev/null
@@ -1,480 +0,0 @@
-\documentclass[10pt,letterpaper]{article}
-\usepackage[latin1]{inputenc}
-\usepackage{amsmath}
-\usepackage{amsfonts}
-\usepackage{amssymb}
-\author{Ron Minnich}
-\title{Kconfig usage in coreboot v2}
-\begin{document}
-\section{Introduction}
-This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them.
-\section{Kconfig variations}
-Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard.
-
-For variables set by the user, see src/console/Kconfig.
-
-For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent.
-
-Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally.
-
-\section{Makefile and Makefile.inc}
-There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y.
-
-Make is not recursive. There is only one make process.
-\subsection{subdirs usage}
-Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y.
-
-We define the common rules for which variation to use below.
-\subsection{object file specification}
-There are several different types of objects specified in the tree. They are:
-\begin{description}
-\item[obj]objects for the ram part of the code
-\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
-\item[initobj]seperately-compiled code for the ROM section of coreboot
-\end{description}
-These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax.
-
-\section{Example: AMD serengeti cheetah}
-\subsection{mainboard/Kconfig}
-Defines Vendor variables. Currently defined variables are:
-Sources all Kconfig files in the vendor directories.
-\input{ mainboardkconfig.tex}
-\subsection{mainboard/Makefile.inc}
-There is none at this time.
-\subsection{mainboard/$<$vendor$>$/Kconfig}
-We use the amd as a model. The only action currently taken is to source all Kconfig's in the
-subdirectories.
-\subsection{mainboard/$<$vendor$>$/Makefile.inc}
-We use amd as a model. There is currently no Makefile.inc at this level.
-\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig}
-The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines
-and rules in here determine everything about how a mainboard target is built.
-We will use serengeti\_cheetah as a model. It defines these variables.
-\input{ mainboardkconfig.tex}
-\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc}
-This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece.
-Note that this is the mainboard as of August, 2009, and it may change over time.
-\subsubsection{objects}
-We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional:
-\begin{verbatim}
-driver-y += mainboard.o
-
-#needed by irq_tables and mptable and acpi_tables
-obj-y += get_bus_conf.o
-obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
-obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
-obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
-obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
-obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
-
-#./ssdt.o is in northbridge/amd/amdk8/Config.lb
-obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o
-obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o
-obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o
-driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
-
-# This is part of the conversion to init-obj and away from included code.
-
-initobj-y += crt0.o
-\end{verbatim}
-\subsubsection{romcc legacy support}
-We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define
-crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the
-old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally.
-\begin{verbatim}
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
-crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
-crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
-crt0-y += auto.inc
-
-ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/arch/i386/lib/failover.lds
-
-\end{verbatim}
-\subsubsection{POST\_EVALUATION}
-POST\_EVALUATION rules should be placed after this section:
-\begin{verbatim}
-ifdef POST_EVALUATION
-\end{verbatim}
-to ensure that the values of variables are correct.
-Here are the post-evaluation rules for this mainboard:
-\begin{verbatim}
-$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
- mv dsdt.hex $@
-
-$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
-
-$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
- iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
- mv pci2.hex ssdt2.c
-
-$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
- iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
- perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
- mv pci3.hex ssdt3.c
-
-$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
- iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
- perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
- mv pci4.hex ssdt4.c
-
-$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h
- $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@
- perl -e 's/\.rodata/.rom.data/g' -pi $@
- perl -e 's/\.text/.section .rom.text/g' -pi $@
-
-\end{verbatim}
-The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables.
-\subsubsection{devicetree.cb}
-Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard
-properly, as it defines topology and chips that can be defined no other way.
-Let's go through the tree.
-\begin{verbatim}
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_F
- device lapic 0 on end
- end
- end
-\end{verbatim}
-This topology is always somewhat confusing to newcomers, and even to coreboot veterans.
-
-We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we
-have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge
-somewhere, since it runs memory.
-
-
-What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the
-CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains
-its own APIC, and will define any parameters needed. In this case, we have a northbridge of type
-{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on,
-which connects to a {\it cpu/amd/socket\_F},
-which has a local apic, which is on.
-
-Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here
-is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
-BIOSes) that the BSP be CPU 0; any CPU will do.
-\begin{verbatim}
- device domain 0 on
- chip northbridge/amd/amdk8
- device pci 18.0 on # northbridge
- # devices on link 0, link 0 == LDT 0
-\end{verbatim}
-Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On
-Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up.
-\begin{verbatim}
- chip southbridge/amd/amd8132
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
-\end{verbatim}
-This is the 8132, a bridge to a secondary PCI bus.
-\begin{verbatim}
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 off end
- device pci 1.0 off end
- end
-\end{verbatim}
-The 8111 is a bridge to other busses and to the legacy ISA devices such as superio.
-\begin{verbatim}
- device pci 1.0 on
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
-\end{verbatim}
-The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the
-2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN.
-\begin{verbatim}
- device pci 1.1 on end
- device pci 1.2 on end
-\end{verbatim}
-More devices. These statements set up placeholders in the device tree.
-\begin{verbatim}
- device pci 1.3 on
- chip drivers/i2c/i2cmux # pca9556 smbus mux
- device i2c 18 on #0 pca9516 1
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- end
- device i2c 18 on #1 pca9516 2
- chip drivers/generic/generic #dimm 1-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 1-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 1-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 1-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic #dimm 1-2-0
- device i2c 54 on end
- end
- chip drivers/generic/generic #dimm 1-2-1
- device i2c 55 on end
- end
- chip drivers/generic/generic #dimm 1-3-0
- device i2c 56 on end
- end
- chip drivers/generic/generic #dimm 1-3-1
- device i2c 57 on end
- end
- end
- end
- end # acpi
-\end{verbatim}
-These are the i2c devices.
-\begin{verbatim}
- device pci 1.5 off end
- device pci 1.6 off end
-\end{verbatim}
-More placeholders.
-\begin{verbatim}
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- end
- end # device pci 18.0
-
-\end{verbatim}
-These "register" commands set controls in the southbridge.
-\begin{verbatim}
- device pci 18.0 on end
- device pci 18.0 on end
-\end{verbatim}
-These are the other two hypertransport links.
-\begin{verbatim}
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
-\end{verbatim}
-The 18.1 devices are, again, northbridge control for various k8 functions.
-\begin{verbatim}
- end
- \end{verbatim}
-That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here.
-\begin{verbatim}
- chip northbridge/amd/amdk8
- device pci 19.0 on # northbridge
- chip southbridge/amd/amd8151
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 1.0 on end
- end
- end # device pci 19.0
-
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- end
-
-
-\end{verbatim}
-
-\subsection{cpu socket}
-The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only
-the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus
-of all defines and Makefile controls for building the CPU components of a board.
-
-\subsubsection{ cpu/Kconfig}
-Defines variables. Current variables are:
-\input{cpukconfig.tex}
-Sources all Kconfig files in the vendor directories.
-\subsubsection{ cpu/Makefile.inc}
-Unconditionally sources all Makefile.inc in the vendor directories.
-
-\subsection{cpu/$<$vendor$>$/Kconfig}
-The only action currently taken is to source all Kconfig's in the
-subdirectories.
-\subsection{cpu/$<$vendor$>$/Makefile.inc}
-{\em Conditionally} source the socket directories.
-Example:
-\begin{verbatim}
-subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F
-\end{verbatim}
-.
-CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file.
-
-\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig}
-Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that
-the socket, as much as possible, should control the models, because the models may plug into many sockets.
-Socket\_F currently sets:
-\input{socketfkconfig.tex}
-
-It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced.
-
-\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig}
-CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that
-if needed.
-\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc}
-The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional
-compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all}
-objects, because it is not possible to determine at build time what options may be needed for a given model CPU.
-This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc.
-
-\subsection{northbridge}
-\subsubsection{northbridge/Kconfig}
-No variables. Source all vendor directory Kconfigs.
-\subsubsection{northbridge/Makefile.inc}
-No variables. unconditionally include all vendor Makefile.inc
-\subsubsection{northbridge/$<$vendor$>$/Kconfig}
-No variables. Source all chip directory Kconfigs.
-\subsubsection{northbridge/$<$vendor$>$/Makefile.inc}
-No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
-is the name of the part, e.g.
-\begin{verbatim}
-subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
-\end{verbatim}
-.
-\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
-Typically a small number of variables. One defines the part name. Here is an example
-of the variables defined for the K8.
-\begin{verbatim}
-config NORTHBRIDGE_AMD_AMDK8
- bool
- default n
-
-config AGP_APERTURE_SIZE
- hex
- default 0x4000000
-\end{verbatim}
-\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
-Typically very small set of rules, and very simple.
-Since this file is already conditionally included,
-we don't need to test for the chipset CONFIG variable. We
-can therefore test other variables (which is part of the reason
-we set up conditional inclusion of this file, instead
-of unconditionally including it). Here is an example from AMD K8.
-Note that we can make a variable conditional on the ACPI tables.
-\begin{verbatim}
-driver-y += northbridge.o
-driver-y += misc_control.o
-obj-y += get_sblk_pci1234.o
-obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o
-\end{verbatim}
-
-\subsection{southbridge}
-\subsubsection{southbridge/Kconfig}
-No variables. Source all vendor directory Kconfigs.
-\subsubsection{southbridge/Makefile.inc}
-No variables. {\em Unconditionally} include all vendor Makefile.inc
-\subsubsection{southbridge/$<$vendor$>$/Kconfig}
-No variables. Source all chip directory Kconfigs.
-\subsubsection{southbridge/$<$vendor$>$/Makefile.inc}
-No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
-is the name of the part, e.g.
-\begin{verbatim}
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
-\end{verbatim}
-.
-\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
-Typically a small number of variables. One defines the part name. Here is an example
-of the variables defined for the K8.
-\begin{verbatim}
-config SOUTHBRIDGE_AMD_AMD8111
- bool
- default n
-
-\end{verbatim}
-\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
-Typically very small set of rules, and very simple.
-Since this file is already conditionally included,
-we don't need to test for the chipset CONFIG variable. We
-can therefore test other variables (which is part of the reason
-we set up conditional inclusion of this file, instead
-of unconditionally including it). Here is an example from AMD 8111.
-No conditionals in this one yet.
-\begin{verbatim}
-driver-y += amd8111.o
-driver-y += amd8111_usb.o
-driver-y += amd8111_lpc.o
-driver-y += amd8111_ide.o
-driver-y += amd8111_acpi.o
-driver-y += amd8111_usb2.o
-driver-y += amd8111_ac97.o
-driver-y += amd8111_nic.o
-driver-y += amd8111_pci.o
-driver-y += amd8111_smbus.o
-obj-y += amd8111_reset.o
-\end{verbatim}
-
-\subsubsection{vendor and part}
-\subsection{southbridge}
-\subsubsection{vendor and part}
-\subsection{superio}
-\subsection{drivers/i2c}
-This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed.
-To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have:
-\begin{verbatim}
-\end{verbatim}
-
-\subsubsection{vendor and part}
-
-\end{document}
diff --git a/documentation/Makefile b/documentation/Makefile
deleted file mode 100644
index 1e00444..0000000
--- a/documentation/Makefile
+++ /dev/null
@@ -1,71 +0,0 @@
-#
-# Makefile for coreboot paper.
-# hacked together by Stefan Reinauer <stepan(a)openbios.org>
-#
-
-PDFLATEX=pdflatex -t a4
-
-FIGS=codeflow.pdf hypertransport.pdf
-
-all: CorebootPortingGuide.pdf Kconfig.pdf
-
-SVG2PDF=$(shell which svg2pdf)
-INKSCAPE=$(shell which inkscape)
-CONVERT=$(shell which convert)
-
-codeflow.pdf: codeflow.svg
-ifneq ($(strip $(SVG2PDF)),)
- svg2pdf $< $@
-else ifneq ($(strip $(INKSCAPE)),)
- inkscape $< --export-pdf=$@
-else ifneq ($(strip $(CONVERT)),)
- convert $< $@
-endif
-
-hypertransport.pdf: hypertransport.svg
-ifneq ($(strip $(SVG2PDF)),)
- svg2pdf $< $@
-else ifneq ($(strip $(INKSCAPE)),)
- inkscape $< --export-pdf=$@
-else ifneq ($(strip $(CONVERT)),)
- convert $< $@
-endif
-
-CorebootPortingGuide.toc: $(FIGS) CorebootBuildingGuide.tex
- # 2 times to make sure we have a current toc.
- $(PDFLATEX) CorebootBuildingGuide.tex
- $(PDFLATEX) CorebootBuildingGuide.tex
-
-CorebootPortingGuide.pdf: $(FIGS) CorebootBuildingGuide.tex CorebootPortingGuide.toc
- $(PDFLATEX) CorebootBuildingGuide.tex
-
-Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex
- $(PDFLATEX) $<
-
-# quick, somebody! make me a macro!
-mainboardkconfig.tex: ../src/mainboard/Kconfig
- cat beginverbatim.tex > $@
- grep '^config' $< | awk '{print $2}' >>$@
- cat endverbatim.tex >> $@
-
-skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig
- cat beginverbatim.tex > $@
- grep '^config' $< | awk '{print $2}' >>$@
- cat endverbatim.tex >> $@
-
-cpukconfig.tex: ../src/cpu/Kconfig
- cat beginverbatim.tex > $@
- grep '^config' $< | awk '{print $2}' >>$@
- cat endverbatim.tex >> $@
-
-socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig
- cat beginverbatim.tex > $@
- grep '^config' $< | awk '{print $2}' >>$@
- cat endverbatim.tex >> $@
-
-clean:
- rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex
-
-distclean: clean
- rm -f CorebootPortingGuide.pdf Kconfig.pdf
-
diff --git a/documentation/POSTCODES b/documentation/POSTCODES
deleted file mode 100644
index 85ad4d7..0000000
--- a/documentation/POSTCODES
+++ /dev/null
@@ -1,26 +0,0 @@
--------------------------------------------------------------------------------
-coreboot POST Codes
--------------------------------------------------------------------------------
-
-This is an (incomplete) list of POST codes emitted by coreboot v4.
-
-0x10 Entry into protected mode
-0x01 Entry into 'crt0.s' reset code jumps to here
-0x11 Start copying coreboot to RAM with decompression if compressed
-0x12 Copy/decompression finished jumping to RAM
-0x80 Entry into coreboot in RAM
-0x13 Entry into c_start
-0xfe Pre call to hardwaremain()
-0x39 Console is initialized
-0x40 Console boot message succeeded
-0x66 Devices have been enumerated
-0x88 Devices have been configured
-0x89 Devices have been enabled
-0xf8 Entry into elf boot
-0xf3 Jumping to payload
-
-Errors (used in several places):
-
-0xee Not supposed to get here
-0xff Elfload fail or die() called
-
diff --git a/documentation/RFC/chip.tex b/documentation/RFC/chip.tex
deleted file mode 100644
index 5e366b8..0000000
--- a/documentation/RFC/chip.tex
+++ /dev/null
@@ -1,266 +0,0 @@
- RFC for the chip specification architecture
-
-\begin{abstract}
-At the end of this document is the original message that motivated the
-change.
-\end{abstract}
-
-\section{Scope}
-This document defines how LinuxBIOS programmers can specify chips that
-are used, specified, and initalized. The current scope is for superio
-chips, but the architecture should allow for specification of other chips such
-as southbridges. Multiple chips of same or different type are supported.
-
-\section{Goals}
-The goals of the new chip architecture are these:
-\begin{itemize}
-\item seperate implementation details from specification in the Config file
-(translation: no more C code in Config files)
-\item make the specification easier for people to use and understand
-\item remove private details of a given chip to the chip file as much
-as possible
-\item allow unique register-set-specifiers for each chip
-\end{itemize}
-
-\section{Specification in the Config file}
-The specification looks like this:
-\begin{verbatim}
-chip <name> [path=<path>] ["<configuration>"]
-\end{verbatim}
-The name is in the standard LinuxBIOS form of type/vendor/name, e.g.
-"southbridge/intel/piix4e" or "superio/ite/it8671f". The class of the
-chip is derived from the first pathname component of the name, and the chip
-configuration is derived from the following components.
-
-The path defines the access mechanism to the chip.
-It is optional. If present, it overrides the default path to the chip.
-
-The configuration defines chip-specific configuration details, and is also
-optional. Note that an empty configuration will leave the chip with
-no enabled resources. This may be desirable in some cases.
-
-\section{Results of specifying a chip}
-
-When one or more chips are specified, the data about the chips
-is saved until the entire file is parsed. At this point, the config tool
-creates a file in the build directory called chip.c This file contains
-a common struct containing information about
-each individual chip and an array of pointers to these structures.
-
-For each chip, there are two structures. The structures contain control
-information for the chip, and register initialization information. The
-names of the structures are derived by ``flattening'' the chip name,
-as in the current linuxbios. For example, superio/ite/xyz uses
-two structs, one called superio_ite_xyz_control and one called
-superio_ite_xyz_init. The control struct is initialized from the
-chip name and path information, and has a pointer to the
-config struct. The config struct is initialized from the quote string
-
-\begin{verbatim}
-From rminnich(a)lanl.gov Fri May 16 10:34:13 2003
-Date: Tue, 13 May 2003 08:11:46 -0600 (MDT)
-From: ron minnich <rminnich(a)lanl.gov>
-To: linuxbios(a)clustermatic.org
-Subject: RFC:new superio proposal
-
-Abstract:
- The superio architecture for linuxbios has worked for the last 2
-years but is being stretched to the limit by the changes in superio chips.
-The architecture depended on superio resources being relatively constant
-between chips, but this assumption no longer holds. In this document we
-propose several alternatives and solicit comments.
-
-Overview:
-The superio architecture in linuxbios was developed over time, and
-modified as circumstances required. In the beginning it was relatively
-simple and assumed only one superio per mainboard. The latest version
-allows an arbitrary number of superios per mainboard, and allows complete
-specification of the superio base I/O address along with the specification
-of reasonable default valures for both the base I/O address and the
-superio parameters such as serial enable, baud rate, and so on.
-
-Specification of superio control parameters is done by a configuration
-line such as:
-
-nsuperio sis/950 com1={1} floppy=1 lpt=1
-
-This fragment sets the superio type to sis/950; sets com1, floppy, and lpt
-to enabled; and leaves the defaults to com1 (baud rate, etc.) to the
-default values.
-
-While it is not obvious, these configuration parameters are fragments of a
-C initializer. The initializers are used to build a statically initialized
-structure of this type:
-
-struct superio {
- struct superio_control *super; // the ops for the device.
- unsigned int port; // if non-zero, overrides the default port
- // com ports. This is not done as an array (yet).
- // We think it's easier to set up from python if it is not an
- // array.
- struct com_ports com1, com2, com3, com4;
- // DMA, if it exists.
- struct lpt_ports lpt1, lpt2;
- /* flags for each device type. Unsigned int. */
- // low order bit ALWAYS means enable. Next bit means to enable
- // LPT is in transition, so we leave this here for the moment.
- // The winbond chips really stretched the way this works.
- // so many functions!
- unsigned int ide, floppy, lpt;
- unsigned int keyboard, cir, game;
- unsigned int gpio1, gpio2, gpio3;
- unsigned int acpi,hwmonitor;
-};
-
-These structures are, in turn, created and statically initialized by a
-config-tool-generated structure that defines all the superios. This file
-is called nsuperio.c, is created for each mainboard you build, only
-appears in the build directory, and looks like this:
-
-===
-extern struct superio_control superio_winbond_w83627hf_control;
-
-struct superio superio_winbond_w83627hf= {
- &superio_winbond_w83627hf_control,
- .com1={1}, .com2={1}, .floppy=1, .lpt=1, .keyboard=1, .hwmonitor=1};
-
-struct superio *all_superio[] = {&superio_winbond_w83627hf,
-};
-
-unsigned long nsuperio = 1;
-===
-
-This example shows a board with one superio (nsuperio). The superio
-consists of a winbond w83627hf, with com1, com2, floppy, lpt, keyboard,
-and hwmonitor enabled. Note that this structure also allows for
-over-riding the default superio base, although that capability is rarely
-used.
-
-The control structure is used to define how to access the superio for
-purposes of control. It looks like this:
-===
-struct superio_control {
- void (*pre_pci_init)(struct superio *s);
- void (*init)(struct superio *s);
- void (*finishup)(struct superio *s);
- unsigned int defaultport; /* the defaultport. Can be overridden
- * by commands in config
- */
- // This is the print name for debugging
- char *name;
-};
-===
-
-There are three methods for stages of hardwaremain. First is pre_pci_init
-(for chips like the acer southbridge that require you to enable some
-resources BEFORE pci scan); init, called during the 'middle' phase of
-hardwaremain; and finishup, called before the payload is loaded.
-
-This approach was inspired by and borrows heavily on the Plan 9 kernel
-configuration tools.
-
-The problem:
-
-When the first version of the superio structure came out it was much
-smaller. It has grown and in the limit this structure is the union of all
-possibly superio chips. Obviously, in the long term, this is not
-practical: we can not anticipate all possible superio chips for all time.
-
-The common PC BIOS solution to this type of problem is to continue with
-binary structures but add version numbers to them, so that all code that
-uses a given structure has to check the version number. Personally, I find
-this grotesque and would rather not work this way.
-
-Using textual strings for configuration is something I find far more
-attractive. Plan 9 has shown that this approach has no real limits and
-suffices for configuration tasks. The Linux kernel does more limited use
-of strings for configuration, but still depends on them. Strings are
-easier to read and work with than binary structures, and more important, a
-lot easier to deal with when things start going wrong.
-
-The proposed solution:
-
-What follows are three possible ideas for specifying superio resources and
-their settings.
-
-A common part of the new idea is to eliminate the common superio
-structure, due to the many variations in chips, and make it invisible
-outside a given superio source file -- the superio structure is now
-private to a given superio. Thus, sis/950/superio.c would contain its own
-superio structure definitions, and also might contain more than once
-instance of these structures (consider a board with 2 sis 950 chips).
-
-The control structure would change as follows:
-struct superio_control {
- int (*create)(struct superio *s);
- void (*pre_pci_init)(struct superio *s);
- void (*init)(struct superio *s);
- void (*finishup)(struct superio *s);
- unsigned int defaultport; /* the defaultport. Can be overridden
- * by commands in config
- */
- // This is the print name for debugging
- char *name;
-};
-
-I.e. we add a new function for creating the superio.
-
-Communication of superio settings from linuxbios to the superio would be
-via textual strings. The superio structure becomes this:
-
-struct superio {
- struct superio_control *super; // the ops for the device.
- unsigned int port; // if non-zero, overrides the default port
- struct configuration *config;
-};
-
-
-So now the question becomes, what is the configuration structure?
-There are several choices. The simplest, from my point of view, are
-keyword-value pairs:
-struct configuration {
- const char *keyword;
- const char *value;
-};
-
-These get filled in by the config tool as before. The linuxbios libary can
-then provide a generic parsing function for the superios to use.
-
-The remaining question is how should the superio command look in
-freebios2?
-
-superio sis/950 "com1=115200,8n1 lpt=1 com2=9600"
-
-or
-
-superio sis/950 "com1baud=115200 lpt=1 com1chars=8n1"
-
-or
-
-superio sis/950 ((com1 115200 8n1) (lpt 1))
-
-So, my questions:
-
-1. Does this new scheme look workable. If not, what needs to change?
-2. What should the 'struct configuration' be? does keyword/value work?
-3. what should the superio command look like?
-
-Comments welcome.
-
-I'd like to adopt this "RFC" approach for freebios2 as much as we can.
-There was a lot of give-and-take in the early days of linuxbios about
-structure and it proved useful. There's a lot that will start happening in
-freebios2 now, and we need to try to make sure it will work for everyone.
-
-Those of you who are doing mainboards, please look at freebios2 and see
-how it looks for you. There's a lot of good work that has been done (not
-by me so far, thanks Eric and Stefan), and more that needs to be done.
-Consider trying out romcc as an "assembly code killer". See how it fits
-together and if you can work with it or need changes. Bring comments back
-to this list.
-
-thanks
-
-ron
-
-\end{verbatim}
diff --git a/documentation/RFC/config.tex b/documentation/RFC/config.tex
deleted file mode 100644
index 6d6c433..0000000
--- a/documentation/RFC/config.tex
+++ /dev/null
@@ -1,291 +0,0 @@
- New config language for LinuxBIOS
-
-\begin{abstract}
-We describe the new configuration language for LinuxBIOS.
-\end{abstract}
-
-\section{Scope}
-This document defines the new configuration language for LinuxBIOS.
-
-\section{Goals}
-The goals of the new language are these:
-\begin{itemize}
-\item Simplified Makefiles so people can see what is set
-\item Move from the regular-expression-based language to something
-a bit more comprehensible and flexible
-\item make the specification easier for people to use and understand
-\item allow unique register-set-specifiers for each chip
-\item allow generic register-set-specifiers for each chip
-\item generate static initialization code, as needed, for the
-specifiers.
-\end{itemize}
-
-\section{Language}
-Here is the new language. It is very similar to the old one, differing
-in only a few respects. It borrows heavily from Greg Watson's suggestions.
-
-I am presenting it in a pseudo-BNF in the hopes it will be easier. Things
-in '' are keywords; things in ``'' are strings in the actual text.
-\begin{verbatim}
-#exprs are composed of factor or factor + factor etc.
-expr ::= factor ( ``+'' factor | ``-'' factor | )*
-#factors are term or term * term or term / term or ...
-factor ::= term ( ``*'' term | ``/'' term | ... )*
-#
-unary-op ::= ``!'' ID
-# term is a number, hexnumber, ID, unary-op, or a full-blown expression
-term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)''
-
-# Option command. Can be an expression or quote-string.
-# Options are used in the config tool itself (in expressions and 'if')
-# and are also passed to the C compiler when building linuxbios.
-# It is an error to have two option commands in a file.
-# It is an error to have an option command after the ID has been used
-# in an expression (i.e. 'set after used' is an error)
-option ::= 'option' ID '=' (``value'' | term)
-
-# Default command. The ID is set to this value if no option command
-# is scanned.
-# Multiple defaults for an ID will produce warning, but not errors.
-# It is OK to scan a default command after use of an ID.
-# Options always over-ride defaults.
-default ::= 'default' ID '=' (``value'' | term)
-
-# the mainboard, southbridge, northbridge commands
-# cause sourcing of Config.lb files as in the old config tool
-# as parts are sourced, a device tree is built. The structure
-# of the tree is determined by the structure of the components
-# as they are specified. To attach a superio to a southbridge, for
-# example, one would do this:
-# southbridge acer/5432
-# superio nsc/123
-# end
-# end
-# the tool generates static initializers for this hierarchy.
-
-# add C code to the current component (motherboard, etc. )
-# to initialise the component-INDEPENDENT structure members
-init ::= 'init' ``CODE''
-
-# add C code to the current component (motherboard, etc. )
-# to initialise the component-DEPENDENT structure members
-register ::= 'register' ``CODE''
-
-
-# mainboard command
-# statements in this block will set variables controlling the mainboard,
-# and will also place components (northbridge etc.) in the device tree
-# under this mainboard
-mainboard ::= 'mainboard' PATH (statements)* 'end'
-
-# standard linuxbios commands
-southbridge ::= 'southbridge' PATH (statemnts)* 'end'
-northbridge ::= 'northbridge' PATH (statemnts)* 'end'
-superio ::= 'superio PATH (statemnts)* 'end'
-cpu ::= 'cpu' PATH (statemnts)* 'end'
-arch ::= 'arch' PATH (statemnts)* 'end'
-
-# files for building linuxbios
-# include a file in crt0.S
-mainboardinit ::= 'mainboardinit' PATH
-
-# object file
-object ::= 'object' PATH
-# driver objects are just built into the image in a different way
-driver ::= 'driver' PATH
-
-# Use the Config.lb file in the PATH
-dir ::= 'dir' PATH
-
-# add a file to the set of ldscript files
-ldscript ::= 'ldscript' PATH
-
-# dependencies or actions for the makerule command
-dep ::= 'dep' ``dependency-string''
-act ::= 'act' ``actions''
-depsacts ::= (dep | act)*
-# set up a makerule
-#
-makerule ::= 'makerule' PATH depsacts
-
-#defines for use in makefiles only
-# note usable in the config tool, not passed to cc
-makedefine ::= 'makedefine' ``RAWTEXT''
-
-# add an action to an existing make rule
-addaction ::= 'addaction' PATH ``ACTION''
-
-# statements
-statement ::=
- option
- | default
- | cpu
- | arch
- | northbridge
- | southbridge
- | superio
- | object
- | driver
- | mainboardinit
- | makerule
- | makedefine
- | addaction
- | init
- | register
- | iif
- | dir
- | ldscript
-
-statements ::= (statement)*
-
-# target directory specification
-target ::= 'target' PATH
-
-# and the whole thing
-board ::= target (option)* mainboard
-
-\end{verbatim}
-
-\subsubsection{Command definitions}
-\subsubsubsection{option}
-\subsubsubsection{default}
-\subsubsubsection{cpu}
-\subsubsubsection{arch}
-\subsubsubsection{northbridge}
-\subsubsubsection{southbridge}
-\subsubsubsection{superio}
-\subsubsubsection{object}
-\subsubsubsection{driver}
-\subsubsubsection{mainboardinit}
-\subsubsubsection{makerule}
-\subsubsubsection{makedefine}
-\subsubsubsection{addaction}
-\subsubsubsection{init}
-\subsubsubsection{register}
-\subsubsubsection{iif}
-\subsubsubsection{dir}
-\subsubsubsection{ldscript}
-
-
-A sample file:
-
-\begin{verbatim}
-target x
-
-# over-ride the default rom size in the mainboard file
-option CONFIG_ROM_SIZE=1024*1024
-mainboard amd/solo
-end
-
-\end{verbatim}
-
-Sample mainboard file
-\begin{verbatim}
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-arch i386 end
-cpu k8 end
-#
-option CONFIG_DEBUG=1
-default CONFIG_USE_FALLBACK_IMAGE=1
-option A=(1+2)
-option B=0xa
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-ldscript cpu/i386/entry16.lds
-ldscript cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if CONFIG_USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript cpu/i386/reset16.lds
-else
- mainboardinit cpu/i386/reset32.inc
- ldscript cpu/i386/reset32.lds
-end
-.
-.
-.
-if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
-#
-###
-### Romcc output
-###
-#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E"
-#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
-#mainboardinit ./failover.inc
-makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E"
-makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
-mainboardinit ./auto.inc
-#
-###
-### Include the secondary Configuration files
-###
-northbridge amd/amdk8
-end
-southbridge amd/amd8111
-end
-#mainboardinit arch/i386/smp/secondary.inc
-superio nsc/pc87360
- register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
-end
-dir /pc80
-##dir /src/superio/winbond/w83627hf
-cpu p5 end
-cpu p6 end
-cpu k7 end
-cpu k8 end
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-driver mainboard.o
-object static_devices.o
-if CONFIG_HAVE_MP_TABLE object mptable.o end
-if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
-### Location of the DIMM EEPROMS on the SMBUS
-### This is fixed into a narrow range by the DIMM package standard.
-###
-option SMBUS_MEM_DEVICE_START=(0xa << 3)
-option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
-option SMBUS_MEM_DEVICE_INC=1
-#
-### The linuxBIOS bootloader.
-###
-option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
-option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-#
-
-\end{verbatim}
-
-I've found the output of the new tool to be easier to
-handle. Makefile.settings looks like this, for example:
-\begin{verbatim}
-TOP:=/home/rminnich/src/yapps2/freebios2
-TARGET_DIR:=x
-export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
-export CONFIG_ARCH:=i386
-export CONFIG_RAMBASE:=0x4000
-export CONFIG_ROM_IMAGE_SIZE:=65535
-export CONFIG_PAYLOAD_SIZE:=131073
-export CONFIG_MAX_CPUS:=1
-export CONFIG_HEAP_SIZE:=8192
-export CONFIG_STACK_SIZE:=8192
-export CONFIG_MEMORY_HOLE:=0
-export COREBOOT_VERSION:=1.1.0
-export CC:=$(CONFIG_CROSS_COMPILE)gcc
-
-\end{verbatim}
-
-In other words, instead of expressions, we see the values. It's easier to
-deal with.
-
diff --git a/documentation/abi-data-consumption.txt b/documentation/abi-data-consumption.txt
deleted file mode 100644
index 81442e7..0000000
--- a/documentation/abi-data-consumption.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-This text describes the ABI coreboot presents to downstream users. Such
-users are payloads and/or operating systems. Therefore, this text serves
-at what can be relied on for downstream consumption. Anything not explicitly
-listed as consumable is subject to change without notice.
-
-Background and Usage
-
-coreboot passes information to downstream users using coreboot tables. These
-table definitions can be found in src/include/boot/coreboot_tables.h and
-payloads/libpayload/include/coreboot_tables.h respectively within coreboot
-and libpayload. One of the most vital and important pieces of information
-found within these tables is the memory map of the system indicating
-available and reserved memory.
-
-In 2009 cbmem was added to coreboot. The "CBMEM high table memory manager"
-serves a way for coreboot to bookkeep its own internal data. While some
-of this data may be exposed through the coreboot tables the data structures
-used to manage the data within the cbmem area is subject to change.
-
-Provided the above, if one needs a piece of data exposed to the OS
-or payload it should reside within the coreboot tables. If it isn't there
-then a code change will be required to add it to the coreboot tables.
diff --git a/documentation/beginverbatim.tex b/documentation/beginverbatim.tex
deleted file mode 100644
index 453714c..0000000
--- a/documentation/beginverbatim.tex
+++ /dev/null
@@ -1 +0,0 @@
-\begin{verbatim}
diff --git a/documentation/cbfs.txt b/documentation/cbfs.txt
deleted file mode 100644
index 7ecc901..0000000
--- a/documentation/cbfs.txt
+++ /dev/null
@@ -1,421 +0,0 @@
-
-Received: from www.crouse-house.com ([199.45.160.146]
- for coreboot(a)coreboot.org; Fri, 19 Dec 2008 23:11:59 +0100
-From: Jordan Crouse <jordan(a)cosmicpenguin.net>
-
-
-Greetings. I apologize for the incompleteness of what I am about to
-discuss. I was planning on working on it leisurely, but my employment
-circumstances changed and I've been trying to get it completed in a
-hurry before I had to leave it behind.
-
-I've been thinking a lot about LAR lately, and ways to make it more
-extensible and robust. Marc and I have been trading ideas back and
-forth for a number of months, and over time a clear idea of what I
-wanted to do started to take shape.
-
-My goal was to add small things to LAR while retaining the overall
-scheme. Over time, the scheme evolved slightly, but I think you'll find
-that it remains true to the original idea. Below is the beginnings of
-an architecture document - I did it in text form, but if met with
-aclaim, it should be wikified. This presents what I call CBFS - the
-next generation LAR for next generation Coreboot. Its easier to
-describe what it is by describing what changed:
-
-A header has been added somewhere in the bootblock similar to Carl
-Daniel's scheme. In addition to the coreboot information, the header
-reports the size of the ROM, the alignment of the blocks, and the offset
-of the first component in the CBFS. The master header provides all
-the information LAR needs plus the magic number information flashrom needs.
-
-Each "file" (or component, as I style them) now has a type associated
-with it. The type is used by coreboot to identify the type of file that
-it is loading, and it can also be used by payloads to group items in the
-CBFS by type (i.e - bayou can ask for all components that are payloads).
-
-The header on each "file" (or component, as I like to style them) has
-been simplified - We now only store the length, the type, the checksum,
-and the offset to the data. The name scheme remains the same. The
-addtional information, which is component specific, has been moved to
-the component itself (see below).
-
-The components are arranged in the ROM aligned along the specified
-alignment from the master header - this is to facilitate partial re-write.
-
-Other then that, the LAR ideas remain pretty much the same.
-
-The plan for moving the metadata to the components is to allow many
-different kinds of components, not all of which are groked by coreboot.
- However, there are three essential component types that are groked by
-coreboot, and they are defined:
-
-stage - the stage is being parsed from the original ELF, and stored in
-the ROM as a single blob of binary data. The load address, start
-address, compression type and length are stored in the component sub-header.
-
-payload - this is essentially SELF in different clothing - same idea as
-SELF, with the sub-header as above.
-
-optionrom - This is in flux - right now, the optionrom is stored
-unadulterated and uncompressed, but that is likely to be changed.
-
-Following this email are two replies containing the v3 code and a new
-ROM tool to implement this respectively. I told you that I was trying
-to get this out before I disappear, and I'm not kidding - the code is
-compile tested and not run-tested. I hope that somebody will embrace
-this code and take it the rest of the way, otherwise it will die a
-pretty short death.
-
-I realize that this will start an awesome flamewar, and I'm looking
-forward to it. Thanks for listening to me over the years - and good
-luck with coreboot. When you all make a million dollars, send me a few
-bucks, will you?
-
-Jordan
-
-Coreboot CBFS Specification
-Jordan Crouse <jordan(a)cosmicpenguin.net>
-
-= Introduction =
-
-This document describes the coreboot CBFS specification (from here
-referred to as CBFS). CBFS is a scheme for managing independent chunks
-of data in a system ROM. Though not a true filesystem, the style and
-concepts are similar.
-
-
-= Architecture =
-
-The CBFS architecture looks like the following:
-
-/---------------\ <-- Start of ROM
-| /-----------\ | --|
-| | Header | | |
-| |-----------| | |
-| | Name | | |-- Component
-| |-----------| | |
-| |Data | | |
-| |.. | | |
-| \-----------/ | --|
-| |
-| /-----------\ |
-| | Header | |
-| |-----------| |
-| | Name | |
-| |-----------| |
-| |Data | |
-| |.. | |
-| \-----------/ |
-| |
-| ... |
-| /-----------\ |
-| | | |
-| | Bootblock | |
-| | --------- | |
-| | Reset | | <- 0xFFFFFFF0
-| \-----------/ |
-\---------------/
-
-
-The CBFS architecture consists of a binary associated with a physical
-ROM disk referred hereafter as the ROM. A number of independent of
-components, each with a header prepended on to data are located within
-the ROM. The components are nominally arranged sequentially, though they
-are aligned along a pre-defined boundary.
-
-The bootblock occupies the last 20k of the ROM. Within
-the bootblock is a master header containing information about the ROM
-including the size, alignment of the components, and the offset of the
-start of the first CBFS component within the ROM.
-
-= Master Header =
-
-The master header contains essential information about the ROM that is
-used by both the CBFS implementation within coreboot at runtime as well
-as host based utilities to create and manage the ROM. The master header
-will be located somewhere within the bootblock (last 20k of the ROM). A
-pointer to the location of the header will be located at offset
--4 from the end of the ROM. This translates to address 0xFFFFFFFC on a
-normal x86 system. The pointer will be to physical memory somewhere
-between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot
-to locate the header at run time. Build time utilities will
-need to read the pointer and do the appropriate math to locate the header.
-
-The following is the structure of the master header:
-
-struct cbfs_header {
- u32 magic;
- u32 version;
- u32 romsize;
- u32 bootblocksize;
- u32 align;
- u32 offset;
- u32 architecture;
- u32 pad[1];
-} __attribute__((packed));
-
-The meaning of each member is as follows:
-
-'magic' is a 32 bit number that identifies the ROM as a CBFS type. The
-magic
-number is 0x4F524243, which is 'ORBC' in ASCII.
-
-'version' is a version number for CBFS header. cbfs_header structure may be
-different if version is not matched.
-
-'romsize' is the size of the ROM in bytes. Coreboot will subtract 'size' from
-0xFFFFFFFF to locate the beginning of the ROM in memory.
-
-'bootblocksize' is the size of bootblock reserved in firmware image.
-
-'align' is the number of bytes that each component is aligned to within the
-ROM. This is used to make sure that each component is aligned correctly
-with
-regards to the erase block sizes on the ROM - allowing one to replace a
-component at runtime without disturbing the others.
-
-'offset' is the offset of the the first CBFS component (from the start of
-the ROM). This is to allow for arbitrary space to be left at the beginning
-of the ROM for things like embedded controller firmware.
-
-'architecture' describes which architecture (x86, arm, ...) this CBFS is created
-for.
-
-= Bootblock =
-The bootblock is a mandatory component in the ROM. It is located in the
-last
-20k of the ROM space, and contains, among other things, the location of the
-master header and the entry point for the loader firmware. The bootblock
-does not have a component header attached to it.
-
-= Components =
-
-CBFS components are placed in the ROM starting at 'offset' specified in
-the master header and ending at the bootblock. Thus the total size
-available
-for components in the ROM is (ROM size - 20k - 'offset'). Each CBFS
-component is to be aligned according to the 'align' value in the header.
-Thus, if a component of size 1052 is located at offset 0 with an 'align'
-value
-of 1024, the next component will be located at offset 2048.
-
-Each CBFS component will be indexed with a unique ASCII string name of
-unlimited size.
-
-Each CBFS component starts with a header:
-
-struct cbfs_file {
- char magic[8];
- unsigned int len;
- unsigned int type;
- unsigned int checksum;
- unsigned int offset;
-};
-
-'magic' is a magic value used to identify the header. During runtime,
-coreboot will scan the ROM looking for this value. The default magic is
-the string 'LARCHIVE'.
-
-'len' is the length of the data, not including the size of the header and
-the size of the name.
-
-'type' is a 32 bit number indicating the type of data that is attached.
-The data type is used in a number of ways, as detailed in the section
-below.
-
-'checksum' is a 32bit checksum of the entire component, including the
-header and name.
-
-'offset' is the start of the component data, based off the start of the
-header.
-The difference between the size of the header and offset is the size of the
-component name.
-
-Immediately following the header will be the name of the component,
-which will
-null terminated and 16 byte aligned. The following picture shows the
-structure of the header:
-
-/--------\ <- start
-| Header |
-|--------| <- sizeof(struct cbfs_file)
-| Name |
-|--------| <- 'offset'
-| Data |
-| ... |
-\--------/ <- start + 'offset' + 'len'
-
-== Searching Alogrithm ==
-
-To locate a specific component in the ROM, one starts at the 'offset'
-specified in the CBFS master header. For this example, the offset will
-be 0.
-
- From that offset, the code should search for the magic string on the
-component, jumping 'align' bytes each time. So, assuming that 'align' is
-16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc.
-If the offset ever exceeds the allowable range for CBFS components, then no
-component was found.
-
-Upon recognizing a component, the software then has to search for the
-specific name of the component. This is accomplished by comparing the
-desired name with the string on the component located at
-offset + sizeof(struct cbfs_file). If the string matches, then the
-component
-has been located, otherwise the software should add 'offset' + 'len' to
-the offset and resume the search for the magic value.
-
-== Data Types ==
-
-The 'type' member of struct cbfs_file is used to identify the content
-of the component data, and is used by coreboot and other
-run-time entities to make decisions about how to handle the data.
-
-There are three component types that are essential to coreboot, and so
-are defined here.
-
-=== Stages ===
-
-Stages are code loaded by coreboot during the boot process. They are
-essential to a successful boot. Stages are comprised of a single blob
-of binary data that is to be loaded into a particular location in memory
-and executed. The uncompressed header contains information about how
-large the data is, and where it should be placed, and what additional memory
-needs to be cleared.
-
-Stages are assigned a component value of 0x10. When coreboot sees this
-component type, it knows that it should pass the data to a sub-function
-that will process the stage.
-
-The following is the format of a stage component:
-
-/--------\
-| Header |
-|--------|
-| Binary |
-| .. |
-\--------/
-
-The header is defined as:
-
-struct cbfs_stage {
- unsigned int compression;
- unsigned long long entry;
- unsigned long long load;
- unsigned int len;
- unsigned int memlen;
-};
-
-'compression' is an integer defining how the data is compressed. There
-are three compression types defined by this version of the standard:
-none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional
-types may be added assuming that coreboot understands how to handle the scheme.
-
-'entry' is a 64 bit value indicating the location where the program
-counter should jump following the loading of the stage. This should be
-an absolute physical memory address.
-
-'load' is a 64 bit value indicating where the subsequent data should be
-loaded. This should be an absolute physical memory address.
-
-'len' is the length of the compressed data in the component.
-
-'memlen' is the amount of memory that will be used by the component when
-it is loaded.
-
-The component data will start immediately following the header.
-
-When coreboot loads a stage, it will first zero the memory from 'load' to
-'memlen'. It will then decompress the component data according to the
-specified scheme and place it in memory starting at 'load'. Following that,
-it will jump execution to the address specified by 'entry'.
-Some components are designed to execute directly from the ROM - coreboot
-knows which components must do that and will act accordingly.
-
-=== Payloads ===
-
-Payloads are loaded by coreboot following the boot process.
-
-Stages are assigned a component value of 0x20. When coreboot sees this
-component type, it knows that it should pass the data to a sub-function
-that will process the payload. Furthermore, other run time
-applications such as 'bayou' may easily index all available payloads
-on the system by searching for the payload type.
-
-
-The following is the format of a stage component:
-
-/-----------\
-| Header |
-| Segment 1 |
-| Segment 2 |
-| ... |
-|-----------|
-| Binary |
-| .. |
-\-----------/
-
-The header is as follows:
-
-struct cbfs_payload {
- struct cbfs_payload_segment segments;
-}
-
-The header contains a number of segments corresponding to the segments
-that need to be loaded for the payload.
-
-The following is the structure of each segment header:
-
-struct cbfs_payload_segment {
- unsigned int type;
- unsigned int compression;
- unsigned int offset;
- unsigned long long load_addr;
- unsigned int len;
- unsigned int mem_len;
-};
-
-'type' is the type of segment, one of the following:
-
-PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code
-PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data
-PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment
- should be zeroed
-PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for
- the payload
-PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point
- for the payload
-
-'compression' is the compression scheme for the segment. Each segment can
-be independently compressed. There are three compression types defined by
-this version of the standard: none (0x0), lzma (0x1), and nrv2b
-(0x02, deprecated), though additional types may be added assuming that
-coreboot understands how to handle the scheme.
-
-'offset' is the address of the data within the component, starting from
-the component header.
-
-'load_addr' is a 64 bit value indicating where the segment should be placed
-in memory.
-
-'len' is a 32 bit value indicating the size of the segment within the
-component.
-
-'mem_len' is the size of the data when it is placed into memory.
-
-The data will located immediately following the last segment.
-
-=== Option ROMS ===
-
-The third specified component type will be Option ROMs. Option ROMS will
-have component type '0x30'. They will have no additional header, the
-uncompressed binary data will be located in the data portion of the
-component.
-
-=== NULL ===
-
-There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is
-the "don't care" component type. This can be used when the component
-type is not necessary (such as when the name of the component is unique.
-i.e. option_table). It is recommended that all components be assigned a
-unique type, but NULL can be used when the type does not matter.
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diff --git a/documentation/coreboot_logo.png b/documentation/coreboot_logo.png
deleted file mode 100644
index dde1aa6..0000000
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diff --git a/documentation/endverbatim.tex b/documentation/endverbatim.tex
deleted file mode 100644
index f832f3f..0000000
--- a/documentation/endverbatim.tex
+++ /dev/null
@@ -1 +0,0 @@
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diff --git a/documentation/gcov.txt b/documentation/gcov.txt
deleted file mode 100644
index 896ec93..0000000
--- a/documentation/gcov.txt
+++ /dev/null
@@ -1,227 +0,0 @@
-This patch contains our local modifications for gcov-io.h and libgcov.c.
-The file gcov-iov.h is taken from a gcc build (produced at compile
-time). The file gcov-io.c is unchanged.
-
---- gcc-4.7.2/gcc/gcov-io.h 2011-12-04 10:27:19.000000000 -0800
-+++ coreboot/src/lib/gcov-io.h 2013-01-12 16:45:57.000000000 -0800
-@@ -163,6 +163,24 @@
- #ifndef GCC_GCOV_IO_H
- #define GCC_GCOV_IO_H
-
-+#ifdef __COREBOOT__
-+#define GCOV_LINKAGE /* nothing */
-+/* We need the definitions for
-+ BITS_PER_UNIT and
-+ LONG_LONG_TYPE_SIZE
-+ They are defined in gcc/defaults.h and gcc/config/<arch_depend_files>
-+ (like, gcc/config/i386/i386.h). And it can be overridden by setting
-+ in build scripts. Here I hardcoded the value for x86. */
-+#define BITS_PER_UNIT 8
-+#define LONG_LONG_TYPE_SIZE 64
-+
-+/* There are many gcc_assertions. Set the vaule to 1 if we want a warning
-+ message if the assertion fails. */
-+#ifndef ENABLE_ASSERT_CHECKING
-+#define ENABLE_ASSERT_CHECKING 1
-+#endif
-+#endif /* __COREBOOT__ */
-+
- #if IN_LIBGCOV
- /* About the target */
-
-@@ -232,7 +250,9 @@
- is not also used in a DSO. */
- #if IN_LIBGCOV
-
-+#ifndef __COREBOOT__
- #include "tconfig.h"
-+#endif /* __COREBOOT__ */
-
- #define gcov_var __gcov_var
- #define gcov_open __gcov_open
-@@ -455,8 +475,10 @@
- /* Register a new object file module. */
- extern void __gcov_init (struct gcov_info *) ATTRIBUTE_HIDDEN;
-
-+#ifndef __COREBOOT__
- /* Called before fork, to avoid double counting. */
- extern void __gcov_flush (void) ATTRIBUTE_HIDDEN;
-+#endif
-
- /* The merge function that just sums the counters. */
- extern void __gcov_merge_add (gcov_type *, unsigned) ATTRIBUTE_HIDDEN;
---- gcc-4.7.2/libgcc/libgcov.c 2012-01-11 10:50:21.000000000 -0800
-+++ coreboot/src/lib/libgcov.c 2013-01-16 09:45:11.000000000 -0800
-@@ -25,12 +25,41 @@
- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
- <http://www.gnu.org/licenses/>. */
-
-+#define __COREBOOT__
-+#ifdef __COREBOOT__
-+#include <stdlib.h>
-+#include <string.h>
-+#include <console/console.h>
-+#include <assert.h>
-+typedef s32 pid_t;
-+#define gcc_assert(x) ASSERT(x)
-+#define fprintf(file, x...) printk(BIOS_ERR, x)
-+#define alloca(size) __builtin_alloca (size)
-+#include "gcov-glue.c"
-+
-+/* Define MACROs to be used by coreboot compilation. */
-+# define L_gcov
-+# define L_gcov_interval_profiler
-+# define L_gcov_pow2_profiler
-+# define L_gcov_one_value_profiler
-+# define L_gcov_indirect_call_profiler
-+# define L_gcov_average_profiler
-+# define L_gcov_ior_profiler
-+
-+# define HAVE_CC_TLS 0
-+# define __GCOV_KERNEL__
-+
-+# define IN_LIBGCOV 1
-+# define IN_GCOV 0
-+#else /* __COREBOOT__ */
- #include "tconfig.h"
- #include "tsystem.h"
- #include "coretypes.h"
- #include "tm.h"
- #include "libgcc_tm.h"
-+#endif /* __COREBOOT__ */
-
-+#ifndef __COREBOOT__
- #if defined(inhibit_libc)
- #define IN_LIBGCOV (-1)
- #else
-@@ -41,6 +70,7 @@
- #define GCOV_LINKAGE /* nothing */
- #endif
- #endif
-+#endif /* __COREBOOT__ */
- #include "gcov-io.h"
-
- #if defined(inhibit_libc)
-@@ -68,12 +98,17 @@
-
- #else
-
-+#ifndef __COREBOOT__
- #include <string.h>
- #if GCOV_LOCKED
- #include <fcntl.h>
- #include <errno.h>
- #include <sys/stat.h>
- #endif
-+#else
-+void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)),
-+ unsigned n_counters __attribute__ ((unused))) {}
-+#endif /* __COREBOOT__ */
-
- #ifdef L_gcov
- #include "gcov-io.c"
-@@ -99,6 +134,10 @@
- static int
- create_file_directory (char *filename)
- {
-+#ifdef __COREBOOT__
-+ (void) filename;
-+ return 0;
-+#else
- #if !defined(TARGET_POSIX_IO) && !defined(_WIN32)
- (void) filename;
- return -1;
-@@ -137,6 +176,7 @@
- };
- return 0;
- #endif
-+#endif
- }
-
- static struct gcov_fn_buffer *
-@@ -279,7 +319,7 @@
- struct gcov_ctr_summary *cs_ptr;
- const struct gcov_ctr_info *ci_ptr;
- unsigned t_ix;
-- int f_ix;
-+ int f_ix = 0;
- gcov_unsigned_t c_num;
- const char *gcov_prefix;
- int gcov_prefix_strip = 0;
-@@ -329,6 +369,7 @@
- }
- }
-
-+#ifndef __COREBOOT__
- {
- /* Check if the level of dirs to strip off specified. */
- char *tmp = getenv("GCOV_PREFIX_STRIP");
-@@ -352,6 +393,7 @@
- prefix_length--;
- }
- else
-+#endif
- prefix_length = 0;
-
- /* If no prefix was specified and a prefix stip, then we assume
-@@ -696,8 +738,10 @@
- if (filename_length > gcov_max_filename)
- gcov_max_filename = filename_length;
-
-+#ifndef __COREBOOT__
- if (!gcov_list)
- atexit (gcov_exit);
-+#endif
-
- info->next = gcov_list;
- gcov_list = info;
-@@ -767,14 +811,15 @@
-
- #ifdef L_gcov_merge_single
- /* The profile merging function for choosing the most common value.
-- It is given an array COUNTERS of N_COUNTERS old counters and it
-- reads the same number of counters from the gcov file. The counters
-- are split into 3-tuples where the members of the tuple have
-- meanings:
--
-- -- the stored candidate on the most common value of the measured entity
-- -- counter
-- -- total number of evaluations of the value */
-+ * It is given an array COUNTERS of N_COUNTERS old counters and it
-+ * reads the same number of counters from the gcov file. The counters
-+ * are split into 3-tuples where the members of the tuple have
-+ * meanings:
-+ *
-+ * -- the stored candidate on the most common value of the measured entity
-+ * -- counter
-+ * -- total number of evaluations of the value
-+ */
- void
- __gcov_merge_single (gcov_type *counters, unsigned n_counters)
- {
-@@ -805,15 +850,16 @@
-
- #ifdef L_gcov_merge_delta
- /* The profile merging function for choosing the most common
-- difference between two consecutive evaluations of the value. It is
-- given an array COUNTERS of N_COUNTERS old counters and it reads the
-- same number of counters from the gcov file. The counters are split
-- into 4-tuples where the members of the tuple have meanings:
--
-- -- the last value of the measured entity
-- -- the stored candidate on the most common difference
-- -- counter
-- -- total number of evaluations of the value */
-+ * difference between two consecutive evaluations of the value. It is
-+ * given an array COUNTERS of N_COUNTERS old counters and it reads the
-+ * same number of counters from the gcov file. The counters are split
-+ * into 4-tuples where the members of the tuple have meanings:
-+ *
-+ * -- the last value of the measured entity
-+ * -- the stored candidate on the most common difference
-+ * -- counter
-+ * -- total number of evaluations of the value
-+ */
- void
- __gcov_merge_delta (gcov_type *counters, unsigned n_counters)
- {
diff --git a/documentation/hypertransport.svg b/documentation/hypertransport.svg
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diff --git a/documentation/submodules.txt b/documentation/submodules.txt
deleted file mode 100644
index 631e351..0000000
--- a/documentation/submodules.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Use of git submodules in coreboot
-=================================
-coreboot uses git submodules to keep certain parts of the tree separate,
-with two major use cases:
-
-First, we use a vendor tool by NVIDIA for systems based on their SoC
-and since they publish it through git, we can just import it into our
-tree using submodules.
-
-Second, lots of boards these days require binaries and we want to keep
-them separate from coreboot proper to clearly delineate shiny Open Source
-from ugly blobs.
-Since we don't want to impose blobs on users who really don't need them,
-that repository is only downloaded and checked out on explicit request.
-
-Handling submodules
--------------------
-For the most part, submodules should be automatically checked out on the
-first execution of the coreboot Makefile.
-
-To manually fetch all repositories (eg. when you want to prepare the tree
-for archiving, or to use it without network access), run
-
- $ git submodule update --init --checkout
-
-This also checks out the binaries below `3rdparty/`
-
-Mirroring coreboot
-------------------
-When running a coreboot mirror to checkout from, for full operation, you
-should also mirror the blobs and nvidia-cbootimage repository, and place
-them in the same directory as the coreboot repository mirror.
-
-That is, when residing in coreboot's repository, `cd ../blobs.git`
-should move you to the blobs repository.
-
-With that, no matter what the URL of your coreboot repository is, the
-git client (of a sufficiently new version) is able to pick up the other
-repositories transparently.
-
-Minimum requirements
---------------------
-git needs to be able to handle relative paths to submodule repositories,
-and it needs to know about non-automatic submodules.
-
-For these features, we require git version 1.7.6.1 or newer.
1
0
Patch merged into coreboot/master: 29ed46c 3rdparty/vboot: Add vboot
by gerrit＠coreboot.org 05 May '15
by gerrit＠coreboot.org 05 May '15
05 May '15
the following patch was just integrated into master:
commit 29ed46caccd5cea8401c5d133895fa3a9d6f5030
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue May 5 20:41:04 2015 +0200
3rdparty/vboot: Add vboot
This allows providing a verified boot mechanism in the
default distribution, as well as reusing vboot code like
its crypto primitives for reasonably secure checksums over
CBFS files.
Change-Id: I729b249776b2bf7aa4b2f69bb18ec655b9b08d90
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/10107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/10107 for details.
-gerrit
1
0