Patch set updated for coreboot: 410ca72 northbridge/intel/pineview: Add minimal Pineview northbridge.
Damien Zammit (damien@zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10073
-gerrit
commit 410ca722d0a3b9c9828c28bf7ccf083687b61043 Author: Damien Zammit damien@zamaudio.com Date: Sun May 3 21:34:38 2015 +1000
northbridge/intel/pineview: Add minimal Pineview northbridge.
Based on i945. Tested on Intel D510MO mainboard.
Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit damien@zamaudio.com --- src/northbridge/intel/pineview/Kconfig | 73 +++++++++++++++ src/northbridge/intel/pineview/Makefile.inc | 31 ++++++ src/northbridge/intel/pineview/acpi.c | 76 +++++++++++++++ src/northbridge/intel/pineview/bootblock.c | 22 +++++ src/northbridge/intel/pineview/pineview.h | 140 ++++++++++++++++++++++++++++ src/northbridge/intel/pineview/ram_calc.c | 62 ++++++++++++ src/northbridge/intel/pineview/udelay.c | 82 ++++++++++++++++ 7 files changed, 486 insertions(+)
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig new file mode 100644 index 0000000..4d6dcc2 --- /dev/null +++ b/src/northbridge/intel/pineview/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_PINEVIEW + bool + +if NORTHBRIDGE_INTEL_PINEVIEW + +config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + #select HAVE_DEBUG_RAM_SETUP + select LAPIC_MONOTONIC_TIMER + select VGA + select PER_DEVICE_ACPI_TABLES + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/pineview/bootblock.c" + +config VGA_BIOS_ID + string + default "8086,a001" + +config CHANNEL_XOR_RANDOMIZATION + bool + default n + +config OVERRIDE_CLOCK_DISABLE + bool + default n + help + Usually system firmware turns off system memory clock + signals to unused SO-DIMM slots to reduce EMI and power + consumption. + However, some boards do not like unused clock signals to + be disabled. + +config MAXIMUM_SUPPORTED_FREQUENCY + int + default 0 + help + If non-zero, this designates the maximum DDR frequency + the board supports, despite what the chipset should be + capable of. + +config CHECK_SLFRCS_ON_RESUME + def_bool n + help + On some boards it may be neccessary to hard reset early + during resume from S3 if the SLFRCS register indicates that + a memory channel is not guaranteed to be in self-refresh. + On other boards the check always creates a false positive, + effectively making it impossible to resume. + +endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc new file mode 100644 index 0000000..657da33 --- /dev/null +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -0,0 +1,31 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += ram_calc.c +#ramstage-y += northbridge.c +#ramstage-y += gma.c +ramstage-y += acpi.c + +romstage-y += ram_calc.c +#romstage-y += raminit.c +#romstage-y += early_init.c +#romstage-y += errata.c +#romstage-y += debug.c + +smm-y += udelay.c diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c new file mode 100644 index 0000000..ae5fc37 --- /dev/null +++ b/src/northbridge/intel/pineview/acpi.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cbmem.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> +#include "pineview.h" + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 pciexbar_reg; + int max_buses; + + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + if (!dev) + return current; + + pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & (1 << 0))) + return current; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + max_buses = 256; + break; + case 1: // 128M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + max_buses = 128; + break; + case 2: // 64M + pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + max_buses = 64; + break; + default: // RSVD + return current; + } + + if (!pciexbar) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, max_buses - 1); + + return current; +} diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c new file mode 100644 index 0000000..d524f83 --- /dev/null +++ b/src/northbridge/intel/pineview/bootblock.c @@ -0,0 +1,22 @@ +#include <arch/io.h> +#include "pineview.h" + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h new file mode 100644 index 0000000..ff7129d --- /dev/null +++ b/src/northbridge/intel/pineview/pineview.h @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) Damien Zammit damien@zamaudio.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H +#define NORTHBRIDGE_INTEL_PINEVIEW_H + +/* Northbridge BARs */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#include "../../../southbridge/intel/i82801gx/i82801gx.h" + +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ + +/* Display defines for the interrupt 15h handler */ +#define INT15_5F35_CL_DISPLAY_DEFAULT 0 +#define INT15_5F35_CL_DISPLAY_CRT (1 << 0) +#define INT15_5F35_CL_DISPLAY_TV (1 << 1) +#define INT15_5F35_CL_DISPLAY_EFP (1 << 2) +#define INT15_5F35_CL_DISPLAY_LCD (1 << 3) +#define INT15_5F35_CL_DISPLAY_CRT2 (1 << 4) +#define INT15_5F35_CL_DISPLAY_TV2 (1 << 5) +#define INT15_5F35_CL_DISPLAY_EFP2 (1 << 6) +#define INT15_5F35_CL_DISPLAY_LCD2 (1 << 7) + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + +#define GGC 0x52 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) +#define DEVEN_D2F0 (1 << 3) +#define DEVEN_D2F1 (1 << 4) + +#ifndef BOARD_DEVEN +#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) +#endif /* BOARD_DEVEN */ + +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 + +#define LAC 0x97 /* Legacy Access Control */ +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAM 0x9e /* Extended System Management RAM Control */ + +#define TOM 0xa0 +#define TOUUD 0xa2 +#define GBSM 0xa4 +#define BGSM 0xa8 +#define TSEGMB 0xac +#define TOLUD 0xb0 /* Top of Low Used Memory */ +#define ERRSTS 0xc8 +#define ERRCMD 0xca +#define SMICMD 0xcc +#define SCICMD 0xce +#define CGDIS 0xd8 +#define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0 0xe0 +#define DEV0T 0xf0 +#define MSLCK 0xf4 +#define MID0 0xf8 +#define DEBUP0 0xfc + +/* Device 0:1.0 PCI configuration space (PCI Express) */ + +#define BCTRL1 0x3e /* 16bit */ +#define PEGSTS 0x214 /* 32bit */ + + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define GMADR 0x18 +#define GTTADR 0x1c +#define BSM 0x5c +#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ + + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +/* + * EPBAR - Egress Port Root Complex Register Block + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +/* provided by mainboard code */ +void setup_ich7_gpios(void); + +#endif /* __ACPI__ */ + +#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */ diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c new file mode 100644 index 0000000..6f19c1e --- /dev/null +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "pineview.h" + +static unsigned long find_ramtop(void) +{ + u32 tom; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), BSM); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x100000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x200000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x800000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long) tom; +} + +void *cbmem_top(void) +{ + return (void *) find_ramtop(); +} diff --git a/src/northbridge/intel/pineview/udelay.c b/src/northbridge/intel/pineview/udelay.c new file mode 100644 index 0000000..60ca9fb --- /dev/null +++ b/src/northbridge/intel/pineview/udelay.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> + +/** + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; /* ticks per us */ + + msr = rdmsr(MSR_FSB_FREQ); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + + multiply_to_tsc(&tscd, us, d); + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}
-
Damien Zammit