coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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1299 discussions

New patch to review for coreboot: 277eb3e southbridge/i82801gx: Add NM10 southbridge LPC id, treat as ICH7
by Damien Zammit 03 May '15

03 May '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10072 -gerrit commit 277eb3e2b0f6e6e3508c4b9ed513298a0db2d402 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun May 3 18:38:18 2015 +1000 southbridge/i82801gx: Add NM10 southbridge LPC id, treat as ICH7 Change-Id: Iffa30d9c9f67930fa21a5e7967dc1386b80a2be8 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/southbridge/intel/i82801gx/lpc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6b9d11e..d4ca81c 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -670,6 +670,13 @@ static const struct pci_driver ich7m_ich7u_lpc __pci_driver = { .device = 0x27b9, }; +/* 82NM10 (NM10) */ +static const struct pci_driver nm10_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27bc, +}; + /* 82801GHM (ICH7-M DH) */ static const struct pci_driver ich7m_dh_lpc __pci_driver = { .ops = &device_ops,

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New patch to review for coreboot: ed8a98e spi: Remove out of date comment and alphabetically order flash table
by David Imhoff 03 May '15

03 May '15

David Imhoff (dimhoff_devel(a)xs4all.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10068 -gerrit commit ed8a98e54c169e21d6eb7511eb838ba7c3b15e42 Author: David Imhoff <dimhoff_devel(a)xs4all.nl> Date: Sun May 3 14:06:21 2015 +0200 spi: Remove out of date comment and alphabetically order flash table What is described by the comment has already been fixed in f0d038f4. This also means that STM_ID_N25Q128 doesn't have to be at the top of stmicro_spi_flash_table anymore. Change-Id: I7a9e9a0cdfdb1cf34e914e186fc6957c1d9b5ca6 Signed-off-by: David Imhoff <dimhoff_devel(a)xs4all.nl> --- src/drivers/spi/stmicro.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 3e35120..3cec0be 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -60,11 +60,6 @@ #define STM_ID_N25Q256A 0xba19 #define STM_ID_N25Q128 0xbb18 -/* Some SPI flash share the same .idcode1 (idcode[2]). To handle this without - * (possibly) breaking existing implementations, add the new device at the top - * of the flash table array and set its .idcode1 = STM_ID_USE_ALT_ID. The .id - * is then (idcode[1] << 8 | idcode[2]). - */ struct stmicro_spi_flash_params { u16 device_id; u8 op_erase; @@ -88,14 +83,6 @@ static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { { - .device_id = STM_ID_N25Q128, - .op_erase = CMD_M25PXX_SSE, - .page_size = 256, - .pages_per_sector = 16, - .nr_sectors = 4096, - .name = "N25Q128", - }, - { .device_id = STM_ID_M25P10, .op_erase = CMD_M25PXX_SE, .page_size = 256, @@ -160,6 +147,14 @@ static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { .name = "M25P128", }, { + .device_id = STM_ID_N25Q128, + .op_erase = CMD_M25PXX_SSE, + .page_size = 256, + .pages_per_sector = 16, + .nr_sectors = 4096, + .name = "N25Q128", + }, + { .device_id = STM_ID_N25Q256A, .page_size = 256, .pages_per_sector = 256,

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New patch to review for coreboot: 2334401 spi: Changed 'page' to 'sector' in log message
by David Imhoff 03 May '15

03 May '15

David Imhoff (dimhoff_devel(a)xs4all.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10067 -gerrit commit 2334401134ba381f12e001713a510a7bd3de2966 Author: David Imhoff <dimhoff_devel(a)xs4all.nl> Date: Sun May 3 13:47:49 2015 +0200 spi: Changed 'page' to 'sector' in log message The log message said 'page size' while actually the sector size was printed. This is confusing since for stmicro page size != sector size. Change-Id: I795a4b7c1bc8de2538a87fd4ba56f5a78d9ca2ac Signed-off-by: David Imhoff <dimhoff_devel(a)xs4all.nl> --- src/drivers/spi/spi_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d40f72a..b8469b9 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -381,7 +381,7 @@ flash_detected: tseg_relocate((void **)&flash->name); #endif - printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n", + printk(BIOS_INFO, "SF: Detected %s with sector size %x, total %x\n", flash->name, flash->sector_size, flash->size); spi_flash_dev = flash;

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Patch set updated for coreboot: 9733880 cbfstool/Makefile*: Use `LDFLAGS` instead of `LINKFLAGS`
by Paul Menzel 03 May '15

03 May '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10064 -gerrit commit 97338801761c323f7984992a19aac3611520481f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 3 09:35:32 2015 +0200 cbfstool/Makefile*: Use `LDFLAGS` instead of `LINKFLAGS` Commit 0e53931f (cbfstool: Clean up in preparation for adding new files) split out the flags and introduced the variable `LINKFLAGS`. Rename it to `LDFLAGS` which is more commonly used. Change-Id: Ib6299f8ef5cf30dbe05bfae36f30ae4371f0a738 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbfstool/Makefile | 4 ++-- util/cbfstool/Makefile.inc | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 9595773..86338db 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -7,7 +7,7 @@ CFLAGS += -std=c99 -Werror -Wall -Wextra CFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow CFLAGS += -Wstrict-prototypes -Wwrite-strings CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h -LINKFLAGS += -g3 +LDFLAGS += -g3 CBFSTOOL_BINARY:=$(obj)/cbfstool CBFSTOOL_COMMON:=common.o cbfs_image.o compress.o fit.o @@ -30,7 +30,7 @@ all: .dependencies $(CBFSTOOL_BINARY) $(RMODTOOL_BINARY) $(obj)/%: $(obj)/%.o mkdir -p $(dir $@) - $(HOSTCC) $(LINKFLAGS) -o $@ $^ $(LDLIBS) + $(HOSTCC) $(LDFLAGS) -o $@ $^ $(LDLIBS) $(obj)/%.o: %.c mkdir -p $(dir $@) $(HOSTCC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $< diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index a846e99..5bf0b70 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -28,7 +28,7 @@ TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings TOOLCPPFLAGS ?= -D_POSIX_C_SOURCE=200809L # strdup() from string.h -TOOLLINKFLAGS ?= +TOOLLDFLAGS ?= ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32) TOOLFLAGS+=-mno-ms-bitfields @@ -48,11 +48,11 @@ $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lzma/C/%.c $(objutil)/cbfstool/cbfstool: $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" - $(HOSTCC) $(TOOLLINKFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) $(objutil)/cbfstool/rmodtool: $(addprefix $(objutil)/cbfstool/,$(rmodobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" - $(HOSTCC) $(TOOLLINKFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(rmodobj)) + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(rmodobj)) # Tolerate lzma sdk warnings $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual

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New patch to review for coreboot: 26329de cpu/intel/socket_atom_d5xx: Add Intel Atom D5xx cpu and socket.
by Damien Zammit 03 May '15

03 May '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10066 -gerrit commit 26329de655582728909118497663e40bf08ddea9 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun May 3 19:49:37 2015 +1000 cpu/intel/socket_atom_d5xx: Add Intel Atom D5xx cpu and socket. Will push a working romstage for Intel D510MO board soon that boots to UART console. Change-Id: I82a630c9836c099d0fcc62e019c20f328a75151d Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/model_106cx/model_106cx_init.c | 1 + src/cpu/intel/socket_atom_d5xx/Kconfig | 20 +++++++++++++++++++ src/cpu/intel/socket_atom_d5xx/Makefile.inc | 10 ++++++++++ src/cpu/intel/socket_atom_d5xx/socket_atom_d5xx.c | 24 +++++++++++++++++++++++ 6 files changed, 57 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index de76e3e..8b98d4a 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -23,6 +23,7 @@ source src/cpu/intel/haswell/Kconfig # Sockets/Slots source src/cpu/intel/slot_2/Kconfig source src/cpu/intel/slot_1/Kconfig +source src/cpu/intel/socket_atom_d5xx/Kconfig source src/cpu/intel/socket_BGA956/Kconfig source src/cpu/intel/socket_FC_PGA370/Kconfig source src/cpu/intel/socket_mFCBGA479/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 51451e9..b1d8737 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -3,6 +3,7 @@ # # Therefore: ONLY include Makefile.inc from socket directories! +subdirs-$(CONFIG_CPU_INTEL_SOCKET_ATOM_D5XX) += socket_atom_d5xx subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index b201474..da603dd 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -152,6 +152,7 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x106c0 }, /* Intel Atom 230 */ + { X86_VENDOR_INTEL, 0x106ca }, /* Intel Atom D5xx */ { 0, 0 }, }; diff --git a/src/cpu/intel/socket_atom_d5xx/Kconfig b/src/cpu/intel/socket_atom_d5xx/Kconfig new file mode 100644 index 0000000..b8ac1e3 --- /dev/null +++ b/src/cpu/intel/socket_atom_d5xx/Kconfig @@ -0,0 +1,20 @@ +config CPU_INTEL_SOCKET_ATOM_D5XX + bool + +if CPU_INTEL_SOCKET_ATOM_D5XX + +config SOCKET_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_MODEL_106CX + select MMX + select SSE + +config DCACHE_RAM_BASE + hex + default 0xfffe0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_INTEL_SOCKET_ATOM_D5XX diff --git a/src/cpu/intel/socket_atom_d5xx/Makefile.inc b/src/cpu/intel/socket_atom_d5xx/Makefile.inc new file mode 100644 index 0000000..13dd799 --- /dev/null +++ b/src/cpu/intel/socket_atom_d5xx/Makefile.inc @@ -0,0 +1,10 @@ +ramstage-y += socket_atom_d5xx.c +subdirs-y += ../model_106cx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_atom_d5xx/socket_atom_d5xx.c b/src/cpu/intel/socket_atom_d5xx/socket_atom_d5xx.c new file mode 100644 index 0000000..092592d --- /dev/null +++ b/src/cpu/intel/socket_atom_d5xx/socket_atom_d5xx.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +struct chip_operations cpu_intel_socket_atom_ops = { + CHIP_NAME("Socket Atom D5xx CPU") +};

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New patch to review for coreboot: 5f2c710 southbridge/i82801gx: Add x_EN defines for LPC_EN
by Damien Zammit 03 May '15

03 May '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10065 -gerrit commit 5f2c7106160fc95e15e16bafce7c5599eb8dcbee Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun May 3 18:43:04 2015 +1000 southbridge/i82801gx: Add x_EN defines for LPC_EN Change-Id: I3ae67f4f6136361d67d4fdae2a5a29b7b1a75478 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/southbridge/intel/i82801gx/i82801gx.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index ee13b7d..92f63d2 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -97,6 +97,16 @@ int southbridge_detect_s3_resume(void); #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ /* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c

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New patch to review for coreboot: 880bb6a cbfstool/Makefile*: Use `LDFLAGS` instead of `LINKFLAGS`
by Paul Menzel 03 May '15

03 May '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10064 -gerrit commit 880bb6a26741bb0e32fa7303f721351786691902 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 3 09:35:32 2015 +0200 cbfstool/Makefile*: Use `LDFLAGS` instead of `LINKFLAGS` Commit 0e53931f (cbfstool: Clean up in preparation for adding new files) split out the flags and introduced the variable `LINKFLAGS`. Rename it to `LDFLAGS` which is more commonly used. Change-Id: Ib6299f8ef5cf30dbe05bfae36f30ae4371f0a738 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbfstool/Makefile | 4 ++-- util/cbfstool/Makefile.inc | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 9595773..86338db 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -7,7 +7,7 @@ CFLAGS += -std=c99 -Werror -Wall -Wextra CFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow CFLAGS += -Wstrict-prototypes -Wwrite-strings CPPFLAGS += -D_POSIX_C_SOURCE=200809L # strdup() from string.h -LINKFLAGS += -g3 +LDFLAGS += -g3 CBFSTOOL_BINARY:=$(obj)/cbfstool CBFSTOOL_COMMON:=common.o cbfs_image.o compress.o fit.o @@ -30,7 +30,7 @@ all: .dependencies $(CBFSTOOL_BINARY) $(RMODTOOL_BINARY) $(obj)/%: $(obj)/%.o mkdir -p $(dir $@) - $(HOSTCC) $(LINKFLAGS) -o $@ $^ $(LDLIBS) + $(HOSTCC) $(LDFLAGS) -o $@ $^ $(LDLIBS) $(obj)/%.o: %.c mkdir -p $(dir $@) $(HOSTCC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $< diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index a846e99..5bf0b70 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -28,7 +28,7 @@ TOOLCFLAGS ?= -std=c99 -Werror -Wall -Wextra TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings TOOLCPPFLAGS ?= -D_POSIX_C_SOURCE=200809L # strdup() from string.h -TOOLLINKFLAGS ?= +TOOLLDFLAGS ?= ifeq ($(shell uname -s | cut -c-7 2>/dev/null), MINGW32) TOOLFLAGS+=-mno-ms-bitfields @@ -48,11 +48,11 @@ $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lzma/C/%.c $(objutil)/cbfstool/cbfstool: $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" - $(HOSTCC) $(TOOLLINKFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) $(objutil)/cbfstool/rmodtool: $(addprefix $(objutil)/cbfstool/,$(rmodobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" - $(HOSTCC) $(TOOLLINKFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(rmodobj)) + $(HOSTCC) $(TOOLLDFLAGS) -o $@ $(addprefix $(objutil)/cbfstool/,$(rmodobj)) # Tolerate lzma sdk warnings $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual

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Patch set updated for coreboot: 1b0c8d7 superio/smsc/sch311x: Add support for SCH3112, SCH3114 and SCH3116 Super I/Os
by Damien Zammit 03 May '15

03 May '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7626 -gerrit commit 1b0c8d73fc6ee2a48afe60990454d040775e2f85 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Dec 2 20:24:31 2014 +1100 superio/smsc/sch311x: Add support for SCH3112, SCH3114 and SCH3116 Super I/Os Includes a command to share all 2-6 serial ports among a single IRQ. Tested on Intel D510MO (not in tree yet) Change-Id: I759d458bb03e145a68fe04617521ce079cc2be2f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sch311x/Makefile.inc | 21 ++++++++ src/superio/smsc/sch311x/sch311x.h | 36 +++++++++++++ src/superio/smsc/sch311x/sch311x_early_init.c | 73 +++++++++++++++++++++++++++ src/superio/smsc/sch311x/superio.c | 68 +++++++++++++++++++++++++ 6 files changed, 201 insertions(+) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 6aaa112..a47d127 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -47,5 +47,7 @@ config SUPERIO_SMSC_SMSCSUPERIO select SUPERIO_WANTS_14MHZ_CLOCK config SUPERIO_SMSC_SIO1036 bool +config SUPERIO_SMSC_SCH311X + bool config SUPERIO_SMSC_SCH4037 bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index a89b6ac..2397d6c 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -32,4 +32,5 @@ subdirs-y += kbc1100 subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 +subdirs-y += sch311x subdirs-y += sch4037 diff --git a/src/superio/smsc/sch311x/Makefile.inc b/src/superio/smsc/sch311x/Makefile.inc new file mode 100644 index 0000000..de0e724 --- /dev/null +++ b/src/superio/smsc/sch311x/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-$(CONFIG_SUPERIO_SMSC_SCH311X) += sch311x_early_init.c +ramstage-$(CONFIG_SUPERIO_SMSC_SCH311X) += superio.c diff --git a/src/superio/smsc/sch311x/sch311x.h b/src/superio/smsc/sch311x/sch311x.h new file mode 100644 index 0000000..f9cd089 --- /dev/null +++ b/src/superio/smsc/sch311x/sch311x.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_311X_H +#define SUPERIO_SCH_311X_H + +#define SCH311X_FDD 0 /* FDD */ +#define SCH311X_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH311X_KBC 7 /* KBC */ +#define SCH311X_RUNTIME 0x0A /* Runtime */ +#define SMSCSUPERIO_SP3 0x0B /* Com3 */ +#define SMSCSUPERIO_SP4 0x0C /* Com4 */ +#define SMSCSUPERIO_SP5 0x0D /* Com5 */ +#define SMSCSUPERIO_SP6 0x0E /* Com6 */ + +void sch311x_early_init(unsigned port); + +#endif /* SUPERIO_SCH_311X_H */ diff --git a/src/superio/smsc/sch311x/sch311x_early_init.c b/src/superio/smsc/sch311x/sch311x_early_init.c new file mode 100644 index 0000000..4b0db47 --- /dev/null +++ b/src/superio/smsc/sch311x/sch311x_early_init.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "sch311x.h" + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + unsigned port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + unsigned port = dev >> 8; + outb(0xaa, port); +} + +void sch311x_early_init(unsigned port) +{ + pnp_devfn_t dev; + + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /* Auto power management */ + pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config(dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enable High speed, disable MIDI support, + * Share 1x IRQ among all serial ports */ + pnp_write_config(dev, 0xF0, 0xC2); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV(port, SCH311X_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/sch311x/superio.c b/src/superio/smsc/sch311x/superio.c new file mode 100644 index 0000000..e28ff77 --- /dev/null +++ b/src/superio/smsc/sch311x/superio.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC SCH311X Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <pc80/keyboard.h> +#include <stdlib.h> + +#include "sch311x.h" + +static void sch311x_init(struct device *dev) +{ + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + case SCH311X_KBC: + pc_keyboard_init(); + break; + default: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = sch311x_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH311X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_sch311x_ops = { + CHIP_NAME("SMSC SCH311x Super I/O") + .enable_dev = enable_dev, +};

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Patch set updated for coreboot: 064f1cf usbdebug: Add FTDI FT232H support
by Kyösti Mälkki 03 May '15

03 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10063 -gerrit commit 064f1cff354ec2bd8b76c27c51d467c64d1da1fd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun May 3 06:27:11 2015 +0300 usbdebug: Add FTDI FT232H support Tested with gizmosphere/gizmo1 Explorer add-on board, which exposes the following device: 0x0403 Future Technology Devices International, Ltd 0x6014 FT232H Single HS USB-UART/FIFO IC For now UART is hard-coded to 115200, 8n1, no flow-control. Change-Id: I4081f84f7700751ccbf079e7fcbb1467aa71d872 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/Kconfig | 6 ++++ src/drivers/usb/gadget.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 91 insertions(+), 2 deletions(-) diff --git a/src/drivers/usb/Kconfig b/src/drivers/usb/Kconfig index b0baa42..c5c1ec7 100644 --- a/src/drivers/usb/Kconfig +++ b/src/drivers/usb/Kconfig @@ -89,6 +89,12 @@ config USBDEBUG_DONGLE_BEAGLEBONE_BLACK help Use this with BeagleBone Black. +config USBDEBUG_DONGLE_FTDI_FT232H + bool "FTDI FT232H UART" + help + Use this with FT232H usb-to-uart. Configuration is hard-coded + to use 115200, 8n1, no flow control. + endchoice config USBDEBUG_OPTIONAL_HUB_PORT diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index 5dd7993..7f88149 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -224,6 +224,85 @@ small_write: return 0; } +/* FTDI FT232H UART programming. */ +#define FTDI_SIO_SET_FLOW_CTRL_REQUEST 0x02 +#define FTDI_SIO_SET_BAUDRATE_REQUEST 0x03 +#define FTDI_SIO_SET_DATA_REQUEST 0x04 +#define FTDI_SIO_SET_BITMODE_REQUEST 0x0b + +static int probe_for_ftdi(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe) +{ + int ret; + u8 devnum = 0; + u8 uart_if = 1; /* FTDI_INTERFACE_A 1 */ + + /* Move the device to 127 if it isn't already there */ + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0); + if (ret < 0) { + dprintk(BIOS_INFO, "Could not move attached device to %d.\n", + USB_DEBUG_DEVNUM); + return -2; + } + devnum = USB_DEBUG_DEVNUM; + dprintk(BIOS_INFO, "EHCI debug device renamed to %d.\n", devnum); + + /* Send Set Configure request to device. */ + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0); + if (ret < 0) { + dprintk(BIOS_INFO, "FTDI set configuration failed.\n"); + return -2; + } + + ret = dbgp_control_msg(ehci_debug, devnum, + USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, + FTDI_SIO_SET_BITMODE_REQUEST, 0, uart_if, NULL, 0); + if (ret < 0) { + dprintk(BIOS_INFO, "FTDI SET_BITMODE failed.\n"); + return -3; + } + ret = dbgp_control_msg(ehci_debug, devnum, + USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, + FTDI_SIO_SET_BAUDRATE_REQUEST, + 0xc068, 0x0200 | uart_if, NULL, 0); + if (ret < 0) { + dprintk(BIOS_INFO, "FTDI SET_BAUDRATE failed.\n"); + return -3; + } + ret = dbgp_control_msg(ehci_debug, devnum, + USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, + FTDI_SIO_SET_DATA_REQUEST, + 0x0008, uart_if, NULL, 0); + if (ret < 0) { + dprintk(BIOS_INFO, "FTDI SET_DATA failed.\n"); + return -3; + } + ret = dbgp_control_msg(ehci_debug, devnum, + USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, + FTDI_SIO_SET_FLOW_CTRL_REQUEST, + 0x0000, uart_if, NULL, 0); + if (ret < 0) { + dprintk(BIOS_INFO, "FTDI SET_FLOW_CTRL failed.\n"); + return -3; + } + + pipe[DBGP_CONSOLE_EPOUT].endpoint = 0x02; + pipe[DBGP_CONSOLE_EPIN].endpoint = 0x81; + + ack_set_configuration(pipe, devnum, 1000); + + /* Perform a small write. */ + ret = dbgp_bulk_write_x(&pipe[DBGP_CONSOLE_EPOUT], "USB\r\n", 5); + if (ret < 0) { + dprintk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret); + return -4; + } + dprintk(BIOS_INFO, "Test write done\n"); + return 0; +} int dbgp_probe_gadget(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe) { @@ -238,9 +317,13 @@ int dbgp_probe_gadget(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe) } } - ret = probe_for_debug_descriptor(ehci_debug, pipe); + if (IS_ENABLED(CONFIG_USBDEBUG_DONGLE_FTDI_FT232H)) { + ret = probe_for_ftdi(ehci_debug, pipe); + } else { + ret = probe_for_debug_descriptor(ehci_debug, pipe); + } if (ret < 0) { - dprintk(BIOS_INFO, "Could not enable gadget using Debug Descriptor.\n"); + dprintk(BIOS_INFO, "Could not enable debug dongle.\n"); return ret; }

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Patch merged into coreboot/master: 58649b0 src/southbridge/intel/i82801ix: Add GPIO register locations
by gerrit＠coreboot.org 03 May '15

03 May '15

the following patch was just integrated into master: commit 58649b058baecf24a07a2bc85fff68b339d67503 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 5 18:03:15 2015 -0500 src/southbridge/intel/i82801ix: Add GPIO register locations Change-Id: I226a1a6bc6b1f921c03f8ec57875a88314928aeb Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/9318 for details. -gerrit

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coreboot-gerrit May 2015