New patch to review for coreboot: 26329de cpu/intel/socket_atom_d5xx: Add Intel Atom D5xx cpu and socket.
Damien Zammit (damien@zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10066
-gerrit
commit 26329de655582728909118497663e40bf08ddea9 Author: Damien Zammit damien@zamaudio.com Date: Sun May 3 19:49:37 2015 +1000
cpu/intel/socket_atom_d5xx: Add Intel Atom D5xx cpu and socket.
Will push a working romstage for Intel D510MO board soon that boots to UART console.
Change-Id: I82a630c9836c099d0fcc62e019c20f328a75151d Signed-off-by: Damien Zammit damien@zamaudio.com --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/model_106cx/model_106cx_init.c | 1 + src/cpu/intel/socket_atom_d5xx/Kconfig | 20 +++++++++++++++++++ src/cpu/intel/socket_atom_d5xx/Makefile.inc | 10 ++++++++++ src/cpu/intel/socket_atom_d5xx/socket_atom_d5xx.c | 24 +++++++++++++++++++++++ 6 files changed, 57 insertions(+)
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index de76e3e..8b98d4a 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -23,6 +23,7 @@ source src/cpu/intel/haswell/Kconfig # Sockets/Slots source src/cpu/intel/slot_2/Kconfig source src/cpu/intel/slot_1/Kconfig +source src/cpu/intel/socket_atom_d5xx/Kconfig source src/cpu/intel/socket_BGA956/Kconfig source src/cpu/intel/socket_FC_PGA370/Kconfig source src/cpu/intel/socket_mFCBGA479/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 51451e9..b1d8737 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -3,6 +3,7 @@ # # Therefore: ONLY include Makefile.inc from socket directories!
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_ATOM_D5XX) += socket_atom_d5xx subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index b201474..da603dd 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -152,6 +152,7 @@ static struct device_operations cpu_dev_ops = {
static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x106c0 }, /* Intel Atom 230 */ + { X86_VENDOR_INTEL, 0x106ca }, /* Intel Atom D5xx */ { 0, 0 }, };
diff --git a/src/cpu/intel/socket_atom_d5xx/Kconfig b/src/cpu/intel/socket_atom_d5xx/Kconfig new file mode 100644 index 0000000..b8ac1e3 --- /dev/null +++ b/src/cpu/intel/socket_atom_d5xx/Kconfig @@ -0,0 +1,20 @@ +config CPU_INTEL_SOCKET_ATOM_D5XX + bool + +if CPU_INTEL_SOCKET_ATOM_D5XX + +config SOCKET_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_MODEL_106CX + select MMX + select SSE + +config DCACHE_RAM_BASE + hex + default 0xfffe0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_INTEL_SOCKET_ATOM_D5XX diff --git a/src/cpu/intel/socket_atom_d5xx/Makefile.inc b/src/cpu/intel/socket_atom_d5xx/Makefile.inc new file mode 100644 index 0000000..13dd799 --- /dev/null +++ b/src/cpu/intel/socket_atom_d5xx/Makefile.inc @@ -0,0 +1,10 @@ +ramstage-y += socket_atom_d5xx.c +subdirs-y += ../model_106cx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +subdirs-y += ../speedstep diff --git a/src/cpu/intel/socket_atom_d5xx/socket_atom_d5xx.c b/src/cpu/intel/socket_atom_d5xx/socket_atom_d5xx.c new file mode 100644 index 0000000..092592d --- /dev/null +++ b/src/cpu/intel/socket_atom_d5xx/socket_atom_d5xx.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +struct chip_operations cpu_intel_socket_atom_ops = { + CHIP_NAME("Socket Atom D5xx CPU") +};
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Damien Zammit