coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 69d7aec samus: Update thermal max for broadwell
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 69d7aecdaf66e50217d530aa5cb158bc15b01b85 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 3 08:53:21 2014 -0800 samus: Update thermal max for broadwell Broadwell Tj_max is 105C, update accordingly. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus Change-Id: I001e17287ebbcbfdd909428e149a95878734dab9 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: fb1de7a9e1d84f592b785a1b495e4aaf434f23a2 Original-Change-Id: If6a3fd682f4ee9b8010982870a61b76e33010fd4 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226952 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9270 for details. -gerrit

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Patch merged into coreboot/master: d416124 samus: Assign GPIO2 to HP_AMP_SHDN_L
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit d416124f059eeca5a7b0ba5cd3857865d8014104 Author: Ben Zhang <benzh(a)chromium.org> Date: Tue Sep 30 17:00:05 2014 -0700 samus: Assign GPIO2 to HP_AMP_SHDN_L BUG=chrome-os-partner:29649 BRANCH=samus TEST=Audio playback to headphone works Change-Id: I35efa3b97abbba50cbee4c25acfaeb155fc1238f Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: e2c0ede19c6b700c8d0bf01ff9d3a54984c5d784 Original-Change-Id: Ib51aace52026688dc8972047e5d934c80138ff80 Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221294 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9269 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9269 for details. -gerrit

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Patch merged into coreboot/master: dcf2d38 samus: Make codec interrupt active high
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit dcf2d38f02024616a05aa6b9231776a8726202a9 Author: Ben Zhang <benzh(a)chromium.org> Date: Tue Sep 30 12:55:04 2014 -0700 samus: Make codec interrupt active high The codec interrupt needs to be active high because multiple interrupt sources share this line: 1) Headphone plug detect 2) Mic present 3) Hotword detect These interrupt sources are OR-ed together. BUG=chrome-os-partner:29649 BRANCH=samus TEST=Jack detection works on samus Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980 Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220588 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9268 for details. -gerrit

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Patch merged into coreboot/master: 94fea49 Broadwell: Fix PCIe L1 Sub-State capability ID not filled.
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 94fea491df7beaf02b2cd01d3b4366e9baa82a89 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Tue Sep 30 14:17:35 2014 +0800 Broadwell: Fix PCIe L1 Sub-State capability ID not filled. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 31d7276fbdca67937bcdf0d5c2af371a2fd1a510 Original-BUG=chrome-os-partner:31424,chromeos-os-partner:32380 Original-TEST=Build a BIOS image and check the value is applied correctly. Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Original-Change-Id: I0adda3643776b259a635a021babd983090f1df43 Original-Reviewed-on: https://chromium-review.googlesource.com/220475 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Id88c11ed128b44c3a60ef1a141b99071c1ee15d3 Reviewed-on: http://review.coreboot.org/9267 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9267 for details. -gerrit

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Patch merged into coreboot/master: e1ca8a3 samus: Add codec platform data for jack detect
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit e1ca8a3d42da15fbe7a8be928bdd531f26298dd6 Author: Ben Zhang <benzh(a)chromium.org> Date: Mon Oct 20 17:27:42 2014 -0700 samus: Add codec platform data for jack detect GPIO IRQ support has been added in upstream rt5677 driver, with new jack detect platform config options. BUG=chrome-os-partner:29649 BRANCH=samus TEST=headphone and mic detect works on Samus Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502 Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224513 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9266 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9266 for details. -gerrit

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Patch merged into coreboot/master: e566220 samus: Change GPIO controller label to INT3437:00
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit e56622025190b685e4c11c2641de902cfdd87af2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 17 13:49:22 2014 -0700 samus: Change GPIO controller label to INT3437:00 This matches the label exported by the GPIO controller in the kernel and allows more speicific matches if there are other devices that also export GPIOs. BUG=chrome-os-partner:33098 BRANCH=samus TEST=crossystem wpsw_cur returns 1 Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14 Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224136 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9265 for details. -gerrit

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Patch merged into coreboot/master: 24a849d samus: Enable update screen for software sync
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 24a849d4c18a9784d5e1df693c1398294e10572e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 16 17:06:32 2014 -0700 samus: Enable update screen for software sync Since the PD software sync is slow enable support for displaying a screen telling the user that something is happening. BUG=chrome-os-partner:32379 BRANCH=samus TEST=manual testing: 1) in normal mode, with EC/PD in RW, ensure that they are rebooted to RO and the VGA Option ROM is loaded and the wait screen is displayed, and then the system is rebooted at the end and the VGA Option ROM is not loaded. 2) same as #1 with EC/PD in RO already, same result 3) same as #1 with system in developer mode, same result except there is no reboot at the end of software sync 4) same as #1 with system in developer mode and EC/PD in RO, ensure that there is no extra reboot at the beginning or end of software sync. Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2 Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223850 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9264 for details. -gerrit

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Patch merged into coreboot/master: 8283344 samus: Add smbios_mainboard_version to define board version
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 82833446b6e0878a43fbe7f0014bdf00f6f241db Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 13 13:12:38 2014 -0700 samus: Add smbios_mainboard_version to define board version Instead of having this in mosys just have coreboot report the board version in SMBIOS tables. BUG=chrome-os-partner:32359 BRANCH=samus TEST=build and boot on samus, check /sys/class/dmi/id/product_version Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89 Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223096 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9263 for details. -gerrit

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Patch merged into coreboot/master: 0b92a5e broadwell: Fix building with USE=quiet-cb
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 0b92a5e6076dfc9c03140ad61c0f9588a85b2e41 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 3 15:34:09 2014 -0700 broadwell: Fix building with USE=quiet-cb This function needs to be available in different LOGLEVELs. BUG=chrome-os-partner:28234 BRANCH=samus TEST=USE=quiet-cb emerge-samus coreboot Change-Id: Ib56995db64a7417a637eb8a93350fc40e6f83340 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 716d26c82a7df1dccf8956f301ab0e103fcedcff Original-Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221540 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9262 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9262 for details. -gerrit

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Patch merged into coreboot/master: 88b004d samus: Add codec platform info in ACPI
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 88b004d6fc0c68218716f3952395872aede61951 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 3 15:33:10 2014 -0700 samus: Add codec platform info in ACPI This is the specific codec setup platform data for samus. BUG=chrome-os-partner:29649 BRANCH=samus TEST=emerge-samus coreboot Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221539 Original-Reviewed-by: Ben Zhang <benzh(a)chromium.org> Reviewed-on: http://review.coreboot.org/9261 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9261 for details. -gerrit

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coreboot-gerrit April 2015