coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 4a69c34 Broadwell: Pass TSC value to romstage_main
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 4a69c34d54d587ba00c6c8e4f9056596014a7541 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Nov 20 16:56:44 2014 -0800 Broadwell: Pass TSC value to romstage_main The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831 Original-Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Original-Reviewed-on: https://chromium-review.googlesource.com/231173 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9280 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9280 for details. -gerrit

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Patch merged into coreboot/master: 9f5a5c5 Add table driven way to add platform specific reg_script routines
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 9f5a5c532343fe72753fc507b0f2ef1a26afabd3 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Aug 29 13:38:59 2014 -0700 Add table driven way to add platform specific reg_script routines Extend lib/reg_script.c to use a platform table to declare additional platform specific register access routine functions. REG_SCRIPT_TYPE_PLATFORM_BASE is the starting value for platform specific register types. Additional register access types may be defined above this value. The type and access routines are placed into reg_script_type_table. The Baytrail type value for IOSF was left the enumeration since it was already defined and is being used for Braswell. BRANCH=none BUG=None TEST=Use the following steps to test: 1. Build for a Baytrail platform 2. Build for the Samus platform 3. Add a platform_bus_table routine to a platform which returns the address of an array of reg_script_bus_entry structures and the number of entries in the array. Change-Id: Ic99d345c4b067c52b4e9c47e59ed4472a05bc1a5 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 2d9fecf4287dff6311a81d818603212248f1a248 Original-Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/215645 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Change-Id: I7cd37abc5a08cadb3166d4048f65b919b86ab5db Original-Reviewed-on: https://chromium-review.googlesource.com/229612 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9279 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9279 for details. -gerrit

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Patch merged into coreboot/master: a19a4e1 samus: Add new memory type
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit a19a4e1d64ab0dbf531a3fbeb7cdda331a3ed6ca Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Nov 19 12:12:18 2014 -0800 samus: Add new memory type Add a new memory type for the next build, and rename the existing ones to drop the Gb suffix. BUG=chrome-os-partner:33924 BRANCH=samus TEST=build and boot on samus Change-Id: Iedcd3823aa80c93fc2aadbc486d74b40c9bd4279 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: bcc9827965182a7d0d5325189d55eb76f5c2f0e7 Original-Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230769 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9278 for details. -gerrit

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Patch merged into coreboot/master: 573429b samus: Set codec PDM clock output to 3MHz
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 573429b09dafa94dac4e1c2b0d9ed33d64676963 Author: Ben Zhang <benzh(a)chromium.org> Date: Mon Nov 17 17:21:09 2014 -0800 samus: Set codec PDM clock output to 3MHz Currently the rt5677 codec outputs 6MHz PDM clock which is out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS pin is pulled down to PGND with a 47k resistor, so the expected PDM clock is 64*FS (~3MHz) according to its datasheet. The corresponding kernel patch that adds the PDM clock config option is https://chromium-review.googlesource.com/#/c/230303/ BUG=chrome-os-partner:33303 BRANCH=samus TEST=flash coreboot with this patch and see PDM CLK went from 6MHz to 3MHz on samus with a scope. Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648 Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230344 Original-Reviewed-by: Dylan Reid <dgreid(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/9277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9277 for details. -gerrit

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Patch merged into coreboot/master: f208905 broadwell: fix typo in pei_data
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit f208905fda0784111b494771f2c60d76eefebdc7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Nov 19 09:02:29 2014 -0800 broadwell: fix typo in pei_data This was copied and pasted more than it should have been... BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5008f2992d8ab3b952042415af6d7844788e14fc Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: bff4570dffa413c4fc4dfd8c49920f6b951e944a Original-Change-Id: I2af9a30f3df733af147e8759f78a9802d2296c0f Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230753 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9276 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9276 for details. -gerrit

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Patch merged into coreboot/master: 2e073fc broadwell: Add USB3 PHY tuning fields to PEI DATA
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 2e073fc43934d376dcebe7c7a7e64d45384f21b1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 17 13:05:50 2014 -0800 broadwell: Add USB3 PHY tuning fields to PEI DATA These are board specific adjustments that can be made for each USB3 port. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Iaa3ce09419dfd64e3e8187f6dc073a8c68565337 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 21000496bb4560c9d1452a128335bbf24ca1b0aa Original-Change-Id: Iab92ff7b0218d4abd9eba8a94d34ddd9a30ddb87 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230231 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9275 for details. -gerrit

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Patch merged into coreboot/master: c1b5275 samus: Change touchscreen bootloader mode i2c address
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit c1b52757d98ea60fbdd67ea99a8e9a26584b4970 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 17 13:06:52 2014 -0800 samus: Change touchscreen bootloader mode i2c address This value apparently changed to 0x27 in the hardware but was never adjusted in firmware. BUG=chrome-os-partner:33790 BRANCH=samus TEST=build and boot on samus Change-Id: Ib610fc6522715e3c841c337d420ec63563bec798 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: e01d3b47bf49861e9d53fc8db41890fe4c91ff9b Original-Change-Id: I10ca7b77068491e143f8bf2463b481eada910618 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230232 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9274 for details. -gerrit

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Patch merged into coreboot/master: 09920e2 samus: Enable GSPI0 interface
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 09920e2de316751b9bbebad41e78404b025b79ec Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 3 15:46:59 2014 -0800 samus: Enable GSPI0 interface This will be connected to the coded for firmware upload. BUG=chrome-os-partner:33495 BRANCH=samus TEST=build and boot on samus, check that GSPI driver is loaded Change-Id: Ife41394e31af9dab03495b34609cb119525f9b19 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: bbf26154da675845251c54f71d1df9df8d2a4fd5 Original-Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228835 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9273 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9273 for details. -gerrit

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Patch merged into coreboot/master: 97acc5e Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 97acc5e88603ac82cd5bebc59b74f033d1e06096 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Fri Oct 31 00:32:09 2014 -0700 Baytrail: Fix no_dev_behind_port not executed for RP1/2/3. BRANCH=master BUG=chrome-os-partner:33113 TEST=Build a image and test on Rambi. Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: I37add87e6fd3e7ad4eee09b8e0b312a2a89c7948 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 59b4c94be46b4397de7cb32726da9fa216e75a4c Original-Change-Id: I22c8f9730cc0e1ecc991f2dd7f2a1e7c548a1789 Original-Reviewed-on: https://chromium-review.googlesource.com/226654 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen(a)intel.com> Original-Tested-by: Kenji Chen <kenji.chen(a)intel.com> Reviewed-on: http://review.coreboot.org/9272 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9272 for details. -gerrit

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Patch merged into coreboot/master: c37dd50 samus: Enable GPIO9 as touchpad wake
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit c37dd507e0619afd3e92e64d5a0630ac502ec76f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Nov 3 12:48:11 2014 -0800 samus: Enable GPIO9 as touchpad wake With EVT2 systems GPIO9 is now used for touchpad wake. BUG=chrome-os-partner:32232 BRANCH=samus TEST=suspend/resume by touchpad on samus, with kernel workaround to disable setting of T19 in atmel driver mxt_suspend() 51 | 2014-11-03 12:41:34 | ACPI Enter | S3 52 | 2014-11-03 12:41:37 | ACPI Wake | S3 53 | 2014-11-03 12:41:37 | Wake Source | GPIO | 9 Change-Id: I67c1a6591dc287fc780889950e78c731a5a65d44 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 8512a6e5266edaf77d300f47bd26c501f00361d7 Original-Change-Id: I8120747986e694b64d464826f87c9afa68af157a Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227157 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9271 for details. -gerrit

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coreboot-gerrit April 2015