coreboot-gerrit April 2015

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

Patch set updated for coreboot: 0462cb2 arm64: Add verstage support
by Aaron Durbin 04 Apr '15

04 Apr '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9255 -gerrit commit 0462cb2cc77d5f7d07aebbdde80cb2e8722b7650 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Oct 2 16:43:19 2014 -0700 arm64: Add verstage support This stage is not tested on any hardware. BUG=None BRANCH=None TEST=Compiles successfully for rush_ryu and veyron_pinky Original-Change-Id: I6dd266471c815895bb3dd53d34aacc8fe825eeb6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221911 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 907ea2d1f8c9f01d815e8673695dd5271322c7a8) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I617a742d4a387be947086dae33e9a913f742a8d1 --- src/arch/arm64/Makefile.inc | 20 ++++++++++++++++++++ src/arch/arm64/armv8/Makefile.inc | 14 ++++++++++++++ src/arch/arm64/armv8/lib/Makefile.inc | 4 ++++ 3 files changed, 38 insertions(+) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c1f1112..59330a5 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -76,6 +76,26 @@ $(objcbfs)/bootblock.debug: $(src)/arch/arm64/bootblock.ld $(obj)/ldoptions $$(b endif # CONFIG_ARCH_BOOTBLOCK_ARM64 +############################################################################### +# verification stage +############################################################################### + +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) + +$(objcbfs)/verstage.debug: $$(verstage-objs) $$(VB2_LIB) $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld $(obj)/config.h + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --start-group $(verstage-objs) $(VBS_LIB) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + +verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c +verstage-y += div0.c +verstage-y += eabi_compat.c +verstage-y += ../../lib/memset.c +verstage-y += ../../lib/memcpy.c +verstage-y += ../../lib/memmove.c +verstage-y += stages.c + +endif # CONFIG_ARCH_VERSTAGE_ARM64 + ################################################################################ # romstage ################################################################################ diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index ae9f38d..f0c5bbb 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -46,6 +46,20 @@ bootblock-S-ccopts += $(armv8_asm_flags) endif ################################################################################ +## verstage +################################################################################ +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM_V8_64),y) + +verstage-y += cache.c +verstage-y += cpu.S +verstage-y += exception.c + +verstage-c-ccopts += $(armv8_flags) +verstage-S-ccopts += $(armv8_asm_flags) + +endif + +################################################################################ ## romstage ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc index 0622593..7e647bd 100644 --- a/src/arch/arm64/armv8/lib/Makefile.inc +++ b/src/arch/arm64/armv8/lib/Makefile.inc @@ -26,6 +26,10 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) bootblock-y += $(lib_access) endif +ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y) +verstage-y += $(lib_access) +endif + ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) romstage-y += $(lib_access) endif

1 0

Patch merged into coreboot/master: 08884e3 rk3288: set cpu frequency up to 1.8GHz
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 08884e39cd3c7d0d0250e0e7921d12b5ae10ada1 Author: huang lin <hl(a)rock-chips.com> Date: Fri Oct 10 20:28:47 2014 -0700 rk3288: set cpu frequency up to 1.8GHz before the rkclk_init(), we must set rk808 buck1 voltage up to 1300mv BUG=chrome-os-partner:32716, chrome-os-partner:31896 TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1300mv and check the cpu frequency up to 1.8GHz Original-Change-Id: I6a8c6e35bd7cc6017f2def72876a9170977f206e Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222957 Original-Reviewed-by: Doug Anderson <dianders(a)chromium.org> (cherry picked from commit 2e7e7c265691250d4a1b3ff94fe70b0a05f23e16) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iff89d959456dd4d36f4293435caf7b4f7bdaf6fd Reviewed-on: http://review.coreboot.org/9260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9260 for details. -gerrit

1 0

Patch merged into coreboot/master: 8affee5 rk3288: guarantee i2c low period more than 1.3us
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 8affee58975f28e6a22fe3a474bd8bdd9a9cc05a Author: huang lin <hl(a)rock-chips.com> Date: Fri Oct 10 23:26:21 2014 -0700 rk3288: guarantee i2c low period more than 1.3us change i2c clock low period and high period proportion to 7:3 guarantee the low period more than 1.3us BUG=None TEST=Boot on veyron_pinky rev2,check the i2c clock frequency Original-Change-Id: I235e9e3ff54ab3b9cabad36bab58a8409f7005a0 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223002 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 57a5d90d394086483e0dcdd6279678658d07d842) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I6b0c9dfa540354f6463ed90c9f3f9503a4d5749e Reviewed-on: http://review.coreboot.org/9259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9259 for details. -gerrit

1 0

Patch merged into coreboot/master: 45e16fc t132: Enable SMMU translations
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 45e16fc19913224c124cba0ca0ac22e949de9e9a Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Oct 10 01:31:02 2014 -0700 t132: Enable SMMU translations BUG=None BRANCH=None TEST=Verified by reading back the value of SMMU_CONFIG register that enable bit is set to 1 Original-Change-Id: Iccc870141f9b9729971bf12119f9f3dae8181a43 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222770 Original-Reviewed-by: Olof Johansson <olofj(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit a06b36f9003d801709d83a8faed6fc04bb91df1b) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iae3949940a5a0efa2761542974d5c209178ce397 Reviewed-on: http://review.coreboot.org/9258 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9258 for details. -gerrit

1 0

Patch merged into coreboot/master: 834d2b9 tegra132: Store ODMDATA from BCT into PMC scratch for use by kernel
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 834d2b98dea3eb976b41a988d053278d88ce541d Author: Tom Warren <twarren(a)nvidia.com> Date: Thu Oct 9 16:01:33 2014 -0700 tegra132: Store ODMDATA from BCT into PMC scratch for use by kernel In able to do earlyprintk spew on LP0 resume, the kernel needs to know the board UART. ODMDATA (in bct/odmdata.cfg) contains this info, and the kernel looks for it in PMC_SCRATCH20. Fetch the ODMDATA word from the BCT copy stored in IRAM by the BootROM. BUG=chrome-os-partner:32015 BRANCH=none TEST=Built for Rush and Ryu OK. Dumped PMC_SCRATCH20 in TegraShell on Rush and confirmed value is what's in odmdata.cfg. Original-Change-Id: I63f33558ee8b00bd6c1e313efcd531e1d5fc67eb Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222402 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 3f6a21afdb81f7d2ae90119c563535b4c87c9ade) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9819ffdf0f7618f0dd8dc50f81b5b26d6f94bfbd Reviewed-on: http://review.coreboot.org/9257 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9257 for details. -gerrit

1 0

Patch merged into coreboot/master: acbf32a tegra132: remove framebuffer reservation
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit acbf32a0422555b5edfaa60559dbcaf90adb4167 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 7 16:16:48 2014 -0500 tegra132: remove framebuffer reservation There's no need to reserve the framebuffer within coreboot. If the payloads need a framebuffer they can allocate one themselves. BUG=chrome-os-partner:31355 BRANCH=None TEST=Built and booted on ryu. Original-Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221726 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 1ff8da9fed414fceeda3f94b296312f4531b320f) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I4e7c0417824f2be9836b1bc2bb99322c78490ca2 Reviewed-on: http://review.coreboot.org/9256 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9256 for details. -gerrit

1 0

Patch merged into coreboot/master: b6092b7 veyron_pinky/rk3288: Use KHz, MHz and GHz constants
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit b6092b7e396d5e7ab55cb7c11375b6a8fec7cd61 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 6 13:41:28 2014 -0700 veyron_pinky/rk3288: Use KHz, MHz and GHz constants Use the previously added frequency constants in patch titled 'stddef: Add KHz, MHz and GHz constants'. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac Reviewed-on: http://review.coreboot.org/9254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9254 for details. -gerrit

1 0

Patch merged into coreboot/master: 46826c3 stddef: Add KHz, MHz and GHz constants
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 46826c36bf1af1dcb4535f0838933f01f600a9d7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Apr 2 15:43:12 2015 -0500 stddef: Add KHz, MHz and GHz constants This patch adds some simple constants to more easily write and do math with frequencies, analogous to the existing KiB, MiB and GiB constants for sizes. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I1e708b0aa53533c9ab999793ca2273c6dc68b5f6 Reviewed-on: http://review.coreboot.org/9253 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9253 for details. -gerrit

1 0

Patch merged into coreboot/master: d3f1579 samus: Disable USB Port 5
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit d3f1579df9978215263393e5dead21d3dc92c3a6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 10 08:11:56 2014 -0800 samus: Disable USB Port 5 This device is not used in current builds and should be disabled to help EMI. BUG=chrome-os-partner:34117 BRANCH=samus TEST=build and boot on samus Change-Id: I5c34f1f6c84d9de04a42e16fa32f57d4f9d1e478 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: 00a9b2ad8512f84beff7358dad0ec028478c57d2 Original-Change-Id: I62541e343dcaa3cd31c81b73d8c27a5efcf3ad60 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234403 Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/9282 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9282 for details. -gerrit

1 0

Patch merged into coreboot/master: 7f28e4e broadwell: Enable turbo ratio if available
by gerrit＠coreboot.org 04 Apr '15

04 Apr '15

the following patch was just integrated into master: commit 7f28e4ee01cb91750ce6fb84e77e5c7c86afd3ea Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Dec 10 08:16:43 2014 -0800 broadwell: Enable turbo ratio if available When turning up the CPU frequency set it to turbo if that is a possibility. Also only set the frequency on the boot CPU since that is all we need it on, this will allow the 1-core turbo ratio. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I573eb7a507305814ec48cc2f624b8e6ddad43f84 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Id: d408c1b462983c682d61c6c447692391c2b52183 Original-Change-Id: Ib5ad746767ee0a56bc7e59de679a9342f053c0e5 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234401 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/9281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/9281 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2015