Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9575
-gerrit
commit bea94e0c4058ba0418be572a097bdacb62381c52
Author: Jimmy Zhang <jimmzhang(a)nvidia.com>
Date: Thu Dec 4 17:24:43 2014 -0800
rush: Add gpio config for PWR button and LID open switch
Due to CL https://chromium-review.googlesource.com/231250,
depthcharge now detects gpio state based on gpio configurations
done by coreboot instead of redoing configuration at
depthcharge. However, PWR button and LID open pins have not
been configured in coreboot. So, add the missing code here.
Otherwise, TOT coreboot/depthcharge rush build can not load
in kernel.
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build rush and test with pwr button press and lid switch
Change-Id: I7acc5e021fa769f68d4cbfd7202df325d4ea73c2
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: a25dff24a2dcd33fcd15eb766432414af215c3ab
Original-Change-Id: I6c322cd987967920f236aae653294db079678408
Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233322
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rush/bootblock.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c
index eb61cdd..6680cba 100644
--- a/src/mainboard/google/rush/bootblock.c
+++ b/src/mainboard/google/rush/bootblock.c
@@ -50,6 +50,12 @@ static const struct pad_config padcfgs[] = {
PAD_CFG_GPIO_INPUT(GPIO_X1_AUD, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_ROW17, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
+
+ /* Power Button */
+ PAD_CFG_GPIO_INPUT(KB_COL0, PINMUX_PULL_NONE),
+
+ /* Lid Open Switch */
+ PAD_CFG_GPIO_INPUT(KB_ROW4, PINMUX_PULL_UP),
};
static const struct pad_config i2cpad[] = {
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9574
-gerrit
commit 1603dd1fb04a4cd7bba78aa84ca9b3101d7dcc93
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Dec 4 14:57:52 2014 -0800
storm: Fix timer init order problem
Commit 257aaee9e3a (arm: Add bootblock_mainboard_early_init() for
pre-console initialization) inadvertently moved the timer initialization
after console initialization for IPQ806x, which is apparently not a good
idea for this platform. This patch solves the issue by moving
init_timer() to bootblock_mainboard_early_init(), which is the new hook
explicitly provided to perform pre-console tasks.
BRANCH=None
BUG=None
TEST=Built and booted Storm with 257aaee9e reverted. Noticed that it was
already broken. Bisected coreboot and tracked down breakage to commit
a126a62f (ipq8064: use the new utility to build bootblock). Built and
booted successfully with this patch and a revert of a126a62f to confirm
that the bug in question here is fixed.
Change-Id: I4a3faa2aec8ff1fbbe6c389f1d048475aa944418
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 752d1f879f9bd841f18bd84842491f747458cf52
Original-Change-Id: Ie4aa2d06cb6fda6d5ff8dd5ea052257fb7b8a24b
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/233290
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
---
src/mainboard/google/storm/Makefile.inc | 1 +
src/mainboard/google/storm/bootblock.c | 26 ++++++++++++++++++++++++++
src/soc/qualcomm/ipq806x/Makefile.inc | 1 -
src/soc/qualcomm/ipq806x/bootblock.c | 26 --------------------------
4 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc
index 6ee0841..80727b6 100644
--- a/src/mainboard/google/storm/Makefile.inc
+++ b/src/mainboard/google/storm/Makefile.inc
@@ -17,6 +17,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+bootblock-y += bootblock.c
bootblock-y += cdp.c
romstage-y += romstage.c
diff --git a/src/mainboard/google/storm/bootblock.c b/src/mainboard/google/storm/bootblock.c
new file mode 100644
index 0000000..fc9f8f3
--- /dev/null
+++ b/src/mainboard/google/storm/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <bootblock_common.h>
+#include <delay.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ init_timer();
+}
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 27967dc..604cdc1 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -17,7 +17,6 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += gpio.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
diff --git a/src/soc/qualcomm/ipq806x/bootblock.c b/src/soc/qualcomm/ipq806x/bootblock.c
deleted file mode 100644
index a079d42..0000000
--- a/src/soc/qualcomm/ipq806x/bootblock.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <bootblock_common.h>
-#include <delay.h>
-
-void bootblock_soc_init(void)
-{
- init_timer();
-}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9573
-gerrit
commit 11b2a0522bc1792314425e7021ca1b2fcebed1d9
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Sun Nov 30 16:10:46 2014 -0800
ipq8064: use the new utility to build bootblock
The first blob in the Storm bootimage is a concatenation of the
Uber-sbl produced by the qca-firmware ebuild and the coreboot
bootblock.
The new tool is used to add the bootblock to uber-sbl and update the
size values in the combined header.
BRANCH=storm
BUG=chrome-os-partner:34161
TEST=no execution tests yet, the build succeeds.
Change-Id: I4f1fe8a97ffab04eee4f82bc43e6f5406dd9bb42
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: a126a62f65a568d62fe35bdcf27eaec38fd1a997
Original-Change-Id: Iec3c1e943f1f9ee5ca20320a6365fc4aa5516e38
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232310
Original-Reviewed-by: Manoj Juneja <mjuneja(a)qti.qualcomm.com>
Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
---
src/soc/qualcomm/ipq806x/Kconfig | 2 +-
src/soc/qualcomm/ipq806x/Makefile.inc | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index 8cc7233..0136a18 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -41,7 +41,7 @@ config MBN_ENCAPSULATION
config SBL_BLOB
depends on USE_BLOBS
string "file name of the Qualcomm SBL blob"
- default "3rdparty/cpu/qualcomm/ipq8064/sbls.bin"
+ default "3rdparty/cpu/qualcomm/ipq806x/uber-sbl.mbn"
help
The path and filename of the binary blob containing
ipq806x early initialization code, as supplied by the
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 5dfca4d..27967dc 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -57,8 +57,8 @@ $(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
# Create a complete bootblock which will start up the system
$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \
$(objcbfs)/bootblock.mbn
- @printf " CAT $(subst $(obj)/,,$(@))\n"
- @cat $^ > $@.tmp
+ @printf " MBNCAT $(subst $(obj)/,,$(@))\n"
+ @util/ipqheader/mbncat.py -o $@.tmp $^
@mv $@.tmp $@
endif
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9572
-gerrit
commit 10bd06e3678d8a1c75ded0e58508bfbc98b38e71
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Sun Nov 30 13:05:38 2014 -0800
util: ipq8064: utility to create uber-SBL
With the Storm image layout reworked, the very first blob read out of
NOR SPI flash by the IPQ8064 maskrom is supposed to be a concatenation
of three binaries: one to run on RPM, another one to run on AP, and
the third one - the actual coreboot bootblock.
This layout allows to greatly reduce the size and complexity of the
two first blobs, as they do not need to include the SPI driver.
The first binary in the input file list starts with the combined
header, describing the rest of the blob. This utility copies the first
input file into output, updating the combined header with the total
size of the concatenated binaries.
The second and third binaries in the combined image are required to be
aligned at 256 byte offset in the file as calculated off the end of
the combined header. The new utility allows to concatenate two or
three files, always expecting the first file to be prepended by the
combined header.
For further reference below is the utility's help message:
mbncat.py: [-v] [-h] [-o Output MBN] sbl1 sbl2 [bootblock]
Concatenates up to three mbn files: two SBLs and a coreboot bootblock
-h This message
-v verbose
-o Output file name, (default: sbl-ro.mbn)
BRANCH=none
BUG=chrome-os-partner:34161
TEST=run the new utility and compared the result with the output of
the vendor provided tool. The output files are exactly the same.
Change-Id: I1d3b3634ecc3f46ea88adb9b6c4fbfc017cc06ac
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 94008340bc5eaf19d286b3feaa4091e5c5e285aa
Original-Change-Id: I00724f7c75703fc90d7971c3cb337c33ca96f2b5
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232047
Original-Reviewed-by: Manoj Juneja <mjuneja(a)qti.qualcomm.com>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
---
util/ipqheader/mbncat.py | 200 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 200 insertions(+)
diff --git a/util/ipqheader/mbncat.py b/util/ipqheader/mbncat.py
new file mode 100755
index 0000000..39c9d80
--- /dev/null
+++ b/util/ipqheader/mbncat.py
@@ -0,0 +1,200 @@
+#!/usr/bin/python
+# Copyright (c) 2014, The Linux Foundation. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above
+# copyright notice, this list of conditions and the following
+# disclaimer in the documentation and/or other materials provided
+# with the distribution.
+# * Neither the name of The Linux Foundation nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+
+# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import struct
+import sys
+import os
+
+"""A utility to generate ipq8064 uber SBL..
+
+The very first blob (aka 'uber SBL') read out of NOR SPI flash by the IPQ8064
+maskrom is supposed to be a concatenation of up to three binaries: one to run
+on the RPM, another one to run on the AP, and the third one - the actual
+coreboot bootblock.
+
+The uber SBL starts with the combined header descriptor of 80 bytes, with the
+first two 4 byte words set to certain values, and the total size of the
+payload saved at offsets 28 and 32.
+
+To generate the uber SBL this utility expects two or three input file names in
+the command line, the first file including the described header, and the
+following one(s) - in QCA MBN format. This allows to create the uber SBL in
+one or two invocations.
+
+The input files are concatenated together aligned at 256 byte boundary offset
+from the combined header. See Usage() below for more details.
+
+The resulting uber SBL file is prepended by the same combined header adjusted
+to reflect the new total file size.
+"""
+
+DEFAULT_OUTPUT_FILE_NAME = 'sbl-ro.mbn'
+
+class NorSbl:
+ """Object representing the uber SBL."""
+
+ NOR_SBL1_HEADER = '<II72s'
+ NOR_SBL1_HEADER_SZ = struct.calcsize(NOR_SBL1_HEADER)
+ ALIGNMENT = 256 # Make sure this == UBER_SBL_PAD_SIZE
+ NOR_CODE_WORD = 0x844bdcd1
+ MAGIC_NUM = 0x73d71034
+
+ def __init__(self, sbl1, verbose):
+ """Initialize the object and verify the first file in the sequence.
+
+ Args:
+ sbl1: string, the name of the first out of the three input blobs,
+ must be prepended by the combined header.
+ verbose: boolean, if True - print debug information on the console.
+ """
+ self.verbose = verbose
+ self.mbn_file_names = []
+ if self.verbose:
+ print 'Reading ' + sbl1
+
+ try:
+ self.sbl1 = open(sbl1, 'rb').read()
+ except IOError as e:
+ print 'I/O error({0}): {1}'.format(e.errno, e.strerror)
+ raise
+
+ (codeword, magic, _) = struct.unpack_from(
+ self.NOR_SBL1_HEADER, self.sbl1)
+
+ if codeword != self.NOR_CODE_WORD:
+ print '\n\nError: Unexpected Codeword!'
+ print 'Codeword : ' + ('0x%x' % self.NOR_CODE_WORD) + \
+ ' != ' + ('0x%x' % codeword)
+ sys.exit(-1)
+
+ if magic != self.MAGIC_NUM:
+ print '\n\nError: Unexpected Magic!'
+ print 'Magic : ' + ('0x%x' % self.MAGIC_NUM) + \
+ ' != ' + ('0x%x' % magic)
+ sys.exit(-1)
+
+ def Append(self, src):
+ """Add a file to the list of files to be concatenated"""
+ self.mbn_file_names.append(src)
+
+ def PadOutput(self, outfile, size):
+ """Pad output file to the required alignment.
+
+ Adds 0xff to the passed in file to get its size to the ALIGNMENT
+ boundary.
+
+ Args:
+ outfile: file handle of the file to be padded
+ size: int, current size of the file
+
+ Returns number of bytes in the added padding.
+ """
+
+ # Is padding needed?
+ overflow = size % self.ALIGNMENT
+ if overflow:
+ pad_size = self.ALIGNMENT - overflow
+ pad = '\377' * pad_size
+ outfile.write(pad)
+ if self.verbose:
+ print 'Added %d byte padding' % pad_size
+ return pad_size
+ return 0
+
+ def Create(self, out_file_name):
+ """Create the uber SBL.
+
+ Concatenate input files with the appropriate padding and update the
+ combined header to reflect the new blob size.
+
+ Args:
+ out_file_name: string, name of the file to save the generated uber
+ SBL in.
+ """
+ outfile = open(out_file_name, 'wb')
+ total_size = len(self.sbl1) - self.NOR_SBL1_HEADER_SZ
+ outfile.write(self.sbl1)
+
+ for mbn_file_name in self.mbn_file_names:
+ total_size += self.PadOutput(outfile, total_size)
+ mbn_file_data = open(mbn_file_name, 'r').read()
+ outfile.write(mbn_file_data)
+ if self.verbose:
+ print 'Added %s (%d bytes)' % (mbn_file_name,
+ len(mbn_file_data))
+ total_size += len(mbn_file_data)
+
+ outfile.seek(28)
+ outfile.write(struct.pack('<I', total_size))
+ outfile.write(struct.pack('<I', total_size))
+
+
+def Usage(v):
+ print '%s: [-v] [-h] [-o Output MBN] sbl1 sbl2 [bootblock]' % (
+ os.path.basename(sys.argv[0]))
+ print
+ print 'Concatenates up to three mbn files: two SBLs and a coreboot bootblock'
+ print ' -h This message'
+ print ' -v verbose'
+ print ' -o Output file name, (default: %s)\n' % DEFAULT_OUTPUT_FILE_NAME
+ sys.exit(v)
+
+def main():
+ verbose = 0
+ mbn_output = DEFAULT_OUTPUT_FILE_NAME
+ i = 0
+
+ while i < (len(sys.argv) - 1):
+ i += 1
+ if (sys.argv[i] == '-h'):
+ Usage(0) # doesn't return
+
+ if (sys.argv[i] == '-o'):
+ mbn_output = sys.argv[i + 1]
+ i += 1
+ continue
+
+ if (sys.argv[i] == '-v'):
+ verbose = 1
+ continue
+
+ break
+
+ argv = sys.argv[i:]
+ if len(argv) < 2 or len(argv) > 3:
+ Usage(-1)
+
+ nsbl = NorSbl(argv[0], verbose)
+
+ for mbnf in argv[1:]:
+ nsbl.Append(mbnf)
+
+ nsbl.Create(mbn_output)
+
+if __name__ == '__main__':
+ main()
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9571
-gerrit
commit ccdea55a50f02bc3a9b90af3db2936430a4e4c4d
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Sat Nov 29 15:06:26 2014 -0800
spi: support controllers with limited transfer size capabilities
Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI
read and write transactions. Limiting transfer size in the wrapper
allows to provide the API user with unlimited transfer size
transactions.
The tranfer size limitation is added to the spi_slave structure, which
is set up by the controller driver. The value of zero in this field
means 'unlimited transfer size'. It will work with existion drivers,
as they all either keep structures in the bss segment, or initialize
them to all zeros.
This patch addresses the problem for reads only, as coreboot is not
expected to require to write long chunks into SPI devices.
BRANCH=none
BUG=chrome-os-partner:32441, chrome-os-partner:31438
TEST=set transfer size limit to artificially low value (4K) and
observed proper operation on both Pistachio and ipq8086: both
Storm and Urara booted through romstage and ramstage.
Change-Id: Ibb96aa499c3eec458c94bf1193fbbbf5f54e1477
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 4f064fdca5b6c214e7a7f2751dc24e33cac2ea45
Original-Change-Id: I9df24f302edc872bed991ea450c0af33a1c0ff7b
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232239
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
---
src/drivers/spi/spi_flash.c | 44 ++++++++++++++++++++++--------------
src/drivers/spi/spi_flash_internal.h | 14 ------------
src/include/spi-generic.h | 5 ++++
src/soc/imgtec/pistachio/spi.c | 5 ++++
4 files changed, 37 insertions(+), 31 deletions(-)
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index d737ee9..607fb21 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -79,8 +79,8 @@ int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
return ret;
}
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len)
+static int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
+ size_t cmd_len, void *data, size_t data_len)
{
int ret = do_spi_flash_cmd(spi, cmd, cmd_len, data, data_len);
if (ret) {
@@ -108,41 +108,51 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
return ret;
}
-int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len)
+static int spi_flash_cmd_read_array(struct spi_slave *spi, u8 *cmd,
+ size_t cmd_len, u32 offset,
+ size_t len, void *data)
{
- struct spi_slave *spi = flash->spi;
- int ret;
+ while (len) {
+ size_t transfer_size;
- spi->rw = SPI_READ_FLAG;
- ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
+ if (spi->max_transfer_size)
+ transfer_size = min(len, spi->max_transfer_size);
+ else
+ transfer_size = len;
- return ret;
+ spi_flash_addr(offset, cmd);
+
+ if (spi_flash_cmd_read(spi, cmd, cmd_len, data, transfer_size))
+ break;
+
+ offset += transfer_size;
+ data = (void *)((uintptr_t)data + transfer_size);
+ len -= transfer_size;
+ }
+
+ return len != 0;
}
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- struct spi_slave *spi = flash->spi;
u8 cmd[5];
cmd[0] = CMD_READ_ARRAY_FAST;
- spi_flash_addr(offset, cmd);
cmd[4] = 0x00;
- return spi_flash_cmd_read(spi, cmd, sizeof(cmd), data, len);
+ return spi_flash_cmd_read_array(flash->spi, cmd, sizeof(cmd),
+ offset, len, data);
}
int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset,
- size_t len, void *data)
+ size_t len, void *data)
{
- struct spi_slave *spi = flash->spi;
u8 cmd[4];
cmd[0] = CMD_READ_ARRAY_SLOW;
- spi_flash_addr(offset, cmd);
-
- return spi_flash_cmd_read(spi, cmd, sizeof(cmd), data, len);
+ return spi_flash_cmd_read_array(flash->spi, cmd, sizeof(cmd),
+ offset, len, data);
}
int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h
index 6f18484..4798b10 100644
--- a/src/drivers/spi/spi_flash_internal.h
+++ b/src/drivers/spi/spi_flash_internal.h
@@ -32,13 +32,6 @@
/* Send a single-byte command to the device and read the response */
int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
-/*
- * Send a multi-byte command to the device and read the response. Used
- * for flash array reads, etc.
- */
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len);
-
int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
size_t len, void *data);
@@ -52,13 +45,6 @@ int spi_flash_cmd_read_slow(struct spi_flash *flash, u32 offset,
int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
const void *data, size_t data_len);
-/*
- * Same as spi_flash_cmd_read() except it also claims/releases the SPI
- * bus. Used as common part of the ->read() operation.
- */
-int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
- size_t cmd_len, void *data, size_t data_len);
-
/* Send a command to the device and wait for some bit to clear itself. */
int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
u8 cmd, u8 poll_bit);
diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h
index bd0020f..4de138c 100644
--- a/src/include/spi-generic.h
+++ b/src/include/spi-generic.h
@@ -43,11 +43,16 @@
* bus: ID of the bus that the slave is attached to.
* cs: ID of the chip select connected to the slave.
* rw: Read or Write flag
+ * max_transfer_size: maximum amount of bytes which can be sent in a single
+ * read or write transaction, usually this is a controller
+ * property, kept in the slave structure for convenience. Zero in
+ * this field means 'unlimited'.
*/
struct spi_slave {
unsigned int bus;
unsigned int cs;
unsigned int rw;
+ unsigned int max_transfer_size;
int force_programmer_specific;
struct spi_flash * (*programmer_specific_probe) (struct spi_slave *spi);
};
diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c
index 69682d0..5522f24 100644
--- a/src/soc/imgtec/pistachio/spi.c
+++ b/src/soc/imgtec/pistachio/spi.c
@@ -25,6 +25,9 @@
#error "Unsupported SPI driver API"
#endif
+/* Imgtec controller uses 16 bit packet length. */
+#define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1)
+
struct img_spi_slave {
struct spi_slave slave;
/* SPIM instance device parameters */
@@ -441,6 +444,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
slave->bus = bus;
slave->cs = cs;
slave->rw = SPI_READ_FLAG | SPI_WRITE_FLAG;
+ slave->max_transfer_size = IMGTEC_SPI_MAX_TRANSFER_SIZE;
+
device_parameters->bitrate = 64;
device_parameters->cs_setup = 0;
device_parameters->cs_hold = 0;
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9569
-gerrit
commit 29e94223c0a3e6f63865ce4f39966437f93c79bb
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Sat Nov 29 14:35:49 2014 -0800
mips: HACK disable caches in bootblock startup code
Until proper MIPS cache management is available it is necessary to
disable data and instruction caches, otherwise code placed in memory
stays in data cache and is not available for instruction fetched.
BRANCH=none
BUG=chrome-os-partner:31438,chrome-os-partner:34127
TEST=coreboot loading rombase and rambase now succeeds.
Change-Id: I4147e1325edc0b9bb951cd7ce18d5f104f3eaec0
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 93d5bfa1d01fbbabbabef33a22287ceeea28b15b
Original-Change-Id: Ib195ed6e5f08ccaa6bbe3325c2199171bfb63b88
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232191
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/arch/mips/bootblock.S | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/arch/mips/bootblock.S b/src/arch/mips/bootblock.S
index 8899fe0..ed31b24 100644
--- a/src/arch/mips/bootblock.S
+++ b/src/arch/mips/bootblock.S
@@ -36,6 +36,16 @@ _start:
bne $t0, $t1, 1b
addi $t0, $t0, 4
+ /*
+ * Disable caches for now, proper cache management is coming soon.
+ * http://crosbug.com/p/34127
+ */
+ mfc0 $t0, $16
+ li $t1, -8
+ and $t0, $t0, $t1
+ ori $t0, $t0, 2
+ mtc0 $t0, $16
+
/* Run main */
b main
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9567
-gerrit
commit 3b0c41698ce40877c93767a93c31cb9f695b358d
Author: Sourabh Banerjee <sbanerje(a)codeaurora.org>
Date: Tue Jan 20 15:18:40 2015 +0530
tpm: wait for valid bit to be set in TPM access register before using tpm
As per the TCG PC Client TPM Interface Specification v1.2, bit 7 of the
access register (tmpRegValiSts bit) stays "0" until the TPM has complete
through self test and initialization. This bit is set "1" to indicate that
the other bits in the register are valid.
BRANCH=chromeos-2013.04
BUG=chrome-os-partner:35328
TEST=Booted up storm p0.2 and whirwind sp3.
Verified TPM chip is detected and reported in coreboot logs.
Change-Id: I1049139fc155bfd2e1f29e3b8a7b9d2da6360857
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 006fc93c6308d6f3fa220f00708708aa62cc676c
Original-Change-Id: I9df3388ee1ef6e4a9d200d99aea1838963747ecf
Original-Signed-off-by: Sourabh Banerjee <sbanerje(a)codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242222
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org>
---
src/drivers/i2c/tpm/tis.c | 29 ++++++++++++++++++++++++++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c
index 696634d..d9a7651 100644
--- a/src/drivers/i2c/tpm/tis.c
+++ b/src/drivers/i2c/tpm/tis.c
@@ -29,6 +29,7 @@
#include <device/i2c.h>
#include <tpm.h>
#include "tpm.h"
+#include <timer.h>
#include <console/console.h>
@@ -37,6 +38,7 @@ struct tpm_chip g_chip;
#define TPM_CMD_COUNT_BYTE 2
#define TPM_CMD_ORDINAL_BYTE 6
+#define TPM_VALID_STATUS (1 << 7)
int tis_open(void)
{
@@ -74,12 +76,33 @@ int tis_init(void)
{
int bus = CONFIG_DRIVER_TPM_I2C_BUS;
int chip = CONFIG_DRIVER_TPM_I2C_ADDR;
+ struct stopwatch sw;
+ uint8_t buf = 0;
+ int ret;
+ long sw_run_duration = 750;
/*
- * Probe TPM twice; the first probing might fail because TPM is asleep,
- * and the probing can wake up TPM.
+ * Probe TPM. Check if the TPM_ACCESS register's ValidSts bit is set(1)
+ * If the bit remains clear(0) then claim that init has failed.
*/
- if (i2c_writeb(bus, chip, 0, 0) && i2c_writeb(bus, chip, 0, 0))
+ stopwatch_init_msecs_expire(&sw, sw_run_duration);
+ do {
+ ret = i2c_readb(bus, chip, 0, &buf);
+ if (!ret && (buf & TPM_VALID_STATUS)) {
+ sw_run_duration = stopwatch_duration_msecs(&sw);
+ break;
+ }
+ } while (!stopwatch_expired(&sw));
+
+ printk(BIOS_INFO,
+ "%s: ValidSts bit %s(%d) in TPM_ACCESS register after %ld ms\n",
+ __func__, (buf & TPM_VALID_STATUS) ? "set" : "clear",
+ (buf & TPM_VALID_STATUS) >> 7, sw_run_duration);
+
+ /*
+ * Claim failure if the ValidSts (bit 7) is clear.
+ */
+ if (!(buf & TPM_VALID_STATUS))
return -1;
return 0;