Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9301
-gerrit
commit f6366430022cf307b6d5e9d81068993496830ac4
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Sat Apr 4 03:05:17 2015 +0200
Fix dependency issue in Chrome OS vendor code
make *config was complaining about mainboards selecting a virtual
dev switch when CONFIG_CHROMEOS is not enabled.
While the long term cleanup should be to move the option out of
CONFIG_CHROMEOS and make it not be a user changeable option, this
approach is contained to vendorcode/ and gets rid of the warning.
Change-Id: Id090eb31d1307af7a0d1f9fbe641534dc24b24a9
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/vendorcode/google/chromeos/Kconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index cb15d13..214f0ba 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -169,4 +169,12 @@ source src/vendorcode/google/chromeos/vboot1/Kconfig
source src/vendorcode/google/chromeos/vboot2/Kconfig
endif # CHROMEOS
+if !CHROMEOS
+config VIRTUAL_DEV_SWITCH
+ bool
+ default n
+ depends on MAINBOARD_HAS_CHROMEOS
+ help
+ Whether this platform has a virtual developer switch.
+endif
endmenu
the following patch was just integrated into master:
commit a555f749cbff688854b459336d4a112aa7e292d6
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Mon Nov 24 13:01:11 2014 -0800
fmap: allocate memory as much as discovered fmap size
fmap_find used to read 4096 bytes from the fmap offset blindly. instead, we read
the fmap header first to calcurate the size of the fmap. Then, we read flash
again exactly as much as the discovered fmap.
BUG=none
BRANCH=ToT
TEST=Booted Storm and Peppy. Built all current boards.
Change-Id: Iaa50c1bc3401c77b433af11406d4b9d2e4e722e8
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 755ff66ab0a4d05e6d5410c11a6badb9fcb77a0d
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Change-Id: Ie5058d181e6565acb70bf108464682dd0e6c1f64
Original-Reviewed-on: https://chromium-review.googlesource.com/231685
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9556
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9556 for details.
-gerrit
the following patch was just integrated into master:
commit 2e2288de350f8d64ff8c4023eaf71f763d9e1a7f
Author: huang lin <hl(a)rock-chips.com>
Date: Tue Nov 25 09:27:13 2014 +0800
rk3288: reset edp after edp clock source select
edp must reset when device power up, otherwise the edp
register maybe uncertain, now the edp source clock default
select 27M, and in pinky and jerry board we use 24M as edp
sourec clock, if we want to reset edp, we must after the clock
source select 24M.
BUG=chrome-os-partner:34023
TEST=Booted Veyron jerry and read edid normal
BRANCH=None
Change-Id: I4b03dbabe5d3d595d2d56efb0cd82f510f8d2e1b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 2292da77cc2322b85c4b4f4f20e4ebcc4c4d060d
Original-Change-Id: Ica031d2d52deb539c1a0a56968786d6952b3d0e8
Original-Signed-off-by: huang lin <hl(a)rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/231336
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-by: Daniel Kurtz <djkurtz(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9555
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9555 for details.
-gerrit
the following patch was just integrated into master:
commit f757bf8e769333f850e03f150d1973862a978644
Author: Katie Roberts-Hoffman <katierh(a)chromium.org>
Date: Wed Nov 19 18:17:52 2014 -0800
Add google/veyron_mighty board
Essentially a copy of veyron_jerry for now.
BUG=chrome-os-partner:33269
TEST=build
Change-Id: Ie2d115d57fe4b6359fa6bb16a2e85e88ec99e991
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9ec25b9cf2985786e55f0b85c3849ccbd42bddd4
Original-Change-Id: Icc45c8f8bf9f6916ba7187dde277d15cc60df8a2
Original-Signed-off-by: Katie Roberts-Hoffman <katierh(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230961
Original-Commit-Id: 407b8b74a068220d8051dd0d85d9c4ec3ea14d51
Original-Change-Id: I546dbc41ccd191159e96b851424fcb37902a57ec
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231691
Reviewed-on: http://review.coreboot.org/9554
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9554 for details.
-gerrit
the following patch was just integrated into master:
commit 40f558e8f4f77ab70a8a2eb9bdfa850e362cb553
Author: huang lin <hl(a)rock-chips.com>
Date: Fri Sep 19 14:51:52 2014 +0800
rockchip: support display
Implement VOP and eDP drivers, vop and edp clock configuration,
framebuffer allocation and display configuration logic.
The eDP driver reads panel EDID to determine panel dimensions
and the pixel clock used by the VOP.
The pixel clock is generating using the NPLL.
BUG=chrome-os-partner:31897
TEST=Booted Veyron Pinky and display normal
BRANCH=None
Change-Id: I01b5c347a3433a108806aec61aa3a875cab8c129
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: e4f863b0b57f2f5293ea8015db86cf7f8acc5853
Original-Change-Id: I61214f55e96bc1dcda9b0f700e5db11e49e5e533
Original-Signed-off-by: huang lin <hl(a)rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219050
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9553
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9553 for details.
-gerrit
the following patch was just integrated into master:
commit 1c8f2a6f968bec72a7060ba264f44fbea96d68e9
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Nov 13 15:51:00 2014 -0800
veyron*: select VIRTUAL_DEV_SWITCH
Like most newer Chromebooks, Pinky and Jerry do not have physical
dev switches.
BUG=chrome-os-partner:33395
BRANCH=none
TEST=built and booted on Pinky, crossystem prints a valid value for
devsw_cur instead of an error.
Change-Id: If97ffa6f99eb31c05915f3ee82aaf6bd252d29e4
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: db302d7286d3e7df9442928dac1d611a2c103163
Original-Change-Id: I186518a59699d293c7938221b3ae45b27361c255
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229680
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9552
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9552 for details.
-gerrit
the following patch was just integrated into master:
commit 5016820cc95697151552c64c14ca1e06013a881f
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Nov 10 21:37:12 2014 -0800
veyron: Adapt to new board revisions
This patch adds support for Pinky rev3 (board ID 2) and Jerry rev2: the
power button GPIO changed polarity to low, the 5V_DRV pin for USB power
was moved to the AP again (welcome back!), and the EMMC_RST_L is now
finally on a port with the right IO voltage so we don't need any weird
pull-up tricks anymore. Since there are very few Jerry rev1s around,
we'll just move it over to the new code directly without introducing
board ID differences (also, because I have no idea how they stuffed it
this time... is this one actually called rev2?).
BRANCH=None
BUG=None
TEST=Still boots on my Pinky rev2, though that doesn't say much.
Change-Id: Id11044cedcaac5a4ae07e696893823925107a6db
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 55344a9518ff04edcef01bcd40817e9e4b613717
Original-Change-Id: Iddee360fbda357ecde4ae5fbb5c3a01fe0c22474
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229010
Original-Reviewed-by: Lin Huang <hl(a)rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9551
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9551 for details.
-gerrit
the following patch was just integrated into master:
commit 63451c73bd8fc587247b2e75587b1137fdbebf38
Author: Julius Werner <jwerner(a)chromium.org>
Date: Mon Nov 10 19:53:45 2014 -0800
veyron_jerry: Port CPU overshoot prevention
This patch ports commit 567f616f (rk3288: slowly raise to max cpu
voltage to prevent overshoot) to Veyron_Jerry. It also fixes include
ordering and some comment grammar in the affected code.
BRANCH=None
BUG=chrome-os-partner:32716
TEST=None
Change-Id: I4ac14a38e4b3acc4926d4f51f409ff12d9c841cf
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 679014bc843788e8d4d5f5c7470ae76f8be5e942
Original-Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228938
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9550
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9550 for details.
-gerrit
the following patch was just integrated into master:
commit 539e856643f9a7396638c05db5c4dbfb136e292b
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Nov 6 16:51:02 2014 -0800
veyron*: sdram_get_ram_code() -> ram_code()
This enables RAM_CODE_SUPPORT for veyron* platforms and uses the
generic gpio_get_binaries() function to read RAM_ID GPIOs.
BUG=chrome-os-partner:31728
BRANCH=none
TEST=built and booted on pinky
Change-Id: I7a03e42a270bec7036004375d36734bfdfe6e528
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: a325b204ff88131dfb0bdd3dfedb3c007cd98010
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Change-Id: Ibc4c61687f1c59311cbf6b48371f9a9125dbe115
Original-Reviewed-on: https://chromium-review.googlesource.com/227249
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9549
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9549 for details.
-gerrit
the following patch was just integrated into master:
commit a0abd51e4edb6b00c82032234b8ae1868e6d965e
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Fri Nov 7 13:48:49 2014 -0800
veyron*: use gpio_base2_value() in board_id()
This makes board_id() use the generic gpio_base2_value() function
to obtain the value of the board ID straps.
BUG=none
BRANCH=none
TEST=tested on pinky
Change-Id: I15c1310889b989c34638fd342011aef5fe7bcec1
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: fcbb8a6998a66531326afe16b232395d49fee64d
Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Original-Change-Id: I5847bf1c5b26bcaf7d36103f31bb255b31ff8185
Original-Reviewed-on: https://chromium-review.googlesource.com/228370
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9548
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9548 for details.
-gerrit